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| * Freescale 83xx and 512x PCI bridges | |
| Freescale 83xx and 512x SOCs include the same PCI bridge core. | |
| 83xx/512x specific notes: | |
| - reg: should contain two address length tuples | |
| The first is for the internal PCI bridge registers | |
| The second is for the PCI config space access registers | |
| Example (MPC8313ERDB) | |
| pci0: pci@e0008500 { | |
| interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
| interrupt-map = < | |
| /* IDSEL 0x0E -mini PCI */ | |
| 0x7000 0x0 0x0 0x1 &ipic 18 0x8 | |
| 0x7000 0x0 0x0 0x2 &ipic 18 0x8 | |
| 0x7000 0x0 0x0 0x3 &ipic 18 0x8 | |
| 0x7000 0x0 0x0 0x4 &ipic 18 0x8 | |
| /* IDSEL 0x0F - PCI slot */ | |
| 0x7800 0x0 0x0 0x1 &ipic 17 0x8 | |
| 0x7800 0x0 0x0 0x2 &ipic 18 0x8 | |
| 0x7800 0x0 0x0 0x3 &ipic 17 0x8 | |
| 0x7800 0x0 0x0 0x4 &ipic 18 0x8>; | |
| interrupt-parent = <&ipic>; | |
| interrupts = <66 0x8>; | |
| bus-range = <0x0 0x0>; | |
| ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 | |
| 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 | |
| 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; | |
| clock-frequency = <66666666>; | |
| #interrupt-cells = <1>; | |
| #size-cells = <2>; | |
| #address-cells = <3>; | |
| reg = <0xe0008500 0x100 /* internal registers */ | |
| 0xe0008300 0x8>; /* config space access registers */ | |
| compatible = "fsl,mpc8349-pci"; | |
| device_type = "pci"; | |
| }; |
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| Marvell 88PG867/88PG868 voltage regulators | |
| Required properties: | |
| - compatible: one of "marvell,88pg867", "marvell,88pg868"; | |
| - reg: I2C slave address. | |
| Optional subnodes for regulators: "buck1", "buck2", using common regulator | |
| bindings given in <Documentation/devicetree/bindings/regulator/regulator.txt>. | |
| Example: | |
| pg868@19 { | |
| compatible = "marvell,88pg868"; | |
| reg = <0x19>; | |
| vcpu: buck1 { | |
| regulator-boot-on; | |
| regulator-always-on; | |
| regulator-min-microvolt = <1000000>; | |
| regulator-max-microvolt = <1350000>; | |
| }; | |
| }; |
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| Marvell 88PM800 regulator | |
| Required properties: | |
| - compatible: "marvell,88pm800" | |
| - reg: I2C slave address | |
| - regulators: A node that houses a sub-node for each regulator within the | |
| device. Each sub-node is identified using the node's name (or the deprecated | |
| regulator-compatible property if present), with valid values listed below. | |
| The content of each sub-node is defined by the standard binding for | |
| regulators; see regulator.txt. | |
| The valid names for regulators are: | |
| buck1, buck2, buck3, buck4, buck5, ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, | |
| ldo8, ldo9, ldo10, ldo11, ldo12, ldo13, ldo14, ldo15, ldo16, ldo17, ldo18, ldo19 | |
| Example: | |
| pmic: 88pm800@31 { | |
| compatible = "marvell,88pm800"; | |
| reg = <0x31>; | |
| regulators { | |
| buck1 { | |
| regulator-min-microvolt = <600000>; | |
| regulator-max-microvolt = <3950000>; | |
| regulator-boot-on; | |
| regulator-always-on; | |
| }; | |
| ldo1 { | |
| regulator-min-microvolt = <600000>; | |
| regulator-max-microvolt = <15000000>; | |
| regulator-boot-on; | |
| regulator-always-on; | |
| }; | |
| ... | |
| }; | |
| }; |
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| Marvell 88PM860x regulator | |
| Required properties: | |
| - compatible: "marvell,88pm860x" | |
| - reg: I2C slave address | |
| - regulators: A node that houses a sub-node for each regulator within the | |
| device. Each sub-node is identified using the regulator-compatible | |
| property, with valid values listed below. | |
| Example: | |
| pmic: 88pm860x@34 { | |
| compatible = "marvell,88pm860x"; | |
| reg = <0x34>; | |
| regulators { | |
| BUCK1 { | |
| regulator-min-microvolt = <1000000>; | |
| regulator-max-microvolt = <1500000>; | |
| regulator-boot-on; | |
| regulator-always-on; | |
| }; | |
| BUCK3 { | |
| regulator-min-microvolt = <1000000>; | |
| regulator-max-microvolt = <3000000>; | |
| regulator-boot-on; | |
| regulator-always-on; | |
| }; | |
| }; | |
| }; |
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| GPIO controllers on MPC8xxx SoCs | |
| This is for the non-QE/CPM/GUTs GPIO controllers as found on | |
| 8349, 8572, 8610 and compatible. | |
| Every GPIO controller node must have #gpio-cells property defined, | |
| this information will be used to translate gpio-specifiers. | |
| See bindings/gpio/gpio.txt for details of how to specify GPIO | |
| information for devices. | |
| The GPIO module usually is connected to the SoC's internal interrupt | |
| controller, see bindings/interrupt-controller/interrupts.txt (the | |
| interrupt client nodes section) for details how to specify this GPIO | |
| module's interrupt. | |
| The GPIO module may serve as another interrupt controller (cascaded to | |
| the SoC's internal interrupt controller). See the interrupt controller | |
| nodes section in bindings/interrupt-controller/interrupts.txt for | |
| details. | |
| Required properties: | |
| - compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio" | |
| for 83xx, "fsl,mpc8572-gpio" for 85xx, or | |
| "fsl,mpc8610-gpio" for 86xx. | |
| - #gpio-cells: Should be two. The first cell is the pin number | |
| and the second cell is used to specify optional | |
| parameters (currently unused). | |
| - interrupts: Interrupt mapping for GPIO IRQ. | |
| - gpio-controller: Marks the port as GPIO controller. | |
| Optional properties: | |
| - interrupt-controller: Empty boolean property which marks the GPIO | |
| module as an IRQ controller. | |
| - #interrupt-cells: Should be two. Defines the number of integer | |
| cells required to specify an interrupt within | |
| this interrupt controller. The first cell | |
| defines the pin number, the second cell | |
| defines additional flags (trigger type, | |
| trigger polarity). Note that the available | |
| set of trigger conditions supported by the | |
| GPIO module depends on the actual SoC. | |
| Example of gpio-controller nodes for a MPC8347 SoC: | |
| gpio1: gpio-controller@c00 { | |
| #gpio-cells = <2>; | |
| compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; | |
| reg = <0xc00 0x100>; | |
| interrupt-parent = <&ipic>; | |
| interrupts = <74 0x8>; | |
| gpio-controller; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| }; | |
| gpio2: gpio-controller@d00 { | |
| #gpio-cells = <2>; | |
| compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; | |
| reg = <0xd00 0x100>; | |
| interrupt-parent = <&ipic>; | |
| interrupts = <75 0x8>; | |
| gpio-controller; | |
| }; | |
| Example of a peripheral using the GPIO module as an IRQ controller: | |
| funkyfpga@0 { | |
| compatible = "funky-fpga"; | |
| ... | |
| interrupt-parent = <&gpio1>; | |
| interrupts = <4 3>; | |
| }; |
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| Resume Control | |
| -------------- | |
| Available on Marvell SOCs: 98DX3336 and 98DX4251 | |
| Required properties: | |
| - compatible: must be "marvell,98dx3336-resume-ctrl" | |
| - reg: Should contain resume control registers location and length | |
| Example: | |
| resume@20980 { | |
| compatible = "marvell,98dx3336-resume-ctrl"; | |
| reg = <0x20980 0x10>; | |
| }; |
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| Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings | |
| ---------------------------------------------------------------------- | |
| Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families | |
| shall have the following property: | |
| Required root node property: | |
| compatible: must contain "marvell,armadaxp-98dx3236" | |
| In addition, boards using the Marvell 98DX3336 SoC shall have the | |
| following property: | |
| Required root node property: | |
| compatible: must contain "marvell,armadaxp-98dx3336" | |
| In addition, boards using the Marvell 98DX4251 SoC shall have the | |
| following property: | |
| Required root node property: | |
| compatible: must contain "marvell,armadaxp-98dx4251" |
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| Aardvark PCIe controller | |
| This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC. | |
| The Device Tree node describing an Aardvark PCIe controller must | |
| contain the following properties: | |
| - compatible: Should be "marvell,armada-3700-pcie" | |
| - reg: range of registers for the PCIe controller | |
| - interrupts: the interrupt line of the PCIe controller | |
| - #address-cells: set to <3> | |
| - #size-cells: set to <2> | |
| - device_type: set to "pci" | |
| - ranges: ranges for the PCI memory and I/O regions | |
| - #interrupt-cells: set to <1> | |
| - msi-controller: indicates that the PCIe controller can itself | |
| handle MSI interrupts | |
| - msi-parent: pointer to the MSI controller to be used | |
| - interrupt-map-mask and interrupt-map: standard PCI properties to | |
| define the mapping of the PCIe interface to interrupt numbers. | |
| - bus-range: PCI bus numbers covered | |
| - phys: the PCIe PHY handle | |
| - max-link-speed: see pci.txt | |
| - reset-gpios: see pci.txt | |
| In addition, the Device Tree describing an Aardvark PCIe controller | |
| must include a sub-node that describes the legacy interrupt controller | |
| built into the PCIe controller. This sub-node must have the following | |
| properties: | |
| - interrupt-controller | |
| - #interrupt-cells: set to <1> | |
| Example: | |
| pcie0: pcie@d0070000 { | |
| compatible = "marvell,armada-3700-pcie"; | |
| device_type = "pci"; | |
| reg = <0 0xd0070000 0 0x20000>; | |
| #address-cells = <3>; | |
| #size-cells = <2>; | |
| bus-range = <0x00 0xff>; | |
| interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
| #interrupt-cells = <1>; | |
| msi-controller; | |
| msi-parent = <&pcie0>; | |
| ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ | |
| 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ | |
| interrupt-map-mask = <0 0 0 7>; | |
| interrupt-map = <0 0 0 1 &pcie_intc 0>, | |
| <0 0 0 2 &pcie_intc 1>, | |
| <0 0 0 3 &pcie_intc 2>, | |
| <0 0 0 4 &pcie_intc 3>; | |
| phys = <&comphy1 0>; | |
| pcie_intc: interrupt-controller { | |
| interrupt-controller; | |
| #interrupt-cells = <1>; | |
| }; | |
| }; |
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| * AB8500 Multi-Functional Device (MFD) | |
| Required parent device properties: | |
| - compatible : contains "stericsson,ab8500" or "stericsson,ab8505"; | |
| - interrupts : contains the IRQ line for the AB8500 | |
| - interrupt-controller : describes the AB8500 as an Interrupt Controller (has its own domain) | |
| - #interrupt-cells : should be 2, for 2-cell format | |
| - The first cell is the AB8500 local IRQ number | |
| - The second cell is used to specify optional parameters | |
| - bits[3:0] trigger type and level flags: | |
| 1 = low-to-high edge triggered | |
| 2 = high-to-low edge triggered | |
| 4 = active high level-sensitive | |
| 8 = active low level-sensitive | |
| The AB8500 consists of a large and varied group of sub-devices: | |
| Device IRQ Names Supply Names Description | |
| ------ --------- ------------ ----------- | |
| ab8500-bm : : : Battery Manager | |
| ab8500-btemp : : : Battery Temperature | |
| ab8500-charger : : : Battery Charger | |
| ab8500-codec : : : Audio Codec | |
| ab8500-fg : : vddadc : Fuel Gauge | |
| : NCONV_ACCU : : Accumulate N Sample Conversion | |
| : BATT_OVV : : Battery Over Voltage | |
| : LOW_BAT_F : : LOW threshold battery voltage | |
| : CC_INT_CALIB : : Coulomb Counter Internal Calibration | |
| : CCEOC : : Coulomb Counter End of Conversion | |
| ab8500-btemp : : vtvout : Battery Temperature | |
| : BAT_CTRL_INDB : : Battery Removal Indicator | |
| : BTEMP_LOW : : Btemp < BtempLow, if battery temperature is lower than -10°C | |
| : BTEMP_LOW_MEDIUM : : BtempLow < Btemp < BtempMedium,if battery temperature is between -10 and 0°C | |
| : BTEMP_MEDIUM_HIGH : : BtempMedium < Btemp < BtempHigh,if battery temperature is between 0°C and MaxTemp | |
| : BTEMP_HIGH : : Btemp > BtempHigh, if battery temperature is higher than MaxTemp | |
| ab8500-charger : : vddadc : Charger interface | |
| : MAIN_CH_UNPLUG_DET : : main charger unplug detection management (not in 8505) | |
| : MAIN_CHARGE_PLUG_DET : : main charger plug detection management (not in 8505) | |
| : MAIN_EXT_CH_NOT_OK : : main charger not OK | |
| : MAIN_CH_TH_PROT_R : : Die temp is above main charger | |
| : MAIN_CH_TH_PROT_F : : Die temp is below main charger | |
| : VBUS_DET_F : : VBUS falling detected | |
| : VBUS_DET_R : : VBUS rising detected | |
| : USB_LINK_STATUS : : USB link status has changed | |
| : USB_CH_TH_PROT_R : : Die temp is above usb charger | |
| : USB_CH_TH_PROT_F : : Die temp is below usb charger | |
| : USB_CHARGER_NOT_OKR : : allowed USB charger not ok detection | |
| : VBUS_OVV : : Overvoltage on Vbus ball detected (USB charge is stopped) | |
| : CH_WD_EXP : : Charger watchdog detected | |
| ab8500-gpadc : HW_CONV_END : vddadc : Analogue to Digital Converter | |
| SW_CONV_END : : | |
| ab8500-gpio : : : GPIO Controller (AB8500) | |
| ab8505-gpio : : : GPIO Controller (AB8505) | |
| ab8500-ponkey : ONKEY_DBF : : Power-on Key | |
| ONKEY_DBR : : | |
| ab8500-pwm : : : Pulse Width Modulator | |
| ab8500-regulator : : : Regulators (AB8500) | |
| ab8505-regulator : : : Regulators (AB8505) | |
| ab8500-rtc : 60S : : Real Time Clock | |
| : ALARM : : | |
| ab8500-sysctrl : : : System Control | |
| ab8500-usb : ID_WAKEUP_R : vddulpivio18 : Universal Serial Bus | |
| : ID_WAKEUP_F : v-ape : | |
| : VBUS_DET_F : musb_1v8 : | |
| : VBUS_DET_R : : | |
| : USB_LINK_STATUS : : | |
| : USB_ADP_PROBE_PLUG : : | |
| : USB_ADP_PROBE_UNPLUG : : | |
| Required child device properties: | |
| - compatible : "stericsson,ab8500-[bm|btemp|charger|fg|gpadc|gpio|ponkey| | |
| pwm|regulator|rtc|sysctrl|usb]"; | |
| A few child devices require ADC channels from the GPADC node. Those follow the | |
| standard bindings from | |
| https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml | |
| and Documentation/devicetree/bindings/iio/adc/adc.yaml | |
| abx500-temp : io-channels "aux1" and "aux2" for measuring external | |
| temperatures. | |
| ab8500-fg : io-channel "main_bat_v" for measuring main battery voltage, | |
| ab8500-btemp : io-channels "btemp_ball" and "bat_ctrl" for measuring the | |
| battery voltage. | |
| ab8500-charger : io-channels "main_charger_v", "main_charger_c", "vbus_v", | |
| "usb_charger_c" for measuring voltage and current of the | |
| different charging supplies. | |
| Optional child device properties: | |
| - interrupts : contains the device IRQ(s) using the 2-cell format (see above) | |
| - interrupt-names : contains names of IRQ resource in the order in which they were | |
| supplied in the interrupts property | |
| - <supply_name>-supply : contains a phandle to the regulator supply node in Device Tree | |
| Non-standard child device properties: | |
| - Audio CODEC: | |
| - stericsson,amic[1|2]-type-single-ended : Single-ended Analoge Mic (default: differential) | |
| - stericsson,amic1a-bias-vamic2 : Analoge Mic wishes to use a non-standard Vamic | |
| - stericsson,amic1b-bias-vamic2 : Analoge Mic wishes to use a non-standard Vamic | |
| - stericsson,amic2-bias-vamic1 : Analoge Mic wishes to use a non-standard Vamic | |
| - stericsson,earpeice-cmv : Earpeice voltage (only: 950 | 1100 | 1270 | 1580) | |
| ab8500 { | |
| compatible = "stericsson,ab8500"; | |
| interrupts = <0 40 0x4>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| ab8500-rtc { | |
| compatible = "stericsson,ab8500-rtc"; | |
| interrupts = <17 0x4 | |
| 18 0x4>; | |
| interrupt-names = "60S", "ALARM"; | |
| }; | |
| ab8500-gpadc { | |
| compatible = "stericsson,ab8500-gpadc"; | |
| interrupts = <32 0x4 | |
| 39 0x4>; | |
| interrupt-names = "HW_CONV_END", "SW_CONV_END"; | |
| vddadc-supply = <&ab8500_ldo_tvout_reg>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| #io-channel-cells = <1>; | |
| /* GPADC channels */ | |
| bat_ctrl: channel@1 { | |
| reg = <0x01>; | |
| }; | |
| btemp_ball: channel@2 { | |
| reg = <0x02>; | |
| }; | |
| main_charger_v: channel@3 { | |
| reg = <0x03>; | |
| }; | |
| acc_detect1: channel@4 { | |
| reg = <0x04>; | |
| }; | |
| acc_detect2: channel@5 { | |
| reg = <0x05>; | |
| }; | |
| adc_aux1: channel@6 { | |
| reg = <0x06>; | |
| }; | |
| adc_aux2: channel@7 { | |
| reg = <0x07>; | |
| }; | |
| main_batt_v: channel@8 { | |
| reg = <0x08>; | |
| }; | |
| vbus_v: channel@9 { | |
| reg = <0x09>; | |
| }; | |
| main_charger_c: channel@a { | |
| reg = <0x0a>; | |
| }; | |
| usb_charger_c: channel@b { | |
| reg = <0x0b>; | |
| }; | |
| bk_bat_v: channel@c { | |
| reg = <0x0c>; | |
| }; | |
| die_temp: channel@d { | |
| reg = <0x0d>; | |
| }; | |
| usb_id: channel@e { | |
| reg = <0x0e>; | |
| }; | |
| xtal_temp: channel@12 { | |
| reg = <0x12>; | |
| }; | |
| vbat_true_meas: channel@13 { | |
| reg = <0x13>; | |
| }; | |
| bat_ctrl_and_ibat: channel@1c { | |
| reg = <0x1c>; | |
| }; | |
| vbat_meas_and_ibat: channel@1d { | |
| reg = <0x1d>; | |
| }; | |
| vbat_true_meas_and_ibat: channel@1e { | |
| reg = <0x1e>; | |
| }; | |
| bat_temp_and_ibat: channel@1f { | |
| reg = <0x1f>; | |
| }; | |
| }; | |
| ab8500_temp { | |
| compatible = "stericsson,abx500-temp"; | |
| io-channels = <&gpadc 0x06>, | |
| <&gpadc 0x07>; | |
| io-channel-name = "aux1", "aux2"; | |
| }; | |
| ab8500_battery: ab8500_battery { | |
| stericsson,battery-type = "LIPO"; | |
| thermistor-on-batctrl; | |
| }; | |
| ab8500_fg { | |
| compatible = "stericsson,ab8500-fg"; | |
| battery = <&ab8500_battery>; | |
| io-channels = <&gpadc 0x08>; | |
| io-channel-name = "main_bat_v"; | |
| }; | |
| ab8500_btemp { | |
| compatible = "stericsson,ab8500-btemp"; | |
| battery = <&ab8500_battery>; | |
| io-channels = <&gpadc 0x02>, | |
| <&gpadc 0x01>; | |
| io-channel-name = "btemp_ball", | |
| "bat_ctrl"; | |
| }; | |
| ab8500_charger { | |
| compatible = "stericsson,ab8500-charger"; | |
| battery = <&ab8500_battery>; | |
| vddadc-supply = <&ab8500_ldo_tvout_reg>; | |
| io-channels = <&gpadc 0x03>, | |
| <&gpadc 0x0a>, | |
| <&gpadc 0x09>, | |
| <&gpadc 0x0b>; | |
| io-channel-name = "main_charger_v", | |
| "main_charger_c", | |
| "vbus_v", | |
| "usb_charger_c"; | |
| }; | |
| ab8500-usb { | |
| compatible = "stericsson,ab8500-usb"; | |
| interrupts = < 90 0x4 | |
| 96 0x4 | |
| 14 0x4 | |
| 15 0x4 | |
| 79 0x4 | |
| 74 0x4 | |
| 75 0x4>; | |
| interrupt-names = "ID_WAKEUP_R", | |
| "ID_WAKEUP_F", | |
| "VBUS_DET_F", | |
| "VBUS_DET_R", | |
| "USB_LINK_STATUS", | |
| "USB_ADP_PROBE_PLUG", | |
| "USB_ADP_PROBE_UNPLUG"; | |
| vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; | |
| v-ape-supply = <&db8500_vape_reg>; | |
| musb_1v8-supply = <&db8500_vsmps2_reg>; | |
| }; | |
| ab8500-ponkey { | |
| compatible = "stericsson,ab8500-ponkey"; | |
| interrupts = <6 0x4 | |
| 7 0x4>; | |
| interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; | |
| }; | |
| ab8500-sysctrl { | |
| compatible = "stericsson,ab8500-sysctrl"; | |
| }; | |
| ab8500-pwm { | |
| compatible = "stericsson,ab8500-pwm"; | |
| }; | |
| codec: ab8500-codec { | |
| compatible = "stericsson,ab8500-codec"; | |
| stericsson,earpeice-cmv = <950>; /* Units in mV. */ | |
| }; | |
| ab8500-regulators { | |
| compatible = "stericsson,ab8500-regulator"; | |
| ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { | |
| /* | |
| * See: Documentation/devicetree/bindings/regulator/regulator.txt | |
| * for more information on regulators | |
| */ | |
| }; | |
| }; | |
| }; |
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| * Abilis TB10x GPIO controller | |
| Required Properties: | |
| - compatible: Should be "abilis,tb10x-gpio" | |
| - reg: Address and length of the register set for the device | |
| - gpio-controller: Marks the device node as a gpio controller. | |
| - #gpio-cells: Should be <2>. The first cell is the pin number and the | |
| second cell is used to specify optional parameters: | |
| - bit 0 specifies polarity (0 for normal, 1 for inverted). | |
| - abilis,ngpio: the number of GPIO pins this driver controls. | |
| Optional Properties: | |
| - interrupt-controller: Marks the device node as an interrupt controller. | |
| - #interrupt-cells: Should be <1>. Interrupts are triggered on both edges. | |
| - interrupts: Defines the interrupt line connecting this GPIO controller to | |
| its parent interrupt controller. | |
| GPIO ranges are specified as described in | |
| Documentation/devicetree/bindings/gpio/gpio.txt | |
| Example: | |
| gpioa: gpio@ff140000 { | |
| compatible = "abilis,tb10x-gpio"; | |
| interrupt-controller; | |
| #interrupt-cells = <1>; | |
| interrupt-parent = <&tb10x_ictl>; | |
| interrupts = <27 2>; | |
| reg = <0xFF140000 0x1000>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| abilis,ngpio = <3>; | |
| gpio-ranges = <&iomux 0 0 0>; | |
| gpio-ranges-group-names = "gpioa_pins"; | |
| }; |
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| TB10x Top Level Interrupt Controller | |
| ==================================== | |
| The Abilis TB10x SOC contains a custom interrupt controller. It performs | |
| one-to-one mapping of external interrupt sources to CPU interrupts and | |
| provides support for reconfigurable trigger modes. | |
| Required properties | |
| ------------------- | |
| - compatible: Should be "abilis,tb10x-ictl" | |
| - reg: specifies physical base address and size of register range. | |
| - interrupt-congroller: Identifies the node as an interrupt controller. | |
| - #interrupt cells: Specifies the number of cells used to encode an interrupt | |
| source connected to this controller. The value shall be 2. | |
| - interrupts: Specifies the list of interrupt lines which are handled by | |
| the interrupt controller in the parent controller's notation. Interrupts | |
| are mapped one-to-one to parent interrupts. | |
| Example | |
| ------- | |
| intc: interrupt-controller { /* Parent interrupt controller */ | |
| interrupt-controller; | |
| #interrupt-cells = <1>; /* For example below */ | |
| /* ... */ | |
| }; | |
| tb10x_ictl: pic@2000 { /* TB10x interrupt controller */ | |
| compatible = "abilis,tb10x-ictl"; | |
| reg = <0x2000 0x20>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| interrupt-parent = <&intc>; | |
| interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 | |
| 20 21 22 23 24 25 26 27 28 29 30 31>; | |
| }; |
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| Abilis Systems TB10x pin controller | |
| =================================== | |
| Required properties | |
| ------------------- | |
| - compatible: should be "abilis,tb10x-iomux"; | |
| - reg: should contain the physical address and size of the pin controller's | |
| register range. | |
| Function definitions | |
| -------------------- | |
| Functions are defined (and referenced) by sub-nodes of the pin controller. | |
| Every sub-node defines exactly one function (implying a set of pins). | |
| Every function is associated to one named pin group inside the pin controller | |
| driver and these names are used to associate pin group predefinitions to pin | |
| controller sub-nodes. | |
| Required function definition subnode properties: | |
| - abilis,function: should be set to the name of the function's pin group. | |
| The following pin groups are available: | |
| - GPIO ports: gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog, | |
| gpioh, gpioi, gpioj, gpiok, gpiol, gpiom, gpion | |
| - Serial TS input ports: mis0, mis1, mis2, mis3, mis4, mis5, mis6, mis7 | |
| - Parallel TS input ports: mip1, mip3, mip5, mip7 | |
| - Serial TS output ports: mos0, mos1, mos2, mos3 | |
| - Parallel TS output port: mop | |
| - CI+ port: ciplus | |
| - CableCard (Mcard) port: mcard | |
| - Smart card ports: stc0, stc1 | |
| - UART ports: uart0, uart1 | |
| - SPI ports: spi1, spi3 | |
| - JTAG: jtag | |
| All other ports of the chip are not multiplexed and thus not managed by this | |
| driver. | |
| GPIO ranges definition | |
| ---------------------- | |
| The named pin groups of GPIO ports can be used to define GPIO ranges as | |
| explained in Documentation/devicetree/bindings/gpio/gpio.txt. | |
| Example | |
| ------- | |
| iomux: iomux@ff10601c { | |
| compatible = "abilis,tb10x-iomux"; | |
| reg = <0xFF10601c 0x4>; | |
| pctl_gpio_a: pctl-gpio-a { | |
| abilis,function = "gpioa"; | |
| }; | |
| pctl_uart0: pctl-uart0 { | |
| abilis,function = "uart0"; | |
| }; | |
| }; | |
| uart@ff100000 { | |
| compatible = "snps,dw-apb-uart"; | |
| reg = <0xFF100000 0x100>; | |
| clock-frequency = <166666666>; | |
| interrupts = <25 1>; | |
| reg-shift = <2>; | |
| reg-io-width = <4>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pctl_uart0>; | |
| }; | |
| gpioa: gpio@ff140000 { | |
| compatible = "abilis,tb10x-gpio"; | |
| reg = <0xFF140000 0x1000>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| ngpio = <3>; | |
| gpio-ranges = <&iomux 0 0>; | |
| gpio-ranges-group-names = "gpioa"; | |
| }; |
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| Abracon ABX80X I2C ultra low power RTC/Alarm chip | |
| The Abracon ABX80X family consist of the ab0801, ab0803, ab0804, ab0805, ab1801, | |
| ab1803, ab1804 and ab1805. The ab0805 is the superset of ab080x and the ab1805 | |
| is the superset of ab180x. | |
| Required properties: | |
| - "compatible": should one of: | |
| "abracon,abx80x" | |
| "abracon,ab0801" | |
| "abracon,ab0803" | |
| "abracon,ab0804" | |
| "abracon,ab0805" | |
| "abracon,ab1801" | |
| "abracon,ab1803" | |
| "abracon,ab1804" | |
| "abracon,ab1805" | |
| "microcrystal,rv1805" | |
| Using "abracon,abx80x" will enable chip autodetection. | |
| - "reg": I2C bus address of the device | |
| Optional properties: | |
| The abx804 and abx805 have a trickle charger that is able to charge the | |
| connected battery or supercap. Both the following properties have to be defined | |
| and valid to enable charging: | |
| - "abracon,tc-diode": should be "standard" (0.6V) or "schottky" (0.3V) | |
| - "abracon,tc-resistor": should be <0>, <3>, <6> or <11>. 0 disables the output | |
| resistor, the other values are in kOhm. |
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| Generic AC97 Device Properties | |
| This documents describes the devicetree bindings for an ac97 controller child | |
| node describing ac97 codecs. | |
| Required properties: | |
| -compatible : Must be "ac97,vendor_id1,vendor_id2 | |
| The ids shall be the 4 characters hexadecimal encoding, such as | |
| given by "%04x" formatting of printf | |
| -reg : Must be the ac97 codec number, between 0 and 3 | |
| Example: | |
| ac97: sound@40500000 { | |
| compatible = "marvell,pxa270-ac97"; | |
| reg = < 0x40500000 0x1000 >; | |
| interrupts = <14>; | |
| reset-gpios = <&gpio 95 GPIO_ACTIVE_HIGH>; | |
| #sound-dai-cells = <1>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = < &pinctrl_ac97_default >; | |
| clocks = <&clks CLK_AC97>, <&clks CLK_AC97CONF>; | |
| clock-names = "AC97CLK", "AC97CONFCLK"; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| audio-codec@0 { | |
| reg = <0>; | |
| compatible = "ac97,574d,4c13"; | |
| clocks = <&fixed_wm9713_clock>; | |
| clock-names = "ac97_clk"; | |
| } | |
| }; |
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| ACT88xx regulators | |
| ------------------- | |
| Required properties: | |
| - compatible: "active-semi,act8846" or "active-semi,act8865" or "active-semi,act8600" | |
| - reg: I2C slave address | |
| Optional properties: | |
| - system-power-controller: Telling whether or not this pmic is controlling | |
| the system power. See Documentation/devicetree/bindings/power/power-controller.txt . | |
| - active-semi,vsel-high: Indicates the VSEL pin is high. | |
| If this property is missing, assume the VSEL pin is low(0). | |
| Optional input supply properties: | |
| - for act8600: | |
| - vp1-supply: The input supply for DCDC_REG1 | |
| - vp2-supply: The input supply for DCDC_REG2 | |
| - vp3-supply: The input supply for DCDC_REG3 | |
| - inl-supply: The input supply for LDO_REG5, LDO_REG6, LDO_REG7 and LDO_REG8 | |
| SUDCDC_REG4, LDO_REG9 and LDO_REG10 do not have separate supplies. | |
| - for act8846: | |
| - vp1-supply: The input supply for REG1 | |
| - vp2-supply: The input supply for REG2 | |
| - vp3-supply: The input supply for REG3 | |
| - vp4-supply: The input supply for REG4 | |
| - inl1-supply: The input supply for REG5, REG6 and REG7 | |
| - inl2-supply: The input supply for REG8 and LDO_REG9 | |
| - inl3-supply: The input supply for REG10, REG11 and REG12 | |
| - for act8865: | |
| - vp1-supply: The input supply for DCDC_REG1 | |
| - vp2-supply: The input supply for DCDC_REG2 | |
| - vp3-supply: The input supply for DCDC_REG3 | |
| - inl45-supply: The input supply for LDO_REG1 and LDO_REG2 | |
| - inl67-supply: The input supply for LDO_REG3 and LDO_REG4 | |
| Any standard regulator properties can be used to configure the single regulator. | |
| regulator-initial-mode, regulator-allowed-modes and regulator-mode could be specified | |
| for act8865 using mode values from dt-bindings/regulator/active-semi,8865-regulator.h | |
| file. | |
| The valid names for regulators are: | |
| - for act8846: | |
| REG1, REG2, REG3, REG4, REG5, REG6, REG7, REG8, REG9, REG10, REG11, REG12 | |
| - for act8865: | |
| DCDC_REG1, DCDC_REG2, DCDC_REG3, LDO_REG1, LDO_REG2, LDO_REG3, LDO_REG4. | |
| - for act8600: | |
| DCDC_REG1, DCDC_REG2, DCDC_REG3, SUDCDC_REG4, LDO_REG5, LDO_REG6, LDO_REG7, | |
| LDO_REG8, LDO_REG9, LDO_REG10, | |
| Example: | |
| -------- | |
| #include <dt-bindings/regulator/active-semi,8865-regulator.h> | |
| i2c1: i2c@f0018000 { | |
| pmic: act8865@5b { | |
| compatible = "active-semi,act8865"; | |
| reg = <0x5b>; | |
| active-semi,vsel-high; | |
| regulators { | |
| vcc_1v8_reg: DCDC_REG1 { | |
| regulator-name = "VCC_1V8"; | |
| regulator-min-microvolt = <1800000>; | |
| regulator-max-microvolt = <1800000>; | |
| regulator-always-on; | |
| }; | |
| vcc_1v2_reg: DCDC_REG2 { | |
| regulator-name = "VCC_1V2"; | |
| regulator-min-microvolt = <1100000>; | |
| regulator-max-microvolt = <1300000>; | |
| regulator-always-on; | |
| regulator-allowed-modes = <ACT8865_REGULATOR_MODE_FIXED>, | |
| <ACT8865_REGULATOR_MODE_LOWPOWER>; | |
| regulator-initial-mode = <ACT8865_REGULATOR_MODE_FIXED>; | |
| regulator-state-mem { | |
| regulator-on-in-suspend; | |
| regulator-suspend-min-microvolt = <1150000>; | |
| regulator-suspend-max-microvolt = <1150000>; | |
| regulator-changeable-in-suspend; | |
| regulator-mode = <ACT8865_REGULATOR_MODE_LOWPOWER>; | |
| }; | |
| }; | |
| vcc_3v3_reg: DCDC_REG3 { | |
| regulator-name = "VCC_3V3"; | |
| regulator-min-microvolt = <3300000>; | |
| regulator-max-microvolt = <3300000>; | |
| regulator-always-on; | |
| }; | |
| vddana_reg: LDO_REG1 { | |
| regulator-name = "VDDANA"; | |
| regulator-min-microvolt = <3300000>; | |
| regulator-max-microvolt = <3300000>; | |
| regulator-always-on; | |
| regulator-allowed-modes = <ACT8865_REGULATOR_MODE_NORMAL>, | |
| <ACT8865_REGULATOR_MODE_LOWPOWER>; | |
| regulator-initial-mode = <ACT8865_REGULATOR_MODE_NORMAL>; | |
| regulator-state-mem { | |
| regulator-off-in-suspend; | |
| }; | |
| }; | |
| vddfuse_reg: LDO_REG2 { | |
| regulator-name = "FUSE_2V5"; | |
| regulator-min-microvolt = <2500000>; | |
| regulator-max-microvolt = <2500000>; | |
| }; | |
| }; | |
| }; | |
| }; |
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| Device-Tree bindings for regulators of Active-semi ACT8945A Multi-Function Device | |
| Required properties: | |
| - compatible: "active-semi,act8945a", please refer to ../mfd/act8945a.txt. | |
| Optional properties: | |
| - active-semi,vsel-high: Indicates if the VSEL pin is set to logic-high. | |
| If this property is missing, assume the VSEL pin is set to logic-low. | |
| Optional input supply properties: | |
| - vp1-supply: The input supply for REG_DCDC1 | |
| - vp2-supply: The input supply for REG_DCDC2 | |
| - vp3-supply: The input supply for REG_DCDC3 | |
| - inl45-supply: The input supply for REG_LDO1 and REG_LDO2 | |
| - inl67-supply: The input supply for REG_LDO3 and REG_LDO4 | |
| Any standard regulator properties can be used to configure the single regulator. | |
| regulator-initial-mode, regulator-allowed-modes and regulator-mode could be | |
| specified using mode values from dt-bindings/regulator/active-semi,8945a-regulator.h | |
| file. | |
| The valid names for regulators are: | |
| REG_DCDC1, REG_DCDC2, REG_DCDC3, REG_LDO1, REG_LDO2, REG_LDO3, REG_LDO4. | |
| Example: | |
| #include <dt-bindings/regulator/active-semi,8945a-regulator.h> | |
| pmic@5b { | |
| compatible = "active-semi,act8945a"; | |
| reg = <0x5b>; | |
| active-semi,vsel-high; | |
| regulators { | |
| vdd_1v35_reg: REG_DCDC1 { | |
| regulator-name = "VDD_1V35"; | |
| regulator-min-microvolt = <1350000>; | |
| regulator-max-microvolt = <1350000>; | |
| regulator-always-on; | |
| regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>, | |
| <ACT8945A_REGULATOR_MODE_LOWPOWER>; | |
| regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>; | |
| regulator-state-mem { | |
| regulator-on-in-suspend; | |
| regulator-suspend-min-microvolt=<1400000>; | |
| regulator-suspend-max-microvolt=<1400000>; | |
| regulator-changeable-in-suspend; | |
| regulator-mode=<ACT8945A_REGULATOR_MODE_LOWPOWER>; | |
| }; | |
| }; | |
| vdd_1v2_reg: REG_DCDC2 { | |
| regulator-name = "VDD_1V2"; | |
| regulator-min-microvolt = <1100000>; | |
| regulator-max-microvolt = <1300000>; | |
| regulator-always-on; | |
| regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_FIXED>, | |
| <ACT8945A_REGULATOR_MODE_LOWPOWER>; | |
| regulator-initial-mode = <ACT8945A_REGULATOR_MODE_FIXED>; | |
| regulator-state-mem { | |
| regulator-off-in-suspend; | |
| }; | |
| }; | |
| vdd_3v3_reg: REG_DCDC3 { | |
| regulator-name = "VDD_3V3"; | |
| regulator-min-microvolt = <3300000>; | |
| regulator-max-microvolt = <3300000>; | |
| regulator-always-on; | |
| }; | |
| vdd_fuse_reg: REG_LDO1 { | |
| regulator-name = "VDD_FUSE"; | |
| regulator-min-microvolt = <2500000>; | |
| regulator-max-microvolt = <2500000>; | |
| regulator-always-on; | |
| regulator-allowed-modes = <ACT8945A_REGULATOR_MODE_NORMAL>, | |
| <ACT8945A_REGULATOR_MODE_LOWPOWER>; | |
| regulator-initial-mode = <ACT8945A_REGULATOR_MODE_NORMAL>; | |
| regulator-state-mem { | |
| regulator-off-in-suspend; | |
| }; | |
| }; | |
| vdd_3v3_lp_reg: REG_LDO2 { | |
| regulator-name = "VDD_3V3_LP"; | |
| regulator-min-microvolt = <3300000>; | |
| regulator-max-microvolt = <3300000>; | |
| regulator-always-on; | |
| }; | |
| vdd_led_reg: REG_LDO3 { | |
| regulator-name = "VDD_LED"; | |
| regulator-min-microvolt = <3300000>; | |
| regulator-max-microvolt = <3300000>; | |
| regulator-always-on; | |
| }; | |
| vdd_sdhc_1v8_reg: REG_LDO4 { | |
| regulator-name = "VDD_SDHC_1V8"; | |
| regulator-min-microvolt = <1800000>; | |
| regulator-max-microvolt = <1800000>; | |
| regulator-always-on; | |
| }; | |
| }; | |
| }; |
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| Device-Tree bindings for Active-semi ACT8945A MFD driver | |
| Required properties: | |
| - compatible: "active-semi,act8945a". | |
| - reg: the I2C slave address for the ACT8945A chip | |
| The chip exposes two subdevices: | |
| - a regulators: see ../regulator/act8945a-regulator.txt | |
| - a charger: see ../power/act8945a-charger.txt | |
| Example: | |
| pmic@5b { | |
| compatible = "active-semi,act8945a"; | |
| reg = <0x5b>; | |
| active-semi,vsel-high; | |
| regulators { | |
| vdd_1v35_reg: REG_DCDC1 { | |
| regulator-name = "VDD_1V35"; | |
| regulator-min-microvolt = <1350000>; | |
| regulator-max-microvolt = <1350000>; | |
| regulator-always-on; | |
| }; | |
| vdd_1v2_reg: REG_DCDC2 { | |
| regulator-name = "VDD_1V2"; | |
| regulator-min-microvolt = <1100000>; | |
| regulator-max-microvolt = <1300000>; | |
| regulator-always-on; | |
| }; | |
| vdd_3v3_reg: REG_DCDC3 { | |
| regulator-name = "VDD_3V3"; | |
| regulator-min-microvolt = <3300000>; | |
| regulator-max-microvolt = <3300000>; | |
| regulator-always-on; | |
| }; | |
| vdd_fuse_reg: REG_LDO1 { | |
| regulator-name = "VDD_FUSE"; | |
| regulator-min-microvolt = <2500000>; | |
| regulator-max-microvolt = <2500000>; | |
| regulator-always-on; | |
| }; | |
| vdd_3v3_lp_reg: REG_LDO2 { | |
| regulator-name = "VDD_3V3_LP"; | |
| regulator-min-microvolt = <3300000>; | |
| regulator-max-microvolt = <3300000>; | |
| regulator-always-on; | |
| }; | |
| vdd_led_reg: REG_LDO3 { | |
| regulator-name = "VDD_LED"; | |
| regulator-min-microvolt = <3300000>; | |
| regulator-max-microvolt = <3300000>; | |
| regulator-always-on; | |
| }; | |
| vdd_sdhc_1v8_reg: REG_LDO4 { | |
| regulator-name = "VDD_SDHC_1V8"; | |
| regulator-min-microvolt = <1800000>; | |
| regulator-max-microvolt = <1800000>; | |
| regulator-always-on; | |
| }; | |
| }; | |
| charger { | |
| compatible = "active-semi,act8945a-charger"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; | |
| interrupt-parent = <&pioA>; | |
| interrupts = <45 IRQ_TYPE_LEVEL_LOW>; | |
| active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>; | |
| active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>; | |
| active-semi,input-voltage-threshold-microvolt = <6600>; | |
| active-semi,precondition-timeout = <40>; | |
| active-semi,total-timeout = <3>; | |
| }; | |
| }; |
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| * Actions Semi Owl Clock Management Unit (CMU) | |
| The Actions Semi Owl Clock Management Unit generates and supplies clock | |
| to various controllers within the SoC. The clock binding described here is | |
| applicable to S900, S700 and S500 SoC's. | |
| Required Properties: | |
| - compatible: should be one of the following, | |
| "actions,s900-cmu" | |
| "actions,s700-cmu" | |
| "actions,s500-cmu" | |
| - reg: physical base address of the controller and length of memory mapped | |
| region. | |
| - clocks: Reference to the parent clocks ("hosc", "losc") | |
| - #clock-cells: should be 1. | |
| - #reset-cells: should be 1. | |
| Each clock is assigned an identifier, and client nodes can use this identifier | |
| to specify the clock which they consume. | |
| All available clocks are defined as preprocessor macros in corresponding | |
| dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or | |
| actions,s500-cmu.h header and can be used in device tree sources. | |
| External clocks: | |
| The hosc clock used as input for the plls is generated outside the SoC. It is | |
| expected that it is defined using standard clock bindings as "hosc". | |
| Actions Semi S900 CMU also requires one more clock: | |
| - "losc" - internal low frequency oscillator | |
| Example: Clock Management Unit node: | |
| cmu: clock-controller@e0160000 { | |
| compatible = "actions,s900-cmu"; | |
| reg = <0x0 0xe0160000 0x0 0x1000>; | |
| clocks = <&hosc>, <&losc>; | |
| #clock-cells = <1>; | |
| #reset-cells = <1>; | |
| }; | |
| Example: UART controller node that consumes clock generated by the clock | |
| management unit: | |
| uart: serial@e012a000 { | |
| compatible = "actions,s900-uart", "actions,owl-uart"; | |
| reg = <0x0 0xe012a000 0x0 0x2000>; | |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cmu CLK_UART5>; | |
| }; |
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| Actions Semi Owl Smart Power System (SPS) | |
| Required properties: | |
| - compatible : "actions,s500-sps" for S500 | |
| "actions,s700-sps" for S700 | |
| "actions,s900-sps" for S900 | |
| - reg : Offset and length of the register set for the device. | |
| - #power-domain-cells : Must be 1. | |
| See macros in: | |
| include/dt-bindings/power/owl-s500-powergate.h for S500 | |
| include/dt-bindings/power/owl-s700-powergate.h for S700 | |
| include/dt-bindings/power/owl-s900-powergate.h for S900 | |
| Example: | |
| sps: power-controller@b01b0100 { | |
| compatible = "actions,s500-sps"; | |
| reg = <0xb01b0100 0x100>; | |
| #power-domain-cells = <1>; | |
| }; |
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| Actions Semi Owl Timer | |
| Required properties: | |
| - compatible : "actions,s500-timer" for S500 | |
| "actions,s700-timer" for S700 | |
| "actions,s900-timer" for S900 | |
| - reg : Offset and length of the register set for the device. | |
| - interrupts : Should contain the interrupts. | |
| - interrupt-names : Valid names are: "2hz0", "2hz1", | |
| "timer0", "timer1", "timer2", "timer3" | |
| See ../resource-names.txt | |
| Example: | |
| timer@b0168000 { | |
| compatible = "actions,s500-timer"; | |
| reg = <0xb0168000 0x100>; | |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-names = "timer0", "timer1"; | |
| }; |
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| Actions Semi Owl UART | |
| Required properties: | |
| - compatible : "actions,s500-uart", "actions,owl-uart" for S500 | |
| "actions,s900-uart", "actions,owl-uart" for S900 | |
| - reg : Offset and length of the register set for the device. | |
| - interrupts : Should contain UART interrupt. | |
| Example: | |
| uart3: serial@b0126000 { | |
| compatible = "actions,s500-uart", "actions,owl-uart"; | |
| reg = <0xb0126000 0x1000>; | |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
| }; |
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| Actions Semi S700 Pin Controller | |
| This binding describes the pin controller found in the S700 SoC. | |
| Required Properties: | |
| - compatible: Should be "actions,s700-pinctrl" | |
| - reg: Should contain the register base address and size of | |
| the pin controller. | |
| - clocks: phandle of the clock feeding the pin controller | |
| - gpio-controller: Marks the device node as a GPIO controller. | |
| - gpio-ranges: Specifies the mapping between gpio controller and | |
| pin-controller pins. | |
| - #gpio-cells: Should be two. The first cell is the gpio pin number | |
| and the second cell is used for optional parameters. | |
| - interrupt-controller: Marks the device node as an interrupt controller. | |
| - #interrupt-cells: Specifies the number of cells needed to encode an | |
| interrupt. Shall be set to 2. The first cell | |
| defines the interrupt number, the second encodes | |
| the trigger flags described in | |
| bindings/interrupt-controller/interrupts.txt | |
| - interrupts: The interrupt outputs from the controller. There is one GPIO | |
| interrupt per GPIO bank. The number of interrupts listed depends | |
| on the number of GPIO banks on the SoC. The interrupts must be | |
| ordered by bank, starting with bank 0. | |
| Please refer to pinctrl-bindings.txt in this directory for details of the | |
| common pinctrl bindings used by client devices, including the meaning of the | |
| phrase "pin configuration node". | |
| The pin configuration nodes act as a container for an arbitrary number of | |
| subnodes. Each of these subnodes represents some desired configuration for a | |
| pin, a group, or a list of pins or groups. This configuration can include the | |
| mux function to select on those group(s), and various pin configuration | |
| parameters, such as pull-up, drive strength, etc. | |
| PIN CONFIGURATION NODES: | |
| The name of each subnode is not important; all subnodes should be enumerated | |
| and processed purely based on their content. | |
| Each subnode only affects those parameters that are explicitly listed. In | |
| other words, a subnode that lists a mux function but no pin configuration | |
| parameters implies no information about any pin configuration parameters. | |
| Similarly, a pin subnode that describes a pullup parameter implies no | |
| information about e.g. the mux function. | |
| Pinmux functions are available only for the pin groups while pinconf | |
| parameters are available for both pin groups and individual pins. | |
| The following generic properties as defined in pinctrl-bindings.txt are valid | |
| to specify in a pin configuration subnode: | |
| Required Properties: | |
| - pins: An array of strings, each string containing the name of a pin. | |
| These pins are used for selecting the pull control and schmitt | |
| trigger parameters. The following are the list of pins | |
| available: | |
| eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer, | |
| eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk, | |
| eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, | |
| i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, | |
| pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2, | |
| ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp, | |
| lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap, | |
| lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, | |
| lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, | |
| lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, | |
| dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, | |
| sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, | |
| sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx, | |
| uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, | |
| uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk, | |
| i2c1_sdata, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1, | |
| csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3, | |
| sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2, | |
| dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_wrb, | |
| dnand_rdb, dnand_rdbn, dnand_dqs, dnand_dqsn, dnand_rb0, | |
| dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, dnand_ceb2, | |
| dnand_ceb3, porb, clko_25m, bsel, pkg0, pkg1, pkg2, pkg3 | |
| - groups: An array of strings, each string containing the name of a pin | |
| group. These pin groups are used for selecting the pinmux | |
| functions. | |
| rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp, | |
| rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp, | |
| rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp, | |
| i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp, | |
| i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, | |
| ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp, | |
| dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp, | |
| lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, dsi_dnp1_cp_d2_mfp, | |
| dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp, | |
| uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, | |
| sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp, | |
| uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, uart0_tx_mfp, | |
| i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, pcm1_clk_mfp, | |
| pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, dnand_acle_ce0_mfp, | |
| nand_ceb2_mfp, nand_ceb3_mfp | |
| These pin groups are used for selecting the drive strength | |
| parameters. | |
| sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv, | |
| rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv, | |
| smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv, | |
| pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv, | |
| dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, spi0_all_drv, | |
| uart0_rx_drv, uart0_tx_drv, uart2_all_drv, i2c0_all_drv, i2c12_all_drv, | |
| sens0_pclk_drv, sens0_ckout_drv, uart3_all_drv | |
| - function: An array of strings, each string containing the name of the | |
| pinmux functions. These functions can only be selected by | |
| the corresponding pin groups. The following are the list of | |
| pinmux functions available: | |
| nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1, | |
| uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, | |
| pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0, | |
| sd0, sd1, sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30, | |
| clko_25m, mipi_csi, nand, spdif, sirq0, sirq1, sirq2, bt, lcd0 | |
| Optional Properties: | |
| - bias-pull-down: No arguments. The specified pins should be configured as | |
| pull down. | |
| - bias-pull-up: No arguments. The specified pins should be configured as | |
| pull up. | |
| - input-schmitt-enable: No arguments: Enable schmitt trigger for the specified | |
| pins | |
| - input-schmitt-disable: No arguments: Disable schmitt trigger for the specified | |
| pins | |
| - drive-strength: Integer. Selects the drive strength for the specified | |
| pins in mA. | |
| Valid values are: | |
| <2> | |
| <4> | |
| <8> | |
| <12> | |
| Example: | |
| pinctrl: pinctrl@e01b0000 { | |
| compatible = "actions,s700-pinctrl"; | |
| reg = <0x0 0xe01b0000 0x0 0x1000>; | |
| clocks = <&cmu CLK_GPIO>; | |
| gpio-controller; | |
| gpio-ranges = <&pinctrl 0 0 136>; | |
| #gpio-cells = <2>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
| uart3-default: uart3-default { | |
| pinmux { | |
| groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp"; | |
| function = "uart3"; | |
| }; | |
| pinconf { | |
| groups = "uart3_all_drv"; | |
| drive-strength = <2>; | |
| }; | |
| }; | |
| }; |
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| Actions Semi S900 Pin Controller | |
| This binding describes the pin controller found in the S900 SoC. | |
| Required Properties: | |
| - compatible: Should be "actions,s900-pinctrl" | |
| - reg: Should contain the register base address and size of | |
| the pin controller. | |
| - clocks: phandle of the clock feeding the pin controller | |
| - gpio-controller: Marks the device node as a GPIO controller. | |
| - gpio-ranges: Specifies the mapping between gpio controller and | |
| pin-controller pins. | |
| - #gpio-cells: Should be two. The first cell is the gpio pin number | |
| and the second cell is used for optional parameters. | |
| - interrupt-controller: Marks the device node as an interrupt controller. | |
| - #interrupt-cells: Specifies the number of cells needed to encode an | |
| interrupt. Shall be set to 2. The first cell | |
| defines the interrupt number, the second encodes | |
| the trigger flags described in | |
| bindings/interrupt-controller/interrupts.txt | |
| - interrupts: The interrupt outputs from the controller. There is one GPIO | |
| interrupt per GPIO bank. The number of interrupts listed depends | |
| on the number of GPIO banks on the SoC. The interrupts must be | |
| ordered by bank, starting with bank 0. | |
| Please refer to pinctrl-bindings.txt in this directory for details of the | |
| common pinctrl bindings used by client devices, including the meaning of the | |
| phrase "pin configuration node". | |
| The pin configuration nodes act as a container for an arbitrary number of | |
| subnodes. Each of these subnodes represents some desired configuration for a | |
| pin, a group, or a list of pins or groups. This configuration can include the | |
| mux function to select on those group(s), and various pin configuration | |
| parameters, such as pull-up, drive strength, etc. | |
| PIN CONFIGURATION NODES: | |
| The name of each subnode is not important; all subnodes should be enumerated | |
| and processed purely based on their content. | |
| Each subnode only affects those parameters that are explicitly listed. In | |
| other words, a subnode that lists a mux function but no pin configuration | |
| parameters implies no information about any pin configuration parameters. | |
| Similarly, a pin subnode that describes a pullup parameter implies no | |
| information about e.g. the mux function. | |
| Pinmux functions are available only for the pin groups while pinconf | |
| parameters are available for both pin groups and individual pins. | |
| The following generic properties as defined in pinctrl-bindings.txt are valid | |
| to specify in a pin configuration subnode: | |
| Required Properties: | |
| - pins: An array of strings, each string containing the name of a pin. | |
| These pins are used for selecting the pull control and schmitt | |
| trigger parameters. The following are the list of pins | |
| available: | |
| eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv, | |
| eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio, | |
| sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0, | |
| i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, | |
| pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5, | |
| eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11, | |
| lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, | |
| lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, | |
| lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, | |
| lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, | |
| sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1, | |
| sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk, | |
| spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, | |
| uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, | |
| uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx, | |
| uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata, | |
| i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1, | |
| csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3, | |
| csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, | |
| dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk, | |
| csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp, | |
| sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3, | |
| nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs, | |
| nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1, | |
| nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2, | |
| nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs, | |
| nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1, | |
| nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3 | |
| - groups: An array of strings, each string containing the name of a pin | |
| group. These pin groups are used for selecting the pinmux | |
| functions. | |
| lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp, | |
| sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp, | |
| rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp, | |
| rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp, | |
| i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp, | |
| pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp, | |
| eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp, | |
| eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp, | |
| lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp, | |
| spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, | |
| uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, | |
| sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp, | |
| uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp, | |
| csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp, | |
| dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp, | |
| nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp, | |
| csi1_dn0_dp0_mfp, uart4_rx_tx_mfp | |
| These pin groups are used for selecting the drive strength | |
| parameters. | |
| sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv, | |
| rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv, | |
| rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv, | |
| sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv, | |
| i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv, | |
| lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv, | |
| sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv, | |
| spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv, | |
| uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv | |
| These pin groups are used for selecting the slew rate | |
| parameters. | |
| sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr, | |
| rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr, | |
| rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr, | |
| i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr, | |
| pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr, | |
| spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr, | |
| uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr, | |
| sensor0_sr | |
| - function: An array of strings, each string containing the name of the | |
| pinmux functions. These functions can only be selected by | |
| the corresponding pin groups. The following are the list of | |
| pinmux functions available: | |
| eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0, | |
| uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, | |
| pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0, | |
| sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds, | |
| usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0, | |
| nand1, spdif, sirq0, sirq1, sirq2 | |
| Optional Properties: | |
| - bias-bus-hold: No arguments. The specified pins should retain the previous | |
| state value. | |
| - bias-high-impedance: No arguments. The specified pins should be configured | |
| as high impedance. | |
| - bias-pull-down: No arguments. The specified pins should be configured as | |
| pull down. | |
| - bias-pull-up: No arguments. The specified pins should be configured as | |
| pull up. | |
| - input-schmitt-enable: No arguments: Enable schmitt trigger for the specified | |
| pins | |
| - input-schmitt-disable: No arguments: Disable schmitt trigger for the specified | |
| pins | |
| - slew-rate: Integer. Sets slew rate for the specified pins. | |
| Valid values are: | |
| <0> - Slow | |
| <1> - Fast | |
| - drive-strength: Integer. Selects the drive strength for the specified | |
| pins in mA. | |
| Valid values are: | |
| <2> | |
| <4> | |
| <8> | |
| <12> | |
| Example: | |
| pinctrl: pinctrl@e01b0000 { | |
| compatible = "actions,s900-pinctrl"; | |
| reg = <0x0 0xe01b0000 0x0 0x1000>; | |
| clocks = <&cmu CLK_GPIO>; | |
| gpio-controller; | |
| gpio-ranges = <&pinctrl 0 0 146>; | |
| #gpio-cells = <2>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
| uart2-default: uart2-default { | |
| pinmux { | |
| groups = "lvds_oep_odn_mfp"; | |
| function = "uart2"; | |
| }; | |
| pinconf { | |
| groups = "lvds_oep_odn_drv"; | |
| drive-strength = <12>; | |
| }; | |
| }; | |
| }; |
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| * Analog Devices AD5820 autofocus coil | |
| Required Properties: | |
| - compatible: Must contain one of: | |
| - "adi,ad5820" | |
| - "adi,ad5821" | |
| - "adi,ad5823" | |
| - reg: I2C slave address | |
| - VANA-supply: supply of voltage for VANA pin | |
| Optional properties: | |
| - enable-gpios : GPIO spec for the XSHUTDOWN pin. The XSHUTDOWN signal is | |
| active low, a high level on the pin enables the device. | |
| Example: | |
| ad5820: coil@c { | |
| compatible = "adi,ad5820"; | |
| reg = <0x0c>; | |
| VANA-supply = <&vaux4>; | |
| enable-gpios = <&msmgpio 26 GPIO_ACTIVE_HIGH>; | |
| }; | |
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| * Analog Devices AD7879(-1)/AD7889(-1) touchscreen interface (SPI/I2C) | |
| Required properties: | |
| - compatible : for SPI slave, use "adi,ad7879" | |
| for I2C slave, use "adi,ad7879-1" | |
| - reg : SPI chipselect/I2C slave address | |
| See spi-bus.txt for more SPI slave properties | |
| - interrupts : touch controller interrupt | |
| - touchscreen-max-pressure : maximum reported pressure | |
| - adi,resistance-plate-x : total resistance of X-plate (for pressure | |
| calculation) | |
| Optional properties: | |
| - touchscreen-swapped-x-y : X and Y axis are swapped (boolean) | |
| - adi,first-conversion-delay : 0-12: In 128us steps (starting with 128us) | |
| 13 : 2.560ms | |
| 14 : 3.584ms | |
| 15 : 4.096ms | |
| This property has to be a '/bits/ 8' value | |
| - adi,acquisition-time : 0: 2us | |
| 1: 4us | |
| 2: 8us | |
| 3: 16us | |
| This property has to be a '/bits/ 8' value | |
| - adi,median-filter-size : 0: disabled | |
| 1: 4 measurements | |
| 2: 8 measurements | |
| 3: 16 measurements | |
| This property has to be a '/bits/ 8' value | |
| - adi,averaging : 0: 2 middle values (1 if median disabled) | |
| 1: 4 middle values | |
| 2: 8 middle values | |
| 3: 16 values | |
| This property has to be a '/bits/ 8' value | |
| - adi,conversion-interval: : 0 : convert one time only | |
| 1-255: 515us + val * 35us (up to 9.440ms) | |
| This property has to be a '/bits/ 8' value | |
| - gpio-controller : Switch AUX/VBAT/GPIO pin to GPIO mode | |
| Example: | |
| touchscreen0@2c { | |
| compatible = "adi,ad7879-1"; | |
| reg = <0x2c>; | |
| interrupt-parent = <&gpio1>; | |
| interrupts = <13 IRQ_TYPE_EDGE_FALLING>; | |
| touchscreen-max-pressure = <4096>; | |
| adi,resistance-plate-x = <120>; | |
| adi,first-conversion-delay = /bits/ 8 <3>; | |
| adi,acquisition-time = /bits/ 8 <1>; | |
| adi,median-filter-size = /bits/ 8 <2>; | |
| adi,averaging = /bits/ 8 <1>; | |
| adi,conversion-interval = /bits/ 8 <255>; | |
| }; | |
| touchscreen1@1 { | |
| compatible = "adi,ad7879"; | |
| spi-max-frequency = <5000000>; | |
| reg = <1>; | |
| spi-cpol; | |
| spi-cpha; | |
| gpio-controller; | |
| interrupt-parent = <&gpio1>; | |
| interrupts = <13 IRQ_TYPE_EDGE_FALLING>; | |
| touchscreen-max-pressure = <4096>; | |
| adi,resistance-plate-x = <120>; | |
| adi,first-conversion-delay = /bits/ 8 <3>; | |
| adi,acquisition-time = /bits/ 8 <1>; | |
| adi,median-filter-size = /bits/ 8 <2>; | |
| adi,averaging = /bits/ 8 <1>; | |
| adi,conversion-interval = /bits/ 8 <255>; | |
| }; |
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| ADC attached resistor ladder buttons | |
| ------------------------------------ | |
| Required properties: | |
| - compatible: "adc-keys" | |
| - io-channels: Phandle to an ADC channel | |
| - io-channel-names = "buttons"; | |
| - keyup-threshold-microvolt: Voltage above or equal to which all the keys are | |
| considered up. | |
| Optional properties: | |
| - poll-interval: Poll interval time in milliseconds | |
| - autorepeat: Boolean, Enable auto repeat feature of Linux input | |
| subsystem. | |
| Each button (key) is represented as a sub-node of "adc-keys": | |
| Required subnode-properties: | |
| - label: Descriptive name of the key. | |
| - linux,code: Keycode to emit. | |
| - press-threshold-microvolt: voltage above or equal to which this key is | |
| considered pressed. | |
| No two values of press-threshold-microvolt may be the same. | |
| All values of press-threshold-microvolt must be less than | |
| keyup-threshold-microvolt. | |
| Example: | |
| #include <dt-bindings/input/input.h> | |
| adc-keys { | |
| compatible = "adc-keys"; | |
| io-channels = <&lradc 0>; | |
| io-channel-names = "buttons"; | |
| keyup-threshold-microvolt = <2000000>; | |
| button-up { | |
| label = "Volume Up"; | |
| linux,code = <KEY_VOLUMEUP>; | |
| press-threshold-microvolt = <1500000>; | |
| }; | |
| button-down { | |
| label = "Volume Down"; | |
| linux,code = <KEY_VOLUMEDOWN>; | |
| press-threshold-microvolt = <1000000>; | |
| }; | |
| button-enter { | |
| label = "Enter"; | |
| linux,code = <KEY_ENTER>; | |
| press-threshold-microvolt = <500000>; | |
| }; | |
| }; | |
| +--------------------------------+------------------------+ | |
| | 2.000.000 <= value | no key pressed | | |
| +--------------------------------+------------------------+ | |
| | 1.500.000 <= value < 2.000.000 | KEY_VOLUMEUP pressed | | |
| +--------------------------------+------------------------+ | |
| | 1.000.000 <= value < 1.500.000 | KEY_VOLUMEDOWN pressed | | |
| +--------------------------------+------------------------+ | |
| | 500.000 <= value < 1.000.000 | KEY_ENTER pressed | | |
| +--------------------------------+------------------------+ | |
| | value < 500.000 | no key pressed | | |
| +--------------------------------+------------------------+ |
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| TI ADC128D818 ADC System Monitor With Temperature Sensor | |
| -------------------------------------------------------- | |
| Operation modes: | |
| - Mode 0: 7 single-ended voltage readings (IN0-IN6), | |
| 1 temperature reading (internal) | |
| - Mode 1: 8 single-ended voltage readings (IN0-IN7), | |
| no temperature | |
| - Mode 2: 4 pseudo-differential voltage readings | |
| (IN0-IN1, IN3-IN2, IN4-IN5, IN7-IN6), | |
| 1 temperature reading (internal) | |
| - Mode 3: 4 single-ended voltage readings (IN0-IN3), | |
| 2 pseudo-differential voltage readings | |
| (IN4-IN5, IN7-IN6), | |
| 1 temperature reading (internal) | |
| If no operation mode is configured via device tree, the driver keeps the | |
| currently active chip operation mode (default is mode 0). | |
| Required node properties: | |
| - compatible: must be set to "ti,adc128d818" | |
| - reg: I2C address of the device | |
| Optional node properties: | |
| - ti,mode: Operation mode (u8) (see above). | |
| Example (operation mode 2): | |
| adc128d818@1d { | |
| compatible = "ti,adc128d818"; | |
| reg = <0x1d>; | |
| ti,mode = /bits/ 8 <2>; | |
| }; |
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| * ADF7242 IEEE 802.15.4 * | |
| Required properties: | |
| - compatible: should be "adi,adf7242", "adi,adf7241" | |
| - spi-max-frequency: maximal bus speed (12.5 MHz) | |
| - reg: the chipselect index | |
| - interrupts: the interrupt generated by the device via pin IRQ1. | |
| IRQ_TYPE_LEVEL_HIGH (4) or IRQ_TYPE_EDGE_FALLING (1) | |
| Example: | |
| adf7242@0 { | |
| compatible = "adi,adf7242"; | |
| spi-max-frequency = <10000000>; | |
| reg = <0>; | |
| interrupts = <98 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-parent = <&gpio3>; | |
| }; |
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| Analog Devices ADAU1701 | |
| Required properties: | |
| - compatible: Should contain "adi,adau1701" | |
| - reg: The i2c address. Value depends on the state of ADDR0 | |
| and ADDR1, as wired in hardware. | |
| Optional properties: | |
| - reset-gpio: A GPIO spec to define which pin is connected to the | |
| chip's !RESET pin. If specified, the driver will | |
| assert a hardware reset at probe time. | |
| - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs | |
| the ADAU's PLL config pins are connected to. | |
| The state of the pins are set according to the | |
| configured clock divider on ASoC side before the | |
| firmware is loaded. | |
| - adi,pin-config: An array of 12 numerical values selecting one of the | |
| pin configurations as described in the datasheet, | |
| table 53. Note that the value of this property has | |
| to be prefixed with '/bits/ 8'. | |
| - avdd-supply: Power supply for AVDD, providing 3.3V | |
| - dvdd-supply: Power supply for DVDD, providing 3.3V | |
| Examples: | |
| i2c_bus { | |
| adau1701@34 { | |
| compatible = "adi,adau1701"; | |
| reg = <0x34>; | |
| reset-gpio = <&gpio 23 0>; | |
| avdd-supply = <&vdd_3v3_reg>; | |
| dvdd-supply = <&vdd_3v3_reg>; | |
| adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>; | |
| adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4 | |
| 0x4 0x4 0x4 0x4 0x4 0x4>; | |
| }; | |
| }; |
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| Analog Devices ADAU1361/ADAU1461/ADAU1761/ADAU1961/ADAU1381/ADAU1781 | |
| Required properties: | |
| - compatible: Should contain one of the following: | |
| "adi,adau1361" | |
| "adi,adau1461" | |
| "adi,adau1761" | |
| "adi,adau1961" | |
| "adi,adau1381" | |
| "adi,adau1781" | |
| - reg: The i2c address. Value depends on the state of ADDR0 | |
| and ADDR1, as wired in hardware. | |
| Optional properties: | |
| - clock-names: If provided must be "mclk". | |
| - clocks: phandle + clock-specifiers for the clock that provides | |
| the audio master clock for the device. | |
| Examples: | |
| #include <dt-bindings/sound/adau17x1.h> | |
| i2c_bus { | |
| adau1361@38 { | |
| compatible = "adi,adau1761"; | |
| reg = <0x38>; | |
| clock-names = "mclk"; | |
| clocks = <&audio_clock>; | |
| }; | |
| }; |
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| Analog Devices ADAU7002 Stereo PDM-to-I2S/TDM Converter | |
| Required properties: | |
| - compatible: Must be "adi,adau7002" | |
| Optional properties: | |
| - IOVDD-supply: Phandle and specifier for the power supply providing the IOVDD | |
| supply as covered in Documentation/devicetree/bindings/regulator/regulator.txt | |
| If this property is not present it is assumed that the supply pin is | |
| hardwired to always on. | |
| Example: | |
| adau7002: pdm-to-i2s { | |
| compatible = "adi,adau7002"; | |
| IOVDD-supply = <&supply>; | |
| }; |
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| Bindings for Analog Devices ADG792A/G Triple 4:1 Multiplexers | |
| Required properties: | |
| - compatible : "adi,adg792a" or "adi,adg792g" | |
| - #mux-control-cells : <0> if parallel (the three muxes are bound together | |
| with a single mux controller controlling all three muxes), or <1> if | |
| not (one mux controller for each mux). | |
| * Standard mux-controller bindings as described in mux-controller.yaml | |
| Optional properties for ADG792G: | |
| - gpio-controller : if present, #gpio-cells below is required. | |
| - #gpio-cells : should be <2> | |
| - First cell is the GPO line number, i.e. 0 or 1 | |
| - Second cell is used to specify active high (0) | |
| or active low (1) | |
| Optional properties: | |
| - idle-state : if present, array of states that the mux controllers will have | |
| when idle. The special state MUX_IDLE_AS_IS is the default and | |
| MUX_IDLE_DISCONNECT is also supported. | |
| States 0 through 3 correspond to signals A through D in the datasheet. | |
| Example: | |
| /* | |
| * Three independent mux controllers (of which one is used). | |
| * Mux 0 is disconnected when idle, mux 1 idles in the previously | |
| * selected state and mux 2 idles with signal B. | |
| */ | |
| &i2c0 { | |
| mux: mux-controller@50 { | |
| compatible = "adi,adg792a"; | |
| reg = <0x50>; | |
| #mux-control-cells = <1>; | |
| idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 1>; | |
| }; | |
| }; | |
| adc-mux { | |
| compatible = "io-channel-mux"; | |
| io-channels = <&adc 0>; | |
| io-channel-names = "parent"; | |
| mux-controls = <&mux 2>; | |
| channels = "sync-1", "", "out"; | |
| }; | |
| /* | |
| * Three parallel muxes with one mux controller, useful e.g. if | |
| * the adc is differential, thus needing two signals to be muxed | |
| * simultaneously for correct operation. | |
| */ | |
| &i2c0 { | |
| pmux: mux-controller@50 { | |
| compatible = "adi,adg792a"; | |
| reg = <0x50>; | |
| #mux-control-cells = <0>; | |
| idle-state = <1>; | |
| }; | |
| }; | |
| diff-adc-mux { | |
| compatible = "io-channel-mux"; | |
| io-channels = <&adc 0>; | |
| io-channel-names = "parent"; | |
| mux-controls = <&pmux>; | |
| channels = "sync-1", "", "out"; | |
| }; |
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| Bindings for Analog Devices ADGS1408/1409 8:1/Dual 4:1 Mux | |
| Required properties: | |
| - compatible : Should be one of | |
| * "adi,adgs1408" | |
| * "adi,adgs1409" | |
| * Standard mux-controller bindings as described in mux-controller.yaml | |
| Optional properties for ADGS1408/1409: | |
| - gpio-controller : if present, #gpio-cells is required. | |
| - #gpio-cells : should be <2> | |
| - First cell is the GPO line number, i.e. 0 to 3 | |
| for ADGS1408 and 0 to 4 for ADGS1409 | |
| - Second cell is used to specify active high (0) | |
| or active low (1) | |
| Optional properties: | |
| - idle-state : if present, the state that the mux controller will have | |
| when idle. The special state MUX_IDLE_AS_IS is the default and | |
| MUX_IDLE_DISCONNECT is also supported. | |
| States 0 through 7 correspond to signals S1 through S8 in the datasheet. | |
| For ADGS1409 only states 0 to 3 are available. | |
| Example: | |
| /* | |
| * One mux controller. | |
| * Mux state set to idle as is (no idle-state declared) | |
| */ | |
| &spi0 { | |
| mux: mux-controller@0 { | |
| compatible = "adi,adgs1408"; | |
| reg = <0>; | |
| spi-max-frequency = <1000000>; | |
| #mux-control-cells = <0>; | |
| }; | |
| } | |
| adc-mux { | |
| compatible = "io-channel-mux"; | |
| io-channels = <&adc 1>; | |
| io-channel-names = "parent"; | |
| mux-controls = <&mux>; | |
| channels = "out_a0", "out_a1", "test0", "test1", | |
| "out_b0", "out_b1", "testb0", "testb1"; | |
| }; |
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| Analog Devices AXI-DMAC DMA controller | |
| Required properties: | |
| - compatible: Must be "adi,axi-dmac-1.00.a". | |
| - reg: Specification for the controllers memory mapped register map. | |
| - interrupts: Specification for the controllers interrupt. | |
| - clocks: Phandle and specifier to the controllers AXI interface clock | |
| - #dma-cells: Must be 1. | |
| Required sub-nodes: | |
| - adi,channels: This sub-node must contain a sub-node for each DMA channel. For | |
| the channel sub-nodes the following bindings apply. They must match the | |
| configuration options of the peripheral as it was instantiated. | |
| Required properties for adi,channels sub-node: | |
| - #size-cells: Must be 0 | |
| - #address-cells: Must be 1 | |
| Required channel sub-node properties: | |
| - reg: Which channel this node refers to. | |
| - adi,source-bus-width, | |
| adi,destination-bus-width: Width of the source or destination bus in bits. | |
| - adi,source-bus-type, | |
| adi,destination-bus-type: Type of the source or destination bus. Must be one | |
| of the following: | |
| 0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface | |
| 1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface | |
| 2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface | |
| Deprecated optional channel properties: | |
| - adi,length-width: Width of the DMA transfer length register. | |
| - adi,cyclic: Must be set if the channel supports hardware cyclic DMA | |
| transfers. | |
| - adi,2d: Must be set if the channel supports hardware 2D DMA transfers. | |
| DMA clients connected to the AXI-DMAC DMA controller must use the format | |
| described in the dma.txt file using a one-cell specifier. The value of the | |
| specifier refers to the DMA channel index. | |
| Example: | |
| dma: dma@7c420000 { | |
| compatible = "adi,axi-dmac-1.00.a"; | |
| reg = <0x7c420000 0x10000>; | |
| interrupts = <0 57 0>; | |
| clocks = <&clkc 16>; | |
| #dma-cells = <1>; | |
| adi,channels { | |
| #size-cells = <0>; | |
| #address-cells = <1>; | |
| dma-channel@0 { | |
| reg = <0>; | |
| adi,source-bus-width = <32>; | |
| adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>; | |
| adi,destination-bus-width = <64>; | |
| adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>; | |
| }; | |
| }; | |
| }; |
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| ADI AXI-I2S controller | |
| The core can be generated with transmit (playback), only receive | |
| (capture) or both directions enabled. | |
| Required properties: | |
| - compatible : Must be "adi,axi-i2s-1.00.a" | |
| - reg : Must contain I2S core's registers location and length | |
| - clocks : Pairs of phandle and specifier referencing the controller's clocks. | |
| The controller expects two clocks, the clock used for the AXI interface and | |
| the clock used as the sampling rate reference clock sample. | |
| - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample | |
| rate reference clock. | |
| - dmas: Pairs of phandle and specifier for the DMA channels that are used by | |
| the core. The core expects two dma channels if both transmit and receive are | |
| enabled, one channel otherwise. | |
| - dma-names : "tx" for the transmit channel, "rx" for the receive channel. | |
| For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties | |
| please check: | |
| * resource-names.txt | |
| * clock/clock-bindings.txt | |
| * dma/dma.txt | |
| Example: | |
| i2s: i2s@77600000 { | |
| compatible = "adi,axi-i2s-1.00.a"; | |
| reg = <0x77600000 0x1000>; | |
| clocks = <&clk 15>, <&audio_clock>; | |
| clock-names = "axi", "ref"; | |
| dmas = <&ps7_dma 0>, <&ps7_dma 1>; | |
| dma-names = "tx", "rx"; | |
| }; |
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| ADI AXI-SPDIF controller | |
| Required properties: | |
| - compatible : Must be "adi,axi-spdif-tx-1.00.a" | |
| - reg : Must contain SPDIF core's registers location and length | |
| - clocks : Pairs of phandle and specifier referencing the controller's clocks. | |
| The controller expects two clocks, the clock used for the AXI interface and | |
| the clock used as the sampling rate reference clock sample. | |
| - clock-names: "axi" for the clock to the AXI interface, "ref" for the sample | |
| rate reference clock. | |
| - dmas: Pairs of phandle and specifier for the DMA channel that is used by | |
| the core. The core expects one dma channel for transmit. | |
| - dma-names : Must be "tx" | |
| For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties | |
| please check: | |
| * resource-names.txt | |
| * clock/clock-bindings.txt | |
| * dma/dma.txt | |
| Example: | |
| spdif: spdif@77400000 { | |
| compatible = "adi,axi-spdif-tx-1.00.a"; | |
| reg = <0x77600000 0x1000>; | |
| clocks = <&clk 15>, <&audio_clock>; | |
| clock-names = "axi", "ref"; | |
| dmas = <&ps7_dma 0>; | |
| dma-names = "tx"; | |
| }; |
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| Analog Devices AXI SPI Engine controller Device Tree Bindings | |
| Required properties: | |
| - compatible : Must be "adi,axi-spi-engine-1.00.a"" | |
| - reg : Physical base address and size of the register map. | |
| - interrupts : Property with a value describing the interrupt | |
| number. | |
| - clock-names : List of input clock names - "s_axi_aclk", "spi_clk" | |
| - clocks : Clock phandles and specifiers (See clock bindings for | |
| details on clock-names and clocks). | |
| - #address-cells : Must be <1> | |
| - #size-cells : Must be <0> | |
| Optional subnodes: | |
| Subnodes are use to represent the SPI slave devices connected to the SPI | |
| master. They follow the generic SPI bindings as outlined in spi-bus.txt. | |
| Example: | |
| spi@@44a00000 { | |
| compatible = "adi,axi-spi-engine-1.00.a"; | |
| reg = <0x44a00000 0x1000>; | |
| interrupts = <0 56 4>; | |
| clocks = <&clkc 15 &clkc 15>; | |
| clock-names = "s_axi_aclk", "spi_clk"; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| /* SPI devices */ | |
| }; |
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| Analog Devices SSM2305 Speaker Amplifier | |
| ======================================== | |
| Required properties: | |
| - compatible : "adi,ssm2305" | |
| - shutdown-gpios : The gpio connected to the shutdown pin. | |
| The gpio signal is ACTIVE_LOW. | |
| Example: | |
| ssm2305: analog-amplifier { | |
| compatible = "adi,ssm2305"; | |
| shutdown-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; | |
| }; |
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| Analog Devices SSM2602, SSM2603 and SSM2604 I2S audio CODEC devices | |
| SSM2602 support both I2C and SPI as the configuration interface, | |
| the selection is made by the MODE strap-in pin. | |
| SSM2603 and SSM2604 only support I2C as the configuration interface. | |
| Required properties: | |
| - compatible : One of "adi,ssm2602", "adi,ssm2603" or "adi,ssm2604" | |
| - reg : the I2C address of the device for I2C, the chip select | |
| number for SPI. | |
| Example: | |
| ssm2602: ssm2602@1a { | |
| compatible = "adi,ssm2602"; | |
| reg = <0x1a>; | |
| }; |
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| * Analog Devices ADP1653 flash LED driver | |
| Required Properties: | |
| - compatible: Must contain "adi,adp1653" | |
| - reg: I2C slave address | |
| - enable-gpios: Specifier of the GPIO connected to EN pin | |
| There are two LED outputs available - flash and indicator. One LED is | |
| represented by one child node, nodes need to be named "flash" and "indicator". | |
| Required properties of the LED child node: | |
| - led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt | |
| Required properties of the flash LED child node: | |
| - flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt | |
| - flash-timeout-us : see Documentation/devicetree/bindings/leds/common.txt | |
| - led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt | |
| Example: | |
| adp1653: led-controller@30 { | |
| compatible = "adi,adp1653"; | |
| reg = <0x30>; | |
| enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */ | |
| flash { | |
| flash-timeout-us = <500000>; | |
| flash-max-microamp = <320000>; | |
| led-max-microamp = <50000>; | |
| }; | |
| indicator { | |
| led-max-microamp = <17500>; | |
| }; | |
| }; |
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| Binding for Texas Instruments ADPLL clock. | |
| Binding status: Unstable - ABI compatibility may be broken in the future | |
| This binding uses the common clock binding[1]. It assumes a | |
| register-mapped ADPLL with two to three selectable input clocks | |
| and three to four children. | |
| [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| Required properties: | |
| - compatible : shall be one of "ti,dm814-adpll-s-clock" or | |
| "ti,dm814-adpll-lj-clock" depending on the type of the ADPLL | |
| - #clock-cells : from common clock binding; shall be set to 1. | |
| - clocks : link phandles of parent clocks clkinp and clkinpulow, note | |
| that the adpll-s-clock also has an optional clkinphif | |
| - reg : address and length of the register set for controlling the ADPLL. | |
| Examples: | |
| adpll_mpu_ck: adpll@40 { | |
| #clock-cells = <1>; | |
| compatible = "ti,dm814-adpll-s-clock"; | |
| reg = <0x40 0x40>; | |
| clocks = <&devosc_ck &devosc_ck &devosc_ck>; | |
| clock-names = "clkinp", "clkinpulow", "clkinphif"; | |
| clock-output-names = "481c5040.adpll.dcoclkldo", | |
| "481c5040.adpll.clkout", | |
| "481c5040.adpll.clkoutx2", | |
| "481c5040.adpll.clkouthif"; | |
| }; | |
| adpll_dsp_ck: adpll@80 { | |
| #clock-cells = <1>; | |
| compatible = "ti,dm814-adpll-lj-clock"; | |
| reg = <0x80 0x30>; | |
| clocks = <&devosc_ck &devosc_ck>; | |
| clock-names = "clkinp", "clkinpulow"; | |
| clock-output-names = "481c5080.adpll.dcoclkldo", | |
| "481c5080.adpll.clkout", | |
| "481c5080.adpll.clkoutldo"; | |
| }; |
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| Device tree bindings for TI's ADS7843, ADS7845, ADS7846, ADS7873, TSC2046 | |
| SPI driven touch screen controllers. | |
| The node for this driver must be a child node of a SPI controller, hence | |
| all mandatory properties described in | |
| Documentation/devicetree/bindings/spi/spi-bus.txt | |
| must be specified. | |
| Additional required properties: | |
| compatible Must be one of the following, depending on the | |
| model: | |
| "ti,tsc2046" | |
| "ti,ads7843" | |
| "ti,ads7845" | |
| "ti,ads7846" | |
| "ti,ads7873" | |
| interrupts An interrupt node describing the IRQ line the chip's | |
| !PENIRQ pin is connected to. | |
| vcc-supply A regulator node for the supply voltage. | |
| Optional properties: | |
| ti,vref-delay-usecs vref supply delay in usecs, 0 for | |
| external vref (u16). | |
| ti,vref-mv The VREF voltage, in millivolts (u16). | |
| Set to 0 to use internal references | |
| (ADS7846). | |
| ti,keep-vref-on set to keep vref on for differential | |
| measurements as well | |
| ti,settle-delay-usec Settling time of the analog signals; | |
| a function of Vcc and the capacitance | |
| on the X/Y drivers. If set to non-zero, | |
| two samples are taken with settle_delay | |
| us apart, and the second one is used. | |
| ~150 uSec with 0.01uF caps (u16). | |
| ti,penirq-recheck-delay-usecs If set to non-zero, after samples are | |
| taken this delay is applied and penirq | |
| is rechecked, to help avoid false | |
| events. This value is affected by the | |
| material used to build the touch layer | |
| (u16). | |
| ti,x-plate-ohms Resistance of the X-plate, | |
| in Ohms (u16). | |
| ti,y-plate-ohms Resistance of the Y-plate, | |
| in Ohms (u16). | |
| ti,x-min Minimum value on the X axis (u16). | |
| ti,y-min Minimum value on the Y axis (u16). | |
| ti,debounce-tol Tolerance used for filtering (u16). | |
| ti,debounce-rep Additional consecutive good readings | |
| required after the first two (u16). | |
| ti,pendown-gpio-debounce Platform specific debounce time for the | |
| pendown-gpio (u32). | |
| pendown-gpio GPIO handle describing the pin the !PENIRQ | |
| line is connected to. | |
| wakeup-source use any event on touchscreen as wakeup event. | |
| (Legacy property support: "linux,wakeup") | |
| touchscreen-size-x General touchscreen binding, see [1]. | |
| touchscreen-size-y General touchscreen binding, see [1]. | |
| touchscreen-max-pressure General touchscreen binding, see [1]. | |
| touchscreen-min-pressure General touchscreen binding, see [1]. | |
| touchscreen-average-samples General touchscreen binding, see [1]. | |
| touchscreen-inverted-x General touchscreen binding, see [1]. | |
| touchscreen-inverted-y General touchscreen binding, see [1]. | |
| touchscreen-swapped-x-y General touchscreen binding, see [1]. | |
| [1] All general touchscreen properties are described in | |
| Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt. | |
| Deprecated properties: | |
| ti,swap-xy swap x and y axis | |
| ti,x-max Maximum value on the X axis (u16). | |
| ti,y-max Maximum value on the Y axis (u16). | |
| ti,pressure-min Minimum reported pressure value | |
| (threshold) - u16. | |
| ti,pressure-max Maximum reported pressure value (u16). | |
| ti,debounce-max Max number of additional readings per | |
| sample (u16). | |
| Example for a TSC2046 chip connected to an McSPI controller of an OMAP SoC:: | |
| spi_controller { | |
| tsc2046@0 { | |
| reg = <0>; /* CS0 */ | |
| compatible = "ti,tsc2046"; | |
| interrupt-parent = <&gpio1>; | |
| interrupts = <8 0>; /* BOOT6 / GPIO 8 */ | |
| spi-max-frequency = <1000000>; | |
| pendown-gpio = <&gpio1 8 0>; | |
| vcc-supply = <®_vcc3>; | |
| ti,x-min = /bits/ 16 <0>; | |
| ti,x-max = /bits/ 16 <8000>; | |
| ti,y-min = /bits/ 16 <0>; | |
| ti,y-max = /bits/ 16 <4800>; | |
| ti,x-plate-ohms = /bits/ 16 <40>; | |
| ti,pressure-max = /bits/ 16 <255>; | |
| wakeup-source; | |
| }; | |
| }; |
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| * Analog Devices adv7343 video encoder | |
| The ADV7343 are high speed, digital-to-analog video encoders in a 64-lead LQFP | |
| package. Six high speed, 3.3 V, 11-bit video DACs provide support for composite | |
| (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard | |
| definition (SD), enhanced definition (ED), or high definition (HD) video | |
| formats. | |
| Required Properties : | |
| - compatible: Must be "adi,adv7343" | |
| Optional Properties : | |
| - adi,power-mode-sleep-mode: on enable the current consumption is reduced to | |
| micro ampere level. All DACs and the internal PLL | |
| circuit are disabled. | |
| - adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows | |
| internal PLL 1 circuit to be powered down and the | |
| oversampling to be switched off. | |
| - ad,adv7343-power-mode-dac: array configuring the power on/off DAC's 1..6, | |
| 0 = OFF and 1 = ON, Default value when this | |
| property is not specified is <0 0 0 0 0 0>. | |
| - ad,adv7343-sd-config-dac-out: array configure SD DAC Output's 1 and 2, 0 = OFF | |
| and 1 = ON, Default value when this property is | |
| not specified is <0 0>. | |
| Example: | |
| i2c0@1c22000 { | |
| ... | |
| ... | |
| adv7343@2a { | |
| compatible = "adi,adv7343"; | |
| reg = <0x2a>; | |
| port { | |
| adv7343_1: endpoint { | |
| adi,power-mode-sleep-mode; | |
| adi,power-mode-pll-ctrl; | |
| /* Use DAC1..3, DAC6 */ | |
| adi,dac-enable = <1 1 1 0 0 1>; | |
| /* Use SD DAC output 1 */ | |
| adi,sd-dac-enable = <1 0>; | |
| }; | |
| }; | |
| }; | |
| ... | |
| }; |
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| Binding for CEVA AHCI SATA Controller | |
| Required properties: | |
| - reg: Physical base address and size of the controller's register area. | |
| - compatible: Compatibility string. Must be 'ceva,ahci-1v84'. | |
| - clocks: Input clock specifier. Refer to common clock bindings. | |
| - interrupts: Interrupt specifier. Refer to interrupt binding. | |
| - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0. | |
| - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1. | |
| The fields for the above parameter must be as shown below: | |
| ceva,pN-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>; | |
| CINMP : COMINIT Negate Minimum Period. | |
| CIBGN : COMINIT Burst Gap Nominal. | |
| CIBGMX: COMINIT Burst Gap Maximum. | |
| CIBGMN: COMINIT Burst Gap Minimum. | |
| - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0. | |
| - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1. | |
| The fields for the above parameter must be as shown below: | |
| ceva,pN-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>; | |
| CWBGMN: COMWAKE Burst Gap Minimum. | |
| CWBGMX: COMWAKE Burst Gap Maximum. | |
| CWBGN: COMWAKE Burst Gap Nominal. | |
| CWNMP: COMWAKE Negate Minimum Period. | |
| - ceva,p0-burst-params: Burst timing value for COM parameter for port 0. | |
| - ceva,p1-burst-params: Burst timing value for COM parameter for port 1. | |
| The fields for the above parameter must be as shown below: | |
| ceva,pN-burst-params = /bits/ 8 <BMX BNM SFD PTST>; | |
| BMX: COM Burst Maximum. | |
| BNM: COM Burst Nominal. | |
| SFD: Signal Failure Detection value. | |
| PTST: Partial to Slumber timer value. | |
| - ceva,p0-retry-params: Retry interval timing value for port 0. | |
| - ceva,p1-retry-params: Retry interval timing value for port 1. | |
| The fields for the above parameter must be as shown below: | |
| ceva,pN-retry-params = /bits/ 16 <RIT RCT>; | |
| RIT: Retry Interval Timer. | |
| RCT: Rate Change Timer. | |
| Optional properties: | |
| - ceva,broken-gen2: limit to gen1 speed instead of gen2. | |
| - phys: phandle for the PHY device | |
| - resets: phandle to the reset controller for the SATA IP | |
| Examples: | |
| ahci@fd0c0000 { | |
| compatible = "ceva,ahci-1v84"; | |
| reg = <0xfd0c0000 0x200>; | |
| interrupt-parent = <&gic>; | |
| interrupts = <0 133 4>; | |
| clocks = <&clkc SATA_CLK_ID>; | |
| ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; | |
| ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; | |
| ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; | |
| ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>; | |
| ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; | |
| ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; | |
| ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; | |
| ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; | |
| ceva,broken-gen2; | |
| phys = <&psgtr 1 PHY_TYPE_SATA 1 1>; | |
| resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; | |
| }; |
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| Device tree binding for the TI DA850 AHCI SATA Controller | |
| --------------------------------------------------------- | |
| Required properties: | |
| - compatible: must be "ti,da850-ahci" | |
| - reg: physical base addresses and sizes of the two register regions | |
| used by the controller: the register map as defined by the | |
| AHCI 1.1 standard and the Power Down Control Register (PWRDN) | |
| for enabling/disabling the SATA clock receiver | |
| - interrupts: interrupt specifier (refer to the interrupt binding) | |
| Example: | |
| sata: sata@218000 { | |
| compatible = "ti,da850-ahci"; | |
| reg = <0x218000 0x2000>, <0x22c018 0x4>; | |
| interrupts = <67>; | |
| }; |
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| Device tree binding for the TI DM816 AHCI SATA Controller | |
| --------------------------------------------------------- | |
| Required properties: | |
| - compatible: must be "ti,dm816-ahci" | |
| - reg: physical base address and size of the register region used by | |
| the controller (as defined by the AHCI 1.1 standard) | |
| - interrupts: interrupt specifier (refer to the interrupt binding) | |
| - clocks: list of phandle and clock specifier pairs (or only | |
| phandles for clock providers with '0' defined for | |
| #clock-cells); two clocks must be specified: the functional | |
| clock and an external reference clock | |
| Example: | |
| sata: sata@4a140000 { | |
| compatible = "ti,dm816-ahci"; | |
| reg = <0x4a140000 0x10000>; | |
| interrupts = <16>; | |
| clocks = <&sysclk5_ck>, <&sata_refclk>; | |
| }; |
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| Binding for Freescale QorIQ AHCI SATA Controller | |
| Required properties: | |
| - reg: Physical base address and size of the controller's register area. | |
| - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where | |
| chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc. | |
| - clocks: Input clock specifier. Refer to common clock bindings. | |
| - interrupts: Interrupt specifier. Refer to interrupt binding. | |
| Optional properties: | |
| - dma-coherent: Enable AHCI coherent DMA operation. | |
| - reg-names: register area names when there are more than 1 register area. | |
| Examples: | |
| sata@3200000 { | |
| compatible = "fsl,ls1021a-ahci"; | |
| reg = <0x0 0x3200000 0x0 0x10000>; | |
| interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&platform_clk 1>; | |
| dma-coherent; | |
| }; |
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| MediaTek Serial ATA controller | |
| Required properties: | |
| - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci". | |
| When using "mediatek,mtk-ahci" compatible strings, you | |
| need SoC specific ones in addition, one of: | |
| - "mediatek,mt7622-ahci" | |
| - reg : Physical base addresses and length of register sets. | |
| - interrupts : Interrupt associated with the SATA device. | |
| - interrupt-names : Associated name must be: "hostc". | |
| - clocks : A list of phandle and clock specifier pairs, one for each | |
| entry in clock-names. | |
| - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm". | |
| - phys : A phandle and PHY specifier pair for the PHY port. | |
| - phy-names : Associated name must be: "sata-phy". | |
| - ports-implemented : See ./ahci-platform.txt for details. | |
| Optional properties: | |
| - power-domains : A phandle and power domain specifier pair to the power | |
| domain which is responsible for collapsing and restoring | |
| power to the peripheral. | |
| - resets : Must contain an entry for each entry in reset-names. | |
| See ../reset/reset.txt for details. | |
| - reset-names : Associated names must be: "axi", "sw", "reg". | |
| - mediatek,phy-mode : A phandle to the system controller, used to enable | |
| SATA function. | |
| Example: | |
| sata: sata@1a200000 { | |
| compatible = "mediatek,mt7622-ahci", | |
| "mediatek,mtk-ahci"; | |
| reg = <0 0x1a200000 0 0x1100>; | |
| interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-names = "hostc"; | |
| clocks = <&pciesys CLK_SATA_AHB_EN>, | |
| <&pciesys CLK_SATA_AXI_EN>, | |
| <&pciesys CLK_SATA_ASIC_EN>, | |
| <&pciesys CLK_SATA_RBC_EN>, | |
| <&pciesys CLK_SATA_PM_EN>; | |
| clock-names = "ahb", "axi", "asic", "rbc", "pm"; | |
| phys = <&u3port1 PHY_TYPE_SATA>; | |
| phy-names = "sata-phy"; | |
| ports-implemented = <0x1>; | |
| power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; | |
| resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, | |
| <&pciesys MT7622_SATA_PHY_SW_RST>, | |
| <&pciesys MT7622_SATA_PHY_REG_RST>; | |
| reset-names = "axi", "sw", "reg"; | |
| mediatek,phy-mode = <&pciesys>; | |
| }; |
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| * AHCI SATA Controller | |
| SATA nodes are defined to describe on-chip Serial ATA controllers. | |
| Each SATA controller should have its own node. | |
| It is possible, but not required, to represent each port as a sub-node. | |
| It allows to enable each port independently when dealing with multiple | |
| PHYs. | |
| Required properties: | |
| - compatible : compatible string, one of: | |
| - "brcm,iproc-ahci" | |
| - "hisilicon,hisi-ahci" | |
| - "cavium,octeon-7130-ahci" | |
| - "ibm,476gtr-ahci" | |
| - "marvell,armada-380-ahci" | |
| - "marvell,armada-3700-ahci" | |
| - "snps,dwc-ahci" | |
| - "snps,spear-ahci" | |
| - "generic-ahci" | |
| - interrupts : <interrupt mapping for SATA IRQ> | |
| - reg : <registers mapping> | |
| Please note that when using "generic-ahci" you must also specify a SoC specific | |
| compatible: | |
| compatible = "manufacturer,soc-model-ahci", "generic-ahci"; | |
| Optional properties: | |
| - dma-coherent : Present if dma operations are coherent | |
| - clocks : a list of phandle + clock specifier pairs | |
| - resets : a list of phandle + reset specifier pairs | |
| - target-supply : regulator for SATA target power | |
| - phy-supply : regulator for PHY power | |
| - phys : reference to the SATA PHY node | |
| - phy-names : must be "sata-phy" | |
| - ahci-supply : regulator for AHCI controller | |
| - ports-implemented : Mask that indicates which ports that the HBA supports | |
| are available for software to use. Useful if PORTS_IMPL | |
| is not programmed by the BIOS, which is true with | |
| some embedded SOC's. | |
| Required properties when using sub-nodes: | |
| - #address-cells : number of cells to encode an address | |
| - #size-cells : number of cells representing the size of an address | |
| Sub-nodes required properties: | |
| - reg : the port number | |
| And at least one of the following properties: | |
| - phys : reference to the SATA PHY node | |
| - target-supply : regulator for SATA target power | |
| Examples: | |
| sata@ffe08000 { | |
| compatible = "snps,spear-ahci"; | |
| reg = <0xffe08000 0x1000>; | |
| interrupts = <115>; | |
| }; | |
| With sub-nodes: | |
| sata@f7e90000 { | |
| compatible = "marvell,berlin2q-achi", "generic-ahci"; | |
| reg = <0xe90000 0x1000>; | |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&chip CLKID_SATA>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| sata0: sata-port@0 { | |
| reg = <0>; | |
| phys = <&sata_phy 0>; | |
| target-supply = <®_sata0>; | |
| }; | |
| sata1: sata-port@1 { | |
| reg = <1>; | |
| phys = <&sata_phy 1>; | |
| target-supply = <®_sata1>;; | |
| }; | |
| }; |
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| STMicroelectronics STi SATA controller | |
| This binding describes a SATA device. | |
| Required properties: | |
| - compatible : Must be "st,ahci" | |
| - reg : Physical base addresses and length of register sets | |
| - interrupts : Interrupt associated with the SATA device | |
| - interrupt-names : Associated name must be; "hostc" | |
| - clocks : The phandle for the clock | |
| - clock-names : Associated name must be; "ahci_clk" | |
| - phys : The phandle for the PHY port | |
| - phy-names : Associated name must be; "ahci_phy" | |
| Optional properties: | |
| - resets : The power-down, soft-reset and power-reset lines of SATA IP | |
| - reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst" | |
| Example: | |
| /* Example for stih407 family silicon */ | |
| sata0: sata@9b20000 { | |
| compatible = "st,ahci"; | |
| reg = <0x9b20000 0x1000>; | |
| interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; | |
| interrupt-names = "hostc"; | |
| phys = <&phy_port0 PHY_TYPE_SATA>; | |
| phy-names = "ahci_phy"; | |
| resets = <&powerdown STIH407_SATA0_POWERDOWN>, | |
| <&softreset STIH407_SATA0_SOFTRESET>, | |
| <&softreset STIH407_SATA0_PWR_SOFTRESET>; | |
| reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; | |
| clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; | |
| clock-names = "ahci_clk"; | |
| }; |
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| AK4104 S/PDIF transmitter | |
| This device supports SPI mode only. | |
| Required properties: | |
| - compatible : "asahi-kasei,ak4104" | |
| - reg : The chip select number on the SPI bus | |
| - vdd-supply : A regulator node, providing 2.7V - 3.6V | |
| Optional properties: | |
| - reset-gpios : a GPIO spec for the reset pin. If specified, it will be | |
| deasserted before communication to the device starts. | |
| Example: | |
| spdif: ak4104@0 { | |
| compatible = "asahi-kasei,ak4104"; | |
| reg = <0>; | |
| spi-max-frequency = <5000000>; | |
| vdd-supply = <&vdd_3v3_reg>; | |
| }; |
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| AK4118 S/PDIF transceiver | |
| This device supports I2C mode. | |
| Required properties: | |
| - compatible : "asahi-kasei,ak4118" | |
| - reg : The I2C address of the device for I2C | |
| - reset-gpios: A GPIO specifier for the reset pin | |
| - irq-gpios: A GPIO specifier for the IRQ pin | |
| Example: | |
| &i2c { | |
| ak4118: ak4118@13 { | |
| #sound-dai-cells = <0>; | |
| compatible = "asahi-kasei,ak4118"; | |
| reg = <0x13>; | |
| reset-gpios = <&gpio 0 GPIO_ACTIVE_LOW> | |
| irq-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; | |
| }; | |
| }; |
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| AK4458 audio DAC | |
| This device supports I2C mode. | |
| Required properties: | |
| - compatible : "asahi-kasei,ak4458" or "asahi-kasei,ak4497" | |
| - reg : The I2C address of the device for I2C | |
| Optional properties: | |
| - reset-gpios: A GPIO specifier for the power down & reset pin | |
| - mute-gpios: A GPIO specifier for the soft mute pin | |
| - AVDD-supply: Analog power supply | |
| - DVDD-supply: Digital power supply | |
| - dsd-path: Select DSD input pins for ak4497 | |
| 0: select #16, #17, #19 pins | |
| 1: select #3, #4, #5 pins | |
| Example: | |
| &i2c { | |
| ak4458: dac@10 { | |
| compatible = "asahi-kasei,ak4458"; | |
| reg = <0x10>; | |
| reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW> | |
| mute-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH> | |
| }; | |
| }; |
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| AK4554 ADC/DAC | |
| Required properties: | |
| - compatible : "asahi-kasei,ak4554" | |
| Example: | |
| ak4554-adc-dac { | |
| compatible = "asahi-kasei,ak4554"; | |
| }; |
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| AK5386 Single-ended 24-Bit 192kHz delta-sigma ADC | |
| This device has no control interface. | |
| Required properties: | |
| - compatible : "asahi-kasei,ak5386" | |
| Optional properties: | |
| - reset-gpio : a GPIO spec for the reset/power down pin. | |
| If specified, it will be deasserted at probe time. | |
| - va-supply : a regulator spec, providing 5.0V | |
| - vd-supply : a regulator spec, providing 3.3V | |
| Example: | |
| spdif: ak5386@0 { | |
| compatible = "asahi-kasei,ak5386"; | |
| reset-gpio = <&gpio0 23>; | |
| va-supply = <&vdd_5v0_reg>; | |
| vd-supply = <&vdd_3v3_reg>; | |
| }; |
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| AK5558 8 channel differential 32-bit delta-sigma ADC | |
| This device supports I2C mode only. | |
| Required properties: | |
| - compatible : "asahi-kasei,ak5558" or "asahi-kasei,ak5552". | |
| - reg : The I2C address of the device. | |
| Optional properties: | |
| - reset-gpios: A GPIO specifier for the power down & reset pin. | |
| - AVDD-supply: Analog power supply | |
| - DVDD-supply: Digital power supply | |
| Example: | |
| &i2c { | |
| ak5558: adc@10 { | |
| compatible = "asahi-kasei,ak5558"; | |
| reg = <0x10>; | |
| reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; | |
| }; | |
| }; |
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| Asahi Kasei Microdevices AK7375 voice coil lens driver | |
| AK7375 is a camera voice coil lens. | |
| Mandatory properties: | |
| - compatible: "asahi-kasei,ak7375" | |
| - reg: I2C slave address |
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| IBM Akebono board device tree | |
| ============================= | |
| The IBM Akebono board is a development board for the PPC476GTR SoC. | |
| 0) The root node | |
| Required properties: | |
| - model : "ibm,akebono". | |
| - compatible : "ibm,akebono" , "ibm,476gtr". | |
| 1.a) The Secure Digital Host Controller Interface (SDHCI) node | |
| Represent the Secure Digital Host Controller Interfaces. | |
| Required properties: | |
| - compatible : should be "ibm,476gtr-sdhci","generic-sdhci". | |
| - reg : should contain the SDHCI registers location and length. | |
| - interrupts : should contain the SDHCI interrupt. | |
| 1.b) The Advanced Host Controller Interface (AHCI) SATA node | |
| Represents the advanced host controller SATA interface. | |
| Required properties: | |
| - compatible : should be "ibm,476gtr-ahci". | |
| - reg : should contain the AHCI registers location and length. | |
| - interrupts : should contain the AHCI interrupt. | |
| 1.c) The FPGA node | |
| The Akebono board stores some board information such as the revision | |
| number in an FPGA which is represented by this node. | |
| Required properties: | |
| - compatible : should be "ibm,akebono-fpga". | |
| - reg : should contain the FPGA registers location and length. | |
| 1.d) The AVR node | |
| The Akebono board has an Atmel AVR microprocessor attached to the I2C | |
| bus as a power controller for the board. | |
| Required properties: | |
| - compatible : should be "ibm,akebono-avr". | |
| - reg : should contain the I2C bus address for the AVR. |
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| Alpine MSIX controller | |
| See arm,gic-v3.txt for SPI and MSI definitions. | |
| Required properties: | |
| - compatible: should be "al,alpine-msix" | |
| - reg: physical base address and size of the registers | |
| - interrupt-controller: identifies the node as an interrupt controller | |
| - msi-controller: identifies the node as an PCI Message Signaled Interrupt | |
| controller | |
| - al,msi-base-spi: SPI base of the MSI frame | |
| - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0 | |
| Example: | |
| msix: msix { | |
| compatible = "al,alpine-msix"; | |
| reg = <0x0 0xfbe00000 0x0 0x100000>; | |
| interrupt-parent = <&gic>; | |
| interrupt-controller; | |
| msi-controller; | |
| al,msi-base-spi = <160>; | |
| al,msi-num-spis = <160>; | |
| }; |
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| ALC5621/ALC5622/ALC5623 audio Codec | |
| Required properties: | |
| - compatible: "realtek,alc5623" | |
| - reg: the I2C address of the device. | |
| Optional properties: | |
| - add-ctrl: Default register value for Reg-40h, Additional Control | |
| Register. If absent or has the value of 0, the | |
| register is untouched. | |
| - jack-det-ctrl: Default register value for Reg-5Ah, Jack Detect | |
| Control Register. If absent or has value 0, the | |
| register is untouched. | |
| Example: | |
| alc5621: alc5621@1a { | |
| compatible = "alc5621"; | |
| reg = <0x1a>; | |
| add-ctrl = <0x3700>; | |
| jack-det-ctrl = <0x4810>; | |
| }; |
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| ALC5632 audio CODEC | |
| This device supports I2C only. | |
| Required properties: | |
| - compatible : "realtek,alc5632" | |
| - reg : the I2C address of the device. | |
| - gpio-controller : Indicates this device is a GPIO controller. | |
| - #gpio-cells : Should be two. The first cell is the pin number and the | |
| second cell is used to specify optional parameters (currently unused). | |
| Pins on the device (for linking into audio routes): | |
| * SPK_OUTP | |
| * SPK_OUTN | |
| * HP_OUT_L | |
| * HP_OUT_R | |
| * AUX_OUT_P | |
| * AUX_OUT_N | |
| * LINE_IN_L | |
| * LINE_IN_R | |
| * PHONE_P | |
| * PHONE_N | |
| * MIC1_P | |
| * MIC1_N | |
| * MIC2_P | |
| * MIC2_N | |
| * MICBIAS1 | |
| * DMICDAT | |
| Example: | |
| alc5632: alc5632@1e { | |
| compatible = "realtek,alc5632"; | |
| reg = <0x1a>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| }; |
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| Alphascale Clock Controller | |
| The ACC (Alphascale Clock Controller) is responsible of choising proper | |
| clock source, setting deviders and clock gates. | |
| Required properties for the ACC node: | |
| - compatible: must be "alphascale,asm9260-clock-controller" | |
| - reg: must contain the ACC register base and size | |
| - #clock-cells : shall be set to 1. | |
| Simple one-cell clock specifier format is used, where the only cell is used | |
| as an index of the clock inside the provider. | |
| It is encouraged to use dt-binding for clock index definitions. SoC specific | |
| dt-binding should be included to the device tree descriptor. For example | |
| Alphascale ASM9260: | |
| #include <dt-bindings/clock/alphascale,asm9260.h> | |
| This binding contains two types of clock providers: | |
| _AHB_ - AHB gate; | |
| _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider. | |
| All clock specific details can be found in the SoC documentation. | |
| CLKID_AHB_ROM 0 | |
| CLKID_AHB_RAM 1 | |
| CLKID_AHB_GPIO 2 | |
| CLKID_AHB_MAC 3 | |
| CLKID_AHB_EMI 4 | |
| CLKID_AHB_USB0 5 | |
| CLKID_AHB_USB1 6 | |
| CLKID_AHB_DMA0 7 | |
| CLKID_AHB_DMA1 8 | |
| CLKID_AHB_UART0 9 | |
| CLKID_AHB_UART1 10 | |
| CLKID_AHB_UART2 11 | |
| CLKID_AHB_UART3 12 | |
| CLKID_AHB_UART4 13 | |
| CLKID_AHB_UART5 14 | |
| CLKID_AHB_UART6 15 | |
| CLKID_AHB_UART7 16 | |
| CLKID_AHB_UART8 17 | |
| CLKID_AHB_UART9 18 | |
| CLKID_AHB_I2S0 19 | |
| CLKID_AHB_I2C0 20 | |
| CLKID_AHB_I2C1 21 | |
| CLKID_AHB_SSP0 22 | |
| CLKID_AHB_IOCONFIG 23 | |
| CLKID_AHB_WDT 24 | |
| CLKID_AHB_CAN0 25 | |
| CLKID_AHB_CAN1 26 | |
| CLKID_AHB_MPWM 27 | |
| CLKID_AHB_SPI0 28 | |
| CLKID_AHB_SPI1 29 | |
| CLKID_AHB_QEI 30 | |
| CLKID_AHB_QUADSPI0 31 | |
| CLKID_AHB_CAMIF 32 | |
| CLKID_AHB_LCDIF 33 | |
| CLKID_AHB_TIMER0 34 | |
| CLKID_AHB_TIMER1 35 | |
| CLKID_AHB_TIMER2 36 | |
| CLKID_AHB_TIMER3 37 | |
| CLKID_AHB_IRQ 38 | |
| CLKID_AHB_RTC 39 | |
| CLKID_AHB_NAND 40 | |
| CLKID_AHB_ADC0 41 | |
| CLKID_AHB_LED 42 | |
| CLKID_AHB_DAC0 43 | |
| CLKID_AHB_LCD 44 | |
| CLKID_AHB_I2S1 45 | |
| CLKID_AHB_MAC1 46 | |
| CLKID_SYS_CPU 47 | |
| CLKID_SYS_AHB 48 | |
| CLKID_SYS_I2S0M 49 | |
| CLKID_SYS_I2S0S 50 | |
| CLKID_SYS_I2S1M 51 | |
| CLKID_SYS_I2S1S 52 | |
| CLKID_SYS_UART0 53 | |
| CLKID_SYS_UART1 54 | |
| CLKID_SYS_UART2 55 | |
| CLKID_SYS_UART3 56 | |
| CLKID_SYS_UART4 56 | |
| CLKID_SYS_UART5 57 | |
| CLKID_SYS_UART6 58 | |
| CLKID_SYS_UART7 59 | |
| CLKID_SYS_UART8 60 | |
| CLKID_SYS_UART9 61 | |
| CLKID_SYS_SPI0 62 | |
| CLKID_SYS_SPI1 63 | |
| CLKID_SYS_QUADSPI 64 | |
| CLKID_SYS_SSP0 65 | |
| CLKID_SYS_NAND 66 | |
| CLKID_SYS_TRACE 67 | |
| CLKID_SYS_CAMM 68 | |
| CLKID_SYS_WDT 69 | |
| CLKID_SYS_CLKOUT 70 | |
| CLKID_SYS_MAC 71 | |
| CLKID_SYS_LCD 72 | |
| CLKID_SYS_ADCANA 73 | |
| Example of clock consumer with _SYS_ and _AHB_ sinks. | |
| uart4: serial@80010000 { | |
| compatible = "alphascale,asm9260-uart"; | |
| reg = <0x80010000 0x4000>; | |
| clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>; | |
| interrupts = <19>; | |
| }; | |
| Clock consumer with only one, _AHB_ sink. | |
| timer0: timer@80088000 { | |
| compatible = "alphascale,asm9260-timer"; | |
| reg = <0x80088000 0x4000>; | |
| clocks = <&acc CLKID_AHB_TIMER0>; | |
| interrupts = <29>; | |
| }; | |
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| * Alphascale asm9260 SoC Real Time Clock | |
| Required properties: | |
| - compatible: Should be "alphascale,asm9260-rtc" | |
| - reg: Physical base address of the controller and length | |
| of memory mapped region. | |
| - interrupts: IRQ line for the RTC. | |
| - clocks: Reference to the clock entry. | |
| - clock-names: should contain: | |
| * "ahb" for the SoC RTC clock | |
| Example: | |
| rtc0: rtc@800a0000 { | |
| compatible = "alphascale,asm9260-rtc"; | |
| reg = <0x800a0000 0x100>; | |
| clocks = <&acc CLKID_AHB_RTC>; | |
| clock-names = "ahb"; | |
| interrupts = <2>; | |
| }; |
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| Alphascale asm9260 Watchdog timer | |
| Required properties: | |
| - compatible : should be "alphascale,asm9260-wdt". | |
| - reg : Specifies base physical address and size of the registers. | |
| - clocks : the clocks feeding the watchdog timer. See clock-bindings.txt | |
| - clock-names : should be set to | |
| "mod" - source for tick counter. | |
| "ahb" - ahb gate. | |
| - resets : phandle pointing to the system reset controller with | |
| line index for the watchdog. | |
| - reset-names : should be set to "wdt_rst". | |
| Optional properties: | |
| - timeout-sec : shall contain the default watchdog timeout in seconds, | |
| if unset, the default timeout is 30 seconds. | |
| - alphascale,mode : three modes are supported | |
| "hw" - hw reset (default). | |
| "sw" - sw reset. | |
| "debug" - no action is taken. | |
| Example: | |
| watchdog0: watchdog@80048000 { | |
| compatible = "alphascale,asm9260-wdt"; | |
| reg = <0x80048000 0x10>; | |
| clocks = <&acc CLKID_SYS_WDT>, <&acc CLKID_AHB_WDT>; | |
| clock-names = "mod", "ahb"; | |
| interrupts = <55>; | |
| resets = <&rst WDT_RESET>; | |
| reset-names = "wdt_rst"; | |
| timeout-sec = <30>; | |
| alphascale,mode = "hw"; | |
| }; |
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| * Altera Arria10 Development Kit System Resource Chip | |
| Required parent device properties: | |
| - compatible : "altr,a10sr" | |
| - spi-max-frequency : Maximum SPI frequency. | |
| - reg : The SPI Chip Select address for the Arria10 | |
| System Resource chip | |
| - interrupts : The interrupt line the device is connected to. | |
| - interrupt-controller : Marks the device node as an interrupt controller. | |
| - #interrupt-cells : The number of cells to describe an IRQ, should be 2. | |
| The first cell is the IRQ number. | |
| The second cell is the flags, encoded as trigger | |
| masks from ../interrupt-controller/interrupts.txt. | |
| The A10SR consists of these sub-devices: | |
| Device Description | |
| ------ ---------- | |
| a10sr_gpio GPIO Controller | |
| a10sr_rst Reset Controller | |
| Arria10 GPIO | |
| Required Properties: | |
| - compatible : Should be "altr,a10sr-gpio" | |
| - gpio-controller : Marks the device node as a GPIO Controller. | |
| - #gpio-cells : Should be two. The first cell is the pin number and | |
| the second cell is used to specify flags. | |
| See ../gpio/gpio.txt for more information. | |
| Arria10 Peripheral PHY Reset | |
| Required Properties: | |
| - compatible : Should be "altr,a10sr-reset" | |
| - #reset-cells : Should be one. | |
| Example: | |
| resource-manager@0 { | |
| compatible = "altr,a10sr"; | |
| reg = <0>; | |
| spi-max-frequency = <100000>; | |
| interrupt-parent = <&portb>; | |
| interrupts = <5 IRQ_TYPE_LEVEL_LOW>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| a10sr_gpio: gpio-controller { | |
| compatible = "altr,a10sr-gpio"; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| }; | |
| a10sr_rst: reset-controller { | |
| compatible = "altr,a10sr-reset"; | |
| #reset-cells = <1>; | |
| }; | |
| }; |
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| Altera FPGA To SDRAM Bridge Driver | |
| Required properties: | |
| - compatible : Should contain "altr,socfpga-fpga2sdram-bridge" | |
| See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings. | |
| Example: | |
| fpga_bridge3: fpga-bridge@ffc25080 { | |
| compatible = "altr,socfpga-fpga2sdram-bridge"; | |
| reg = <0xffc25080 0x4>; | |
| bridge-enable = <0>; | |
| }; |
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| Altera Freeze Bridge Controller Driver | |
| The Altera Freeze Bridge Controller manages one or more freeze bridges. | |
| The controller can freeze/disable the bridges which prevents signal | |
| changes from passing through the bridge. The controller can also | |
| unfreeze/enable the bridges which allows traffic to pass through the | |
| bridge normally. | |
| Required properties: | |
| - compatible : Should contain "altr,freeze-bridge-controller" | |
| - regs : base address and size for freeze bridge module | |
| See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings. | |
| Example: | |
| freeze-controller@100000450 { | |
| compatible = "altr,freeze-bridge-controller"; | |
| regs = <0x1000 0x10>; | |
| bridge-enable = <0>; | |
| }; |
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| Altera FPGA/HPS Bridge Driver | |
| Required properties: | |
| - regs : base address and size for AXI bridge module | |
| - compatible : Should contain one of: | |
| "altr,socfpga-lwhps2fpga-bridge", | |
| "altr,socfpga-hps2fpga-bridge", or | |
| "altr,socfpga-fpga2hps-bridge" | |
| - resets : Phandle and reset specifier for this bridge's reset | |
| - clocks : Clocks used by this module. | |
| See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings. | |
| Example: | |
| fpga_bridge0: fpga-bridge@ff400000 { | |
| compatible = "altr,socfpga-lwhps2fpga-bridge"; | |
| reg = <0xff400000 0x100000>; | |
| resets = <&rst LWHPS2FPGA_RESET>; | |
| clocks = <&l4_main_clk>; | |
| bridge-enable = <0>; | |
| }; | |
| fpga_bridge1: fpga-bridge@ff500000 { | |
| compatible = "altr,socfpga-hps2fpga-bridge"; | |
| reg = <0xff500000 0x10000>; | |
| resets = <&rst HPS2FPGA_RESET>; | |
| clocks = <&l4_main_clk>; | |
| bridge-enable = <1>; | |
| }; | |
| fpga_bridge2: fpga-bridge@ff600000 { | |
| compatible = "altr,socfpga-fpga2hps-bridge"; | |
| reg = <0xff600000 0x100000>; | |
| resets = <&rst FPGA2HPS_RESET>; | |
| clocks = <&l4_main_clk>; | |
| }; |
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| Altera Mailbox Driver | |
| ===================== | |
| Required properties: | |
| - compatible : "altr,mailbox-1.0". | |
| - reg : physical base address of the mailbox and length of | |
| memory mapped region. | |
| - #mbox-cells: Common mailbox binding property to identify the number | |
| of cells required for the mailbox specifier. Should be 1. | |
| Optional properties: | |
| - interrupts : interrupt number. The interrupt specifier format | |
| depends on the interrupt controller parent. | |
| Example: | |
| mbox_tx: mailbox@100 { | |
| compatible = "altr,mailbox-1.0"; | |
| reg = <0x100 0x8>; | |
| interrupt-parent = < &gic_0 >; | |
| interrupts = <5>; | |
| #mbox-cells = <1>; | |
| }; | |
| mbox_rx: mailbox@200 { | |
| compatible = "altr,mailbox-1.0"; | |
| reg = <0x200 0x8>; | |
| interrupt-parent = < &gic_0 >; | |
| interrupts = <6>; | |
| #mbox-cells = <1>; | |
| }; | |
| Mailbox client | |
| =============== | |
| "mboxes" and the optional "mbox-names" (please see | |
| Documentation/devicetree/bindings/mailbox/mailbox.txt for details). Each value | |
| of the mboxes property should contain a phandle to the mailbox controller | |
| device node and second argument is the channel index. It must be 0 (hardware | |
| support only one channel).The equivalent "mbox-names" property value can be | |
| used to give a name to the communication channel to be used by the client user. | |
| Example: | |
| mclient0: mclient0@400 { | |
| compatible = "client-1.0"; | |
| reg = <0x400 0x10>; | |
| mbox-names = "mbox-tx", "mbox-rx"; | |
| mboxes = <&mbox_tx 0>, | |
| <&mbox_rx 0>; | |
| }; |
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| Altera Passive Serial SPI FPGA Manager | |
| Altera FPGAs support a method of loading the bitstream over what is | |
| referred to as "passive serial". | |
| The passive serial link is not technically SPI, and might require extra | |
| circuits in order to play nicely with other SPI slaves on the same bus. | |
| See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf | |
| Required properties: | |
| - compatible: Must be one of the following: | |
| "altr,fpga-passive-serial", | |
| "altr,fpga-arria10-passive-serial" | |
| - reg: SPI chip select of the FPGA | |
| - nconfig-gpios: config pin (referred to as nCONFIG in the manual) | |
| - nstat-gpios: status pin (referred to as nSTATUS in the manual) | |
| Optional properties: | |
| - confd-gpios: confd pin (referred to as CONF_DONE in the manual) | |
| Example: | |
| fpga: fpga@0 { | |
| compatible = "altr,fpga-passive-serial"; | |
| spi-max-frequency = <20000000>; | |
| reg = <0>; | |
| nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; | |
| nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; | |
| confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; | |
| }; |
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| * Altera PCIe MSI controller | |
| Required properties: | |
| - compatible: should contain "altr,msi-1.0" | |
| - reg: specifies the physical base address of the controller and | |
| the length of the memory mapped region. | |
| - reg-names: must include the following entries: | |
| "csr": CSR registers | |
| "vector_slave": vectors slave port region | |
| - interrupts: specifies the interrupt source of the parent interrupt | |
| controller. The format of the interrupt specifier depends on the | |
| parent interrupt controller. | |
| - num-vectors: number of vectors, range 1 to 32. | |
| - msi-controller: indicates that this is MSI controller node | |
| Example | |
| msi0: msi@0xFF200000 { | |
| compatible = "altr,msi-1.0"; | |
| reg = <0xFF200000 0x00000010 | |
| 0xFF200010 0x00000080>; | |
| reg-names = "csr", "vector_slave"; | |
| interrupt-parent = <&hps_0_arm_gic_0>; | |
| interrupts = <0 42 4>; | |
| msi-controller; | |
| num-vectors = <32>; | |
| }; |
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| * Altera PCIe controller | |
| Required properties: | |
| - compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" | |
| - reg: a list of physical base address and length for TXS and CRA. | |
| For "altr,pcie-root-port-2.0", additional HIP base address and length. | |
| - reg-names: must include the following entries: | |
| "Txs": TX slave port region | |
| "Cra": Control register access region | |
| "Hip": Hard IP region (if "altr,pcie-root-port-2.0") | |
| - interrupts: specifies the interrupt source of the parent interrupt | |
| controller. The format of the interrupt specifier depends | |
| on the parent interrupt controller. | |
| - device_type: must be "pci" | |
| - #address-cells: set to <3> | |
| - #size-cells: set to <2> | |
| - #interrupt-cells: set to <1> | |
| - ranges: describes the translation of addresses for root ports and | |
| standard PCI regions. | |
| - interrupt-map-mask and interrupt-map: standard PCI properties to define the | |
| mapping of the PCIe interface to interrupt numbers. | |
| Optional properties: | |
| - msi-parent: Link to the hardware entity that serves as the MSI controller | |
| for this PCIe controller. | |
| - bus-range: PCI bus numbers covered | |
| Example | |
| pcie_0: pcie@c00000000 { | |
| compatible = "altr,pcie-root-port-1.0"; | |
| reg = <0xc0000000 0x20000000>, | |
| <0xff220000 0x00004000>; | |
| reg-names = "Txs", "Cra"; | |
| interrupt-parent = <&hps_0_arm_gic_0>; | |
| interrupts = <0 40 4>; | |
| interrupt-controller; | |
| #interrupt-cells = <1>; | |
| bus-range = <0x0 0xFF>; | |
| device_type = "pci"; | |
| msi-parent = <&msi_to_gic_gen_0>; | |
| #address-cells = <3>; | |
| #size-cells = <2>; | |
| interrupt-map-mask = <0 0 0 7>; | |
| interrupt-map = <0 0 0 1 &pcie_0 1>, | |
| <0 0 0 2 &pcie_0 2>, | |
| <0 0 0 3 &pcie_0 3>, | |
| <0 0 0 4 &pcie_0 4>; | |
| ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000 | |
| 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>; | |
| }; |
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| Altera Arria10 Partial Reconfiguration IP | |
| Required properties: | |
| - compatible : should contain "altr,a10-pr-ip" | |
| - reg : base address and size for memory mapped io. | |
| Example: | |
| fpga_mgr: fpga-mgr@ff20c000 { | |
| compatible = "altr,a10-pr-ip"; | |
| reg = <0xff20c000 0x10>; | |
| }; |
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| Altera SOCFPGA Arria10 FPGA Manager | |
| Required properties: | |
| - compatible : should contain "altr,socfpga-a10-fpga-mgr" | |
| - reg : base address and size for memory mapped io. | |
| - The first index is for FPGA manager register access. | |
| - The second index is for writing FPGA configuration data. | |
| - resets : Phandle and reset specifier for the device's reset. | |
| - clocks : Clocks used by the device. | |
| Example: | |
| fpga_mgr: fpga-mgr@ffd03000 { | |
| compatible = "altr,socfpga-a10-fpga-mgr"; | |
| reg = <0xffd03000 0x100 | |
| 0xffcfe400 0x20>; | |
| clocks = <&l4_mp_clk>; | |
| resets = <&rst FPGAMGR_RESET>; | |
| }; |
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| Altera SOCFPGA FPGA Manager | |
| Required properties: | |
| - compatible : should contain "altr,socfpga-fpga-mgr" | |
| - reg : base address and size for memory mapped io. | |
| - The first index is for FPGA manager register access. | |
| - The second index is for writing FPGA configuration data. | |
| - interrupts : interrupt for the FPGA Manager device. | |
| Example: | |
| hps_0_fpgamgr: fpgamgr@ff706000 { | |
| compatible = "altr,socfpga-fpga-mgr"; | |
| reg = <0xFF706000 0x1000 | |
| 0xFFB90000 0x1000>; | |
| interrupts = <0 175 4>; | |
| }; |
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| Altera JTAG UART | |
| Required properties: | |
| - compatible : should be "ALTR,juart-1.0" <DEPRECATED> | |
| - compatible : should be "altr,juart-1.0" |
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| Altera UP PS/2 controller | |
| Required properties: | |
| - compatible : should be "ALTR,ps2-1.0". <DEPRECATED> | |
| - compatible : should be "altr,ps2-1.0". |
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| * Altera Triple-Speed Ethernet MAC driver (TSE) | |
| Required properties: | |
| - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should | |
| be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE. | |
| ALTR is supported for legacy device trees, but is deprecated. | |
| altr should be used for all new designs. | |
| - reg: Address and length of the register set for the device. It contains | |
| the information of registers in the same order as described by reg-names | |
| - reg-names: Should contain the reg names | |
| "control_port": MAC configuration space region | |
| "tx_csr": xDMA Tx dispatcher control and status space region | |
| "tx_desc": MSGDMA Tx dispatcher descriptor space region | |
| "rx_csr" : xDMA Rx dispatcher control and status space region | |
| "rx_desc": MSGDMA Rx dispatcher descriptor space region | |
| "rx_resp": MSGDMA Rx dispatcher response space region | |
| "s1": SGDMA descriptor memory | |
| - interrupts: Should contain the TSE interrupts and it's mode. | |
| - interrupt-names: Should contain the interrupt names | |
| "rx_irq": xDMA Rx dispatcher interrupt | |
| "tx_irq": xDMA Tx dispatcher interrupt | |
| - rx-fifo-depth: MAC receive FIFO buffer depth in bytes | |
| - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes | |
| - phy-mode: See ethernet.txt in the same directory. | |
| - phy-handle: See ethernet.txt in the same directory. | |
| - phy-addr: See ethernet.txt in the same directory. A configuration should | |
| include phy-handle or phy-addr. | |
| - altr,has-supplementary-unicast: | |
| If present, TSE supports additional unicast addresses. | |
| Otherwise additional unicast addresses are not supported. | |
| - altr,has-hash-multicast-filter: | |
| If present, TSE supports a hash based multicast filter. | |
| Otherwise, hash-based multicast filtering is not supported. | |
| - mdio device tree subnode: When the TSE has a phy connected to its local | |
| mdio, there must be device tree subnode with the following | |
| required properties: | |
| - compatible: Must be "altr,tse-mdio". | |
| - #address-cells: Must be <1>. | |
| - #size-cells: Must be <0>. | |
| For each phy on the mdio bus, there must be a node with the following | |
| fields: | |
| - reg: phy id used to communicate to phy. | |
| - device_type: Must be "ethernet-phy". | |
| The MAC address will be determined using the optional properties defined in | |
| ethernet.txt. | |
| Example: | |
| tse_sub_0_eth_tse_0: ethernet@1,00000000 { | |
| compatible = "altr,tse-msgdma-1.0"; | |
| reg = <0x00000001 0x00000000 0x00000400>, | |
| <0x00000001 0x00000460 0x00000020>, | |
| <0x00000001 0x00000480 0x00000020>, | |
| <0x00000001 0x000004A0 0x00000008>, | |
| <0x00000001 0x00000400 0x00000020>, | |
| <0x00000001 0x00000420 0x00000020>; | |
| reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; | |
| interrupt-parent = <&hps_0_arm_gic_0>; | |
| interrupts = <0 41 4>, <0 40 4>; | |
| interrupt-names = "rx_irq", "tx_irq"; | |
| rx-fifo-depth = <2048>; | |
| tx-fifo-depth = <2048>; | |
| address-bits = <48>; | |
| max-frame-size = <1500>; | |
| local-mac-address = [ 00 00 00 00 00 00 ]; | |
| phy-mode = "gmii"; | |
| altr,has-supplementary-unicast; | |
| altr,has-hash-multicast-filter; | |
| phy-handle = <&phy0>; | |
| mdio { | |
| compatible = "altr,tse-mdio"; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| phy0: ethernet-phy@0 { | |
| reg = <0x0>; | |
| device_type = "ethernet-phy"; | |
| }; | |
| phy1: ethernet-phy@1 { | |
| reg = <0x1>; | |
| device_type = "ethernet-phy"; | |
| }; | |
| }; | |
| }; | |
| tse_sub_1_eth_tse_0: ethernet@1,00001000 { | |
| compatible = "altr,tse-msgdma-1.0"; | |
| reg = <0x00000001 0x00001000 0x00000400>, | |
| <0x00000001 0x00001460 0x00000020>, | |
| <0x00000001 0x00001480 0x00000020>, | |
| <0x00000001 0x000014A0 0x00000008>, | |
| <0x00000001 0x00001400 0x00000020>, | |
| <0x00000001 0x00001420 0x00000020>; | |
| reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc"; | |
| interrupt-parent = <&hps_0_arm_gic_0>; | |
| interrupts = <0 43 4>, <0 42 4>; | |
| interrupt-names = "rx_irq", "tx_irq"; | |
| rx-fifo-depth = <2048>; | |
| tx-fifo-depth = <2048>; | |
| address-bits = <48>; | |
| max-frame-size = <1500>; | |
| local-mac-address = [ 00 00 00 00 00 00 ]; | |
| phy-mode = "gmii"; | |
| altr,has-supplementary-unicast; | |
| altr,has-hash-multicast-filter; | |
| phy-handle = <&phy1>; | |
| }; |
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| Altera UART | |
| Required properties: | |
| - compatible : should be "ALTR,uart-1.0" <DEPRECATED> | |
| - compatible : should be "altr,uart-1.0" | |
| Optional properties: | |
| - clock-frequency : frequency of the clock input to the UART |
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| Altera Timer | |
| Required properties: | |
| - compatible : should be "altr,timer-1.0" | |
| - reg : Specifies base physical address and size of the registers. | |
| - interrupts : Should contain the timer interrupt number | |
| - clock-frequency : The frequency of the clock that drives the counter, in Hz. | |
| Example: | |
| timer { | |
| compatible = "altr,timer-1.0"; | |
| reg = <0x00400000 0x00000020>; | |
| interrupt-parent = <&cpu>; | |
| interrupts = <11>; | |
| clock-frequency = <125000000>; | |
| }; |
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| Device Tree Clock bindings for Altera's SoCFPGA platform | |
| This binding uses the common clock binding[1]. | |
| [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| Required properties: | |
| - compatible : shall be one of the following: | |
| "altr,socfpga-pll-clock" - for a PLL clock | |
| "altr,socfpga-perip-clock" - The peripheral clock divided from the | |
| PLL clock. | |
| "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and | |
| can get gated. | |
| - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. | |
| - clocks : shall be the input parent clock phandle for the clock. This is | |
| either an oscillator or a pll output. | |
| - #clock-cells : from common clock binding, shall be set to 0. | |
| Optional properties: | |
| - fixed-divider : If clocks have a fixed divider value, use this property. | |
| - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register | |
| and the bit index. | |
| - div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains | |
| the divider register, bit shift, and width. | |
| - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls | |
| the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second | |
| value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct | |
| hold/delay times that is needed for the SD/MMC CIU clock. The values of both | |
| can be 0-315 degrees, in 45 degree increments. |
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| AM33xx MUSB | |
| ~~~~~~~~~~~~~~~ | |
| - compatible: ti,am33xx-usb | |
| - reg: offset and length of the usbss register sets | |
| - ti,hwmods : must be "usb_otg_hs" | |
| The glue layer contains multiple child nodes. It is required to have | |
| at least a control module node, USB node and a PHY node. The second USB | |
| node and its PHY node are optional. The DMA node is also optional. | |
| Reset module | |
| ~~~~~~~~~~~~ | |
| - compatible: ti,am335x-usb-ctrl-module | |
| - reg: offset and length of the "USB control registers" in the "Control | |
| Module" block. A second offset and length for the USB wake up control | |
| in the same memory block. | |
| - reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for | |
| the USB wake up control register. | |
| USB PHY | |
| ~~~~~~~ | |
| compatible: ti,am335x-usb-phy | |
| reg: offset and length of the "USB PHY" register space | |
| ti,ctrl_mod: reference to the "reset module" node | |
| reg-names: phy | |
| The PHY should have a "phy" alias numbered properly in the alias | |
| node. | |
| USB | |
| ~~~ | |
| - compatible: ti,musb-am33xx | |
| - reg: offset and length of "USB Controller Registers", and offset and | |
| length of "USB Core" register space. | |
| - reg-names: control for the ""USB Controller Registers" and "mc" for | |
| "USB Core" register space | |
| - interrupts: USB interrupt number | |
| - interrupt-names: mc | |
| - dr_mode: Should be one of "host", "peripheral" or "otg". | |
| - mentor,multipoint: Should be "1" indicating the musb controller supports | |
| multipoint. This is a MUSB configuration-specific setting. | |
| - mentor,num-eps: Specifies the number of endpoints. This is also a | |
| MUSB configuration-specific setting. Should be set to "16" | |
| - mentor,ram-bits: Specifies the ram address size. Should be set to "12" | |
| - mentor,power: Should be "500". This signifies the controller can supply up to | |
| 500mA when operating in host mode. | |
| - phys: reference to the USB phy | |
| - dmas: specifies the dma channels | |
| - dma-names: specifies the names of the channels. Use "rxN" for receive | |
| and "txN" for transmit endpoints. N specifies the endpoint number. | |
| The controller should have an "usb" alias numbered properly in the alias | |
| node. | |
| DMA | |
| ~~~ | |
| - compatible: ti,am3359-cppi41 | |
| - reg: offset and length of the following register spaces: USBSS, USB | |
| CPPI DMA Controller, USB CPPI DMA Scheduler, USB Queue Manager | |
| - reg-names: glue, controller, scheduler, queuemgr | |
| - #dma-cells: should be set to 2. The first number represents the | |
| endpoint number (0 … 14 for endpoints 1 … 15 on instance 0 and 15 … 29 | |
| for endpoints 1 … 15 on instance 1). The second number is 0 for RX and | |
| 1 for TX transfers. | |
| - #dma-channels: should be set to 30 representing the 15 endpoints for | |
| each USB instance. | |
| Example: | |
| ~~~~~~~~ | |
| The following example contains all the nodes as used on am335x-evm: | |
| aliases { | |
| usb0 = &usb0; | |
| usb1 = &usb1; | |
| phy0 = &usb0_phy; | |
| phy1 = &usb1_phy; | |
| }; | |
| usb: usb@47400000 { | |
| compatible = "ti,am33xx-usb"; | |
| reg = <0x47400000 0x1000>; | |
| ranges; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ti,hwmods = "usb_otg_hs"; | |
| ctrl_mod: control@44e10000 { | |
| compatible = "ti,am335x-usb-ctrl-module"; | |
| reg = <0x44e10620 0x10 | |
| 0x44e10648 0x4>; | |
| reg-names = "phy_ctrl", "wakeup"; | |
| }; | |
| usb0_phy: usb-phy@47401300 { | |
| compatible = "ti,am335x-usb-phy"; | |
| reg = <0x47401300 0x100>; | |
| reg-names = "phy"; | |
| ti,ctrl_mod = <&ctrl_mod>; | |
| #phy-cells = <0>; | |
| }; | |
| usb0: usb@47401000 { | |
| compatible = "ti,musb-am33xx"; | |
| reg = <0x47401400 0x400 | |
| 0x47401000 0x200>; | |
| reg-names = "mc", "control"; | |
| interrupts = <18>; | |
| interrupt-names = "mc"; | |
| dr_mode = "otg" | |
| mentor,multipoint = <1>; | |
| mentor,num-eps = <16>; | |
| mentor,ram-bits = <12>; | |
| mentor,power = <500>; | |
| phys = <&usb0_phy>; | |
| dmas = <&cppi41dma 0 0 &cppi41dma 1 0 | |
| &cppi41dma 2 0 &cppi41dma 3 0 | |
| &cppi41dma 4 0 &cppi41dma 5 0 | |
| &cppi41dma 6 0 &cppi41dma 7 0 | |
| &cppi41dma 8 0 &cppi41dma 9 0 | |
| &cppi41dma 10 0 &cppi41dma 11 0 | |
| &cppi41dma 12 0 &cppi41dma 13 0 | |
| &cppi41dma 14 0 &cppi41dma 0 1 | |
| &cppi41dma 1 1 &cppi41dma 2 1 | |
| &cppi41dma 3 1 &cppi41dma 4 1 | |
| &cppi41dma 5 1 &cppi41dma 6 1 | |
| &cppi41dma 7 1 &cppi41dma 8 1 | |
| &cppi41dma 9 1 &cppi41dma 10 1 | |
| &cppi41dma 11 1 &cppi41dma 12 1 | |
| &cppi41dma 13 1 &cppi41dma 14 1>; | |
| dma-names = | |
| "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", | |
| "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", | |
| "rx14", "rx15", | |
| "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", | |
| "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", | |
| "tx14", "tx15"; | |
| }; | |
| usb1_phy: usb-phy@47401b00 { | |
| compatible = "ti,am335x-usb-phy"; | |
| reg = <0x47401b00 0x100>; | |
| reg-names = "phy"; | |
| ti,ctrl_mod = <&ctrl_mod>; | |
| #phy-cells = <0>; | |
| }; | |
| usb1: usb@47401800 { | |
| compatible = "ti,musb-am33xx"; | |
| reg = <0x47401c00 0x400 | |
| 0x47401800 0x200>; | |
| reg-names = "mc", "control"; | |
| interrupts = <19>; | |
| interrupt-names = "mc"; | |
| dr_mode = "host" | |
| mentor,multipoint = <1>; | |
| mentor,num-eps = <16>; | |
| mentor,ram-bits = <12>; | |
| mentor,power = <500>; | |
| phys = <&usb1_phy>; | |
| dmas = <&cppi41dma 15 0 &cppi41dma 16 0 | |
| &cppi41dma 17 0 &cppi41dma 18 0 | |
| &cppi41dma 19 0 &cppi41dma 20 0 | |
| &cppi41dma 21 0 &cppi41dma 22 0 | |
| &cppi41dma 23 0 &cppi41dma 24 0 | |
| &cppi41dma 25 0 &cppi41dma 26 0 | |
| &cppi41dma 27 0 &cppi41dma 28 0 | |
| &cppi41dma 29 0 &cppi41dma 15 1 | |
| &cppi41dma 16 1 &cppi41dma 17 1 | |
| &cppi41dma 18 1 &cppi41dma 19 1 | |
| &cppi41dma 20 1 &cppi41dma 21 1 | |
| &cppi41dma 22 1 &cppi41dma 23 1 | |
| &cppi41dma 24 1 &cppi41dma 25 1 | |
| &cppi41dma 26 1 &cppi41dma 27 1 | |
| &cppi41dma 28 1 &cppi41dma 29 1>; | |
| dma-names = | |
| "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", | |
| "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", | |
| "rx14", "rx15", | |
| "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", | |
| "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", | |
| "tx14", "tx15"; | |
| }; | |
| cppi41dma: dma-controller@7402000 { | |
| compatible = "ti,am3359-cppi41"; | |
| reg = <0x47400000 0x1000 | |
| 0x47402000 0x1000 | |
| 0x47403000 0x1000 | |
| 0x47404000 0x4000>; | |
| reg-names = "glue", "controller", "scheduler", "queuemgr"; | |
| interrupts = <17>; | |
| interrupt-names = "glue"; | |
| #dma-cells = <2>; | |
| #dma-channels = <30>; | |
| #dma-requests = <256>; | |
| }; | |
| }; |
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| Amazon's Annapurna Labs Fabric Interrupt Controller | |
| Required properties: | |
| - compatible: should be "amazon,al-fic" | |
| - reg: physical base address and size of the registers | |
| - interrupt-controller: identifies the node as an interrupt controller | |
| - #interrupt-cells : must be 2. Specifies the number of cells needed to encode | |
| an interrupt source. Supported trigger types are low-to-high edge | |
| triggered and active high level-sensitive. | |
| - interrupts: describes which input line in the interrupt parent, this | |
| fic's output is connected to. This field property depends on the parent's | |
| binding | |
| Please refer to interrupts.txt in this directory for details of the common | |
| Interrupt Controllers bindings used by client devices. | |
| Example: | |
| amazon_fic: interrupt-controller@fd8a8500 { | |
| compatible = "amazon,al-fic"; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| reg = <0x0 0xfd8a8500 0x0 0x1000>; | |
| interrupt-parent = <&gic>; | |
| interrupts = <GIC_SPI 0x0 IRQ_TYPE_LEVEL_HIGH>; | |
| }; |
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| Amazon's Annapurna Labs Thermal Sensor | |
| Simple thermal device that allows temperature reading by a single MMIO | |
| transaction. | |
| Required properties: | |
| - compatible: "amazon,al-thermal". | |
| - reg: The physical base address and length of the sensor's registers. | |
| - #thermal-sensor-cells: Must be 1. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description. | |
| Example: | |
| thermal: thermal { | |
| compatible = "amazon,al-thermal"; | |
| reg = <0x0 0x05002860 0x0 0x1>; | |
| #thermal-sensor-cells = <0x1>; | |
| }; | |
| thermal-zones { | |
| thermal-z0 { | |
| polling-delay-passive = <250>; | |
| polling-delay = <1000>; | |
| thermal-sensors = <&thermal 0>; | |
| trips { | |
| critical { | |
| temperature = <105000>; | |
| hysteresis = <2000>; | |
| type = "critical"; | |
| }; | |
| }; | |
| }; | |
| }; | |
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| * AMD Cryptographic Coprocessor driver (ccp) | |
| Required properties: | |
| - compatible: Should be "amd,ccp-seattle-v1a" | |
| - reg: Address and length of the register set for the device | |
| - interrupts: Should contain the CCP interrupt | |
| Optional properties: | |
| - dma-coherent: Present if dma operations are coherent | |
| Example: | |
| ccp@e0100000 { | |
| compatible = "amd,ccp-seattle-v1a"; | |
| reg = <0 0xe0100000 0 0x10000>; | |
| interrupt-parent = <&gic>; | |
| interrupts = <0 3 4>; | |
| }; |
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| * AMD 10GbE driver (amd-xgbe) | |
| Required properties: | |
| - compatible: Should be "amd,xgbe-seattle-v1a" | |
| - reg: Address and length of the register sets for the device | |
| - MAC registers | |
| - PCS registers | |
| - SerDes Rx/Tx registers | |
| - SerDes integration registers (1/2) | |
| - SerDes integration registers (2/2) | |
| - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt | |
| listed is required and is the general device interrupt. If the optional | |
| amd,per-channel-interrupt property is specified, then one additional | |
| interrupt for each DMA channel supported by the device should be specified. | |
| The last interrupt listed should be the PCS auto-negotiation interrupt. | |
| - clocks: | |
| - DMA clock for the amd-xgbe device (used for calculating the | |
| correct Rx interrupt watchdog timer value on a DMA channel | |
| for coalescing) | |
| - PTP clock for the amd-xgbe device | |
| - clock-names: Should be the names of the clocks | |
| - "dma_clk" for the DMA clock | |
| - "ptp_clk" for the PTP clock | |
| - phy-mode: See ethernet.txt file in the same directory | |
| Optional properties: | |
| - dma-coherent: Present if dma operations are coherent | |
| - amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate | |
| a unique interrupt for each DMA channel - this requires an additional | |
| interrupt be configured for each DMA channel | |
| - amd,speed-set: Speed capabilities of the device | |
| 0 - 1GbE and 10GbE (default) | |
| 1 - 2.5GbE and 10GbE | |
| The MAC address will be determined using the optional properties defined in | |
| ethernet.txt. | |
| The following optional properties are represented by an array with each | |
| value corresponding to a particular speed. The first array value represents | |
| the setting for the 1GbE speed, the second value for the 2.5GbE speed and | |
| the third value for the 10GbE speed. All three values are required if the | |
| property is used. | |
| - amd,serdes-blwc: Baseline wandering correction enablement | |
| 0 - Off | |
| 1 - On | |
| - amd,serdes-cdr-rate: CDR rate speed selection | |
| - amd,serdes-pq-skew: PQ (data sampling) skew | |
| - amd,serdes-tx-amp: TX amplitude boost | |
| - amd,serdes-dfe-tap-config: DFE taps available to run | |
| - amd,serdes-dfe-tap-enable: DFE taps to enable | |
| Example: | |
| xgbe@e0700000 { | |
| compatible = "amd,xgbe-seattle-v1a"; | |
| reg = <0 0xe0700000 0 0x80000>, | |
| <0 0xe0780000 0 0x80000>, | |
| <0 0xe1240800 0 0x00400>, | |
| <0 0xe1250000 0 0x00060>, | |
| <0 0xe1250080 0 0x00004>; | |
| interrupt-parent = <&gic>; | |
| interrupts = <0 325 4>, | |
| <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>, | |
| <0 323 4>; | |
| amd,per-channel-interrupt; | |
| clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; | |
| clock-names = "dma_clk", "ptp_clk"; | |
| phy-mode = "xgmii"; | |
| mac-address = [ 02 a1 a2 a3 a4 a5 ]; | |
| amd,speed-set = <0>; | |
| amd,serdes-blwc = <1>, <1>, <0>; | |
| amd,serdes-cdr-rate = <2>, <2>, <7>; | |
| amd,serdes-pq-skew = <10>, <10>, <30>; | |
| amd,serdes-tx-amp = <15>, <15>, <10>; | |
| amd,serdes-dfe-tap-config = <3>, <3>, <1>; | |
| amd,serdes-dfe-tap-enable = <0>, <0>, <127>; | |
| }; |
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| * Amlogic AXG Audio Clock Controllers | |
| The Amlogic AXG audio clock controller generates and supplies clock to the | |
| other elements of the audio subsystem, such as fifos, i2s, spdif and pdm | |
| devices. | |
| Required Properties: | |
| - compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D, | |
| "amlogic,g12a-audio-clkc" for G12A, | |
| "amlogic,sm1-audio-clkc" for S905X3. | |
| - reg : physical base address of the clock controller and length of | |
| memory mapped region. | |
| - clocks : a list of phandle + clock-specifier pairs for the clocks listed | |
| in clock-names. | |
| - clock-names : must contain the following: | |
| * "pclk" - Main peripheral bus clock | |
| may contain the following: | |
| * "mst_in[0-7]" - 8 input plls to generate clock signals | |
| * "slv_sclk[0-9]" - 10 slave bit clocks provided by external | |
| components. | |
| * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external | |
| components. | |
| - resets : phandle of the internal reset line | |
| - #clock-cells : should be 1. | |
| - #reset-cells : should be 1 on the g12a (and following) soc family | |
| Each clock is assigned an identifier and client nodes can use this identifier | |
| to specify the clock which they consume. All available clocks are defined as | |
| preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be | |
| used in device tree sources. | |
| Example: | |
| clkc_audio: clock-controller@0 { | |
| compatible = "amlogic,axg-audio-clkc"; | |
| reg = <0x0 0x0 0x0 0xb4>; | |
| #clock-cells = <1>; | |
| clocks = <&clkc CLKID_AUDIO>, | |
| <&clkc CLKID_MPLL0>, | |
| <&clkc CLKID_MPLL1>, | |
| <&clkc CLKID_MPLL2>, | |
| <&clkc CLKID_MPLL3>, | |
| <&clkc CLKID_HIFI_PLL>, | |
| <&clkc CLKID_FCLK_DIV3>, | |
| <&clkc CLKID_FCLK_DIV4>, | |
| <&clkc CLKID_GP0_PLL>; | |
| clock-names = "pclk", | |
| "mst_in0", | |
| "mst_in1", | |
| "mst_in2", | |
| "mst_in3", | |
| "mst_in4", | |
| "mst_in5", | |
| "mst_in6", | |
| "mst_in7"; | |
| resets = <&reset RESET_AUDIO>; | |
| }; |
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| * Amlogic Audio FIFO controllers | |
| Required properties: | |
| - compatible: 'amlogic,axg-toddr' or | |
| 'amlogic,axg-toddr' or | |
| 'amlogic,g12a-frddr' or | |
| 'amlogic,g12a-toddr' or | |
| 'amlogic,sm1-frddr' or | |
| 'amlogic,sm1-toddr' | |
| - reg: physical base address of the controller and length of memory | |
| mapped region. | |
| - interrupts: interrupt specifier for the fifo. | |
| - clocks: phandle to the fifo peripheral clock provided by the audio | |
| clock controller. | |
| - resets: list of reset phandle, one for each entry reset-names. | |
| - reset-names: should contain the following: | |
| * "arb" : memory ARB line (required) | |
| * "rst" : dedicated device reset line (optional) | |
| - #sound-dai-cells: must be 0. | |
| - amlogic,fifo-depth: The size of the controller's fifo in bytes. This | |
| is useful for determining certain configuration such | |
| as the flush threshold of the fifo | |
| Example of FRDDR A on the A113 SoC: | |
| frddr_a: audio-controller@1c0 { | |
| compatible = "amlogic,axg-frddr"; | |
| reg = <0x0 0x1c0 0x0 0x1c>; | |
| #sound-dai-cells = <0>; | |
| interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; | |
| clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; | |
| resets = <&arb AXG_ARB_FRDDR_A>; | |
| fifo-depth = <512>; | |
| }; |
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| * Amlogic Audio PDM input | |
| Required properties: | |
| - compatible: 'amlogic,axg-pdm' or | |
| 'amlogic,g12a-pdm' or | |
| 'amlogic,sm1-pdm' | |
| - reg: physical base address of the controller and length of memory | |
| mapped region. | |
| - clocks: list of clock phandle, one for each entry clock-names. | |
| - clock-names: should contain the following: | |
| * "pclk" : peripheral clock. | |
| * "dclk" : pdm digital clock | |
| * "sysclk" : dsp system clock | |
| - #sound-dai-cells: must be 0. | |
| Optional property: | |
| - resets: phandle to the dedicated reset line of the pdm input. | |
| Example of PDM on the A113 SoC: | |
| pdm: audio-controller@ff632000 { | |
| compatible = "amlogic,axg-pdm"; | |
| reg = <0x0 0xff632000 0x0 0x34>; | |
| #sound-dai-cells = <0>; | |
| clocks = <&clkc_audio AUD_CLKID_PDM>, | |
| <&clkc_audio AUD_CLKID_PDM_DCLK>, | |
| <&clkc_audio AUD_CLKID_PDM_SYSCLK>; | |
| clock-names = "pclk", "dclk", "sysclk"; | |
| }; |
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| Amlogic AXG sound card: | |
| Required properties: | |
| - compatible: "amlogic,axg-sound-card" | |
| - model : User specified audio sound card name, one string | |
| Optional properties: | |
| - audio-aux-devs : List of phandles pointing to auxiliary devices | |
| - audio-widgets : Please refer to widgets.txt. | |
| - audio-routing : A list of the connections between audio components. | |
| Subnodes: | |
| - dai-link: Container for dai-link level properties and the CODEC | |
| sub-nodes. There should be at least one (and probably more) | |
| subnode of this type. | |
| Required dai-link properties: | |
| - sound-dai: phandle and port of the CPU DAI. | |
| Required TDM Backend dai-link properties: | |
| - dai-format : CPU/CODEC common audio format | |
| Optional TDM Backend dai-link properties: | |
| - dai-tdm-slot-rx-mask-{0,1,2,3}: Receive direction slot masks | |
| - dai-tdm-slot-tx-mask-{0,1,2,3}: Transmit direction slot masks | |
| When omitted, mask is assumed to have to no | |
| slots. A valid must have at one slot, so at | |
| least one these mask should be provided with | |
| an enabled slot. | |
| - dai-tdm-slot-num : Please refer to tdm-slot.txt. | |
| If omitted, slot number is set to accommodate the largest | |
| mask provided. | |
| - dai-tdm-slot-width : Please refer to tdm-slot.txt. default to 32 if omitted. | |
| - mclk-fs : Multiplication factor between stream rate and mclk | |
| Backend dai-link subnodes: | |
| - codec: dai-link representing backend links should have at least one subnode. | |
| One subnode for each codec of the dai-link. | |
| dai-link representing frontend links have no codec, therefore have no | |
| subnodes | |
| Required codec subnodes properties: | |
| - sound-dai: phandle and port of the CODEC DAI. | |
| Optional codec subnodes properties: | |
| - dai-tdm-slot-tx-mask : Please refer to tdm-slot.txt. | |
| - dai-tdm-slot-rx-mask : Please refer to tdm-slot.txt. | |
| Example: | |
| sound { | |
| compatible = "amlogic,axg-sound-card"; | |
| model = "AXG-S420"; | |
| audio-aux-devs = <&tdmin_a>, <&tdmout_c>; | |
| audio-widgets = "Line", "Lineout", | |
| "Line", "Linein", | |
| "Speaker", "Speaker1 Left", | |
| "Speaker", "Speaker1 Right"; | |
| "Speaker", "Speaker2 Left", | |
| "Speaker", "Speaker2 Right"; | |
| audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2", | |
| "SPDIFOUT IN 0", "FRDDR_A OUT 3", | |
| "TDM_C Playback", "TDMOUT_C OUT", | |
| "TDMIN_A IN 2", "TDM_C Capture", | |
| "TDMIN_A IN 5", "TDM_C Loopback", | |
| "TODDR_A IN 0", "TDMIN_A OUT", | |
| "Lineout", "Lineout AOUTL", | |
| "Lineout", "Lineout AOUTR", | |
| "Speaker1 Left", "SPK1 OUT_A", | |
| "Speaker2 Left", "SPK2 OUT_A", | |
| "Speaker1 Right", "SPK1 OUT_B", | |
| "Speaker2 Right", "SPK2 OUT_B", | |
| "Linein AINL", "Linein", | |
| "Linein AINR", "Linein"; | |
| dai-link@0 { | |
| sound-dai = <&frddr_a>; | |
| }; | |
| dai-link@1 { | |
| sound-dai = <&toddr_a>; | |
| }; | |
| dai-link@2 { | |
| sound-dai = <&tdmif_c>; | |
| dai-format = "i2s"; | |
| dai-tdm-slot-tx-mask-2 = <1 1>; | |
| dai-tdm-slot-tx-mask-3 = <1 1>; | |
| dai-tdm-slot-rx-mask-1 = <1 1>; | |
| mclk-fs = <256>; | |
| codec@0 { | |
| sound-dai = <&lineout>; | |
| }; | |
| codec@1 { | |
| sound-dai = <&speaker_amp1>; | |
| }; | |
| codec@2 { | |
| sound-dai = <&speaker_amp2>; | |
| }; | |
| codec@3 { | |
| sound-dai = <&linein>; | |
| }; | |
| }; | |
| dai-link@3 { | |
| sound-dai = <&spdifout>; | |
| codec { | |
| sound-dai = <&spdif_dit>; | |
| }; | |
| }; | |
| }; |
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| * Amlogic Audio SPDIF Input | |
| Required properties: | |
| - compatible: 'amlogic,axg-spdifin' or | |
| 'amlogic,g12a-spdifin' or | |
| 'amlogic,sm1-spdifin' | |
| - interrupts: interrupt specifier for the spdif input. | |
| - clocks: list of clock phandle, one for each entry clock-names. | |
| - clock-names: should contain the following: | |
| * "pclk" : peripheral clock. | |
| * "refclk" : spdif input reference clock | |
| - #sound-dai-cells: must be 0. | |
| Optional property: | |
| - resets: phandle to the dedicated reset line of the spdif input. | |
| Example on the A113 SoC: | |
| spdifin: audio-controller@400 { | |
| compatible = "amlogic,axg-spdifin"; | |
| reg = <0x0 0x400 0x0 0x30>; | |
| #sound-dai-cells = <0>; | |
| interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; | |
| clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, | |
| <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; | |
| clock-names = "pclk", "refclk"; | |
| }; |
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| * Amlogic Audio SPDIF Output | |
| Required properties: | |
| - compatible: 'amlogic,axg-spdifout' or | |
| 'amlogic,g12a-spdifout' or | |
| 'amlogic,sm1-spdifout' | |
| - clocks: list of clock phandle, one for each entry clock-names. | |
| - clock-names: should contain the following: | |
| * "pclk" : peripheral clock. | |
| * "mclk" : master clock | |
| - #sound-dai-cells: must be 0. | |
| Optional property: | |
| - resets: phandle to the dedicated reset line of the spdif output. | |
| Example on the A113 SoC: | |
| spdifout: audio-controller@480 { | |
| compatible = "amlogic,axg-spdifout"; | |
| reg = <0x0 0x480 0x0 0x50>; | |
| #sound-dai-cells = <0>; | |
| clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, | |
| <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; | |
| clock-names = "pclk", "mclk"; | |
| }; |
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| * Amlogic Audio TDM formatters | |
| Required properties: | |
| - compatible: 'amlogic,axg-tdmin' or | |
| 'amlogic,axg-tdmout' or | |
| 'amlogic,g12a-tdmin' or | |
| 'amlogic,g12a-tdmout' or | |
| 'amlogic,sm1-tdmin' or | |
| 'amlogic,sm1-tdmout | |
| - reg: physical base address of the controller and length of memory | |
| mapped region. | |
| - clocks: list of clock phandle, one for each entry clock-names. | |
| - clock-names: should contain the following: | |
| * "pclk" : peripheral clock. | |
| * "sclk" : bit clock. | |
| * "sclk_sel" : bit clock input multiplexer. | |
| * "lrclk" : sample clock | |
| * "lrclk_sel": sample clock input multiplexer | |
| Optional property: | |
| - resets: phandle to the dedicated reset line of the tdm formatter. | |
| Example of TDMOUT_A on the S905X2 SoC: | |
| tdmout_a: audio-controller@500 { | |
| compatible = "amlogic,axg-tdmout"; | |
| reg = <0x0 0x500 0x0 0x40>; | |
| resets = <&clkc_audio AUD_RESET_TDMOUT_A>; | |
| clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, | |
| <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, | |
| <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, | |
| <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, | |
| <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; | |
| clock-names = "pclk", "sclk", "sclk_sel", | |
| "lrclk", "lrclk_sel"; | |
| }; |
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| * Amlogic Audio TDM Interfaces | |
| Required properties: | |
| - compatible: 'amlogic,axg-tdm-iface' | |
| - clocks: list of clock phandle, one for each entry clock-names. | |
| - clock-names: should contain the following: | |
| * "sclk" : bit clock. | |
| * "lrclk": sample clock | |
| * "mclk" : master clock | |
| -> optional if the interface is in clock slave mode. | |
| - #sound-dai-cells: must be 0. | |
| Example of TDM_A on the A113 SoC: | |
| tdmif_a: audio-controller@0 { | |
| compatible = "amlogic,axg-tdm-iface"; | |
| #sound-dai-cells = <0>; | |
| clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, | |
| <&clkc_audio AUD_CLKID_MST_A_SCLK>, | |
| <&clkc_audio AUD_CLKID_MST_A_LRCLK>; | |
| clock-names = "mclk", "sclk", "lrclk"; | |
| }; |
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| * Amlogic HDMI Tx control glue | |
| Required properties: | |
| - compatible: "amlogic,g12a-tohdmitx" or | |
| "amlogic,sm1-tohdmitx" | |
| - reg: physical base address of the controller and length of memory | |
| mapped region. | |
| - #sound-dai-cells: should be 1. | |
| - resets: phandle to the dedicated reset line of the hdmitx glue. | |
| Example on the S905X2 SoC: | |
| tohdmitx: audio-controller@744 { | |
| compatible = "amlogic,g12a-tohdmitx"; | |
| reg = <0x0 0x744 0x0 0x4>; | |
| #sound-dai-cells = <1>; | |
| resets = <&clkc_audio AUD_RESET_TOHDMITX>; | |
| }; | |
| Example of an 'amlogic,axg-sound-card': | |
| sound { | |
| compatible = "amlogic,axg-sound-card"; | |
| [...] | |
| dai-link-x { | |
| sound-dai = <&tdmif_a>; | |
| dai-format = "i2s"; | |
| dai-tdm-slot-tx-mask-0 = <1 1>; | |
| codec-0 { | |
| sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; | |
| }; | |
| codec-1 { | |
| sound-dai = <&external_dac>; | |
| }; | |
| }; | |
| dai-link-y { | |
| sound-dai = <&tdmif_c>; | |
| dai-format = "i2s"; | |
| dai-tdm-slot-tx-mask-0 = <1 1>; | |
| codec { | |
| sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>; | |
| }; | |
| }; | |
| dai-link-z { | |
| sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; | |
| codec { | |
| sound-dai = <&hdmi_tx>; | |
| }; | |
| }; | |
| }; |
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| * Amlogic GXBB AO Clock and Reset Unit | |
| The Amlogic GXBB AO clock controller generates and supplies clock to various | |
| controllers within the Always-On part of the SoC. | |
| Required Properties: | |
| - compatible: value should be different for each SoC family as : | |
| - GXBB (S905) : "amlogic,meson-gxbb-aoclkc" | |
| - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc" | |
| - GXM (S912) : "amlogic,meson-gxm-aoclkc" | |
| - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc" | |
| - G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc" | |
| followed by the common "amlogic,meson-gx-aoclkc" | |
| - clocks: list of clock phandle, one for each entry clock-names. | |
| - clock-names: should contain the following: | |
| * "xtal" : the platform xtal | |
| * "mpeg-clk" : the main clock controller mother clock (aka clk81) | |
| * "ext-32k-0" : external 32kHz reference #0 if any (optional) | |
| * "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only) | |
| * "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only) | |
| - #clock-cells: should be 1. | |
| Each clock is assigned an identifier and client nodes can use this identifier | |
| to specify the clock which they consume. All available clocks are defined as | |
| preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be | |
| used in device tree sources. | |
| - #reset-cells: should be 1. | |
| Each reset is assigned an identifier and client nodes can use this identifier | |
| to specify the reset which they consume. All available resets are defined as | |
| preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be | |
| used in device tree sources. | |
| Parent node should have the following properties : | |
| - compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd" | |
| - reg: base address and size of the AO system control register space. | |
| Example: AO Clock controller node: | |
| ao_sysctrl: sys-ctrl@0 { | |
| compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; | |
| reg = <0x0 0x0 0x0 0x100>; | |
| clkc_AO: clock-controller { | |
| compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc"; | |
| #clock-cells = <1>; | |
| #reset-cells = <1>; | |
| clocks = <&xtal>, <&clkc CLKID_CLK81>; | |
| clock-names = "xtal", "mpeg-clk"; | |
| }; | |
| Example: UART controller node that consumes the clock and reset generated | |
| by the clock controller: | |
| uart_AO: serial@4c0 { | |
| compatible = "amlogic,meson-uart"; | |
| reg = <0x4c0 0x14>; | |
| interrupts = <0 90 1>; | |
| clocks = <&clkc_AO CLKID_AO_UART1>; | |
| resets = <&clkc_AO RESET_AO_UART1>; | |
| }; |
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| * Amlogic GXBB Clock and Reset Unit | |
| The Amlogic GXBB clock controller generates and supplies clock to various | |
| controllers within the SoC. | |
| Required Properties: | |
| - compatible: should be: | |
| "amlogic,gxbb-clkc" for GXBB SoC, | |
| "amlogic,gxl-clkc" for GXL and GXM SoC, | |
| "amlogic,axg-clkc" for AXG SoC. | |
| "amlogic,g12a-clkc" for G12A SoC. | |
| "amlogic,g12b-clkc" for G12B SoC. | |
| "amlogic,sm1-clkc" for SM1 SoC. | |
| - clocks : list of clock phandle, one for each entry clock-names. | |
| - clock-names : should contain the following: | |
| * "xtal": the platform xtal | |
| - #clock-cells: should be 1. | |
| Each clock is assigned an identifier and client nodes can use this identifier | |
| to specify the clock which they consume. All available clocks are defined as | |
| preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be | |
| used in device tree sources. | |
| Parent node should have the following properties : | |
| - compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or | |
| "amlogic,meson-axg-hhi-sysctrl" | |
| - reg: base address and size of the HHI system control register space. | |
| Example: Clock controller node: | |
| sysctrl: system-controller@0 { | |
| compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd"; | |
| reg = <0 0 0 0x400>; | |
| clkc: clock-controller { | |
| #clock-cells = <1>; | |
| compatible = "amlogic,gxbb-clkc"; | |
| clocks = <&xtal>; | |
| clock-names = "xtal"; | |
| }; | |
| }; | |
| Example: UART controller node that consumes the clock generated by the clock | |
| controller: | |
| uart_AO: serial@c81004c0 { | |
| compatible = "amlogic,meson-uart"; | |
| reg = <0xc81004c0 0x14>; | |
| interrupts = <0 90 1>; | |
| clocks = <&clkc CLKID_CLK81>; | |
| }; |
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| * Amlogic audio memory arbiter controller | |
| The Amlogic Audio ARB is a simple device which enables or | |
| disables the access of Audio FIFOs to DDR on AXG based SoC. | |
| Required properties: | |
| - compatible: 'amlogic,meson-axg-audio-arb' or | |
| 'amlogic,meson-sm1-audio-arb' | |
| - reg: physical base address of the controller and length of memory | |
| mapped region. | |
| - clocks: phandle to the fifo peripheral clock provided by the audio | |
| clock controller. | |
| - #reset-cells: must be 1. | |
| Example on the A113 SoC: | |
| arb: reset-controller@280 { | |
| compatible = "amlogic,meson-axg-audio-arb"; | |
| reg = <0x0 0x280 0x0 0x4>; | |
| #reset-cells = <1>; | |
| clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; | |
| }; |
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| Amlogic meson GPIO interrupt controller | |
| Meson SoCs contains an interrupt controller which is able to watch the SoC | |
| pads and generate an interrupt on edge or level. The controller is essentially | |
| a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge | |
| or level and polarity. It does not expose all 256 mux inputs because the | |
| documentation shows that the upper part is not mapped to any pad. The actual | |
| number of interrupt exposed depends on the SoC. | |
| Required properties: | |
| - compatible : must have "amlogic,meson8-gpio-intc" and either | |
| "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or | |
| "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or | |
| "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or | |
| "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912) | |
| "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X) | |
| "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2) | |
| "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3) | |
| "amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L) | |
| - reg : Specifies base physical address and size of the registers. | |
| - interrupt-controller : Identifies the node as an interrupt controller. | |
| - #interrupt-cells : Specifies the number of cells needed to encode an | |
| interrupt source. The value must be 2. | |
| - meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These | |
| are the hwirqs used on the parent interrupt controller. | |
| Example: | |
| gpio_interrupt: interrupt-controller@9880 { | |
| compatible = "amlogic,meson-gxbb-gpio-intc", | |
| "amlogic,meson-gpio-intc"; | |
| reg = <0x0 0x9880 0x0 0x10>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| meson,channel-interrupts = <64 65 66 67 68 69 70 71>; | |
| }; |
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| Amlogic Meson Power Controller | |
| ============================== | |
| The Amlogic Meson SoCs embeds an internal Power domain controller. | |
| VPU Power Domain | |
| ---------------- | |
| The Video Processing Unit power domain is controlled by this power controller, | |
| but the domain requires some external resources to meet the correct power | |
| sequences. | |
| The bindings must respect the power domain bindings as described in the file | |
| power-domain.yaml | |
| Device Tree Bindings: | |
| --------------------- | |
| Required properties: | |
| - compatible: should be one of the following : | |
| - "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs | |
| - "amlogic,meson-g12a-pwrc-vpu" for the Meson G12A SoCs | |
| - #power-domain-cells: should be 0 | |
| - amlogic,hhi-sysctrl: phandle to the HHI sysctrl node | |
| - resets: phandles to the reset lines needed for this power demain sequence | |
| as described in ../reset/reset.txt | |
| - clocks: from common clock binding: handle to VPU and VAPB clocks | |
| - clock-names: from common clock binding: must contain "vpu", "vapb" | |
| corresponding to entry in the clocks property. | |
| Parent node should have the following properties : | |
| - compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd" | |
| - reg: base address and size of the AO system control register space. | |
| Example: | |
| ------- | |
| ao_sysctrl: sys-ctrl@0 { | |
| compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; | |
| reg = <0x0 0x0 0x0 0x100>; | |
| pwrc_vpu: power-controller-vpu { | |
| compatible = "amlogic,meson-gx-pwrc-vpu"; | |
| #power-domain-cells = <0>; | |
| amlogic,hhi-sysctrl = <&sysctrl>; | |
| resets = <&reset RESET_VIU>, | |
| <&reset RESET_VENC>, | |
| <&reset RESET_VCBUS>, | |
| <&reset RESET_BT656>, | |
| <&reset RESET_DVIN_RESET>, | |
| <&reset RESET_RDMA>, | |
| <&reset RESET_VENCI>, | |
| <&reset RESET_VENCP>, | |
| <&reset RESET_VDAC>, | |
| <&reset RESET_VDI6>, | |
| <&reset RESET_VENCL>, | |
| <&reset RESET_VID_LOCK>; | |
| clocks = <&clkc CLKID_VPU>, | |
| <&clkc CLKID_VAPB>; | |
| clock-names = "vpu", "vapb"; | |
| }; | |
| }; | |
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| Amlogic SD / eMMC controller for S905/GXBB family SoCs | |
| The MMC 5.1 compliant host controller on Amlogic provides the | |
| interface for SD, eMMC and SDIO devices. | |
| This file documents the properties in addition to those available in | |
| the MMC core bindings, documented by mmc.txt. | |
| Required properties: | |
| - compatible : contains one of: | |
| - "amlogic,meson-gx-mmc" | |
| - "amlogic,meson-gxbb-mmc" | |
| - "amlogic,meson-gxl-mmc" | |
| - "amlogic,meson-gxm-mmc" | |
| - "amlogic,meson-axg-mmc" | |
| - clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names. | |
| - clock-names: Should contain the following: | |
| "core" - Main peripheral bus clock | |
| "clkin0" - Parent clock of internal mux | |
| "clkin1" - Other parent clock of internal mux | |
| The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the | |
| clock rate requested by the MMC core. | |
| - resets : phandle of the internal reset line | |
| Optional properties: | |
| - amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the | |
| DRAM memory, like on the G12A dedicated SDIO controller. | |
| Example: | |
| sd_emmc_a: mmc@70000 { | |
| compatible = "amlogic,meson-gxbb-mmc"; | |
| reg = <0x0 0x70000 0x0 0x2000>; | |
| interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; | |
| clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>; | |
| clock-names = "core", "clkin0", "clkin1"; | |
| pinctrl-0 = <&emmc_pins>; | |
| resets = <&reset RESET_SD_EMMC_A>; | |
| }; |
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| * Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller | |
| The highspeed MMC host controller on Amlogic SoCs provides an interface | |
| for MMC, SD, SDIO and SDHC types of memory cards. | |
| Supported maximum speeds are the ones of the eMMC standard 4.41 as well | |
| as the speed of SD standard 2.0. | |
| The hardware provides an internal "mux" which allows up to three slots | |
| to be controlled. Only one slot can be accessed at a time. | |
| Required properties: | |
| - compatible : must be one of | |
| - "amlogic,meson8-sdio" | |
| - "amlogic,meson8b-sdio" | |
| along with the generic "amlogic,meson-mx-sdio" | |
| - reg : mmc controller base registers | |
| - interrupts : mmc controller interrupt | |
| - #address-cells : must be 1 | |
| - size-cells : must be 0 | |
| - clocks : phandle to clock providers | |
| - clock-names : must contain "core" and "clkin" | |
| Required child nodes: | |
| A node for each slot provided by the MMC controller is required. | |
| NOTE: due to a driver limitation currently only one slot (= child node) | |
| is supported! | |
| Required properties on each child node (= slot): | |
| - compatible : must be "mmc-slot" (see mmc.txt within this directory) | |
| - reg : the slot (or "port") ID | |
| Optional properties on each child node (= slot): | |
| - bus-width : must be 1 or 4 (8-bit bus is not supported) | |
| - for cd and all other additional generic mmc parameters | |
| please refer to mmc.txt within this directory | |
| Examples: | |
| mmc@c1108c20 { | |
| compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; | |
| reg = <0xc1108c20 0x20>; | |
| interrupts = <0 28 1>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; | |
| clock-names = "core", "clkin"; | |
| slot@1 { | |
| compatible = "mmc-slot"; | |
| reg = <1>; | |
| bus-width = <4>; | |
| }; | |
| }; |
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| Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs | |
| This file documents the properties in addition to those available in | |
| the MTD NAND bindings. | |
| Required properties: | |
| - compatible : contains one of: | |
| - "amlogic,meson-gxl-nfc" | |
| - "amlogic,meson-axg-nfc" | |
| - clocks : | |
| A list of phandle + clock-specifier pairs for the clocks listed | |
| in clock-names. | |
| - clock-names: Should contain the following: | |
| "core" - NFC module gate clock | |
| "device" - device clock from eMMC sub clock controller | |
| "rx" - rx clock phase | |
| "tx" - tx clock phase | |
| - amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC | |
| controller port C | |
| Optional children nodes: | |
| Children nodes represent the available nand chips. | |
| Other properties: | |
| see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings. | |
| Example demonstrate on AXG SoC: | |
| sd_emmc_c_clkc: mmc@7000 { | |
| compatible = "amlogic,meson-axg-mmc-clkc", "syscon"; | |
| reg = <0x0 0x7000 0x0 0x800>; | |
| }; | |
| nand-controller@7800 { | |
| compatible = "amlogic,meson-axg-nfc"; | |
| reg = <0x0 0x7800 0x0 0x100>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; | |
| clocks = <&clkc CLKID_SD_EMMC_C>, | |
| <&sd_emmc_c_clkc CLKID_MMC_DIV>, | |
| <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>, | |
| <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>; | |
| clock-names = "core", "device", "rx", "tx"; | |
| amlogic,mmc-syscon = <&sd_emmc_c_clkc>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&nand_pins>; | |
| nand@0 { | |
| reg = <0>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| nand-on-flash-bbt; | |
| }; | |
| }; |
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| Amlogic Meson AXG DWC PCIE SoC controller | |
| Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. | |
| It shares common functions with the PCIe DesignWare core driver and | |
| inherits common properties defined in | |
| Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. | |
| Additional properties are described here: | |
| Required properties: | |
| - compatible: | |
| should contain : | |
| - "amlogic,axg-pcie" for AXG SoC Family | |
| - "amlogic,g12a-pcie" for G12A SoC Family | |
| to identify the core. | |
| - reg: | |
| should contain the configuration address space. | |
| - reg-names: Must be | |
| - "elbi" External local bus interface registers | |
| - "cfg" Meson specific registers | |
| - "config" PCIe configuration space | |
| - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. | |
| - clocks: Must contain an entry for each entry in clock-names. | |
| - clock-names: Must include the following entries: | |
| - "pclk" PCIe GEN 100M PLL clock | |
| - "port" PCIe_x(A or B) RC clock gate | |
| - "general" PCIe Phy clock | |
| - resets: phandle to the reset lines. | |
| - reset-names: must contain "port" and "apb" | |
| - "port" Port A or B reset | |
| - "apb" Share APB reset | |
| - phys: should contain a phandle to the PCIE phy | |
| - phy-names: must contain "pcie" | |
| - device_type: | |
| should be "pci". As specified in snps,dw-pcie.yaml | |
| Example configuration: | |
| pcie: pcie@f9800000 { | |
| compatible = "amlogic,axg-pcie", "snps,dw-pcie"; | |
| reg = <0x0 0xf9800000 0x0 0x400000 | |
| 0x0 0xff646000 0x0 0x2000 | |
| 0x0 0xf9f00000 0x0 0x100000>; | |
| reg-names = "elbi", "cfg", "config"; | |
| reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; | |
| interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; | |
| #interrupt-cells = <1>; | |
| interrupt-map-mask = <0 0 0 0>; | |
| interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; | |
| bus-range = <0x0 0xff>; | |
| #address-cells = <3>; | |
| #size-cells = <2>; | |
| device_type = "pci"; | |
| ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>; | |
| clocks = <&clkc CLKID_USB | |
| &clkc CLKID_PCIE_A | |
| &clkc CLKID_PCIE_CML_EN0>; | |
| clock-names = "general", | |
| "pclk", | |
| "port"; | |
| resets = <&reset RESET_PCIE_A>, | |
| <&reset RESET_PCIE_APB>; | |
| reset-names = "port", | |
| "apb"; | |
| phys = <&pcie_phy>; | |
| phy-names = "pcie"; | |
| }; |
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| Amlogic Meson6 SoCs Timer Controller | |
| Required properties: | |
| - compatible : should be "amlogic,meson6-timer" | |
| - reg : Specifies base physical address and size of the registers. | |
| - interrupts : The four interrupts, one for each timer event | |
| - clocks : phandles to the pclk (system clock) and XTAL clocks | |
| - clock-names : must contain "pclk" and "xtal" | |
| Example: | |
| timer@c1109940 { | |
| compatible = "amlogic,meson6-timer"; | |
| reg = <0xc1109940 0x14>; | |
| interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>, | |
| <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>, | |
| <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>, | |
| <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; | |
| clocks = <&xtal>, <&clk81>; | |
| clock-names = "xtal", "pclk"; | |
| }; |
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| * Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit | |
| The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and | |
| supplies clock to various controllers within the SoC. | |
| Required Properties: | |
| - compatible: must be one of: | |
| - "amlogic,meson8-clkc" for Meson8 (S802) SoCs | |
| - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs | |
| - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs | |
| - #clock-cells: should be 1. | |
| - #reset-cells: should be 1. | |
| - clocks: list of clock phandles, one for each entry in clock-names | |
| - clock-names: should contain the following: | |
| * "xtal": the 24MHz system oscillator | |
| * "ddr_pll": the DDR PLL clock | |
| * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN) | |
| Parent node should have the following properties : | |
| - compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" | |
| - reg: base address and size of the HHI system control register space. | |
| Each clock is assigned an identifier and client nodes can use this identifier | |
| to specify the clock which they consume. All available clocks are defined as | |
| preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be | |
| used in device tree sources. | |
| Similarly a preprocessor macro for each reset line is defined in | |
| dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the | |
| device tree sources). | |
| Example: Clock controller node: | |
| clkc: clock-controller { | |
| compatible = "amlogic,meson8b-clkc"; | |
| #clock-cells = <1>; | |
| #reset-cells = <1>; | |
| }; | |
| Example: UART controller node that consumes the clock generated by the clock | |
| controller: | |
| uart_AO: serial@c81004c0 { | |
| compatible = "amlogic,meson-uart"; | |
| reg = <0xc81004c0 0x14>; | |
| interrupts = <0 90 1>; | |
| clocks = <&clkc CLKID_CLK81>; | |
| }; |
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| = Amlogic Meson GX eFuse device tree bindings = | |
| Required properties: | |
| - compatible: should be "amlogic,meson-gxbb-efuse" | |
| - clocks: phandle to the efuse peripheral clock provided by the | |
| clock controller. | |
| - secure-monitor: phandle to the secure-monitor node | |
| = Data cells = | |
| Are child nodes of eFuse, bindings of which as described in | |
| bindings/nvmem/nvmem.txt | |
| Example: | |
| efuse: efuse { | |
| compatible = "amlogic,meson-gxbb-efuse"; | |
| clocks = <&clkc CLKID_EFUSE>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| secure-monitor = <&sm>; | |
| sn: sn@14 { | |
| reg = <0x14 0x10>; | |
| }; | |
| eth_mac: eth_mac@34 { | |
| reg = <0x34 0x10>; | |
| }; | |
| bid: bid@46 { | |
| reg = <0x46 0x30>; | |
| }; | |
| }; | |
| sm: secure-monitor { | |
| compatible = "amlogic,meson-gxbb-sm"; | |
| }; | |
| = Data consumers = | |
| Are device nodes which consume nvmem data cells. | |
| For example: | |
| eth_mac { | |
| ... | |
| nvmem-cells = <ð_mac>; | |
| nvmem-cell-names = "eth_mac"; | |
| }; |
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| Amlogic Meson6/Meson8/Meson8b efuse | |
| Required Properties: | |
| - compatible: depending on the SoC this should be one of: | |
| - "amlogic,meson6-efuse" | |
| - "amlogic,meson8-efuse" | |
| - "amlogic,meson8b-efuse" | |
| - reg: base address and size of the efuse registers | |
| - clocks: a reference to the efuse core gate clock | |
| - clock-names: must be "core" | |
| All properties and sub-nodes as well as the consumer bindings | |
| defined in nvmem.txt in this directory are also supported. | |
| Example: | |
| efuse: nvmem@0 { | |
| compatible = "amlogic,meson8-efuse"; | |
| reg = <0x0 0x2000>; | |
| clocks = <&clkc CLKID_EFUSE>; | |
| clock-names = "core"; | |
| }; |
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| Analog devices AS3645A device tree bindings | |
| The AS3645A flash LED controller can drive two LEDs, one high current | |
| flash LED and one indicator LED. The high current flash LED can be | |
| used in torch mode as well. | |
| Ranges below noted as [a, b] are closed ranges between a and b, i.e. a | |
| and b are included in the range. | |
| Please also see common.txt in the same directory. | |
| Required properties | |
| =================== | |
| compatible : Must be "ams,as3645a". | |
| reg : The I2C address of the device. Typically 0x30. | |
| #address-cells : 1 | |
| #size-cells : 0 | |
| Required properties of the flash child node (0) | |
| =============================================== | |
| reg: 0 | |
| flash-timeout-us: Flash timeout in microseconds. The value must be in | |
| the range [100000, 850000] and divisible by 50000. | |
| flash-max-microamp: Maximum flash current in microamperes. Has to be | |
| in the range between [200000, 500000] and | |
| divisible by 20000. | |
| led-max-microamp: Maximum torch (assist) current in microamperes. The | |
| value must be in the range between [20000, 160000] and | |
| divisible by 20000. | |
| ams,input-max-microamp: Maximum flash controller input current. The | |
| value must be in the range [1250000, 2000000] | |
| and divisible by 50000. | |
| Optional properties of the flash child node | |
| =========================================== | |
| function : See Documentation/devicetree/bindings/leds/common.txt. | |
| color : See Documentation/devicetree/bindings/leds/common.txt. | |
| label : See Documentation/devicetree/bindings/leds/common.txt (deprecated). | |
| Required properties of the indicator child node (1) | |
| =================================================== | |
| reg: 1 | |
| led-max-microamp: Maximum indicator current. The allowed values are | |
| 2500, 5000, 7500 and 10000. | |
| Optional properties of the indicator child node | |
| =============================================== | |
| function : See Documentation/devicetree/bindings/leds/common.txt. | |
| color : See Documentation/devicetree/bindings/leds/common.txt. | |
| label : See Documentation/devicetree/bindings/leds/common.txt (deprecated). | |
| Example | |
| ======= | |
| #include <dt-bindings/leds/common.h> | |
| as3645a@30 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| reg = <0x30>; | |
| compatible = "ams,as3645a"; | |
| led@0 { | |
| reg = <0x0>; | |
| flash-timeout-us = <150000>; | |
| flash-max-microamp = <320000>; | |
| led-max-microamp = <60000>; | |
| ams,input-max-microamp = <1750000>; | |
| function = LED_FUNCTION_FLASH; | |
| }; | |
| led@1 { | |
| reg = <0x1>; | |
| led-max-microamp = <10000>; | |
| function = LED_FUNCTION_INDICATOR; | |
| }; | |
| }; |
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| Amlogic Meson8 and Meson8b "analog top" registers: | |
| -------------------------------------------------- | |
| The analog top registers contain information about the so-called | |
| "metal revision" (which encodes the "minor version") of the SoC. | |
| Required properties: | |
| - reg: the register range of the analog top registers | |
| - compatible: depending on the SoC this should be one of: | |
| - "amlogic,meson8-analog-top" | |
| - "amlogic,meson8b-analog-top" | |
| along with "syscon" | |
| Example: | |
| analog_top: analog-top@81a8 { | |
| compatible = "amlogic,meson8-analog-top", "syscon"; | |
| reg = <0x81a8 0x14>; | |
| }; |
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| Rockchip RK3288 specific extensions to the Analogix Display Port | |
| ================================ | |
| Required properties: | |
| - compatible: "rockchip,rk3288-dp", | |
| "rockchip,rk3399-edp"; | |
| - reg: physical base address of the controller and length | |
| - clocks: from common clock binding: handle to dp clock. | |
| of memory mapped region. | |
| - clock-names: from common clock binding: | |
| Required elements: "dp" "pclk" | |
| - resets: Must contain an entry for each entry in reset-names. | |
| See ../reset/reset.txt for details. | |
| - pinctrl-names: Names corresponding to the chip hotplug pinctrl states. | |
| - pinctrl-0: pin-control mode. should be <&edp_hpd> | |
| - reset-names: Must include the name "dp" | |
| - rockchip,grf: this soc should set GRF regs, so need get grf here. | |
| - ports: there are 2 port nodes with endpoint definitions as defined in | |
| Documentation/devicetree/bindings/media/video-interfaces.txt. | |
| Port 0: contained 2 endpoints, connecting to the output of vop. | |
| Port 1: contained 1 endpoint, connecting to the input of panel. | |
| Optional property for different chips: | |
| - clocks: from common clock binding: handle to grf_vio clock. | |
| - clock-names: from common clock binding: | |
| Required elements: "grf" | |
| For the below properties, please refer to Analogix DP binding document: | |
| * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt | |
| - phys (required) | |
| - phy-names (required) | |
| - hpd-gpios (optional) | |
| - force-hpd (optional) | |
| ------------------------------------------------------------------------------- | |
| Example: | |
| dp-controller: dp@ff970000 { | |
| compatible = "rockchip,rk3288-dp"; | |
| reg = <0xff970000 0x4000>; | |
| interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; | |
| clock-names = "dp", "pclk"; | |
| phys = <&dp_phy>; | |
| phy-names = "dp"; | |
| rockchip,grf = <&grf>; | |
| resets = <&cru 111>; | |
| reset-names = "dp"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&edp_hpd>; | |
| ports { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| edp_in: port@0 { | |
| reg = <0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| edp_in_vopb: endpoint@0 { | |
| reg = <0>; | |
| remote-endpoint = <&vopb_out_edp>; | |
| }; | |
| edp_in_vopl: endpoint@1 { | |
| reg = <1>; | |
| remote-endpoint = <&vopl_out_edp>; | |
| }; | |
| }; | |
| edp_out: port@1 { | |
| reg = <1>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| edp_out_panel: endpoint { | |
| reg = <0>; | |
| remote-endpoint = <&panel_in_edp> | |
| }; | |
| }; | |
| }; | |
| }; | |
| pinctrl { | |
| edp { | |
| edp_hpd: edp-hpd { | |
| rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>; | |
| }; | |
| }; | |
| }; |
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| Analogix Display Port bridge bindings | |
| Required properties for dp-controller: | |
| -compatible: | |
| platform specific such as: | |
| * "samsung,exynos5-dp" | |
| * "rockchip,rk3288-dp" | |
| * "rockchip,rk3399-edp" | |
| -reg: | |
| physical base address of the controller and length | |
| of memory mapped region. | |
| -interrupts: | |
| interrupt combiner values. | |
| -clocks: | |
| from common clock binding: handle to dp clock. | |
| -clock-names: | |
| from common clock binding: Shall be "dp". | |
| -phys: | |
| from general PHY binding: the phandle for the PHY device. | |
| -phy-names: | |
| from general PHY binding: Should be "dp". | |
| Optional properties for dp-controller: | |
| -force-hpd: | |
| Indicate driver need force hpd when hpd detect failed, this | |
| is used for some eDP screen which don't have hpd signal. | |
| -hpd-gpios: | |
| Hotplug detect GPIO. | |
| Indicates which GPIO should be used for hotplug detection | |
| -port@[X]: SoC specific port nodes with endpoint definitions as defined | |
| in Documentation/devicetree/bindings/media/video-interfaces.txt, | |
| please refer to the SoC specific binding document: | |
| * Documentation/devicetree/bindings/display/exynos/exynos_dp.txt | |
| * Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt | |
| [1]: Documentation/devicetree/bindings/media/video-interfaces.txt | |
| ------------------------------------------------------------------------------- | |
| Example: | |
| dp-controller { | |
| compatible = "samsung,exynos5-dp"; | |
| reg = <0x145b0000 0x10000>; | |
| interrupts = <10 3>; | |
| interrupt-parent = <&combiner>; | |
| clocks = <&clock 342>; | |
| clock-names = "dp"; | |
| phys = <&dp_phy>; | |
| phy-names = "dp"; | |
| }; |
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| * Adaptrum Anarion ethernet controller | |
| This device is a platform glue layer for stmmac. | |
| Please see stmmac.txt for the other unchanged properties. | |
| Required properties: | |
| - compatible: Should be "adaptrum,anarion-gmac", "snps,dwmac" | |
| - phy-mode: Should be "rgmii". Other modes are not currently supported. | |
| Examples: | |
| gmac1: ethernet@f2014000 { | |
| compatible = "adaptrum,anarion-gmac", "snps,dwmac"; | |
| reg = <0xf2014000 0x4000>, <0xf2018100 8>; | |
| interrupt-parent = <&core_intc>; | |
| interrupts = <21>; | |
| interrupt-names = "macirq"; | |
| clocks = <&core_clk>; | |
| clock-names = "stmmaceth"; | |
| phy-mode = "rgmii"; | |
| }; |
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| Andestech ATCPIT100 timer | |
| ------------------------------------------------------------------ | |
| ATCPIT100 is a generic IP block from Andes Technology, embedded in | |
| Andestech AE3XX platforms and other designs. | |
| This timer is a set of compact multi-function timers, which can be | |
| used as pulse width modulators (PWM) as well as simple timers. | |
| It supports up to 4 PIT channels. Each PIT channel is a | |
| multi-function timer and provide the following usage scenarios: | |
| One 32-bit timer | |
| Two 16-bit timers | |
| Four 8-bit timers | |
| One 16-bit PWM | |
| One 16-bit timer and one 8-bit PWM | |
| Two 8-bit timer and one 8-bit PWM | |
| Required properties: | |
| - compatible : Should be "andestech,atcpit100" | |
| - reg : Address and length of the register set | |
| - interrupts : Reference to the timer interrupt | |
| - clocks : a clock to provide the tick rate for "andestech,atcpit100" | |
| - clock-names : should be "PCLK" for the peripheral clock source. | |
| Examples: | |
| timer0: timer@f0400000 { | |
| compatible = "andestech,atcpit100"; | |
| reg = <0xf0400000 0x1000>; | |
| interrupts = <2>; | |
| clocks = <&apb>; | |
| clock-names = "PCLK"; | |
| }; |
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| * Andestech Internal Vector Interrupt Controller | |
| The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller | |
| suitable for a simpler SoC platform not requiring a more sophisticated and | |
| bigger External Vector Interrupt Controller. | |
| Main node required properties: | |
| - compatible : should at least contain "andestech,ativic32". | |
| - interrupt-controller : Identifies the node as an interrupt controller | |
| - #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts | |
| Examples: | |
| intc: interrupt-controller { | |
| compatible = "andestech,ativic32"; | |
| #interrupt-cells = <1>; | |
| interrupt-controller; | |
| }; |
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| Marvell Armada AP80x System Controller | |
| ====================================== | |
| The AP806/AP807 is one of the two core HW blocks of the Marvell Armada | |
| 7K/8K/931x SoCs. It contains system controllers, which provide several | |
| registers giving access to numerous features: clocks, pin-muxing and | |
| many other SoC configuration items. This DT binding allows to describe | |
| these system controllers. | |
| For the top level node: | |
| - compatible: must be: "syscon", "simple-mfd"; | |
| - reg: register area of the AP80x system controller | |
| SYSTEM CONTROLLER 0 | |
| =================== | |
| Clocks: | |
| ------- | |
| The Device Tree node representing the AP806/AP807 system controller | |
| provides a number of clocks: | |
| - 0: reference clock of CPU cluster 0 | |
| - 1: reference clock of CPU cluster 1 | |
| - 2: fixed PLL at 1200 Mhz | |
| - 3: MSS clock, derived from the fixed PLL | |
| Required properties: | |
| - compatible: must be one of: | |
| * "marvell,ap806-clock" | |
| * "marvell,ap807-clock" | |
| - #clock-cells: must be set to 1 | |
| Pinctrl: | |
| -------- | |
| For common binding part and usage, refer to | |
| Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt. | |
| Required properties: | |
| - compatible must be "marvell,ap806-pinctrl", | |
| Available mpp pins/groups and functions: | |
| Note: brackets (x) are not part of the mpp name for marvell,function and given | |
| only for more detailed description in this document. | |
| name pins functions | |
| ================================================================================ | |
| mpp0 0 gpio, sdio(clk), spi0(clk) | |
| mpp1 1 gpio, sdio(cmd), spi0(miso) | |
| mpp2 2 gpio, sdio(d0), spi0(mosi) | |
| mpp3 3 gpio, sdio(d1), spi0(cs0n) | |
| mpp4 4 gpio, sdio(d2), i2c0(sda) | |
| mpp5 5 gpio, sdio(d3), i2c0(sdk) | |
| mpp6 6 gpio, sdio(ds) | |
| mpp7 7 gpio, sdio(d4), uart1(rxd) | |
| mpp8 8 gpio, sdio(d5), uart1(txd) | |
| mpp9 9 gpio, sdio(d6), spi0(cs1n) | |
| mpp10 10 gpio, sdio(d7) | |
| mpp11 11 gpio, uart0(txd) | |
| mpp12 12 gpio, sdio(pw_off), sdio(hw_rst) | |
| mpp13 13 gpio | |
| mpp14 14 gpio | |
| mpp15 15 gpio | |
| mpp16 16 gpio | |
| mpp17 17 gpio | |
| mpp18 18 gpio | |
| mpp19 19 gpio, uart0(rxd), sdio(pw_off) | |
| GPIO: | |
| ----- | |
| For common binding part and usage, refer to | |
| Documentation/devicetree/bindings/gpio/gpio-mvebu.txt. | |
| Required properties: | |
| - compatible: "marvell,armada-8k-gpio" | |
| - offset: offset address inside the syscon block | |
| Optional properties: | |
| - marvell,pwm-offset: offset address of PWM duration control registers inside | |
| the syscon block | |
| Example: | |
| ap_syscon: system-controller@6f4000 { | |
| compatible = "syscon", "simple-mfd"; | |
| reg = <0x6f4000 0x1000>; | |
| ap_clk: clock { | |
| compatible = "marvell,ap806-clock"; | |
| #clock-cells = <1>; | |
| }; | |
| ap_pinctrl: pinctrl { | |
| compatible = "marvell,ap806-pinctrl"; | |
| }; | |
| ap_gpio: gpio { | |
| compatible = "marvell,armada-8k-gpio"; | |
| offset = <0x1040>; | |
| ngpios = <19>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| gpio-ranges = <&ap_pinctrl 0 0 19>; | |
| marvell,pwm-offset = <0x10c0>; | |
| #pwm-cells = <2>; | |
| clocks = <&ap_clk 3>; | |
| }; | |
| }; | |
| SYSTEM CONTROLLER 1 | |
| =================== | |
| Thermal: | |
| -------- | |
| For common binding part and usage, refer to | |
| Documentation/devicetree/bindings/thermal/thermal*.yaml | |
| The thermal IP can probe the temperature all around the processor. It | |
| may feature several channels, each of them wired to one sensor. | |
| It is possible to setup an overheat interrupt by giving at least one | |
| critical point to any subnode of the thermal-zone node. | |
| Required properties: | |
| - compatible: must be one of: | |
| * marvell,armada-ap806-thermal | |
| - reg: register range associated with the thermal functions. | |
| Optional properties: | |
| - interrupts: overheat interrupt handle. Should point to line 18 of the | |
| SEI irqchip. See interrupt-controller/interrupts.txt | |
| - #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer | |
| to this IP and represents the channel ID. There is one sensor per | |
| channel. O refers to the thermal IP internal channel, while positive | |
| IDs refer to each CPU. | |
| Example: | |
| ap_syscon1: system-controller@6f8000 { | |
| compatible = "syscon", "simple-mfd"; | |
| reg = <0x6f8000 0x1000>; | |
| ap_thermal: thermal-sensor@80 { | |
| compatible = "marvell,armada-ap806-thermal"; | |
| reg = <0x80 0x10>; | |
| interrupt-parent = <&sei>; | |
| interrupts = <18>; | |
| #thermal-sensor-cells = <1>; | |
| }; | |
| }; | |
| Cluster clocks: | |
| --------------- | |
| Device Tree Clock bindings for cluster clock of Marvell | |
| AP806/AP807. Each cluster contain up to 2 CPUs running at the same | |
| frequency. | |
| Required properties: | |
| - compatible: must be one of: | |
| * "marvell,ap806-cpu-clock" | |
| * "marvell,ap807-cpu-clock" | |
| - #clock-cells : should be set to 1. | |
| - clocks : shall be the input parent clock(s) phandle for the clock | |
| (one per cluster) | |
| - reg: register range associated with the cluster clocks | |
| ap_syscon1: system-controller@6f8000 { | |
| compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd"; | |
| reg = <0x6f8000 0x1000>; | |
| cpu_clk: clock-cpu@278 { | |
| compatible = "marvell,ap806-cpu-clock"; | |
| clocks = <&ap_clk 0>, <&ap_clk 1>; | |
| #clock-cells = <1>; | |
| reg = <0x278 0xa30>; | |
| }; | |
| }; |
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| Binding for Texas Instruments APLL clock. | |
| Binding status: Unstable - ABI compatibility may be broken in the future | |
| This binding uses the common clock binding[1]. It assumes a | |
| register-mapped APLL with usually two selectable input clocks | |
| (reference clock and bypass clock), with analog phase locked | |
| loop logic for multiplying the input clock to a desired output | |
| clock. This clock also typically supports different operation | |
| modes (locked, low power stop etc.) APLL mostly behaves like | |
| a subtype of a DPLL [2], although a simplified one at that. | |
| [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| [2] Documentation/devicetree/bindings/clock/ti/dpll.txt | |
| Required properties: | |
| - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock" | |
| - #clock-cells : from common clock binding; shall be set to 0. | |
| - clocks : link phandles of parent clocks (clk-ref and clk-bypass) | |
| - reg : address and length of the register set for controlling the APLL. | |
| It contains the information of registers in the following order: | |
| "control" - contains the control register offset | |
| "idlest" - contains the idlest register offset | |
| "autoidle" - contains the autoidle register offset (OMAP2 only) | |
| - ti,clock-frequency : static clock frequency for the clock (OMAP2 only) | |
| - ti,idlest-shift : bit-shift for the idlest field (OMAP2 only) | |
| - ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only) | |
| Examples: | |
| apll_pcie_ck: apll_pcie_ck { | |
| #clock-cells = <0>; | |
| clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; | |
| reg = <0x021c>, <0x0220>; | |
| compatible = "ti,dra7-apll-clock"; | |
| }; | |
| apll96_ck: apll96_ck { | |
| #clock-cells = <0>; | |
| compatible = "ti,omap2-apll-clock"; | |
| clocks = <&sys_ck>; | |
| ti,bit-shift = <2>; | |
| ti,idlest-shift = <8>; | |
| ti,clock-frequency = <96000000>; | |
| reg = <0x0500>, <0x0530>, <0x0520>; | |
| }; |
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| Applied Micro X-Gene SoC DMA nodes | |
| DMA nodes are defined to describe on-chip DMA interfaces in | |
| APM X-Gene SoC. | |
| Required properties for DMA interfaces: | |
| - compatible: Should be "apm,xgene-dma". | |
| - device_type: set to "dma". | |
| - reg: Address and length of the register set for the device. | |
| It contains the information of registers in the following order: | |
| 1st - DMA control and status register address space. | |
| 2nd - Descriptor ring control and status register address space. | |
| 3rd - Descriptor ring command register address space. | |
| 4th - Soc efuse register address space. | |
| - interrupts: DMA has 5 interrupts sources. 1st interrupt is | |
| DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts | |
| are completion interrupts for each DMA channels. | |
| - clocks: Reference to the clock entry. | |
| Optional properties: | |
| - dma-coherent : Present if dma operations are coherent | |
| Example: | |
| dmaclk: dmaclk@1f27c000 { | |
| compatible = "apm,xgene-device-clock"; | |
| #clock-cells = <1>; | |
| clocks = <&socplldiv2 0>; | |
| reg = <0x0 0x1f27c000 0x0 0x1000>; | |
| reg-names = "csr-reg"; | |
| clock-output-names = "dmaclk"; | |
| }; | |
| dma: dma@1f270000 { | |
| compatible = "apm,xgene-storm-dma"; | |
| device_type = "dma"; | |
| reg = <0x0 0x1f270000 0x0 0x10000>, | |
| <0x0 0x1f200000 0x0 0x10000>, | |
| <0x0 0x1b000000 0x0 0x400000>, | |
| <0x0 0x1054a000 0x0 0x100>; | |
| interrupts = <0x0 0x82 0x4>, | |
| <0x0 0xb8 0x4>, | |
| <0x0 0xb9 0x4>, | |
| <0x0 0xba 0x4>, | |
| <0x0 0xbb 0x4>; | |
| dma-coherent; | |
| clocks = <&dmaclk 0>; | |
| }; |
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| * APM X-Gene SoC EDAC node | |
| EDAC node is defined to describe on-chip error detection and correction. | |
| The follow error types are supported: | |
| memory controller - Memory controller | |
| PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache | |
| L3 - L3 cache controller | |
| SoC - SoC IP's such as Ethernet, SATA, and etc | |
| The following section describes the EDAC DT node binding. | |
| Required properties: | |
| - compatible : Shall be "apm,xgene-edac". | |
| - regmap-csw : Regmap of the CPU switch fabric (CSW) resource. | |
| - regmap-mcba : Regmap of the MCB-A (memory bridge) resource. | |
| - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource. | |
| - regmap-efuse : Regmap of the PMD efuse resource. | |
| - regmap-rb : Regmap of the register bus resource. This property | |
| is optional only for compatibility. If the RB | |
| error conditions are not cleared, it will | |
| continuously generate interrupt. | |
| - reg : First resource shall be the CPU bus (PCP) resource. | |
| - interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error | |
| IRQ(s). | |
| Required properties for memory controller subnode: | |
| - compatible : Shall be "apm,xgene-edac-mc". | |
| - reg : First resource shall be the memory controller unit | |
| (MCU) resource. | |
| - memory-controller : Instance number of the memory controller. | |
| Required properties for PMD subnode: | |
| - compatible : Shall be "apm,xgene-edac-pmd" or | |
| "apm,xgene-edac-pmd-v2". | |
| - reg : First resource shall be the PMD resource. | |
| - pmd-controller : Instance number of the PMD controller. | |
| Required properties for L3 subnode: | |
| - compatible : Shall be "apm,xgene-edac-l3" or | |
| "apm,xgene-edac-l3-v2". | |
| - reg : First resource shall be the L3 EDAC resource. | |
| Required properties for SoC subnode: | |
| - compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or | |
| "apm,xgene-edac-l3-soc" for general value reporting | |
| only. | |
| - reg : First resource shall be the SoC EDAC resource. | |
| Example: | |
| csw: csw@7e200000 { | |
| compatible = "apm,xgene-csw", "syscon"; | |
| reg = <0x0 0x7e200000 0x0 0x1000>; | |
| }; | |
| mcba: mcba@7e700000 { | |
| compatible = "apm,xgene-mcb", "syscon"; | |
| reg = <0x0 0x7e700000 0x0 0x1000>; | |
| }; | |
| mcbb: mcbb@7e720000 { | |
| compatible = "apm,xgene-mcb", "syscon"; | |
| reg = <0x0 0x7e720000 0x0 0x1000>; | |
| }; | |
| efuse: efuse@1054a000 { | |
| compatible = "apm,xgene-efuse", "syscon"; | |
| reg = <0x0 0x1054a000 0x0 0x20>; | |
| }; | |
| rb: rb@7e000000 { | |
| compatible = "apm,xgene-rb", "syscon"; | |
| reg = <0x0 0x7e000000 0x0 0x10>; | |
| }; | |
| edac@78800000 { | |
| compatible = "apm,xgene-edac"; | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| ranges; | |
| regmap-csw = <&csw>; | |
| regmap-mcba = <&mcba>; | |
| regmap-mcbb = <&mcbb>; | |
| regmap-efuse = <&efuse>; | |
| regmap-rb = <&rb>; | |
| reg = <0x0 0x78800000 0x0 0x100>; | |
| interrupts = <0x0 0x20 0x4>, | |
| <0x0 0x21 0x4>, | |
| <0x0 0x27 0x4>; | |
| edacmc@7e800000 { | |
| compatible = "apm,xgene-edac-mc"; | |
| reg = <0x0 0x7e800000 0x0 0x1000>; | |
| memory-controller = <0>; | |
| }; | |
| edacpmd@7c000000 { | |
| compatible = "apm,xgene-edac-pmd"; | |
| reg = <0x0 0x7c000000 0x0 0x200000>; | |
| pmd-controller = <0>; | |
| }; | |
| edacl3@7e600000 { | |
| compatible = "apm,xgene-edac-l3"; | |
| reg = <0x0 0x7e600000 0x0 0x1000>; | |
| }; | |
| edacsoc@7e930000 { | |
| compatible = "apm,xgene-edac-soc-v1"; | |
| reg = <0x0 0x7e930000 0x0 0x1000>; | |
| }; | |
| }; |
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| APM X-Gene SoC Ethernet nodes | |
| Ethernet nodes are defined to describe on-chip ethernet interfaces in | |
| APM X-Gene SoC. | |
| Required properties for all the ethernet interfaces: | |
| - compatible: Should state binding information from the following list, | |
| - "apm,xgene-enet": RGMII based 1G interface | |
| - "apm,xgene1-sgenet": SGMII based 1G interface | |
| - "apm,xgene1-xgenet": XFI based 10G interface | |
| - reg: Address and length of the register set for the device. It contains the | |
| information of registers in the same order as described by reg-names | |
| - reg-names: Should contain the register set names | |
| - "enet_csr": Ethernet control and status register address space | |
| - "ring_csr": Descriptor ring control and status register address space | |
| - "ring_cmd": Descriptor ring command register address space | |
| - interrupts: Two interrupt specifiers can be specified. | |
| - First is the Rx interrupt. This irq is mandatory. | |
| - Second is the Tx completion interrupt. | |
| This is supported only on SGMII based 1GbE and 10GbE interfaces. | |
| - channel: Ethernet to CPU, start channel (prefetch buffer) number | |
| - Must map to the first irq and irqs must be sequential | |
| - port-id: Port number (0 or 1) | |
| - clocks: Reference to the clock entry. | |
| - local-mac-address: MAC address assigned to this device | |
| - phy-connection-type: Interface type between ethernet device and PHY device | |
| Required properties for ethernet interfaces that have external PHY: | |
| - phy-handle: Reference to a PHY node connected to this device | |
| - mdio: Device tree subnode with the following required properties: | |
| - compatible: Must be "apm,xgene-mdio". | |
| - #address-cells: Must be <1>. | |
| - #size-cells: Must be <0>. | |
| For the phy on the mdio bus, there must be a node with the following fields: | |
| - compatible: PHY identifier. Please refer ./phy.txt for the format. | |
| - reg: The ID number for the phy. | |
| Optional properties: | |
| - status: Should be "ok" or "disabled" for enabled/disabled. Default is "ok". | |
| - tx-delay: Delay value for RGMII bridge TX clock. | |
| Valid values are between 0 to 7, that maps to | |
| 417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps | |
| Default value is 4, which corresponds to 1611 ps | |
| - rx-delay: Delay value for RGMII bridge RX clock. | |
| Valid values are between 0 to 7, that maps to | |
| 273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps | |
| Default value is 2, which corresponds to 899 ps | |
| - rxlos-gpios: Input gpio from SFP+ module to indicate availability of | |
| incoming signal. | |
| Example: | |
| menetclk: menetclk { | |
| compatible = "apm,xgene-device-clock"; | |
| clock-output-names = "menetclk"; | |
| status = "ok"; | |
| }; | |
| menet: ethernet@17020000 { | |
| compatible = "apm,xgene-enet"; | |
| status = "disabled"; | |
| reg = <0x0 0x17020000 0x0 0xd100>, | |
| <0x0 0x17030000 0x0 0x400>, | |
| <0x0 0x10000000 0x0 0x200>; | |
| reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
| interrupts = <0x0 0x3c 0x4>; | |
| port-id = <0>; | |
| clocks = <&menetclk 0>; | |
| local-mac-address = [00 01 73 00 00 01]; | |
| phy-connection-type = "rgmii"; | |
| phy-handle = <&menetphy>; | |
| mdio { | |
| compatible = "apm,xgene-mdio"; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| menetphy: menetphy@3 { | |
| compatible = "ethernet-phy-id001c.c915"; | |
| reg = <0x3>; | |
| }; | |
| }; | |
| }; | |
| /* Board-specific peripheral configurations */ | |
| &menet { | |
| tx-delay = <4>; | |
| rx-delay = <2>; | |
| status = "ok"; | |
| }; |
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| APM X-Gene hwmon driver | |
| APM X-Gene SOC sensors are accessed over the "SLIMpro" mailbox. | |
| Required properties : | |
| - compatible : should be "apm,xgene-slimpro-hwmon" | |
| - mboxes : use the label reference for the mailbox as the first parameter. | |
| The second parameter is the channel number. | |
| Example : | |
| hwmonslimpro { | |
| compatible = "apm,xgene-slimpro-hwmon"; | |
| mboxes = <&mailbox 7>; | |
| }; |
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| APM X-Gene SoC MDIO node | |
| MDIO node is defined to describe on-chip MDIO controller. | |
| Required properties: | |
| - compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi" | |
| - #address-cells: Must be <1>. | |
| - #size-cells: Must be <0>. | |
| - reg: Address and length of the register set | |
| - clocks: Reference to the clock entry | |
| For the phys on the mdio bus, there must be a node with the following fields: | |
| - compatible: PHY identifier. Please refer ./phy.txt for the format. | |
| - reg: The ID number for the phy. | |
| Example: | |
| mdio: mdio@17020000 { | |
| compatible = "apm,xgene-mdio-rgmii"; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| reg = <0x0 0x17020000 0x0 0xd100>; | |
| clocks = <&menetclk 0>; | |
| }; | |
| /* Board-specific peripheral configurations */ | |
| &mdio { | |
| menetphy: phy@3 { | |
| reg = <0x3>; | |
| }; | |
| sgenet0phy: phy@4 { | |
| reg = <0x4>; | |
| }; | |
| sgenet1phy: phy@5 { | |
| reg = <0x5>; | |
| }; | |
| }; |
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| * APM X-Gene 15Gbps Multi-purpose PHY nodes | |
| PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each | |
| PHY (pair of lanes) has its own node. | |
| Required properties: | |
| - compatible : Shall be "apm,xgene-phy". | |
| - reg : PHY memory resource is the SDS PHY access resource. | |
| - #phy-cells : Shall be 1 as it expects one argument for setting | |
| the mode of the PHY. Possible values are 0 (SATA), | |
| 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI). | |
| Optional properties: | |
| - status : Shall be "ok" if enabled or "disabled" if disabled. | |
| Default is "ok". | |
| - clocks : Reference to the clock entry. | |
| - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial | |
| bit lines from the automatic calibrated position. | |
| Two set of 3-tuple setting for each (up to 3) | |
| supported link speed on the host. Range from 0 to | |
| 127 in unit of one bit period. Default is 10. | |
| - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample | |
| data earlier than the nominal sampling point. 1 means | |
| sample data later than the nominal sampling point. | |
| Two set of 3-tuple setting for each (up to 3) | |
| supported link speed on the host. Default is 0. | |
| - apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) | |
| gain control. Two set of 3-tuple setting for each | |
| (up to 3) supported link speed on the host. Range is | |
| between 0 to 31 in unit of dB. Default is 3. | |
| - apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for | |
| each (up to 3) supported link speed on the host. | |
| Range is between 0 to 199500 in unit of uV. | |
| Default is 199500 uV. | |
| - apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of | |
| 3-tuple setting for each (up to 3) supported link | |
| speed on the host. Range is 0 to 273000 in unit of | |
| uV. Default is 0. | |
| - apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of | |
| 3-tuple setting for each (up to 3) supported link | |
| speed on the host. Range is 0 to 127400 in unit uV. | |
| Default is 0x0. | |
| - apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of | |
| 3-tuple setting for Gen1, Gen2, and Gen3. Range is | |
| between 0 to 0x1f in unit of 18.2mV. Default is 0xf. | |
| - apm,tx-speed : Tx operating speed. One set of 3-tuple for each | |
| supported link speed on the host. | |
| 0 = 1-2Gbps | |
| 1 = 2-4Gbps (1st tuple default) | |
| 2 = 4-8Gbps | |
| 3 = 8-15Gbps (2nd tuple default) | |
| 4 = 2.5-4Gbps | |
| 5 = 4-5Gbps | |
| 6 = 5-6Gbps | |
| 7 = 6-16Gbps (3rd tuple default) | |
| NOTE: PHY override parameters are board specific setting. | |
| Example: | |
| phy1: phy@1f21a000 { | |
| compatible = "apm,xgene-phy"; | |
| reg = <0x0 0x1f21a000 0x0 0x100>; | |
| #phy-cells = <1>; | |
| }; | |
| phy2: phy@1f22a000 { | |
| compatible = "apm,xgene-phy"; | |
| reg = <0x0 0x1f22a000 0x0 0x100>; | |
| #phy-cells = <1>; | |
| }; | |
| phy3: phy@1f23a000 { | |
| compatible = "apm,xgene-phy"; | |
| reg = <0x0 0x1f23a000 0x0 0x100>; | |
| #phy-cells = <1>; | |
| }; |
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| * APM X-Gene SoC PMU bindings | |
| This is APM X-Gene SoC PMU (Performance Monitoring Unit) module. | |
| The following PMU devices are supported: | |
| L3C - L3 cache controller | |
| IOB - IO bridge | |
| MCB - Memory controller bridge | |
| MC - Memory controller | |
| The following section describes the SoC PMU DT node binding. | |
| Required properties: | |
| - compatible : Shall be "apm,xgene-pmu" for revision 1 or | |
| "apm,xgene-pmu-v2" for revision 2. | |
| - regmap-csw : Regmap of the CPU switch fabric (CSW) resource. | |
| - regmap-mcba : Regmap of the MCB-A (memory bridge) resource. | |
| - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource. | |
| - reg : First resource shall be the CPU bus PMU resource. | |
| - interrupts : Interrupt-specifier for PMU IRQ. | |
| Required properties for L3C subnode: | |
| - compatible : Shall be "apm,xgene-pmu-l3c". | |
| - reg : First resource shall be the L3C PMU resource. | |
| Required properties for IOB subnode: | |
| - compatible : Shall be "apm,xgene-pmu-iob". | |
| - reg : First resource shall be the IOB PMU resource. | |
| Required properties for MCB subnode: | |
| - compatible : Shall be "apm,xgene-pmu-mcb". | |
| - reg : First resource shall be the MCB PMU resource. | |
| - enable-bit-index : The bit indicates if the according MCB is enabled. | |
| Required properties for MC subnode: | |
| - compatible : Shall be "apm,xgene-pmu-mc". | |
| - reg : First resource shall be the MC PMU resource. | |
| - enable-bit-index : The bit indicates if the according MC is enabled. | |
| Example: | |
| csw: csw@7e200000 { | |
| compatible = "apm,xgene-csw", "syscon"; | |
| reg = <0x0 0x7e200000 0x0 0x1000>; | |
| }; | |
| mcba: mcba@7e700000 { | |
| compatible = "apm,xgene-mcb", "syscon"; | |
| reg = <0x0 0x7e700000 0x0 0x1000>; | |
| }; | |
| mcbb: mcbb@7e720000 { | |
| compatible = "apm,xgene-mcb", "syscon"; | |
| reg = <0x0 0x7e720000 0x0 0x1000>; | |
| }; | |
| pmu: pmu@78810000 { | |
| compatible = "apm,xgene-pmu-v2"; | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| ranges; | |
| regmap-csw = <&csw>; | |
| regmap-mcba = <&mcba>; | |
| regmap-mcbb = <&mcbb>; | |
| reg = <0x0 0x78810000 0x0 0x1000>; | |
| interrupts = <0x0 0x22 0x4>; | |
| pmul3c@7e610000 { | |
| compatible = "apm,xgene-pmu-l3c"; | |
| reg = <0x0 0x7e610000 0x0 0x1000>; | |
| }; | |
| pmuiob@7e940000 { | |
| compatible = "apm,xgene-pmu-iob"; | |
| reg = <0x0 0x7e940000 0x0 0x1000>; | |
| }; | |
| pmucmcb@7e710000 { | |
| compatible = "apm,xgene-pmu-mcb"; | |
| reg = <0x0 0x7e710000 0x0 0x1000>; | |
| enable-bit-index = <0>; | |
| }; | |
| pmucmcb@7e730000 { | |
| compatible = "apm,xgene-pmu-mcb"; | |
| reg = <0x0 0x7e730000 0x0 0x1000>; | |
| enable-bit-index = <1>; | |
| }; | |
| pmucmc@7e810000 { | |
| compatible = "apm,xgene-pmu-mc"; | |
| reg = <0x0 0x7e810000 0x0 0x1000>; | |
| enable-bit-index = <0>; | |
| }; | |
| pmucmc@7e850000 { | |
| compatible = "apm,xgene-pmu-mc"; | |
| reg = <0x0 0x7e850000 0x0 0x1000>; | |
| enable-bit-index = <1>; | |
| }; | |
| pmucmc@7e890000 { | |
| compatible = "apm,xgene-pmu-mc"; | |
| reg = <0x0 0x7e890000 0x0 0x1000>; | |
| enable-bit-index = <2>; | |
| }; | |
| pmucmc@7e8d0000 { | |
| compatible = "apm,xgene-pmu-mc"; | |
| reg = <0x0 0x7e8d0000 0x0 0x1000>; | |
| enable-bit-index = <3>; | |
| }; | |
| }; |
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| * APM X-Gene 6.0 Gb/s SATA host controller nodes | |
| SATA host controller nodes are defined to describe on-chip Serial ATA | |
| controllers. Each SATA controller (pair of ports) have its own node. | |
| Required properties: | |
| - compatible : Shall contain: | |
| * "apm,xgene-ahci" | |
| - reg : First memory resource shall be the AHCI memory | |
| resource. | |
| Second memory resource shall be the host controller | |
| core memory resource. | |
| Third memory resource shall be the host controller | |
| diagnostic memory resource. | |
| 4th memory resource shall be the host controller | |
| AXI memory resource. | |
| 5th optional memory resource shall be the host | |
| controller MUX memory resource if required. | |
| - interrupts : Interrupt-specifier for SATA host controller IRQ. | |
| - clocks : Reference to the clock entry. | |
| - phys : A list of phandles + phy-specifiers, one for each | |
| entry in phy-names. | |
| - phy-names : Should contain: | |
| * "sata-phy" for the SATA 6.0Gbps PHY | |
| Optional properties: | |
| - dma-coherent : Present if dma operations are coherent | |
| - status : Shall be "ok" if enabled or "disabled" if disabled. | |
| Default is "ok". | |
| Example: | |
| sataclk: sataclk { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <1>; | |
| clock-frequency = <100000000>; | |
| clock-output-names = "sataclk"; | |
| }; | |
| phy2: phy@1f22a000 { | |
| compatible = "apm,xgene-phy"; | |
| reg = <0x0 0x1f22a000 0x0 0x100>; | |
| #phy-cells = <1>; | |
| }; | |
| phy3: phy@1f23a000 { | |
| compatible = "apm,xgene-phy"; | |
| reg = <0x0 0x1f23a000 0x0 0x100>; | |
| #phy-cells = <1>; | |
| }; | |
| sata2: sata@1a400000 { | |
| compatible = "apm,xgene-ahci"; | |
| reg = <0x0 0x1a400000 0x0 0x1000>, | |
| <0x0 0x1f220000 0x0 0x1000>, | |
| <0x0 0x1f22d000 0x0 0x1000>, | |
| <0x0 0x1f22e000 0x0 0x1000>, | |
| <0x0 0x1f227000 0x0 0x1000>; | |
| interrupts = <0x0 0x87 0x4>; | |
| dma-coherent; | |
| clocks = <&sataclk 0>; | |
| phys = <&phy2 0>; | |
| phy-names = "sata-phy"; | |
| }; | |
| sata3: sata@1a800000 { | |
| compatible = "apm,xgene-ahci-pcie"; | |
| reg = <0x0 0x1a800000 0x0 0x1000>, | |
| <0x0 0x1f230000 0x0 0x1000>, | |
| <0x0 0x1f23d000 0x0 0x1000>, | |
| <0x0 0x1f23e000 0x0 0x1000>, | |
| <0x0 0x1f237000 0x0 0x1000>; | |
| interrupts = <0x0 0x88 0x4>; | |
| dma-coherent; | |
| clocks = <&sataclk 0>; | |
| phys = <&phy3 0>; | |
| phy-names = "sata-phy"; | |
| }; |
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| * Microchip AR1020 and AR1021 touchscreen interface (I2C) | |
| Required properties: | |
| - compatible : "microchip,ar1021-i2c" | |
| - reg : I2C slave address | |
| - interrupts : touch controller interrupt | |
| Example: | |
| touchscreen@4d { | |
| compatible = "microchip,ar1021-i2c"; | |
| reg = <0x4d>; | |
| interrupt-parent = <&gpio3>; | |
| interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; | |
| }; |
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| Atheros AR9331 built-in switch | |
| ============================= | |
| It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal | |
| MDIO bus. All PHYs are built-in as well. | |
| Required properties: | |
| - compatible: should be: "qca,ar9331-switch" | |
| - reg: Address on the MII bus for the switch. | |
| - resets : Must contain an entry for each entry in reset-names. | |
| - reset-names : Must include the following entries: "switch" | |
| - interrupt-parent: Phandle to the parent interrupt controller | |
| - interrupts: IRQ line for the switch | |
| - interrupt-controller: Indicates the switch is itself an interrupt | |
| controller. This is used for the PHY interrupts. | |
| - #interrupt-cells: must be 1 | |
| - mdio: Container of PHY and devices on the switches MDIO bus. | |
| See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional | |
| required and optional properties. | |
| Examples: | |
| eth0: ethernet@19000000 { | |
| compatible = "qca,ar9330-eth"; | |
| reg = <0x19000000 0x200>; | |
| interrupts = <4>; | |
| resets = <&rst 9>, <&rst 22>; | |
| reset-names = "mac", "mdio"; | |
| clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; | |
| clock-names = "eth", "mdio"; | |
| phy-mode = "mii"; | |
| phy-handle = <&phy_port4>; | |
| }; | |
| eth1: ethernet@1a000000 { | |
| compatible = "qca,ar9330-eth"; | |
| reg = <0x1a000000 0x200>; | |
| interrupts = <5>; | |
| resets = <&rst 13>, <&rst 23>; | |
| reset-names = "mac", "mdio"; | |
| clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>; | |
| clock-names = "eth", "mdio"; | |
| phy-mode = "gmii"; | |
| fixed-link { | |
| speed = <1000>; | |
| full-duplex; | |
| }; | |
| mdio { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| switch10: switch@10 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "qca,ar9331-switch"; | |
| reg = <0x10>; | |
| resets = <&rst 8>; | |
| reset-names = "switch"; | |
| interrupt-parent = <&miscintc>; | |
| interrupts = <12>; | |
| interrupt-controller; | |
| #interrupt-cells = <1>; | |
| ports { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| switch_port0: port@0 { | |
| reg = <0x0>; | |
| label = "cpu"; | |
| ethernet = <ð1>; | |
| phy-mode = "gmii"; | |
| fixed-link { | |
| speed = <1000>; | |
| full-duplex; | |
| }; | |
| }; | |
| switch_port1: port@1 { | |
| reg = <0x1>; | |
| phy-handle = <&phy_port0>; | |
| phy-mode = "internal"; | |
| }; | |
| switch_port2: port@2 { | |
| reg = <0x2>; | |
| phy-handle = <&phy_port1>; | |
| phy-mode = "internal"; | |
| }; | |
| switch_port3: port@3 { | |
| reg = <0x3>; | |
| phy-handle = <&phy_port2>; | |
| phy-mode = "internal"; | |
| }; | |
| switch_port4: port@4 { | |
| reg = <0x4>; | |
| phy-handle = <&phy_port3>; | |
| phy-mode = "internal"; | |
| }; | |
| }; | |
| mdio { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| interrupt-parent = <&switch10>; | |
| phy_port0: phy@0 { | |
| reg = <0x0>; | |
| interrupts = <0>; | |
| }; | |
| phy_port1: phy@1 { | |
| reg = <0x1>; | |
| interrupts = <0>; | |
| }; | |
| phy_port2: phy@2 { | |
| reg = <0x2>; | |
| interrupts = <0>; | |
| }; | |
| phy_port3: phy@3 { | |
| reg = <0x3>; | |
| interrupts = <0>; | |
| }; | |
| phy_port4: phy@4 { | |
| reg = <0x4>; | |
| interrupts = <0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; |
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| * Synopsys ARC UART : Non standard UART used in some of the ARC FPGA boards | |
| Required properties: | |
| - compatible : "snps,arc-uart" | |
| - reg : offset and length of the register set for the device. | |
| - interrupts : device interrupt | |
| - clock-frequency : the input clock frequency for the UART | |
| - current-speed : baud rate for UART | |
| e.g. | |
| arcuart0: serial@c0fc1000 { | |
| compatible = "snps,arc-uart"; | |
| reg = <0xc0fc1000 0x100>; | |
| interrupts = <5>; | |
| clock-frequency = <80000000>; | |
| current-speed = <115200>; | |
| }; | |
| Note: Each port should have an alias correctly numbered in "aliases" node. | |
| e.g. | |
| aliases { | |
| serial0 = &arcuart0; | |
| }; |
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| * Synopsys ARC EMAC 10/100 Ethernet driver (EMAC) | |
| Required properties: | |
| - compatible: Should be "snps,arc-emac" | |
| - reg: Address and length of the register set for the device | |
| - interrupts: Should contain the EMAC interrupts | |
| - max-speed: see ethernet.txt file in the same directory. | |
| - phy: see ethernet.txt file in the same directory. | |
| Optional properties: | |
| - phy-reset-gpios : Should specify the gpio for phy reset | |
| - phy-reset-duration : Reset duration in milliseconds. Should present | |
| only if property "phy-reset-gpios" is available. Missing the property | |
| will have the duration be 1 millisecond. Numbers greater than 1000 are | |
| invalid and 1 millisecond will be used instead. | |
| Clock handling: | |
| The clock frequency is needed to calculate and set polling period of EMAC. | |
| It must be provided by one of: | |
| - clock-frequency: CPU frequency. | |
| - clocks: reference to the clock supplying the EMAC. | |
| Child nodes of the driver are the individual PHY devices connected to the | |
| MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus. | |
| Examples: | |
| ethernet@c0fc2000 { | |
| compatible = "snps,arc-emac"; | |
| reg = <0xc0fc2000 0x3c>; | |
| interrupts = <6>; | |
| mac-address = [ 00 11 22 33 44 55 ]; | |
| clock-frequency = <80000000>; | |
| /* or */ | |
| clocks = <&emac_clock>; | |
| max-speed = <100>; | |
| phy = <&phy0>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| phy0: ethernet-phy@0 { | |
| reg = <1>; | |
| }; | |
| }; |
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| # | |
| # Feature name: pte_special | |
| # Kconfig: ARCH_HAS_PTE_SPECIAL | |
| # description: arch supports the pte_special()/pte_mkspecial() VM APIs | |
| # | |
| ----------------------- | |
| | arch |status| | |
| ----------------------- | |
| | alpha: | TODO | | |
| | arc: | ok | | |
| | arm: | ok | | |
| | arm64: | ok | | |
| | csky: | TODO | | |
| | h8300: | TODO | | |
| | hexagon: | TODO | | |
| | ia64: | TODO | | |
| | m68k: | TODO | | |
| | microblaze: | TODO | | |
| | mips: | ok | | |
| | nds32: | TODO | | |
| | nios2: | TODO | | |
| | openrisc: | TODO | | |
| | parisc: | TODO | | |
| | powerpc: | ok | | |
| | riscv: | ok | | |
| | s390: | ok | | |
| | sh: | ok | | |
| | sparc: | ok | | |
| | um: | TODO | | |
| | x86: | ok | | |
| | xtensa: | TODO | | |
| ----------------------- |
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| * ARC HS Performance Counters | |
| The ARC HS can be configured with a pipeline performance monitor for counting | |
| CPU and cache events like cache misses and hits. Like conventional PCT there | |
| are 100+ hardware conditions dynamically mapped to up to 32 counters. | |
| It also supports overflow interrupts. | |
| Required properties: | |
| - compatible : should contain | |
| "snps,archs-pct" | |
| Example: | |
| pmu { | |
| compatible = "snps,archs-pct"; | |
| }; |
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| Binding for ArcticSand arc2c0608 LED driver | |
| Required properties: | |
| - compatible: should be "arc,arc2c0608" | |
| - reg: slave address | |
| Optional properties: | |
| - default-brightness: brightness value on boot, value from: 0-4095 | |
| - label: The name of the backlight device | |
| See Documentation/devicetree/bindings/leds/common.txt | |
| - led-sources: List of enabled channels from 0 to 5. | |
| See Documentation/devicetree/bindings/leds/common.txt | |
| - arc,led-config-0: setting for register ILED_CONFIG_0 | |
| - arc,led-config-1: setting for register ILED_CONFIG_1 | |
| - arc,dim-freq: PWM mode frequence setting (bits [3:0] used) | |
| - arc,comp-config: setting for register CONFIG_COMP | |
| - arc,filter-config: setting for register FILTER_CONFIG | |
| - arc,trim-config: setting for register IMAXTUNE | |
| Note: Optional properties not specified will default to values in IC EPROM | |
| Example: | |
| arc2c0608@30 { | |
| compatible = "arc,arc2c0608"; | |
| reg = <0x30>; | |
| default-brightness = <500>; | |
| label = "lcd-backlight"; | |
| linux,default-trigger = "backlight"; | |
| led-sources = <0 1 2 5>; | |
| }; | |
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| ARM AFS - ARM Firmware Suite Partitions | |
| ======================================= | |
| The ARM Firmware Suite is a flash partitioning system found on the | |
| ARM reference designs: Integrator AP, Integrator CP, Versatile AB, | |
| Versatile PB, the RealView family, Versatile Express and Juno. | |
| Required properties: | |
| - compatible : (required) must be "arm,arm-firmware-suite" | |
| Example: | |
| flash@0 { | |
| partitions { | |
| compatible = "arm,arm-firmware-suite"; | |
| }; | |
| }; |
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| * ARMv7M System Timer | |
| ARMv7-M includes a system timer, known as SysTick. Current driver only | |
| implements the clocksource feature. | |
| Required properties: | |
| - compatible : Should be "arm,armv7m-systick" | |
| - reg : The address range of the timer | |
| Required clocking property, have to be one of: | |
| - clocks : The input clock of the timer | |
| - clock-frequency : The rate in HZ in input of the ARM SysTick | |
| Examples: | |
| systick: timer@e000e010 { | |
| compatible = "arm,armv7m-systick"; | |
| reg = <0xe000e010 0x10>; | |
| clocks = <&clk_systick>; | |
| }; | |
| systick: timer@e000e010 { | |
| compatible = "arm,armv7m-systick"; | |
| reg = <0xe000e010 0x10>; | |
| clock-frequency = <90000000>; | |
| }; |
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| ARM HDLCD | |
| This is a display controller found on several development platforms produced | |
| by ARM Ltd and in more modern of its' Fast Models. The HDLCD is an RGB | |
| streamer that reads the data from a framebuffer and sends it to a single | |
| digital encoder (DVI or HDMI). | |
| Required properties: | |
| - compatible: "arm,hdlcd" | |
| - reg: Physical base address and length of the controller's registers. | |
| - interrupts: One interrupt used by the display controller to notify the | |
| interrupt controller when any of the interrupt sources programmed in | |
| the interrupt mask register have activated. | |
| - clocks: A list of phandle + clock-specifier pairs, one for each | |
| entry in 'clock-names'. | |
| - clock-names: A list of clock names. For HDLCD it should contain: | |
| - "pxlclk" for the clock feeding the output PLL of the controller. | |
| Required sub-nodes: | |
| - port: The HDLCD connection to an encoder chip. The connection is modeled | |
| using the OF graph bindings specified in | |
| Documentation/devicetree/bindings/graph.txt. | |
| Optional properties: | |
| - memory-region: phandle to a node describing memory (see | |
| Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be | |
| used for the framebuffer; if not present, the framebuffer may be located | |
| anywhere in memory. | |
| Example: | |
| / { | |
| ... | |
| hdlcd@2b000000 { | |
| compatible = "arm,hdlcd"; | |
| reg = <0 0x2b000000 0 0x1000>; | |
| interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&oscclk5>; | |
| clock-names = "pxlclk"; | |
| port { | |
| hdlcd_output: endpoint@0 { | |
| remote-endpoint = <&hdmi_enc_input>; | |
| }; | |
| }; | |
| }; | |
| /* HDMI encoder on I2C bus */ | |
| i2c@7ffa0000 { | |
| .... | |
| hdmi-transmitter@70 { | |
| compatible = "....."; | |
| reg = <0x70>; | |
| port@0 { | |
| hdmi_enc_input: endpoint { | |
| remote-endpoint = <&hdlcd_output>; | |
| }; | |
| hdmi_enc_output: endpoint { | |
| remote-endpoint = <&hdmi_1_port>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| hdmi1: connector@1 { | |
| compatible = "hdmi-connector"; | |
| type = "a"; | |
| port { | |
| hdmi_1_port: endpoint { | |
| remote-endpoint = <&hdmi_enc_output>; | |
| }; | |
| }; | |
| }; | |
| ... | |
| }; |
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| Device Tree bindings for Arm Komeda display driver | |
| Required properties: | |
| - compatible: Should be "arm,mali-d71" | |
| - reg: Physical base address and length of the registers in the system | |
| - interrupts: the interrupt line number of the device in the system | |
| - clocks: A list of phandle + clock-specifier pairs, one for each entry | |
| in 'clock-names' | |
| - clock-names: A list of clock names. It should contain: | |
| - "aclk": for the main processor clock | |
| - #address-cells: Must be 1 | |
| - #size-cells: Must be 0 | |
| - iommus: configure the stream id to IOMMU, Must be configured if want to | |
| enable iommu in display. for how to configure this node please reference | |
| devicetree/bindings/iommu/arm,smmu-v3.txt, | |
| devicetree/bindings/iommu/iommu.txt | |
| Required properties for sub-node: pipeline@nq | |
| Each device contains one or two pipeline sub-nodes (at least one), each | |
| pipeline node should provide properties: | |
| - reg: Zero-indexed identifier for the pipeline | |
| - clocks: A list of phandle + clock-specifier pairs, one for each entry | |
| in 'clock-names' | |
| - clock-names: should contain: | |
| - "pxclk": pixel clock | |
| - port: each pipeline connect to an encoder input port. The connection is | |
| modeled using the OF graph bindings specified in | |
| Documentation/devicetree/bindings/graph.txt | |
| Optional properties: | |
| - memory-region: phandle to a node describing memory (see | |
| Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) | |
| to be used for the framebuffer; if not present, the framebuffer may | |
| be located anywhere in memory. | |
| Example: | |
| / { | |
| ... | |
| dp0: display@c00000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "arm,mali-d71"; | |
| reg = <0xc00000 0x20000>; | |
| interrupts = <0 168 4>; | |
| clocks = <&dpu_aclk>; | |
| clock-names = "aclk"; | |
| iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>, | |
| <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>, | |
| <&smmu 8>, <&smmu 9>; | |
| dp0_pipe0: pipeline@0 { | |
| clocks = <&fpgaosc2>; | |
| clock-names = "pxclk"; | |
| reg = <0>; | |
| port { | |
| dp0_pipe0_out: endpoint { | |
| remote-endpoint = <&db_dvi0_in>; | |
| }; | |
| }; | |
| }; | |
| dp0_pipe1: pipeline@1 { | |
| clocks = <&fpgaosc2>; | |
| clock-names = "pxclk"; | |
| reg = <1>; | |
| port { | |
| dp0_pipe1_out: endpoint { | |
| remote-endpoint = <&db_dvi1_in>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| ... | |
| }; |
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| ARM Mali-DP | |
| The following bindings apply to a family of Display Processors sold as | |
| licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and | |
| DP650 processors that offer multiple composition layers, support for | |
| rotation and scaling output. | |
| Required properties: | |
| - compatible: should be one of | |
| "arm,mali-dp500" | |
| "arm,mali-dp550" | |
| "arm,mali-dp650" | |
| depending on the particular implementation present in the hardware | |
| - reg: Physical base address and size of the block of registers used by | |
| the processor. | |
| - interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt, | |
| interrupt client nodes. | |
| - interrupt-names: name of the engine inside the processor that will | |
| use the corresponding interrupt. Should be one of "DE" or "SE". | |
| - clocks: A list of phandle + clock-specifier pairs, one for each entry | |
| in 'clock-names' | |
| - clock-names: A list of clock names. It should contain: | |
| - "pclk": for the APB interface clock | |
| - "aclk": for the AXI interface clock | |
| - "mclk": for the main processor clock | |
| - "pxlclk": for the pixel clock feeding the output PLL of the processor. | |
| - arm,malidp-output-port-lines: Array of u8 values describing the number | |
| of output lines per channel (R, G and B). | |
| Required sub-nodes: | |
| - port: The Mali DP connection to an encoder input port. The connection | |
| is modelled using the OF graph bindings specified in | |
| Documentation/devicetree/bindings/graph.txt | |
| Optional properties: | |
| - memory-region: phandle to a node describing memory (see | |
| Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) | |
| to be used for the framebuffer; if not present, the framebuffer may | |
| be located anywhere in memory. | |
| - arm,malidp-arqos-high-level: integer of u32 value describing the ARQoS | |
| levels of DP500's QoS signaling. | |
| Example: | |
| / { | |
| ... | |
| dp0: malidp@6f200000 { | |
| compatible = "arm,mali-dp650"; | |
| reg = <0 0x6f200000 0 0x20000>; | |
| memory-region = <&display_reserved>; | |
| interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>, | |
| <0 168 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-names = "DE", "SE"; | |
| clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>; | |
| clock-names = "pxlclk", "mclk", "aclk", "pclk"; | |
| arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; | |
| arm,malidp-arqos-high-level = <0xd000d000>; | |
| port { | |
| dp0_output: endpoint { | |
| remote-endpoint = <&tda998x_2_input>; | |
| }; | |
| }; | |
| }; | |
| ... | |
| }; |
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| ARM MPS2 timer | |
| The MPS2 platform has simple general-purpose 32 bits timers. | |
| Required properties: | |
| - compatible : Should be "arm,mps2-timer" | |
| - reg : Address and length of the register set | |
| - interrupts : Reference to the timer interrupt | |
| Required clocking property, have to be one of: | |
| - clocks : The input clock of the timer | |
| - clock-frequency : The rate in HZ in input of the ARM MPS2 timer | |
| Examples: | |
| timer1: mps2-timer@40000000 { | |
| compatible = "arm,mps2-timer"; | |
| reg = <0x40000000 0x1000>; | |
| interrupts = <8>; | |
| clocks = <&sysclk>; | |
| }; | |
| timer2: mps2-timer@40001000 { | |
| compatible = "arm,mps2-timer"; | |
| reg = <0x40001000 0x1000>; | |
| interrupts = <9>; | |
| clock-frequency = <25000000>; | |
| }; |
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| ARM MPS2 UART | |
| Required properties: | |
| - compatible : Should be "arm,mps2-uart" | |
| - reg : Address and length of the register set | |
| - interrupts : Reference to the UART RX, TX and overrun interrupts | |
| Required clocking property: | |
| - clocks : The input clock of the UART | |
| Examples: | |
| uart0: serial@40004000 { | |
| compatible = "arm,mps2-uart"; | |
| reg = <0x40004000 0x1000>; | |
| interrupts = <0 1 12>; | |
| clocks = <&sysclk>; | |
| }; |
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| * ARM Nested Vector Interrupt Controller (NVIC) | |
| The NVIC provides an interrupt controller that is tightly coupled to | |
| Cortex-M based processor cores. The NVIC implemented on different SoCs | |
| vary in the number of interrupts and priority bits per interrupt. | |
| Main node required properties: | |
| - compatible : should be one of: | |
| "arm,v6m-nvic" | |
| "arm,v7m-nvic" | |
| "arm,v8m-nvic" | |
| - interrupt-controller : Identifies the node as an interrupt controller | |
| - #interrupt-cells : Specifies the number of cells needed to encode an | |
| interrupt source. The type shall be a <u32> and the value shall be 2. | |
| The 1st cell contains the interrupt number for the interrupt type. | |
| The 2nd cell is the priority of the interrupt. | |
| - reg : Specifies base physical address(s) and size of the NVIC registers. | |
| This is at a fixed address (0xe000e100) and size (0xc00). | |
| - arm,num-irq-priority-bits: The number of priority bits implemented by the | |
| given SoC | |
| Example: | |
| intc: interrupt-controller@e000e100 { | |
| compatible = "arm,v7m-nvic"; | |
| #interrupt-cells = <2>; | |
| #address-cells = <1>; | |
| interrupt-controller; | |
| reg = <0xe000e100 0xc00>; | |
| arm,num-irq-priority-bits = <4>; | |
| }; |
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| * ARM PrimeCell Color LCD Controller PL110/PL111 | |
| See also Documentation/devicetree/bindings/arm/primecell.yaml | |
| Required properties: | |
| - compatible: must be one of: | |
| "arm,pl110", "arm,primecell" | |
| "arm,pl111", "arm,primecell" | |
| - reg: base address and size of the control registers block | |
| - interrupt-names: either the single entry "combined" representing a | |
| combined interrupt output (CLCDINTR), or the four entries | |
| "mbe", "vcomp", "lnbu", "fuf" representing the individual | |
| CLCDMBEINTR, CLCDVCOMPINTR, CLCDLNBUINTR, CLCDFUFINTR interrupts | |
| - interrupts: contains an interrupt specifier for each entry in | |
| interrupt-names | |
| - clock-names: should contain "clcdclk" and "apb_pclk" | |
| - clocks: contains phandle and clock specifier pairs for the entries | |
| in the clock-names property. See | |
| Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| Optional properties: | |
| - memory-region: phandle to a node describing memory (see | |
| Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) | |
| to be used for the framebuffer; if not present, the framebuffer | |
| may be located anywhere in the memory | |
| - max-memory-bandwidth: maximum bandwidth in bytes per second that the | |
| cell's memory interface can handle; if not present, the memory | |
| interface is fast enough to handle all possible video modes | |
| Required sub-nodes: | |
| - port: describes LCD panel signals, following the common binding | |
| for video transmitter interfaces; see | |
| Documentation/devicetree/bindings/media/video-interfaces.txt | |
| Deprecated properties: | |
| The port's endbpoint subnode had this, now deprecated property | |
| in the past. Drivers should be able to survive without it: | |
| - arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values, | |
| defining the way CLD pads are wired up; first value | |
| contains index of the "CLD" external pin (pad) used | |
| as R0 (first bit of the red component), second value | |
| index of the pad used as G0, third value index of the | |
| pad used as B0, see also "LCD panel signal multiplexing | |
| details" paragraphs in the PL110/PL111 Technical | |
| Reference Manuals; this implicitly defines available | |
| color modes, for example: | |
| - PL111 TFT 4:4:4 panel: | |
| arm,pl11x,tft-r0g0b0-pads = <4 15 20>; | |
| - PL110 TFT (1:)5:5:5 panel: | |
| arm,pl11x,tft-r0g0b0-pads = <1 7 13>; | |
| - PL111 TFT (1:)5:5:5 panel: | |
| arm,pl11x,tft-r0g0b0-pads = <3 11 19>; | |
| - PL111 TFT 5:6:5 panel: | |
| arm,pl11x,tft-r0g0b0-pads = <3 10 19>; | |
| - PL110 and PL111 TFT 8:8:8 panel: | |
| arm,pl11x,tft-r0g0b0-pads = <0 8 16>; | |
| - PL110 and PL111 TFT 8:8:8 panel, R & B components swapped: | |
| arm,pl11x,tft-r0g0b0-pads = <16 8 0>; | |
| Example: | |
| clcd@10020000 { | |
| compatible = "arm,pl111", "arm,primecell"; | |
| reg = <0x10020000 0x1000>; | |
| interrupt-names = "combined"; | |
| interrupts = <0 44 4>; | |
| clocks = <&oscclk1>, <&oscclk2>; | |
| clock-names = "clcdclk", "apb_pclk"; | |
| max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */ | |
| port { | |
| clcd_pads: endpoint { | |
| remote-endpoint = <&clcd_panel>; | |
| }; | |
| }; | |
| }; | |
| panel { | |
| compatible = "panel-dpi"; | |
| port { | |
| clcd_panel: endpoint { | |
| remote-endpoint = <&clcd_pads>; | |
| }; | |
| }; | |
| panel-timing { | |
| clock-frequency = <25175000>; | |
| hactive = <640>; | |
| hback-porch = <40>; | |
| hfront-porch = <24>; | |
| hsync-len = <96>; | |
| vactive = <480>; | |
| vback-porch = <32>; | |
| vfront-porch = <11>; | |
| vsync-len = <2>; | |
| }; | |
| }; |
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| * Device tree bindings for ARM PL172/PL175/PL176 MultiPort Memory Controller | |
| Required properties: | |
| - compatible: Must be "arm,primecell" and exactly one from | |
| "arm,pl172", "arm,pl175" or "arm,pl176". | |
| - reg: Must contains offset/length value for controller. | |
| - #address-cells: Must be 2. The partition number has to be encoded in the | |
| first address cell and it may accept values 0..N-1 | |
| (N - total number of partitions). The second cell is the | |
| offset into the partition. | |
| - #size-cells: Must be set to 1. | |
| - ranges: Must contain one or more chip select memory regions. | |
| - clocks: Must contain references to controller clocks. | |
| - clock-names: Must contain "mpmcclk" and "apb_pclk". | |
| - clock-ranges: Empty property indicating that child nodes can inherit | |
| named clocks. Required only if clock tree data present | |
| in device tree. | |
| See clock-bindings.txt | |
| Child chip-select (cs) nodes contain the memory devices nodes connected to | |
| such as NOR (e.g. cfi-flash) and NAND. | |
| Required child cs node properties: | |
| - #address-cells: Must be 2. | |
| - #size-cells: Must be 1. | |
| - ranges: Empty property indicating that child nodes can inherit | |
| memory layout. | |
| - clock-ranges: Empty property indicating that child nodes can inherit | |
| named clocks. Required only if clock tree data present | |
| in device tree. | |
| - mpmc,cs: Chip select number. Indicates to the pl0172 driver | |
| which chipselect is used for accessing the memory. | |
| - mpmc,memory-width: Width of the chip select memory. Must be equal to | |
| either 8, 16 or 32. | |
| Optional child cs node config properties: | |
| - mpmc,async-page-mode: Enable asynchronous page mode. | |
| - mpmc,cs-active-high: Set chip select polarity to active high. | |
| - mpmc,byte-lane-low: Set byte lane state to low. | |
| - mpmc,extended-wait: Enable extended wait. | |
| - mpmc,buffer-enable: Enable write buffer, option is not supported by | |
| PL175 and PL176 controllers. | |
| - mpmc,write-protect: Enable write protect. | |
| Optional child cs node timing properties: | |
| - mpmc,write-enable-delay: Delay from chip select assertion to write | |
| enable (WE signal) in nano seconds. | |
| - mpmc,output-enable-delay: Delay from chip select assertion to output | |
| enable (OE signal) in nano seconds. | |
| - mpmc,write-access-delay: Delay from chip select assertion to write | |
| access in nano seconds. | |
| - mpmc,read-access-delay: Delay from chip select assertion to read | |
| access in nano seconds. | |
| - mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential | |
| accesses in nano seconds. | |
| - mpmc,turn-round-delay: Delay between access to memory banks in nano | |
| seconds. | |
| If any of the above timing parameters are absent, current parameter value will | |
| be taken from the corresponding HW reg. | |
| Example for pl172 with nor flash on chip select 0 shown below. | |
| emc: memory-controller@40005000 { | |
| compatible = "arm,pl172", "arm,primecell"; | |
| reg = <0x40005000 0x1000>; | |
| clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; | |
| clock-names = "mpmcclk", "apb_pclk"; | |
| #address-cells = <2>; | |
| #size-cells = <1>; | |
| ranges = <0 0 0x1c000000 0x1000000 | |
| 1 0 0x1d000000 0x1000000 | |
| 2 0 0x1e000000 0x1000000 | |
| 3 0 0x1f000000 0x1000000>; | |
| cs0 { | |
| #address-cells = <2>; | |
| #size-cells = <1>; | |
| ranges; | |
| mpmc,cs = <0>; | |
| mpmc,memory-width = <16>; | |
| mpmc,byte-lane-low; | |
| mpmc,write-enable-delay = <0>; | |
| mpmc,output-enable-delay = <0>; | |
| mpmc,read-enable-delay = <70>; | |
| mpmc,page-mode-read-delay = <70>; | |
| flash@0,0 { | |
| compatible = "sst,sst39vf320", "cfi-flash"; | |
| reg = <0 0 0x400000>; | |
| bank-width = <2>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| partition@0 { | |
| label = "data"; | |
| reg = <0 0x400000>; | |
| }; | |
| }; | |
| }; | |
| }; |
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| * ARM Versatile FPGA interrupt controller | |
| One or more FPGA IRQ controllers can be synthesized in an ARM reference board | |
| such as the Integrator or Versatile family. The output of these different | |
| controllers are OR:ed together and fed to the CPU tile's IRQ input. Each | |
| instance can handle up to 32 interrupts. | |
| Required properties: | |
| - compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq" | |
| - interrupt-controller: Identifies the node as an interrupt controller | |
| - #interrupt-cells: The number of cells to define the interrupts. Must be 1 | |
| as the FPGA IRQ controller has no configuration options for interrupt | |
| sources. The cell is a u32 and defines the interrupt number. | |
| - reg: The register bank for the FPGA interrupt controller. | |
| - clear-mask: a u32 number representing the mask written to clear all IRQs | |
| on the controller at boot for example. | |
| - valid-mask: a u32 number representing a bit mask determining which of | |
| the interrupts are valid. Unconnected/unused lines are set to 0, and | |
| the system till not make it possible for devices to request these | |
| interrupts. | |
| Example: | |
| pic: pic@14000000 { | |
| compatible = "arm,versatile-fpga-irq"; | |
| #interrupt-cells = <1>; | |
| interrupt-controller; | |
| reg = <0x14000000 0x100>; | |
| clear-mask = <0xffffffff>; | |
| valid-mask = <0x003fffff>; | |
| }; | |
| Optional properties: | |
| - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ | |
| output is simply connected to the input of another IRQ controller, | |
| then the parent IRQ shall be specified in this property. |
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| * ARM CCN (Cache Coherent Network) | |
| Required properties: | |
| - compatible: (standard compatible string) should be one of: | |
| "arm,ccn-502" | |
| "arm,ccn-504" | |
| "arm,ccn-508" | |
| "arm,ccn-512" | |
| - reg: (standard registers property) physical address and size | |
| (16MB) of the configuration registers block | |
| - interrupts: (standard interrupt property) single interrupt | |
| generated by the control block | |
| Example: | |
| ccn@2000000000 { | |
| compatible = "arm,ccn-504"; | |
| reg = <0x20 0x00000000 0 0x1000000>; | |
| interrupts = <0 181 4>; | |
| }; |
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| * ARM SBSA defined generic UART | |
| This UART uses a subset of the PL011 registers and consequently lives | |
| in the PL011 driver. It's baudrate and other communication parameters | |
| cannot be adjusted at runtime, so it lacks a clock specifier here. | |
| Required properties: | |
| - compatible: must be "arm,sbsa-uart" | |
| - reg: exactly one register range | |
| - interrupts: exactly one interrupt specifier | |
| - current-speed: the (fixed) baud rate set by the firmware |
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| Power Management Service Unit(PMSU) | |
| ----------------------------------- | |
| Available on Marvell SOCs: Armada 370, Armada 38x and Armada XP | |
| Required properties: | |
| - compatible: should be one of: | |
| - "marvell,armada-370-pmsu" for Armada 370 or Armada XP | |
| - "marvell,armada-380-pmsu" for Armada 38x | |
| - "marvell,armada-370-xp-pmsu" was used for Armada 370/XP but is now | |
| deprecated and will be removed | |
| - reg: Should contain PMSU registers location and length. | |
| Example: | |
| armada-370-xp-pmsu@22000 { | |
| compatible = "marvell,armada-370-pmsu"; | |
| reg = <0x22000 0x1000>; | |
| }; | |
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| Marvell Armada 370 and Armada XP Platforms Device Tree Bindings | |
| --------------------------------------------------------------- | |
| Boards with a SoC of the Marvell Armada 370 and Armada XP families | |
| shall have the following property: | |
| Required root node property: | |
| compatible: must contain "marvell,armada-370-xp" | |
| In addition, boards using the Marvell Armada 370 SoC shall have the | |
| following property: | |
| Required root node property: | |
| compatible: must contain "marvell,armada370" | |
| In addition, boards using the Marvell Armada XP SoC shall have the | |
| following property: | |
| Required root node property: | |
| compatible: must contain "marvell,armadaxp" | |
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| Device Tree bindings for the Armada 370 DB audio | |
| ================================================ | |
| These Device Tree bindings are used to describe the audio complex | |
| found on the Armada 370 DB platform. | |
| Mandatory properties: | |
| * compatible: must be "marvell,a370db-audio" | |
| * marvell,audio-controller: a phandle that points to the audio | |
| controller of the Armada 370 SoC. | |
| * marvell,audio-codec: a set of three phandles that points to: | |
| 1/ the analog audio codec connected to the Armada 370 SoC | |
| 2/ the S/PDIF transceiver | |
| 3/ the S/PDIF receiver | |
| Example: | |
| sound { | |
| compatible = "marvell,a370db-audio"; | |
| marvell,audio-controller = <&audio_controller>; | |
| marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>; | |
| }; |
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| Marvell Armada 375 Platforms Device Tree Bindings | |
| ------------------------------------------------- | |
| Boards with a SoC of the Marvell Armada 375 family shall have the | |
| following property: | |
| Required root node property: | |
| compatible: must contain "marvell,armada375" |
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| * Armada 37xx CPU Watchdog Timer Controller | |
| Required properties: | |
| - compatible : must be "marvell,armada-3700-wdt" | |
| - reg : base physical address of the controller and length of memory mapped | |
| region. | |
| - clocks : the clock feeding the watchdog timer. See clock-bindings.txt | |
| - marvell,system-controller : reference to syscon node for the CPU Miscellaneous | |
| Registers | |
| Example: | |
| cpu_misc: system-controller@d000 { | |
| compatible = "marvell,armada-3700-cpu-misc", "syscon"; | |
| reg = <0xd000 0x1000>; | |
| }; | |
| wdt: watchdog@8300 { | |
| compatible = "marvell,armada-3700-wdt"; | |
| reg = <0x8300 0x40>; | |
| marvell,system-controller = <&cpu_misc>; | |
| clocks = <&xtalclk>; | |
| }; |
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| Marvell Armada 37xx Platforms Device Tree Bindings | |
| -------------------------------------------------- | |
| Boards using a SoC of the Marvell Armada 37xx family must carry the | |
| following root node property: | |
| - compatible: must contain "marvell,armada3710" | |
| In addition, boards using the Marvell Armada 3720 SoC shall have the | |
| following property before the previous one: | |
| - compatible: must contain "marvell,armada3720" | |
| Example: | |
| compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710"; | |
| Power management | |
| ---------------- | |
| For power management (particularly DVFS and AVS), the North Bridge | |
| Power Management component is needed: | |
| Required properties: | |
| - compatible : should contain "marvell,armada-3700-nb-pm", "syscon"; | |
| - reg : the register start and length for the North Bridge | |
| Power Management | |
| Example: | |
| nb_pm: syscon@14000 { | |
| compatible = "marvell,armada-3700-nb-pm", "syscon"; | |
| reg = <0x14000 0x60>; | |
| } | |
| AVS | |
| --- | |
| For AVS an other component is needed: | |
| Required properties: | |
| - compatible : should contain "marvell,armada-3700-avs", "syscon"; | |
| - reg : the register start and length for the AVS | |
| Example: | |
| avs: avs@11500 { | |
| compatible = "marvell,armada-3700-avs", "syscon"; | |
| reg = <0x11500 0x40>; | |
| } | |
| CZ.NIC's Turris Mox SOHO router Device Tree Bindings | |
| ---------------------------------------------------- | |
| Required root node property: | |
| - compatible: must contain "cznic,turris-mox" |
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| Marvell Armada 38x CA9 MPcore SoC Controller | |
| ============================================ | |
| Required properties: | |
| - compatible: Should be "marvell,armada-380-mpcore-soc-ctrl". | |
| - reg: should be the register base and length as documented in the | |
| datasheet for the CA9 MPcore SoC Control registers | |
| mpcore-soc-ctrl@20d20 { | |
| compatible = "marvell,armada-380-mpcore-soc-ctrl"; | |
| reg = <0x20d20 0x6c>; | |
| }; |
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| * Real Time Clock of the Armada 38x/7K/8K SoCs | |
| RTC controller for the Armada 38x, 7K and 8K SoCs | |
| Required properties: | |
| - compatible : Should be one of the following: | |
| "marvell,armada-380-rtc" for Armada 38x SoC | |
| "marvell,armada-8k-rtc" for Aramda 7K/8K SoCs | |
| - reg: a list of base address and size pairs, one for each entry in | |
| reg-names | |
| - reg names: should contain: | |
| * "rtc" for the RTC registers | |
| * "rtc-soc" for the SoC related registers and among them the one | |
| related to the interrupt. | |
| - interrupts: IRQ line for the RTC. | |
| Example: | |
| rtc@a3800 { | |
| compatible = "marvell,armada-380-rtc"; | |
| reg = <0xa3800 0x20>, <0x184a0 0x0c>; | |
| reg-names = "rtc", "rtc-soc"; | |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
| }; |
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| Marvell Armada 38x Platforms Device Tree Bindings | |
| ------------------------------------------------- | |
| Boards with a SoC of the Marvell Armada 38x family shall have the | |
| following property: | |
| Required root node property: | |
| - compatible: must contain "marvell,armada380" | |
| In addition, boards using the Marvell Armada 385 SoC shall have the | |
| following property before the previous one: | |
| Required root node property: | |
| compatible: must contain "marvell,armada385" | |
| In addition, boards using the Marvell Armada 388 SoC shall have the | |
| following property before the previous one: | |
| Required root node property: | |
| compatible: must contain "marvell,armada388" | |
| Example: | |
| compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380"; |
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| Marvell Armada 39x Platforms Device Tree Bindings | |
| ------------------------------------------------- | |
| Boards with a SoC of the Marvell Armada 39x family shall have the | |
| following property: | |
| Required root node property: | |
| - compatible: must contain "marvell,armada390" | |
| In addition, boards using the Marvell Armada 395 SoC shall have the | |
| following property before the common "marvell,armada390" one: | |
| Required root node property: | |
| compatible: must contain "marvell,armada395" | |
| Example: | |
| compatible = "marvell,a395-gp", "marvell,armada395", "marvell,armada390"; | |
| Boards using the Marvell Armada 398 SoC shall have the following | |
| property before the common "marvell,armada390" one: | |
| Required root node property: | |
| compatible: must contain "marvell,armada398" | |
| Example: | |
| compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390"; |
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| Marvell Armada 8KPlus Platforms Device Tree Bindings | |
| ---------------------------------------------------- | |
| Boards using a SoC of the Marvell Armada 8KP families must carry | |
| the following root node property: | |
| - compatible, with one of the following values: | |
| - "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810" | |
| when the SoC being used is the Armada 8080 | |
| Example: | |
| compatible = "marvell,armada-8080-db", "marvell,armada-8080", | |
| "marvell,armada-ap810-octa", "marvell,armada-ap810" |
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| Marvell Armada CPU reset controller | |
| =================================== | |
| Required properties: | |
| - compatible: Should be "marvell,armada-370-cpu-reset". | |
| - reg: should be register base and length as documented in the | |
| datasheet for the CPU reset registers | |
| cpurst: cpurst@20800 { | |
| compatible = "marvell,armada-370-cpu-reset"; | |
| reg = <0x20800 0x20>; | |
| }; |
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| * Marvell Armada 370/375/380/XP thermal management | |
| Required properties: | |
| - compatible: Should be set to one of the following: | |
| * marvell,armada370-thermal | |
| * marvell,armada375-thermal | |
| * marvell,armada380-thermal | |
| * marvell,armadaxp-thermal | |
| * marvell,armada-ap806-thermal | |
| * marvell,armada-cp110-thermal | |
| Note: these bindings are deprecated for AP806/CP110 and should instead | |
| follow the rules described in: | |
| Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt | |
| Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt | |
| - reg: Device's register space. | |
| Two entries are expected, see the examples below. The first one points | |
| to the status register (4B). The second one points to the control | |
| registers (8B). | |
| Note: The compatibles marvell,armada370-thermal, | |
| marvell,armada380-thermal, and marvell,armadaxp-thermal must point to | |
| "control MSB/control 1", with size of 4 (deprecated binding), or point | |
| to "control LSB/control 0" with size of 8 (current binding). All other | |
| compatibles must point to "control LSB/control 0" with size of 8. | |
| Examples: | |
| /* Legacy bindings */ | |
| thermal@d0018300 { | |
| compatible = "marvell,armada370-thermal"; | |
| reg = <0xd0018300 0x4 | |
| 0xd0018304 0x4>; | |
| }; | |
| ap_thermal: thermal@6f8084 { | |
| compatible = "marvell,armada-ap806-thermal"; | |
| reg = <0x6f808C 0x4>, | |
| <0x6f8084 0x8>; | |
| }; |
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| * Peripheral Clock bindings for Marvell Armada 37xx SoCs | |
| Marvell Armada 37xx SoCs provide peripheral clocks which are | |
| used as clock source for the peripheral of the SoC. | |
| There are two different blocks associated to north bridge and south | |
| bridge. | |
| The peripheral clock consumer should specify the desired clock by | |
| having the clock ID in its "clocks" phandle cell. | |
| The following is a list of provided IDs for Armada 3700 North bridge clocks: | |
| ID Clock name Description | |
| ----------------------------------- | |
| 0 mmc MMC controller | |
| 1 sata_host Sata Host | |
| 2 sec_at Security AT | |
| 3 sac_dap Security DAP | |
| 4 tsecm Security Engine | |
| 5 setm_tmx Serial Embedded Trace Module | |
| 6 avs Adaptive Voltage Scaling | |
| 7 sqf SPI | |
| 8 pwm PWM | |
| 9 i2c_2 I2C 2 | |
| 10 i2c_1 I2C 1 | |
| 11 ddr_phy DDR PHY | |
| 12 ddr_fclk DDR F clock | |
| 13 trace Trace | |
| 14 counter Counter | |
| 15 eip97 EIP 97 | |
| 16 cpu CPU | |
| The following is a list of provided IDs for Armada 3700 South bridge clocks: | |
| ID Clock name Description | |
| ----------------------------------- | |
| 0 gbe-50 50 MHz parent clock for Gigabit Ethernet | |
| 1 gbe-core parent clock for Gigabit Ethernet core | |
| 2 gbe-125 125 MHz parent clock for Gigabit Ethernet | |
| 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1 | |
| 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0 | |
| 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1 | |
| 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0 | |
| 7 gbe1-core Gigabit Ethernet core port 1 | |
| 8 gbe0-core Gigabit Ethernet core port 0 | |
| 9 gbe-bm Gigabit Ethernet Buffer Manager | |
| 10 sdio SDIO | |
| 11 usb32-sub2-sys USB 2 clock | |
| 12 usb32-ss-sys USB 3 clock | |
| 13 pcie PCIe controller | |
| Required properties: | |
| - compatible : shall be "marvell,armada-3700-periph-clock-nb" for the | |
| north bridge block, or | |
| "marvell,armada-3700-periph-clock-sb" for the south bridge block | |
| - reg : must be the register address of North/South Bridge Clock register | |
| - #clock-cells : from common clock binding; shall be set to 1 | |
| - clocks : list of the parent clock phandle in the following order: | |
| TBG-A P, TBG-B P, TBG-A S, TBG-B S and finally the xtal clock. | |
| Example: | |
| nb_perih_clk: nb-periph-clk@13000{ | |
| compatible = "marvell,armada-3700-periph-clock-nb"; | |
| reg = <0x13000 0x1000>; | |
| clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, | |
| <&tbg 3>, <&xtalclk>; | |
| #clock-cells = <1>; | |
| }; |
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| * Time Base Generator Clock bindings for Marvell Armada 37xx SoCs | |
| Marvell Armada 37xx SoCs provide Time Base Generator clocks which are | |
| used as parent clocks for the peripheral clocks. | |
| The TBG clock consumer should specify the desired clock by having the | |
| clock ID in its "clocks" phandle cell. | |
| The following is a list of provided IDs and clock names on Armada 3700: | |
| 0 = TBG A P | |
| 1 = TBG B P | |
| 2 = TBG A S | |
| 3 = TBG B S | |
| Required properties: | |
| - compatible : shall be "marvell,armada-3700-tbg-clock" | |
| - reg : must be the register address of North Bridge PLL register | |
| - #clock-cells : from common clock binding; shall be set to 1 | |
| Example: | |
| tbg: tbg@13200 { | |
| compatible = "marvell,armada-3700-tbg-clock"; | |
| reg = <0x13200 0x1000>; | |
| clocks = <&xtalclk>; | |
| #clock-cells = <1>; | |
| }; |
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| * Xtal Clock bindings for Marvell Armada 37xx SoCs | |
| Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by | |
| reading the gpio latch register. | |
| This node must be a subnode of the node exposing the register address | |
| of the GPIO block where the gpio latch is located. | |
| See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt | |
| Required properties: | |
| - compatible : shall be one of the following: | |
| "marvell,armada-3700-xtal-clock" | |
| - #clock-cells : from common clock binding; shall be set to 0 | |
| Optional properties: | |
| - clock-output-names : from common clock binding; allows overwrite default clock | |
| output names ("xtal") | |
| Example: | |
| pinctrl_nb: pinctrl-nb@13800 { | |
| compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd"; | |
| reg = <0x13800 0x100>, <0x13C00 0x20>; | |
| xtalclk: xtal-clk { | |
| compatible = "marvell,armada-3700-xtal-clock"; | |
| clock-output-names = "xtal"; | |
| #clock-cells = <0>; | |
| }; | |
| }; |
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| Audio Binding for Arndale boards | |
| Required properties: | |
| - compatible : Can be one of the following: | |
| "samsung,arndale-rt5631", | |
| "samsung,arndale-wm1811" | |
| - samsung,audio-cpu: The phandle of the Samsung I2S controller | |
| - samsung,audio-codec: The phandle of the audio codec | |
| Optional: | |
| - samsung,model: The name of the sound-card | |
| Arndale Boards has many audio daughter cards, one of them is | |
| rt5631/alc5631. Below example shows audio bindings for rt5631/ | |
| alc5631 based codec. | |
| Example: | |
| sound { | |
| compatible = "samsung,arndale-rt5631"; | |
| samsung,audio-cpu = <&i2s0> | |
| samsung,audio-codec = <&rt5631>; | |
| }; |
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| Axis crypto engine with PDMA interface. | |
| Required properties: | |
| - compatible : Should be one of the following strings: | |
| "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC | |
| "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC. | |
| - reg: Base address and size for the PDMA register area. | |
| - interrupts: Interrupt handle for the PDMA interrupt line. | |
| Example: | |
| crypto@f4264000 { | |
| compatible = "axis,artpec6-crypto"; | |
| reg = <0xf4264000 0x1000>; | |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
| }; |
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| * Clock bindings for Axis ARTPEC-6 chip | |
| The bindings are based on the clock provider binding in | |
| Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| External clocks: | |
| ---------------- | |
| There are two external inputs to the main clock controller which should be | |
| provided using the common clock bindings. | |
| - "sys_refclk": External 50 Mhz oscillator (required) | |
| - "i2s_refclk": Alternate audio reference clock (optional). | |
| Main clock controller | |
| --------------------- | |
| Required properties: | |
| - #clock-cells: Should be <1> | |
| See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers. | |
| - compatible: Should be "axis,artpec6-clkctrl" | |
| - reg: Must contain the base address and length of the system controller | |
| - clocks: Must contain a phandle entry for each clock in clock-names | |
| - clock-names: Must include the external oscillator ("sys_refclk"). Optional | |
| ones are the audio reference clock ("i2s_refclk") and the audio fractional | |
| dividers ("frac_clk0" and "frac_clk1"). | |
| Examples: | |
| ext_clk: ext_clk { | |
| #clock-cells = <0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <50000000>; | |
| }; | |
| clkctrl: clkctrl@f8000000 { | |
| #clock-cells = <1>; | |
| compatible = "axis,artpec6-clkctrl"; | |
| reg = <0xf8000000 0x48>; | |
| clocks = <&ext_clk>; | |
| clock-names = "sys_refclk"; | |
| }; |
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| Bindings for Synaptics AS370 PVT sensors | |
| Required properties: | |
| - compatible : "syna,as370-hwmon" | |
| - reg : address and length of the register set. | |
| Example: | |
| hwmon@ea0810 { | |
| compatible = "syna,as370-hwmon"; | |
| reg = <0xea0810 0xc>; | |
| }; |
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| AS3711 is an I2C PMIC from Austria MicroSystems with multiple DCDC and LDO power | |
| supplies, a battery charger and an RTC. So far only bindings for the two stepup | |
| DCDC converters are defined. Other DCDC and LDO supplies are configured, using | |
| standard regulator properties, they must belong to a sub-node, called | |
| "regulators" and be called "sd1" to "sd4" and "ldo1" to "ldo8." Stepup converter | |
| configuration should be placed in a subnode, called "backlight." | |
| Compulsory properties: | |
| - compatible : must be "ams,as3711" | |
| - reg : specifies the I2C address | |
| To use the SU1 converter as a backlight source the following two properties must | |
| be provided: | |
| - su1-dev : framebuffer phandle | |
| - su1-max-uA : maximum current | |
| To use the SU2 converter as a backlight source the following two properties must | |
| be provided: | |
| - su2-dev : framebuffer phandle | |
| - su1-max-uA : maximum current | |
| Additionally one of these properties must be provided to select the type of | |
| feedback used: | |
| - su2-feedback-voltage : voltage feedback is used | |
| - su2-feedback-curr1 : CURR1 input used for current feedback | |
| - su2-feedback-curr2 : CURR2 input used for current feedback | |
| - su2-feedback-curr3 : CURR3 input used for current feedback | |
| - su2-feedback-curr-auto: automatic current feedback selection | |
| and one of these to select the over-voltage protection pin | |
| - su2-fbprot-lx-sd4 : LX_SD4 is used for over-voltage protection | |
| - su2-fbprot-gpio2 : GPIO2 is used for over-voltage protection | |
| - su2-fbprot-gpio3 : GPIO3 is used for over-voltage protection | |
| - su2-fbprot-gpio4 : GPIO4 is used for over-voltage protection | |
| If "su2-feedback-curr-auto" is selected, one or more of the following properties | |
| have to be specified: | |
| - su2-auto-curr1 : use CURR1 input for current feedback | |
| - su2-auto-curr2 : use CURR2 input for current feedback | |
| - su2-auto-curr3 : use CURR3 input for current feedback | |
| Example: | |
| as3711@40 { | |
| compatible = "ams,as3711"; | |
| reg = <0x40>; | |
| regulators { | |
| sd4 { | |
| regulator-name = "1.215V"; | |
| regulator-min-microvolt = <1215000>; | |
| regulator-max-microvolt = <1235000>; | |
| }; | |
| ldo2 { | |
| regulator-name = "2.8V CPU"; | |
| regulator-min-microvolt = <2800000>; | |
| regulator-max-microvolt = <2800000>; | |
| regulator-always-on; | |
| regulator-boot-on; | |
| }; | |
| }; | |
| backlight { | |
| compatible = "ams,as3711-bl"; | |
| su2-dev = <&lcdc>; | |
| su2-max-uA = <36000>; | |
| su2-feedback-curr-auto; | |
| su2-fbprot-gpio4; | |
| su2-auto-curr1; | |
| su2-auto-curr2; | |
| su2-auto-curr3; | |
| }; | |
| }; |
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| Regulator of AMS AS3722 PMIC. | |
| Name of the regulator subnode must be "regulators". | |
| Optional properties: | |
| -------------------- | |
| The input supply of regulators are the optional properties on the | |
| regulator node. The AS3722 is having 7 DCDC step-down regulators as | |
| sd[0-6], 10 LDOs as ldo[0-7], ldo[9-11]. The input supply of these | |
| regulators are provided through following properties: | |
| vsup-sd2-supply: Input supply for SD2. | |
| vsup-sd3-supply: Input supply for SD3. | |
| vsup-sd4-supply: Input supply for SD4. | |
| vsup-sd5-supply: Input supply for SD5. | |
| vin-ldo0-supply: Input supply for LDO0. | |
| vin-ldo1-6-supply: Input supply for LDO1 and LDO6. | |
| vin-ldo2-5-7-supply: Input supply for LDO2, LDO5 and LDO7. | |
| vin-ldo3-4-supply: Input supply for LDO3 and LDO4. | |
| vin-ldo9-10-supply: Input supply for LDO9 and LDO10. | |
| vin-ldo11-supply: Input supply for LDO11. | |
| Optional nodes: | |
| -------------- | |
| - regulators : Must contain a sub-node per regulator from the list below. | |
| Each sub-node should contain the constraints and initialization | |
| information for that regulator. See regulator.txt for a | |
| description of standard properties for these sub-nodes. | |
| Additional custom properties are listed below. | |
| sd[0-6], ldo[0-7], ldo[9-11]. | |
| Optional sub-node properties: | |
| ---------------------------- | |
| ams,ext-control: External control of the rail. The option of | |
| this properties will tell which external input is | |
| controlling this rail. Valid values are 0, 1, 2 ad 3. | |
| 0: There is no external control of this rail. | |
| 1: Rail is controlled by ENABLE1 input pin. | |
| 2: Rail is controlled by ENABLE2 input pin. | |
| 3: Rail is controlled by ENABLE3 input pin. | |
| ams,enable-tracking: Enable tracking with SD1, only supported | |
| by LDO3. | |
| Example: | |
| ------- | |
| ams3722: ams3722 { | |
| compatible = "ams,as3722"; | |
| reg = <0x40>; | |
| ... | |
| regulators { | |
| vsup-sd2-supply = <...>; | |
| ... | |
| sd0 { | |
| regulator-name = "vdd_cpu"; | |
| regulator-min-microvolt = <700000>; | |
| regulator-max-microvolt = <1400000>; | |
| regulator-always-on; | |
| ams,ext-control = <2>; | |
| }; | |
| sd1 { | |
| regulator-name = "vdd_core"; | |
| regulator-min-microvolt = <700000>; | |
| regulator-max-microvolt = <1400000>; | |
| regulator-always-on; | |
| ams,ext-control = <1>; | |
| }; | |
| sd2 { | |
| regulator-name = "vddio_ddr"; | |
| regulator-min-microvolt = <1350000>; | |
| regulator-max-microvolt = <1350000>; | |
| regulator-always-on; | |
| }; | |
| sd4 { | |
| regulator-name = "avdd-hdmi-pex"; | |
| regulator-min-microvolt = <1050000>; | |
| regulator-max-microvolt = <1050000>; | |
| regulator-always-on; | |
| }; | |
| sd5 { | |
| regulator-name = "vdd-1v8"; | |
| regulator-min-microvolt = <1800000>; | |
| regulator-max-microvolt = <1800000>; | |
| regulator-always-on; | |
| }; | |
| .... | |
| }; | |
| }; |
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| * ams AS3722 Power management IC. | |
| Required properties: | |
| ------------------- | |
| - compatible: Must be "ams,as3722". | |
| - reg: I2C device address. | |
| - interrupt-controller: AS3722 has internal interrupt controller which takes the | |
| interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well | |
| as external input. | |
| - #interrupt-cells: Should be set to 2 for IRQ number and flags. | |
| The first cell is the IRQ number. IRQ numbers for different interrupt source | |
| of AS3722 are defined at dt-bindings/mfd/as3722.h | |
| The second cell is the flags, encoded as the trigger masks from binding document | |
| interrupts.txt, using dt-bindings/irq. | |
| Optional properties: | |
| -------------------- | |
| - ams,enable-internal-int-pullup: Boolean property, to enable internal pullup on | |
| interrupt pin. Missing this will disable internal pullup on INT pin. | |
| - ams,enable-internal-i2c-pullup: Boolean property, to enable internal pullup on | |
| i2c scl/sda pins. Missing this will disable internal pullup on i2c | |
| scl/sda lines. | |
| - ams,enable-ac-ok-power-on: Boolean property, to enable exit out of power off | |
| mode with AC_OK pin (pin enabled in power off mode). | |
| Optional submodule and their properties: | |
| ======================================= | |
| Pinmux and GPIO: | |
| =============== | |
| Device has 8 GPIO pins which can be configured as GPIO as well as the special IO | |
| functions. | |
| Please refer to pinctrl-bindings.txt in this directory for details of the | |
| common pinctrl bindings used by client devices, including the meaning of the | |
| phrase "pin configuration node". | |
| Following are properties which is needed if GPIO and pinmux functionality | |
| is required: | |
| Required properties: | |
| ------------------- | |
| - gpio-controller: Marks the device node as a GPIO controller. | |
| - #gpio-cells: Number of GPIO cells. Refer to binding document | |
| gpio/gpio.txt | |
| Optional properties: | |
| -------------------- | |
| Following properties are require if pin control setting is required | |
| at boot. | |
| - pinctrl-names: A pinctrl state named "default" be defined, using the | |
| bindings in pinctrl/pinctrl-bindings.txt. | |
| - pinctrl[0...n]: Properties to contain the phandle that refer to | |
| different nodes of pin control settings. These nodes represents | |
| the pin control setting of state 0 to state n. Each of these | |
| nodes contains different subnodes to represents some desired | |
| configuration for a list of pins. This configuration can | |
| include the mux function to select on those pin(s), and | |
| various pin configuration parameters, such as pull-up, | |
| open drain. | |
| Each subnode have following properties: | |
| Required properties: | |
| - pins: List of pins. Valid values of pins properties are: | |
| gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, | |
| gpio6, gpio7 | |
| Optional properties: | |
| function, bias-disable, bias-pull-up, bias-pull-down, | |
| bias-high-impedance, drive-open-drain. | |
| Valid values for function properties are: | |
| gpio, interrupt-out, gpio-in-interrupt, | |
| vsup-vbat-low-undebounce-out, | |
| vsup-vbat-low-debounce-out, | |
| voltage-in-standby, oc-pg-sd0, oc-pg-sd6, | |
| powergood-out, pwm-in, pwm-out, clk32k-out, | |
| watchdog-in, soft-reset-in | |
| Regulators: | |
| =========== | |
| Device has multiple DCDC and LDOs. The node "regulators" is require if regulator | |
| functionality is needed. | |
| Following are properties of regulator subnode. | |
| Optional properties: | |
| ------------------- | |
| The input supply of regulators are the optional properties on the | |
| regulator node. The input supply of these regulators are provided | |
| through following properties: | |
| vsup-sd2-supply: Input supply for SD2. | |
| vsup-sd3-supply: Input supply for SD3. | |
| vsup-sd4-supply: Input supply for SD4. | |
| vsup-sd5-supply: Input supply for SD5. | |
| vin-ldo0-supply: Input supply for LDO0. | |
| vin-ldo1-6-supply: Input supply for LDO1 and LDO6. | |
| vin-ldo2-5-7-supply: Input supply for LDO2, LDO5 and LDO7. | |
| vin-ldo3-4-supply: Input supply for LDO3 and LDO4. | |
| vin-ldo9-10-supply: Input supply for LDO9 and LDO10. | |
| vin-ldo11-supply: Input supply for LDO11. | |
| Optional sub nodes for regulators: | |
| --------------------------------- | |
| The subnodes name is the name of regulator and it must be one of: | |
| sd[0-6], ldo[0-7], ldo[9-11] | |
| Each sub-node should contain the constraints and initialization | |
| information for that regulator. See regulator.txt for a description | |
| of standard properties for these sub-nodes. | |
| Additional optional custom properties are listed below. | |
| ams,ext-control: External control of the rail. The option of | |
| this properties will tell which external input is | |
| controlling this rail. Valid values are 0, 1, 2 ad 3. | |
| 0: There is no external control of this rail. | |
| 1: Rail is controlled by ENABLE1 input pin. | |
| 2: Rail is controlled by ENABLE2 input pin. | |
| 3: Rail is controlled by ENABLE3 input pin. | |
| Missing this property on DT will be assume as no | |
| external control. The external control pin macros | |
| are defined @dt-bindings/mfd/as3722.h | |
| ams,enable-tracking: Enable tracking with SD1, only supported | |
| by LDO3. | |
| Power-off: | |
| ========= | |
| AS3722 supports the system power off by turning off all its rails. | |
| The device node should have the following properties to enable this | |
| functionality | |
| ams,system-power-controller: Boolean, to enable the power off functionality | |
| through this device. | |
| Example: | |
| -------- | |
| #include <dt-bindings/mfd/as3722.h> | |
| ... | |
| ams3722 { | |
| compatible = "ams,as3722"; | |
| reg = <0x48>; | |
| ams,system-power-controller; | |
| interrupt-parent = <&intc>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&as3722_default>; | |
| as3722_default: pinmux { | |
| gpio0 { | |
| pins = "gpio0"; | |
| function = "gpio"; | |
| bias-pull-down; | |
| }; | |
| gpio1_2_4_7 { | |
| pins = "gpio1", "gpio2", "gpio4", "gpio7"; | |
| function = "gpio"; | |
| bias-pull-up; | |
| }; | |
| gpio5 { | |
| pins = "gpio5"; | |
| function = "clk32k_out"; | |
| }; | |
| } | |
| regulators { | |
| vsup-sd2-supply = <...>; | |
| ... | |
| sd0 { | |
| regulator-name = "vdd_cpu"; | |
| regulator-min-microvolt = <700000>; | |
| regulator-max-microvolt = <1400000>; | |
| regulator-always-on; | |
| ams,ext-control = <2>; | |
| }; | |
| sd1 { | |
| regulator-name = "vdd_core"; | |
| regulator-min-microvolt = <700000>; | |
| regulator-max-microvolt = <1400000>; | |
| regulator-always-on; | |
| ams,ext-control = <1>; | |
| }; | |
| sd2 { | |
| regulator-name = "vddio_ddr"; | |
| regulator-min-microvolt = <1350000>; | |
| regulator-max-microvolt = <1350000>; | |
| regulator-always-on; | |
| }; | |
| sd4 { | |
| regulator-name = "avdd-hdmi-pex"; | |
| regulator-min-microvolt = <1050000>; | |
| regulator-max-microvolt = <1050000>; | |
| regulator-always-on; | |
| }; | |
| sd5 { | |
| regulator-name = "vdd-1v8"; | |
| regulator-min-microvolt = <1800000>; | |
| regulator-max-microvolt = <1800000>; | |
| regulator-always-on; | |
| }; | |
| .... | |
| }; | |
| }; |
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| Device tree configuration for the I2C Interrupt Controller on the AST24XX and | |
| AST25XX SoCs. | |
| Required Properties: | |
| - #address-cells : should be 1 | |
| - #size-cells : should be 1 | |
| - #interrupt-cells : should be 1 | |
| - compatible : should be "aspeed,ast2400-i2c-ic" | |
| or "aspeed,ast2500-i2c-ic" | |
| - reg : address start and range of controller | |
| - interrupts : interrupt number | |
| - interrupt-controller : denotes that the controller receives and fires | |
| new interrupts for child busses | |
| Example: | |
| i2c_ic: interrupt-controller@0 { | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| #interrupt-cells = <1>; | |
| compatible = "aspeed,ast2400-i2c-ic"; | |
| reg = <0x0 0x40>; | |
| interrupts = <12>; | |
| interrupt-controller; | |
| }; |
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| * Aspeed BT (Block Transfer) IPMI interface | |
| The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs | |
| (BaseBoard Management Controllers) and the BT interface can be used to | |
| perform in-band IPMI communication with their host. | |
| Required properties: | |
| - compatible : should be one of | |
| "aspeed,ast2400-ibt-bmc" | |
| "aspeed,ast2500-ibt-bmc" | |
| "aspeed,ast2600-ibt-bmc" | |
| - reg: physical address and size of the registers | |
| - clocks: clock for the device | |
| Optional properties: | |
| - interrupts: interrupt generated by the BT interface. without an | |
| interrupt, the driver will operate in poll mode. | |
| Example: | |
| ibt@1e789140 { | |
| compatible = "aspeed,ast2400-ibt-bmc"; | |
| reg = <0x1e789140 0x18>; | |
| interrupts = <8>; | |
| clocks = <&syscon ASPEED_CLK_GATE_LCLK>; | |
| }; |
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| Aspeed Vectored Interrupt Controller | |
| These bindings are for the Aspeed interrupt controller. The AST2400 and | |
| AST2500 SoC families include a legacy register layout before a re-designed | |
| layout, but the bindings do not prescribe the use of one or the other. | |
| Required properties: | |
| - compatible : "aspeed,ast2400-vic" | |
| "aspeed,ast2500-vic" | |
| - interrupt-controller : Identifies the node as an interrupt controller | |
| - #interrupt-cells : Specifies the number of cells needed to encode an | |
| interrupt source. The value shall be 1. | |
| Example: | |
| vic: interrupt-controller@1e6c0080 { | |
| compatible = "aspeed,ast2400-vic"; | |
| interrupt-controller; | |
| #interrupt-cells = <1>; | |
| reg = <0x1e6c0080 0x80>; | |
| }; |
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| Aspeed AST25XX and AST26XX SCU Interrupt Controller | |
| Required Properties: | |
| - #interrupt-cells : must be 1 | |
| - compatible : must be "aspeed,ast2500-scu-ic", | |
| "aspeed,ast2600-scu-ic0" or | |
| "aspeed,ast2600-scu-ic1" | |
| - interrupts : interrupt from the parent controller | |
| - interrupt-controller : indicates that the controller receives and | |
| fires new interrupts for child busses | |
| Example: | |
| syscon@1e6e2000 { | |
| ranges = <0 0x1e6e2000 0x1a8>; | |
| scu_ic: interrupt-controller@18 { | |
| #interrupt-cells = <1>; | |
| compatible = "aspeed,ast2500-scu-ic"; | |
| interrupts = <21>; | |
| interrupt-controller; | |
| }; | |
| }; |
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| * ASPEED AST2400 and AST2500 coprocessor interrupt controller | |
| This file describes the bindings for the interrupt controller present | |
| in the AST2400 and AST2500 BMC SoCs which provides interrupt to the | |
| ColdFire coprocessor. | |
| It is not a normal interrupt controller and it would be rather | |
| inconvenient to create an interrupt tree for it as it somewhat shares | |
| some of the same sources as the main ARM interrupt controller but with | |
| different numbers. | |
| The AST2500 supports a SW generated interrupt | |
| Required properties: | |
| - reg: address and length of the register for the device. | |
| - compatible: "aspeed,cvic" and one of: | |
| "aspeed,ast2400-cvic" | |
| or | |
| "aspeed,ast2500-cvic" | |
| - valid-sources: One cell, bitmap of supported sources for the implementation | |
| Optional properties; | |
| - copro-sw-interrupts: List of interrupt numbers that can be used as | |
| SW interrupts from the ARM to the coprocessor. | |
| (AST2500 only) | |
| Example: | |
| cvic: copro-interrupt-controller@1e6c2000 { | |
| compatible = "aspeed,ast2500-cvic"; | |
| valid-sources = <0xffffffff>; | |
| copro-sw-interrupts = <1>; | |
| reg = <0x1e6c2000 0x80>; | |
| }; |
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| * Device tree bindings for Aspeed SoC Display Controller (GFX) | |
| The Aspeed SoC Display Controller primarily does as its name suggests, but also | |
| participates in pinmux requests on the g5 SoCs. It is therefore considered a | |
| syscon device. | |
| Required properties: | |
| - compatible: "aspeed,ast2500-gfx", "syscon" | |
| - reg: contains offset/length value of the GFX memory | |
| region. | |
| Example: | |
| gfx: display@1e6e6000 { | |
| compatible = "aspeed,ast2500-gfx", "syscon"; | |
| reg = <0x1e6e6000 0x1000>; | |
| }; |
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| ====================================================================== | |
| Device tree bindings for Aspeed AST2400/AST2500 PCI-to-AHB Bridge Control Driver | |
| ====================================================================== | |
| The bridge is available on platforms with the VGA enabled on the Aspeed device. | |
| In this case, the host has access to a 64KiB window into all of the BMC's | |
| memory. The BMC can disable this bridge. If the bridge is enabled, the host | |
| has read access to all the regions of memory, however the host only has read | |
| and write access depending on a register controlled by the BMC. | |
| Required properties: | |
| =================== | |
| - compatible: must be one of: | |
| - "aspeed,ast2400-p2a-ctrl" | |
| - "aspeed,ast2500-p2a-ctrl" | |
| Optional properties: | |
| =================== | |
| - reg: A hint for the memory regions associated with the P2A controller | |
| - memory-region: A phandle to a reserved_memory region to be used for the PCI | |
| to AHB mapping | |
| The p2a-control node should be the child of a syscon node with the required | |
| property: | |
| - compatible : Should be one of the following: | |
| "aspeed,ast2400-scu", "syscon", "simple-mfd" | |
| "aspeed,ast2500-scu", "syscon", "simple-mfd" | |
| Example | |
| =================== | |
| g4 Example | |
| ---------- | |
| syscon: scu@1e6e2000 { | |
| compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; | |
| reg = <0x1e6e2000 0x1a8>; | |
| p2a: p2a-control { | |
| compatible = "aspeed,ast2400-p2a-ctrl"; | |
| memory-region = <&reserved_memory>; | |
| }; | |
| }; |
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| ASPEED AST2400/AST2500 PWM and Fan Tacho controller device driver | |
| The ASPEED PWM controller can support upto 8 PWM outputs. The ASPEED Fan Tacho | |
| controller can support upto 16 Fan tachometer inputs. | |
| There can be upto 8 fans supported. Each fan can have one PWM output and | |
| one/two Fan tach inputs. | |
| Required properties for pwm-tacho node: | |
| - #address-cells : should be 1. | |
| - #size-cells : should be 1. | |
| - #cooling-cells: should be 2. | |
| - reg : address and length of the register set for the device. | |
| - pinctrl-names : a pinctrl state named "default" must be defined. | |
| - pinctrl-0 : phandle referencing pin configuration of the PWM ports. | |
| - compatible : should be "aspeed,ast2400-pwm-tacho" for AST2400 and | |
| "aspeed,ast2500-pwm-tacho" for AST2500. | |
| - clocks : phandle to clock provider with the clock number in the second cell | |
| - resets : phandle to reset controller with the reset number in the second cell | |
| fan subnode format: | |
| =================== | |
| Under fan subnode there can upto 8 child nodes, with each child node | |
| representing a fan. If there are 8 fans each fan can have one PWM port and | |
| one/two Fan tach inputs. | |
| For PWM port can be configured cooling-levels to create cooling device. | |
| Cooling device could be bound to a thermal zone for the thermal control. | |
| Required properties for each child node: | |
| - reg : should specify PWM source port. | |
| integer value in the range 0 to 7 with 0 indicating PWM port A and | |
| 7 indicating PWM port H. | |
| - cooling-levels: PWM duty cycle values in a range from 0 to 255 | |
| which correspond to thermal cooling states. | |
| - aspeed,fan-tach-ch : should specify the Fan tach input channel. | |
| integer value in the range 0 through 15, with 0 indicating | |
| Fan tach channel 0 and 15 indicating Fan tach channel 15. | |
| Atleast one Fan tach input channel is required. | |
| Examples: | |
| pwm_tacho: pwmtachocontroller@1e786000 { | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| #cooling-cells = <2>; | |
| reg = <0x1E786000 0x1000>; | |
| compatible = "aspeed,ast2500-pwm-tacho"; | |
| clocks = <&syscon ASPEED_CLK_APB>; | |
| resets = <&syscon ASPEED_RESET_PWM>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; | |
| fan@0 { | |
| reg = <0x00>; | |
| cooling-levels = /bits/ 8 <125 151 177 203 229 255>; | |
| aspeed,fan-tach-ch = /bits/ 8 <0x00>; | |
| }; | |
| fan@1 { | |
| reg = <0x01>; | |
| aspeed,fan-tach-ch = /bits/ 8 <0x01 0x02>; | |
| }; | |
| }; |
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| The Aspeed System Control Unit manages the global behaviour of the SoC, | |
| configuring elements such as clocks, pinmux, and reset. | |
| Required properties: | |
| - compatible: One of: | |
| "aspeed,ast2400-scu", "syscon", "simple-mfd" | |
| "aspeed,ast2500-scu", "syscon", "simple-mfd" | |
| - reg: contains the offset and length of the SCU memory region | |
| - #clock-cells: should be set to <1> - the system controller is also a | |
| clock provider | |
| - #reset-cells: should be set to <1> - the system controller is also a | |
| reset line provider | |
| Example: | |
| syscon: syscon@1e6e2000 { | |
| compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; | |
| reg = <0x1e6e2000 0x1a8>; | |
| #clock-cells = <1>; | |
| #reset-cells = <1>; | |
| }; | |
| Silicon ID | |
| ----------------- | |
| Families have unique hardware silicon identifiers within the SoC. | |
| Required properties: | |
| - compatible: "aspeed,silicon-id" or: | |
| "aspeed,ast2400-silicon-id" or | |
| "aspeed,ast2500-silicon-id" or | |
| "aspeed,ast2600-silicon-id" | |
| - reg: offset and length of the silicon id information | |
| optionally, a second offset and length describes the unique chip id | |
| The reg should be the unique silicon id register, and | |
| not backwards compatible one in eg. the 2600. | |
| Example: | |
| silicon-id@7c { | |
| compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; | |
| reg = <0x7c 0x4 0x150 0x8>; | |
| }; |
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| Aspeed BMC SoC EDAC node | |
| The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error | |
| correction check). | |
| The memory controller supports SECDED (single bit error correction, double bit | |
| error detection) and single bit error auto scrubbing by reserving 8 bits for | |
| every 64 bit word (effectively reducing available memory to 8/9). | |
| Note, the bootloader must configure ECC mode in the memory controller. | |
| Required properties: | |
| - compatible: should be one of | |
| - "aspeed,ast2400-sdram-edac" | |
| - "aspeed,ast2500-sdram-edac" | |
| - "aspeed,ast2600-sdram-edac" | |
| - reg: sdram controller register set should be <0x1e6e0000 0x174> | |
| - interrupts: should be AVIC interrupt #0 | |
| Example: | |
| edac: sdram@1e6e0000 { | |
| compatible = "aspeed,ast2500-sdram-edac"; | |
| reg = <0x1e6e0000 0x174>; | |
| interrupts = <0>; | |
| }; |
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| * Aspeed Firmware Memory controller | |
| * Aspeed SPI Flash Memory Controller | |
| The Firmware Memory Controller in the Aspeed AST2500 SoC supports | |
| three chip selects, two of which are always of SPI type and the third | |
| can be SPI or NOR type flash. These bindings only describe SPI. | |
| The two SPI flash memory controllers in the AST2500 each support two | |
| chip selects. | |
| Required properties: | |
| - compatible : Should be one of | |
| "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller | |
| "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller | |
| "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller | |
| "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers | |
| - reg : the first contains the control register location and length, | |
| the second contains the memory window mapping address and length | |
| - #address-cells : must be 1 corresponding to chip select child binding | |
| - #size-cells : must be 0 corresponding to chip select child binding | |
| Optional properties: | |
| - interrupts : Should contain the interrupt for the dma device if an | |
| FMC | |
| The child nodes are the SPI flash modules which must have a compatible | |
| property as specified in bindings/mtd/jedec,spi-nor.txt | |
| Optionally, the child node can contain properties for SPI mode (may be | |
| ignored): | |
| - spi-max-frequency - max frequency of spi bus | |
| Example: | |
| fmc: fmc@1e620000 { | |
| compatible = "aspeed,ast2500-fmc"; | |
| reg = < 0x1e620000 0x94 | |
| 0x20000000 0x02000000 >; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| interrupts = <19>; | |
| flash@0 { | |
| reg = < 0 >; | |
| compatible = "jedec,spi-nor"; | |
| /* spi-max-frequency = <>; */ | |
| /* m25p,fast-read; */ | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| }; | |
| }; |
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| * Device tree bindings for Aspeed Video Engine | |
| The Video Engine (VE) embedded in the Aspeed AST2400/2500/2600 SOCs can | |
| capture and compress video data from digital or analog sources. | |
| Required properties: | |
| - compatible: "aspeed,ast2400-video-engine" or | |
| "aspeed,ast2500-video-engine" or | |
| "aspeed,ast2600-video-engine" | |
| - reg: contains the offset and length of the VE memory region | |
| - clocks: clock specifiers for the syscon clocks associated with | |
| the VE (ordering must match the clock-names property) | |
| - clock-names: "vclk" and "eclk" | |
| - resets: reset specifier for the syscon reset associated with | |
| the VE | |
| - interrupts: the interrupt associated with the VE on this platform | |
| Optional properties: | |
| - memory-region: | |
| phandle to a memory region to allocate from, as defined in | |
| Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt | |
| Example: | |
| video-engine@1e700000 { | |
| compatible = "aspeed,ast2500-video-engine"; | |
| reg = <0x1e700000 0x20000>; | |
| clocks = <&syscon ASPEED_CLK_GATE_VCLK>, <&syscon ASPEED_CLK_GATE_ECLK>; | |
| clock-names = "vclk", "eclk"; | |
| resets = <&syscon ASPEED_RESET_VIDEO>; | |
| interrupts = <7>; | |
| memory-region = <&video_engine_memory>; | |
| }; |
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| Aspeed Watchdog Timer | |
| Required properties: | |
| - compatible: must be one of: | |
| - "aspeed,ast2400-wdt" | |
| - "aspeed,ast2500-wdt" | |
| - "aspeed,ast2600-wdt" | |
| - reg: physical base address of the controller and length of memory mapped | |
| region | |
| Optional properties: | |
| - aspeed,reset-type = "cpu|soc|system|none" | |
| Reset behavior - Whenever a timeout occurs the watchdog can be programmed | |
| to generate one of three different, mutually exclusive, types of resets. | |
| Type "none" can be specified to indicate that no resets are to be done. | |
| This is useful in situations where another watchdog engine on chip is | |
| to perform the reset. | |
| If 'aspeed,reset-type=' is not specified the default is to enable system | |
| reset. | |
| Reset types: | |
| - cpu: Reset CPU on watchdog timeout | |
| - soc: Reset 'System on Chip' on watchdog timeout | |
| - system: Reset system on watchdog timeout | |
| - none: No reset is performed on timeout. Assumes another watchdog | |
| engine is responsible for this. | |
| - aspeed,alt-boot: If property is present then boot from alternate block. | |
| - aspeed,external-signal: If property is present then signal is sent to | |
| external reset counter (only WDT1 and WDT2). If not | |
| specified no external signal is sent. | |
| - aspeed,ext-pulse-duration: External signal pulse duration in microseconds | |
| Optional properties for AST2500-compatible watchdogs: | |
| - aspeed,ext-push-pull: If aspeed,external-signal is present, set the pin's | |
| drive type to push-pull. The default is open-drain. | |
| - aspeed,ext-active-high: If aspeed,external-signal is present and and the pin | |
| is configured as push-pull, then set the pulse | |
| polarity to active-high. The default is active-low. | |
| Example: | |
| wdt1: watchdog@1e785000 { | |
| compatible = "aspeed,ast2400-wdt"; | |
| reg = <0x1e785000 0x1c>; | |
| aspeed,reset-type = "system"; | |
| aspeed,external-signal; | |
| }; |
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| Amlogic Meson6/Meson8/Meson8b assist registers: | |
| ----------------------------------------------- | |
| The assist registers contain basic information about the SoC, | |
| for example the encoded SoC part number. | |
| Required properties: | |
| - reg: the register range of the assist registers | |
| - compatible: should be "amlogic,meson-mx-assist" along with "syscon" | |
| Example: | |
| assist: assist@7c00 { | |
| compatible = "amlogic,meson-mx-assist", "syscon"; | |
| reg = <0x7c00 0x200>; | |
| }; |
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| This file has been moved to at24.yaml. |
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| * AT86RF230 IEEE 802.15.4 * | |
| Required properties: | |
| - compatible: should be "atmel,at86rf230", "atmel,at86rf231", | |
| "atmel,at86rf233" or "atmel,at86rf212" | |
| - spi-max-frequency: maximal bus speed, should be set to 7500000 depends | |
| sync or async operation mode | |
| - reg: the chipselect index | |
| - interrupts: the interrupt generated by the device. Non high-level | |
| can occur deadlocks while handling isr. | |
| Optional properties: | |
| - reset-gpio: GPIO spec for the rstn pin | |
| - sleep-gpio: GPIO spec for the slp_tr pin | |
| - xtal-trim: u8 value for fine tuning the internal capacitance | |
| arrays of xtal pins: 0 = +0 pF, 0xf = +4.5 pF | |
| Example: | |
| at86rf231@0 { | |
| compatible = "atmel,at86rf231"; | |
| spi-max-frequency = <7500000>; | |
| reg = <0>; | |
| interrupts = <19 4>; | |
| interrupt-parent = <&gpio3>; | |
| xtal-trim = /bits/ 8 <0x06>; | |
| }; |
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| Device Tree Clock bindings for arch-at91 | |
| This binding uses the common clock binding[1]. | |
| [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| Slow Clock controller: | |
| Required properties: | |
| - compatible : shall be one of the following: | |
| "atmel,at91sam9x5-sckc", | |
| "atmel,sama5d3-sckc", | |
| "atmel,sama5d4-sckc" or | |
| "microchip,sam9x60-sckc": | |
| at91 SCKC (Slow Clock Controller) | |
| - #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0. | |
| - clocks : shall be the input parent clock phandle for the clock. | |
| Optional properties: | |
| - atmel,osc-bypass : boolean property. Set this when a clock signal is directly | |
| provided on XIN. | |
| For example: | |
| sckc@fffffe50 { | |
| compatible = "atmel,at91sam9x5-sckc"; | |
| reg = <0xfffffe50 0x4>; | |
| clocks = <&slow_xtal>; | |
| #clock-cells = <0>; | |
| }; | |
| Power Management Controller (PMC): | |
| Required properties: | |
| - compatible : shall be "atmel,<chip>-pmc", "syscon" or | |
| "microchip,sam9x60-pmc" | |
| <chip> can be: at91rm9200, at91sam9260, at91sam9261, | |
| at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9g15, | |
| at91sam9g25, at91sam9g35, at91sam9x25, at91sam9x35, at91sam9x5, | |
| sama5d2, sama5d3 or sama5d4. | |
| - #clock-cells : from common clock binding; shall be set to 2. The first entry | |
| is the type of the clock (core, system, peripheral or generated) and the | |
| second entry its index as provided by the datasheet | |
| - clocks : Must contain an entry for each entry in clock-names. | |
| - clock-names: Must include the following entries: "slow_clk", "main_xtal" | |
| Optional properties: | |
| - atmel,osc-bypass : boolean property. Set this when a clock signal is directly | |
| provided on XIN. | |
| For example: | |
| pmc: pmc@f0018000 { | |
| compatible = "atmel,sama5d4-pmc", "syscon"; | |
| reg = <0xf0018000 0x120>; | |
| interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
| #clock-cells = <2>; | |
| clocks = <&clk32k>, <&main_xtal>; | |
| clock-names = "slow_clk", "main_xtal"; | |
| }; |
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| Binding for Qualcomm Atheros AR7xxx/AR9XXX reset controller | |
| Please also refer to reset.txt in this directory for common reset | |
| controller binding usage. | |
| Required Properties: | |
| - compatible: has to be "qca,<soctype>-reset", "qca,ar7100-reset" | |
| as fallback | |
| - reg: Base address and size of the controllers memory area | |
| - #reset-cells : Specifies the number of cells needed to encode reset | |
| line, should be 1 | |
| Example: | |
| reset-controller@1806001c { | |
| compatible = "qca,ar9132-reset", "qca,ar7100-reset"; | |
| reg = <0x1806001c 0x4>; | |
| #reset-cells = <1>; | |
| }; |
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| Binding for Qualcomm Atheros AR7xxx/AR9XXX SoC | |
| Each device tree must specify a compatible value for the AR SoC | |
| it uses in the compatible property of the root node. The compatible | |
| value must be one of the following values: | |
| - qca,ar7130 | |
| - qca,ar7141 | |
| - qca,ar7161 | |
| - qca,ar7240 | |
| - qca,ar7241 | |
| - qca,ar7242 | |
| - qca,ar9130 | |
| - qca,ar9132 | |
| - qca,ar9330 | |
| - qca,ar9331 | |
| - qca,ar9341 | |
| - qca,ar9342 | |
| - qca,ar9344 | |
| - qca,qca9556 | |
| - qca,qca9558 |
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| * Andestech L2 cache Controller | |
| The level-2 cache controller plays an important role in reducing memory latency | |
| for high performance systems, such as thoese designs with AndesCore processors. | |
| Level-2 cache controller in general enhances overall system performance | |
| signigicantly and the system power consumption might be reduced as well by | |
| reducing DRAM accesses. | |
| This binding specifies what properties must be available in the device tree | |
| representation of an Andestech L2 cache controller. | |
| Required properties: | |
| - compatible: | |
| Usage: required | |
| Value type: <string> | |
| Definition: "andestech,atl2c" | |
| - reg : Physical base address and size of cache controller's memory mapped | |
| - cache-unified : Specifies the cache is a unified cache. | |
| - cache-level : Should be set to 2 for a level 2 cache. | |
| * Example | |
| cache-controller@e0500000 { | |
| compatible = "andestech,atl2c"; | |
| reg = <0xe0500000 0x1000>; | |
| cache-unified; | |
| cache-level = <2>; | |
| }; |
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| * Advanced Interrupt Controller (AIC) | |
| Required properties: | |
| - compatible: Should be: | |
| - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2", | |
| "sama5d3" or "sama5d4" | |
| - "microchip,<chip>-aic" where <chip> can be "sam9x60" | |
| - interrupt-controller: Identifies the node as an interrupt controller. | |
| - #interrupt-cells: The number of cells to define the interrupts. It should be 3. | |
| The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet). | |
| The second cell is used to specify flags: | |
| bits[3:0] trigger type and level flags: | |
| 1 = low-to-high edge triggered. | |
| 2 = high-to-low edge triggered. | |
| 4 = active high level-sensitive. | |
| 8 = active low level-sensitive. | |
| Valid combinations are 1, 2, 3, 4, 8. | |
| Default flag for internal sources should be set to 4 (active high). | |
| The third cell is used to specify the irq priority from 0 (lowest) to 7 | |
| (highest). | |
| - reg: Should contain AIC registers location and length | |
| - atmel,external-irqs: u32 array of external irqs. | |
| Examples: | |
| /* | |
| * AIC | |
| */ | |
| aic: interrupt-controller@fffff000 { | |
| compatible = "atmel,at91rm9200-aic"; | |
| interrupt-controller; | |
| #interrupt-cells = <3>; | |
| reg = <0xfffff000 0x200>; | |
| }; | |
| /* | |
| * An interrupt generating device that is wired to an AIC. | |
| */ | |
| dma: dma-controller@ffffec00 { | |
| compatible = "atmel,at91sam9g45-dma"; | |
| reg = <0xffffec00 0x200>; | |
| interrupts = <21 4 5>; | |
| }; |
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| * Atmel AT91 Pinmux Controller | |
| The AT91 Pinmux Controller, enables the IC | |
| to share one PAD to several functional blocks. The sharing is done by | |
| multiplexing the PAD input/output signals. For each PAD there are up to | |
| 8 muxing options (called periph modes). Since different modules require | |
| different PAD settings (like pull up, keeper, etc) the controller controls | |
| also the PAD settings parameters. | |
| Please refer to pinctrl-bindings.txt in this directory for details of the | |
| common pinctrl bindings used by client devices, including the meaning of the | |
| phrase "pin configuration node". | |
| Atmel AT91 pin configuration node is a node of a group of pins which can be | |
| used for a specific device or function. This node represents both mux and config | |
| of the pins in that group. The 'pins' selects the function mode(also named pin | |
| mode) this pin can work on and the 'config' configures various pad settings | |
| such as pull-up, multi drive, etc. | |
| Required properties for iomux controller: | |
| - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl" | |
| or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl" | |
| - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be | |
| configured in this periph mode. All the periph and bank need to be describe. | |
| How to create such array: | |
| Each column will represent the possible peripheral of the pinctrl | |
| Each line will represent a pio bank | |
| Take an example on the 9260 | |
| Peripheral: 2 ( A and B) | |
| Bank: 3 (A, B and C) | |
| => | |
| /* A B */ | |
| 0xffffffff 0xffc00c3b /* pioA */ | |
| 0xffffffff 0x7fff3ccf /* pioB */ | |
| 0xffffffff 0x007fffff /* pioC */ | |
| For each peripheral/bank we will describe in a u32 if a pin can be | |
| configured in it by putting 1 to the pin bit (1 << pin) | |
| Let's take the pioA on peripheral B | |
| From the datasheet Table 10-2. | |
| Peripheral B | |
| PA0 MCDB0 | |
| PA1 MCCDB | |
| PA2 | |
| PA3 MCDB3 | |
| PA4 MCDB2 | |
| PA5 MCDB1 | |
| PA6 | |
| PA7 | |
| PA8 | |
| PA9 | |
| PA10 ETX2 | |
| PA11 ETX3 | |
| PA12 | |
| PA13 | |
| PA14 | |
| PA15 | |
| PA16 | |
| PA17 | |
| PA18 | |
| PA19 | |
| PA20 | |
| PA21 | |
| PA22 ETXER | |
| PA23 ETX2 | |
| PA24 ETX3 | |
| PA25 ERX2 | |
| PA26 ERX3 | |
| PA27 ERXCK | |
| PA28 ECRS | |
| PA29 ECOL | |
| PA30 RXD4 | |
| PA31 TXD4 | |
| => 0xffc00c3b | |
| Required properties for pin configuration node: | |
| - atmel,pins: 4 integers array, represents a group of pins mux and config | |
| setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>. | |
| The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B... | |
| PIN_BANK 0 is pioA, PIN_BANK 1 is pioB... | |
| Bits used for CONFIG: | |
| PULL_UP (1 << 0): indicate this pin needs a pull up. | |
| MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive. | |
| Multi-drive is equivalent to open-drain type output. | |
| DEGLITCH (1 << 2): indicate this pin needs deglitch. | |
| PULL_DOWN (1 << 3): indicate this pin needs a pull down. | |
| DIS_SCHMIT (1 << 4): indicate this pin needs to the disable schmitt trigger. | |
| DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the | |
| following values: | |
| 00 - No change (reset state value kept) | |
| 01 - Low | |
| 10 - Medium | |
| 11 - High | |
| OUTPUT (1 << 7): indicate this pin need to be configured as an output. | |
| OUTPUT_VAL (1 << 8): output val (1 = high, 0 = low) | |
| SLEWRATE (1 << 9): slew rate of the pin: 0 = disable, 1 = enable | |
| DEBOUNCE (1 << 16): indicate this pin needs debounce. | |
| DEBOUNCE_VAL (0x3fff << 17): debounce value. | |
| NOTE: | |
| Some requirements for using atmel,at91rm9200-pinctrl binding: | |
| 1. We have pin function node defined under at91 controller node to represent | |
| what pinmux functions this SoC supports. | |
| 2. The driver can use the function node's name and pin configuration node's | |
| name describe the pin function and group hierarchy. | |
| For example, Linux at91 pinctrl driver takes the function node's name | |
| as the function name and pin configuration node's name as group name to | |
| create the map table. | |
| 3. Each pin configuration node should have a phandle, devices can set pins | |
| configurations by referring to the phandle of that pin configuration node. | |
| 4. The gpio controller must be describe in the pinctrl simple-bus. | |
| For each bank the required properties are: | |
| - compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or | |
| "microchip,sam9x60-gpio" | |
| - reg: physical base address and length of the controller's registers | |
| - interrupts: interrupt outputs from the controller | |
| - interrupt-controller: marks the device node as an interrupt controller | |
| - #interrupt-cells: should be 2; refer to ../interrupt-controller/interrupts.txt | |
| for more details. | |
| - gpio-controller | |
| - #gpio-cells: should be 2; the first cell is the GPIO number and the second | |
| cell specifies GPIO flags as defined in <dt-bindings/gpio/gpio.h>. | |
| - clocks: bank clock | |
| Examples: | |
| pinctrl@fffff400 { | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ranges; | |
| compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; | |
| reg = <0xfffff400 0x600>; | |
| pioA: gpio@fffff400 { | |
| compatible = "atmel,at91sam9x5-gpio"; | |
| reg = <0xfffff400 0x200>; | |
| interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; | |
| }; | |
| atmel,mux-mask = < | |
| /* A B */ | |
| 0xffffffff 0xffc00c3b /* pioA */ | |
| 0xffffffff 0x7fff3ccf /* pioB */ | |
| 0xffffffff 0x007fffff /* pioC */ | |
| >; | |
| /* shared pinctrl settings */ | |
| dbgu { | |
| pinctrl_dbgu: dbgu-0 { | |
| atmel,pins = | |
| <1 14 0x1 0x0 /* PB14 periph A */ | |
| 1 15 0x1 0x1>; /* PB15 periph A with pullup */ | |
| }; | |
| }; | |
| }; | |
| dbgu: serial@fffff200 { | |
| compatible = "atmel,at91sam9260-usart"; | |
| reg = <0xfffff200 0x200>; | |
| interrupts = <1 4 7>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_dbgu>; | |
| }; |
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| * Atmel PIO4 Controller | |
| The Atmel PIO4 controller is used to select the function of a pin and to | |
| configure it. | |
| Required properties: | |
| - compatible: | |
| "atmel,sama5d2-pinctrl" | |
| "microchip,sama7g5-pinctrl" | |
| - reg: base address and length of the PIO controller. | |
| - interrupts: interrupt outputs from the controller, one for each bank. | |
| - interrupt-controller: mark the device node as an interrupt controller. | |
| - #interrupt-cells: should be two. | |
| - gpio-controller: mark the device node as a gpio controller. | |
| - #gpio-cells: should be two. | |
| Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for | |
| a general description of GPIO and interrupt bindings. | |
| Please refer to pinctrl-bindings.txt in this directory for details of the | |
| common pinctrl bindings used by client devices. | |
| Subnode format | |
| Each node (or subnode) will list the pins it needs and how to configured these | |
| pins. | |
| node { | |
| pinmux = <PIN_NUMBER_PINMUX>; | |
| GENERIC_PINCONFIG; | |
| }; | |
| Required properties: | |
| - pinmux: integer array. Each integer represents a pin number plus mux and | |
| ioset settings. Use the macros from boot/dts/<soc>-pinfunc.h file to get the | |
| right representation of the pin. | |
| Optional properties: | |
| - GENERIC_PINCONFIG: generic pinconfig options to use: | |
| - bias-disable, bias-pull-down, bias-pull-up, drive-open-drain, | |
| input-schmitt-enable, input-debounce, output-low, output-high. | |
| - for microchip,sama7g5-pinctrl only: | |
| - slew-rate: 0 - disabled, 1 - enabled (default) | |
| - atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for | |
| high drive. The default value is low drive. | |
| Example: | |
| #include <sama5d2-pinfunc.h> | |
| ... | |
| { | |
| pioA: pinctrl@fc038000 { | |
| compatible = "atmel,sama5d2-pinctrl"; | |
| reg = <0xfc038000 0x600>; | |
| interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, | |
| <68 IRQ_TYPE_LEVEL_HIGH 7>, | |
| <69 IRQ_TYPE_LEVEL_HIGH 7>, | |
| <70 IRQ_TYPE_LEVEL_HIGH 7>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| clocks = <&pioA_clk>; | |
| pinctrl_i2c0_default: i2c0_default { | |
| pinmux = <PIN_PD21__TWD0>, | |
| <PIN_PD22__TWCK0>; | |
| bias-disable; | |
| }; | |
| pinctrl_led_gpio_default: led_gpio_default { | |
| pinmux = <PIN_PB0>, | |
| <PIN_PB5>; | |
| bias-pull-up; | |
| atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>; | |
| }; | |
| pinctrl_sdmmc1_default: sdmmc1_default { | |
| cmd_data { | |
| pinmux = <PIN_PA28__SDMMC1_CMD>, | |
| <PIN_PA18__SDMMC1_DAT0>, | |
| <PIN_PA19__SDMMC1_DAT1>, | |
| <PIN_PA20__SDMMC1_DAT2>, | |
| <PIN_PA21__SDMMC1_DAT3>; | |
| bias-pull-up; | |
| }; | |
| ck_cd { | |
| pinmux = <PIN_PA22__SDMMC1_CK>, | |
| <PIN_PA30__SDMMC1_CD>; | |
| bias-disable; | |
| }; | |
| }; | |
| ... | |
| }; | |
| }; | |
| ... |
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| Atmel AT91SAM9260 Real Time Timer | |
| Required properties: | |
| - compatible: should be one of the following: | |
| - "atmel,at91sam9260-rtt" | |
| - "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt" | |
| - reg: should encode the memory region of the RTT controller | |
| - interrupts: rtt alarm/event interrupt | |
| - clocks: should contain the 32 KHz slow clk that will drive the RTT block. | |
| - atmel,rtt-rtc-time-reg: should encode the GPBR register used to store | |
| the time base when the RTT is used as an RTC. | |
| The first cell should point to the GPBR node and the second one | |
| encode the offset within the GPBR block (or in other words, the | |
| GPBR register used to store the time base). | |
| Example: | |
| rtt@fffffd20 { | |
| compatible = "atmel,at91sam9260-rtt"; | |
| reg = <0xfffffd20 0x10>; | |
| interrupts = <1 4 7>; | |
| clocks = <&clk32k>; | |
| atmel,rtt-rtc-time-reg = <&gpbr 0x0>; | |
| }; |
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| Device tree bindings for Atmel capacitive touch device, typically | |
| an Atmel touch sensor connected to AtmegaXX MCU running firmware | |
| based on Qtouch library. | |
| The node for this device must be a child of a I2C controller node, as the | |
| device communicates via I2C. | |
| Required properties: | |
| compatible: Must be "atmel,captouch". | |
| reg: The I2C slave address of the device. | |
| interrupts: Property describing the interrupt line the device | |
| is connected to. The device only has one interrupt | |
| source. | |
| linux,keycodes: Specifies an array of numeric keycode values to | |
| be used for reporting button presses. The array can | |
| contain up to 8 entries. | |
| Optional properties: | |
| autorepeat: Enables the Linux input system's autorepeat | |
| feature on the input device. | |
| Example: | |
| atmel-captouch@51 { | |
| compatible = "atmel,captouch"; | |
| reg = <0x51>; | |
| interrupt-parent = <&tlmm>; | |
| interrupts = <67 IRQ_TYPE_EDGE_FALLING>; | |
| linux,keycodes = <BTN_0>, <BTN_1>, | |
| <BTN_2>, <BTN_3>, | |
| <BTN_4>, <BTN_5>, | |
| <BTN_6>, <BTN_7>; | |
| autorepeat; | |
| }; |
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| * Device tree bindings for Atmel EBI | |
| The External Bus Interface (EBI) controller is a bus where you can connect | |
| asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs). | |
| The EBI provides a glue-less interface to asynchronous memories through the SMC | |
| (Static Memory Controller). | |
| Required properties: | |
| - compatible: "atmel,at91sam9260-ebi" | |
| "atmel,at91sam9261-ebi" | |
| "atmel,at91sam9263-ebi0" | |
| "atmel,at91sam9263-ebi1" | |
| "atmel,at91sam9rl-ebi" | |
| "atmel,at91sam9g45-ebi" | |
| "atmel,at91sam9x5-ebi" | |
| "atmel,sama5d3-ebi" | |
| "microchip,sam9x60-ebi" | |
| - reg: Contains offset/length value for EBI memory mapping. | |
| This property might contain several entries if the EBI | |
| memory range is not contiguous | |
| - #address-cells: Must be 2. | |
| The first cell encodes the CS. | |
| The second cell encode the offset into the CS memory | |
| range. | |
| - #size-cells: Must be set to 1. | |
| - ranges: Encodes CS to memory region association. | |
| - clocks: Clock feeding the EBI controller. | |
| See clock-bindings.txt | |
| Children device nodes are representing device connected to the EBI bus. | |
| Required device node properties: | |
| - reg: Contains the chip-select id, the offset and the length | |
| of the memory region requested by the device. | |
| EBI bus configuration will be defined directly in the device subnode. | |
| Optional EBI/SMC properties: | |
| - atmel,smc-bus-width: width of the asynchronous device's data bus | |
| 8, 16 or 32. | |
| Default to 8 when undefined. | |
| - atmel,smc-byte-access-type "write" or "select" (see Atmel datasheet). | |
| Default to "select" when undefined. | |
| - atmel,smc-read-mode "nrd" or "ncs". | |
| Default to "ncs" when undefined. | |
| - atmel,smc-write-mode "nwe" or "ncs". | |
| Default to "ncs" when undefined. | |
| - atmel,smc-exnw-mode "disabled", "frozen" or "ready". | |
| Default to "disabled" when undefined. | |
| - atmel,smc-page-mode enable page mode if present. The provided value | |
| defines the page size (supported values: 4, 8, | |
| 16 and 32). | |
| - atmel,smc-tdf-mode: "normal" or "optimized". When set to | |
| "optimized" the data float time is optimized | |
| depending on the next device being accessed | |
| (next device setup time is subtracted to the | |
| current device data float time). | |
| Default to "normal" when undefined. | |
| If at least one atmel,smc- property is defined the following SMC timing | |
| properties become mandatory. In the other hand, if none of the atmel,smc- | |
| properties are specified, we assume that the EBI bus configuration will be | |
| handled by the sub-device driver, and none of those properties should be | |
| defined. | |
| All the timings are expressed in nanoseconds (see Atmel datasheet for a full | |
| description). | |
| - atmel,smc-ncs-rd-setup-ns | |
| - atmel,smc-nrd-setup-ns | |
| - atmel,smc-ncs-wr-setup-ns | |
| - atmel,smc-nwe-setup-ns | |
| - atmel,smc-ncs-rd-pulse-ns | |
| - atmel,smc-nrd-pulse-ns | |
| - atmel,smc-ncs-wr-pulse-ns | |
| - atmel,smc-nwe-pulse-ns | |
| - atmel,smc-nwe-cycle-ns | |
| - atmel,smc-nrd-cycle-ns | |
| - atmel,smc-tdf-ns | |
| Example: | |
| ebi: ebi@10000000 { | |
| compatible = "atmel,sama5d3-ebi"; | |
| #address-cells = <2>; | |
| #size-cells = <1>; | |
| atmel,smc = <&hsmc>; | |
| atmel,matrix = <&matrix>; | |
| reg = <0x10000000 0x10000000 | |
| 0x40000000 0x30000000>; | |
| ranges = <0x0 0x0 0x10000000 0x10000000 | |
| 0x1 0x0 0x40000000 0x10000000 | |
| 0x2 0x0 0x50000000 0x10000000 | |
| 0x3 0x0 0x60000000 0x10000000>; | |
| clocks = <&mck>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_ebi_addr>; | |
| nor: flash@0,0 { | |
| compatible = "cfi-flash"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| reg = <0x0 0x0 0x1000000>; | |
| bank-width = <2>; | |
| atmel,smc-read-mode = "nrd"; | |
| atmel,smc-write-mode = "nwe"; | |
| atmel,smc-bus-width = <16>; | |
| atmel,smc-ncs-rd-setup-ns = <0>; | |
| atmel,smc-ncs-wr-setup-ns = <0>; | |
| atmel,smc-nwe-setup-ns = <8>; | |
| atmel,smc-nrd-setup-ns = <16>; | |
| atmel,smc-ncs-rd-pulse-ns = <84>; | |
| atmel,smc-ncs-wr-pulse-ns = <84>; | |
| atmel,smc-nrd-pulse-ns = <76>; | |
| atmel,smc-nwe-pulse-ns = <76>; | |
| atmel,smc-nrd-cycle-ns = <107>; | |
| atmel,smc-nwe-cycle-ns = <84>; | |
| atmel,smc-tdf-ns = <16>; | |
| }; | |
| }; | |
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| Atmel LCDC Framebuffer | |
| ----------------------------------------------------- | |
| Required properties: | |
| - compatible : | |
| "atmel,at91sam9261-lcdc" , | |
| "atmel,at91sam9263-lcdc" , | |
| "atmel,at91sam9g10-lcdc" , | |
| "atmel,at91sam9g45-lcdc" , | |
| "atmel,at91sam9g45es-lcdc" , | |
| "atmel,at91sam9rl-lcdc" , | |
| "atmel,at32ap-lcdc" | |
| - reg : Should contain 1 register ranges(address and length). | |
| Can contain an additional register range(address and length) | |
| for fixed framebuffer memory. Useful for dedicated memories. | |
| - interrupts : framebuffer controller interrupt | |
| - display: a phandle pointing to the display node | |
| Required nodes: | |
| - display: a display node is required to initialize the lcd panel | |
| This should be in the board dts. | |
| - default-mode: a videomode within the display with timing parameters | |
| as specified below. | |
| Optional properties: | |
| - lcd-supply: Regulator for LCD supply voltage. | |
| Example: | |
| fb0: fb@00500000 { | |
| compatible = "atmel,at91sam9g45-lcdc"; | |
| reg = <0x00500000 0x1000>; | |
| interrupts = <23 3 0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_fb>; | |
| display = <&display0>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| }; | |
| Example for fixed framebuffer memory: | |
| fb0: fb@00500000 { | |
| compatible = "atmel,at91sam9263-lcdc"; | |
| reg = <0x00700000 0x1000 0x70000000 0x200000>; | |
| [...] | |
| }; | |
| Atmel LCDC Display | |
| ----------------------------------------------------- | |
| Required properties (as per of_videomode_helper): | |
| - atmel,dmacon: dma controller configuration | |
| - atmel,lcdcon2: lcd controller configuration | |
| - atmel,guard-time: lcd guard time (Delay in frame periods) | |
| - bits-per-pixel: lcd panel bit-depth. | |
| Optional properties (as per of_videomode_helper): | |
| - atmel,lcdcon-backlight: enable backlight | |
| - atmel,lcdcon-backlight-inverted: invert backlight PWM polarity | |
| - atmel,lcd-wiring-mode: lcd wiring mode "RGB" or "BRG" | |
| - atmel,power-control-gpio: gpio to power on or off the LCD (as many as needed) | |
| Example: | |
| display0: display { | |
| bits-per-pixel = <32>; | |
| atmel,lcdcon-backlight; | |
| atmel,dmacon = <0x1>; | |
| atmel,lcdcon2 = <0x80008002>; | |
| atmel,guard-time = <9>; | |
| atmel,lcd-wiring-mode = <1>; | |
| display-timings { | |
| native-mode = <&timing0>; | |
| timing0: timing0 { | |
| clock-frequency = <9000000>; | |
| hactive = <480>; | |
| vactive = <272>; | |
| hback-porch = <1>; | |
| hfront-porch = <1>; | |
| vback-porch = <40>; | |
| vfront-porch = <1>; | |
| hsync-len = <45>; | |
| vsync-len = <1>; | |
| }; | |
| }; | |
| }; |
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| Atmel AT91RM9200 CompactFlash | |
| Required properties: | |
| - compatible : "atmel,at91rm9200-cf". | |
| - reg : should specify localbus address and size used. | |
| - gpios : specifies the gpio pins to control the CF device. Detect | |
| and reset gpio's are mandatory while irq and vcc gpio's are | |
| optional and may be set to 0 if not present. | |
| Example: | |
| compact-flash@50000000 { | |
| compatible = "atmel,at91rm9200-cf"; | |
| reg = <0x50000000 0x30000000>; | |
| gpios = <&pioC 13 0 /* irq */ | |
| &pioC 15 0 /* detect */ | |
| 0 /* vcc */ | |
| &pioC 5 0 /* reset */ | |
| >; | |
| }; |
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| Atmel AT91RM9200 System Timer Watchdog | |
| Required properties: | |
| - compatible: must be "atmel,at91sam9260-wdt". | |
| Example: | |
| watchdog@fffffd00 { | |
| compatible = "atmel,at91rm9200-wdt"; | |
| }; |
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| * Atmel at91sam9g20ek wm8731 audio complex | |
| Required properties: | |
| - compatible: "atmel,at91sam9g20ek-wm8731-audio" | |
| - atmel,model: The user-visible name of this sound complex. | |
| - atmel,audio-routing: A list of the connections between audio components. | |
| - atmel,ssc-controller: The phandle of the SSC controller | |
| - atmel,audio-codec: The phandle of the WM8731 audio codec | |
| Optional properties: | |
| - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt | |
| Example: | |
| sound { | |
| compatible = "atmel,at91sam9g20ek-wm8731-audio"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_pck0_as_mck>; | |
| atmel,model = "wm8731 @ AT91SAMG20EK"; | |
| atmel,audio-routing = | |
| "Ext Spk", "LHPOUT", | |
| "Int MIC", "MICIN"; | |
| atmel,ssc-controller = <&ssc0>; | |
| atmel,audio-codec = <&wm8731>; | |
| }; |
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| * AT91 CAN * | |
| Required properties: | |
| - compatible: Should be "atmel,at91sam9263-can", "atmel,at91sam9x5-can" or | |
| "microchip,sam9x60-can" | |
| - reg: Should contain CAN controller registers location and length | |
| - interrupts: Should contain IRQ line for the CAN controller | |
| Example: | |
| can0: can@f000c000 { | |
| compatible = "atmel,at91sam9x5-can"; | |
| reg = <0xf000c000 0x300>; | |
| interrupts = <40 4 5> | |
| }; |
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| * Atmel ClassD driver under ALSA SoC architecture | |
| Required properties: | |
| - compatible | |
| Should be "atmel,sama5d2-classd". | |
| - reg | |
| Should contain ClassD registers location and length. | |
| - interrupts | |
| Should contain the IRQ line for the ClassD. | |
| - dmas | |
| One DMA specifiers as described in atmel-dma.txt and dma.txt files. | |
| - dma-names | |
| Must be "tx". | |
| - clock-names | |
| Tuple listing input clock names. | |
| Required elements: "pclk" and "gclk". | |
| - clocks | |
| Please refer to clock-bindings.txt. | |
| - assigned-clocks | |
| Should be <&classd_gclk>. | |
| Optional properties: | |
| - pinctrl-names, pinctrl-0 | |
| Please refer to pinctrl-bindings.txt. | |
| - atmel,model | |
| The user-visible name of this sound complex. | |
| The default value is "CLASSD". | |
| - atmel,pwm-type | |
| PWM modulation type, "single" or "diff". | |
| The default value is "single". | |
| - atmel,non-overlap-time | |
| Set non-overlapping time, the unit is nanosecond(ns). | |
| There are four values, | |
| <5>, <10>, <15>, <20>, the default value is <10>. | |
| Non-overlapping will be disabled if not specified. | |
| Example: | |
| classd: classd@fc048000 { | |
| compatible = "atmel,sama5d2-classd"; | |
| reg = <0xfc048000 0x100>; | |
| interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; | |
| dmas = <&dma0 | |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| | AT91_XDMAC_DT_PERID(47))>; | |
| dma-names = "tx"; | |
| clocks = <&classd_clk>, <&classd_gclk>; | |
| clock-names = "pclk", "gclk"; | |
| assigned-clocks = <&classd_gclk>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_classd_default>; | |
| atmel,model = "classd @ SAMA5D2-Xplained"; | |
| atmel,pwm-type = "diff"; | |
| atmel,non-overlap-time = <10>; | |
| }; |
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| * Atmel HW cryptographic accelerators | |
| These are the HW cryptographic accelerators found on some Atmel products. | |
| * Advanced Encryption Standard (AES) | |
| Required properties: | |
| - compatible : Should be "atmel,at91sam9g46-aes". | |
| - reg: Should contain AES registers location and length. | |
| - interrupts: Should contain the IRQ line for the AES. | |
| - dmas: List of two DMA specifiers as described in | |
| atmel-dma.txt and dma.txt files. | |
| - dma-names: Contains one identifier string for each DMA specifier | |
| in the dmas property. | |
| Example: | |
| aes@f8038000 { | |
| compatible = "atmel,at91sam9g46-aes"; | |
| reg = <0xf8038000 0x100>; | |
| interrupts = <43 4 0>; | |
| dmas = <&dma1 2 18>, | |
| <&dma1 2 19>; | |
| dma-names = "tx", "rx"; | |
| * Triple Data Encryption Standard (Triple DES) | |
| Required properties: | |
| - compatible : Should be "atmel,at91sam9g46-tdes". | |
| - reg: Should contain TDES registers location and length. | |
| - interrupts: Should contain the IRQ line for the TDES. | |
| Optional properties: | |
| - dmas: List of two DMA specifiers as described in | |
| atmel-dma.txt and dma.txt files. | |
| - dma-names: Contains one identifier string for each DMA specifier | |
| in the dmas property. | |
| Example: | |
| tdes@f803c000 { | |
| compatible = "atmel,at91sam9g46-tdes"; | |
| reg = <0xf803c000 0x100>; | |
| interrupts = <44 4 0>; | |
| dmas = <&dma1 2 20>, | |
| <&dma1 2 21>; | |
| dma-names = "tx", "rx"; | |
| }; | |
| * Secure Hash Algorithm (SHA) | |
| Required properties: | |
| - compatible : Should be "atmel,at91sam9g46-sha". | |
| - reg: Should contain SHA registers location and length. | |
| - interrupts: Should contain the IRQ line for the SHA. | |
| Optional properties: | |
| - dmas: One DMA specifiers as described in | |
| atmel-dma.txt and dma.txt files. | |
| - dma-names: Contains one identifier string for each DMA specifier | |
| in the dmas property. Only one "tx" string needed. | |
| Example: | |
| sha@f8034000 { | |
| compatible = "atmel,at91sam9g46-sha"; | |
| reg = <0xf8034000 0x100>; | |
| interrupts = <42 4 0>; | |
| dmas = <&dma1 2 17>; | |
| dma-names = "tx"; | |
| }; |
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| * Atmel Data Flash | |
| Required properties: | |
| - compatible : "atmel,<model>", "atmel,<series>", "atmel,dataflash". | |
| The device tree may optionally contain sub-nodes describing partitions of the | |
| address space. See partition.txt for more detail. | |
| Example: | |
| flash@1 { | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; | |
| spi-max-frequency = <25000000>; | |
| reg = <1>; | |
| }; |
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| * Atmel Direct Memory Access Controller (DMA) | |
| Required properties: | |
| - compatible: Should be "atmel,<chip>-dma". | |
| - reg: Should contain DMA registers location and length. | |
| - interrupts: Should contain DMA interrupt. | |
| - #dma-cells: Must be <2>, used to represent the number of integer cells in | |
| the dmas property of client devices. | |
| Example: | |
| dma0: dma@ffffec00 { | |
| compatible = "atmel,at91sam9g45-dma"; | |
| reg = <0xffffec00 0x200>; | |
| interrupts = <21>; | |
| #dma-cells = <2>; | |
| }; | |
| DMA clients connected to the Atmel DMA controller must use the format | |
| described in the dma.txt file, using a three-cell specifier for each channel: | |
| a phandle plus two integer cells. | |
| The three cells in order are: | |
| 1. A phandle pointing to the DMA controller. | |
| 2. The memory interface (16 most significant bits), the peripheral interface | |
| (16 less significant bits). | |
| 3. Parameters for the at91 DMA configuration register which are device | |
| dependent: | |
| - bit 7-0: peripheral identifier for the hardware handshaking interface. The | |
| identifier can be different for tx and rx. | |
| - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP. | |
| Example: | |
| i2c0@i2c@f8010000 { | |
| compatible = "atmel,at91sam9x5-i2c"; | |
| reg = <0xf8010000 0x100>; | |
| interrupts = <9 4 6>; | |
| dmas = <&dma0 1 7>, | |
| <&dma0 1 8>; | |
| dma-names = "tx", "rx"; | |
| }; |
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| * Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit) | |
| The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C | |
| controller and an USART. Only one function can be used at a time and is chosen | |
| at boot time according to the device tree. | |
| Required properties: | |
| - compatible: Should be "atmel,sama5d2-flexcom" | |
| - reg: Should be the offset/length value for Flexcom dedicated | |
| I/O registers (without USART, TWI or SPI registers). | |
| - clocks: Should be the Flexcom peripheral clock from PMC. | |
| - #address-cells: Should be <1> | |
| - #size-cells: Should be <1> | |
| - ranges: Should be one range for the full I/O register region | |
| (including USART, TWI and SPI registers). | |
| - atmel,flexcom-mode: Should be one of the following values: | |
| - <1> for USART | |
| - <2> for SPI | |
| - <3> for I2C | |
| Required child: | |
| A single available child device of type matching the "atmel,flexcom-mode" | |
| property. | |
| The phandle provided by the clocks property of the child is the same as one for | |
| the Flexcom parent. | |
| For other properties, please refer to the documentations of the respective | |
| device: | |
| - ../serial/atmel-usart.txt | |
| - ../spi/spi_atmel.txt | |
| - ../i2c/i2c-at91.txt | |
| Example: | |
| flexcom@f8034000 { | |
| compatible = "atmel,sama5d2-flexcom"; | |
| reg = <0xf8034000 0x200>; | |
| clocks = <&flx0_clk>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ranges = <0x0 0xf8034000 0x800>; | |
| atmel,flexcom-mode = <2>; | |
| spi@400 { | |
| compatible = "atmel,at91rm9200-spi"; | |
| reg = <0x400 0x200>; | |
| interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_flx0_default>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| clocks = <&flx0_clk>; | |
| clock-names = "spi_clk"; | |
| atmel,fifo-size = <32>; | |
| mtd_dataflash@0 { | |
| compatible = "atmel,at25f512b"; | |
| reg = <0>; | |
| spi-max-frequency = <20000000>; | |
| }; | |
| }; | |
| }; |
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| * Device tree bindings for Atmel GPBR (General Purpose Backup Registers) | |
| The GPBR are a set of battery-backed registers. | |
| Required properties: | |
| - compatible: Should be one of the following: | |
| "atmel,at91sam9260-gpbr", "syscon" | |
| "microchip,sam9x60-gpbr", "syscon" | |
| - reg: contains offset/length value of the GPBR memory | |
| region. | |
| Example: | |
| gpbr: gpbr@fffffd50 { | |
| compatible = "atmel,at91sam9260-gpbr", "syscon"; | |
| reg = <0xfffffd50 0x10>; | |
| }; |
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| Device-Tree bindings for Atmel's HLCDC (High-end LCD Controller) PWM driver | |
| The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. | |
| See ../mfd/atmel-hlcdc.txt for more details. | |
| Required properties: | |
| - compatible: value should be one of the following: | |
| "atmel,hlcdc-pwm" | |
| - pinctr-names: the pin control state names. Should contain "default". | |
| - pinctrl-0: should contain the pinctrl states described by pinctrl | |
| default. | |
| - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells | |
| bindings defined in pwm.yaml in this directory. | |
| Example: | |
| hlcdc: hlcdc@f0030000 { | |
| compatible = "atmel,sama5d3-hlcdc"; | |
| reg = <0xf0030000 0x2000>; | |
| clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; | |
| clock-names = "periph_clk","sys_clk", "slow_clk"; | |
| hlcdc_pwm: hlcdc-pwm { | |
| compatible = "atmel,hlcdc-pwm"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_lcd_pwm>; | |
| #pwm-cells = <3>; | |
| }; | |
| }; |
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| Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver | |
| Required properties: | |
| - compatible: value should be one of the following: | |
| "atmel,at91sam9n12-hlcdc" | |
| "atmel,at91sam9x5-hlcdc" | |
| "atmel,sama5d2-hlcdc" | |
| "atmel,sama5d3-hlcdc" | |
| "atmel,sama5d4-hlcdc" | |
| "microchip,sam9x60-hlcdc" | |
| - reg: base address and size of the HLCDC device registers. | |
| - clock-names: the name of the 3 clocks requested by the HLCDC device. | |
| Should contain "periph_clk", "sys_clk" and "slow_clk". | |
| - clocks: should contain the 3 clocks requested by the HLCDC device. | |
| - interrupts: should contain the description of the HLCDC interrupt line | |
| The HLCDC IP exposes two subdevices: | |
| - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt | |
| - a Display Controller: see ../display/atmel/hlcdc-dc.txt | |
| Example: | |
| hlcdc: hlcdc@f0030000 { | |
| compatible = "atmel,sama5d3-hlcdc"; | |
| reg = <0xf0030000 0x2000>; | |
| clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; | |
| clock-names = "periph_clk","sys_clk", "slow_clk"; | |
| interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; | |
| hlcdc-display-controller { | |
| compatible = "atmel,hlcdc-display-controller"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| port@0 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| reg = <0>; | |
| hlcdc_panel_output: endpoint@0 { | |
| reg = <0>; | |
| remote-endpoint = <&panel_input>; | |
| }; | |
| }; | |
| }; | |
| hlcdc_pwm: hlcdc-pwm { | |
| compatible = "atmel,hlcdc-pwm"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_lcd_pwm>; | |
| #pwm-cells = <3>; | |
| }; | |
| }; |
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| * Atmel High Speed MultiMedia Card Interface | |
| This controller on atmel products provides an interface for MMC, SD and SDIO | |
| types of memory cards. | |
| This file documents differences between the core properties described | |
| by mmc.txt and the properties used by the atmel-mci driver. | |
| 1) MCI node | |
| Required properties: | |
| - compatible: should be "atmel,hsmci" | |
| - #address-cells: should be one. The cell is the slot id. | |
| - #size-cells: should be zero. | |
| - at least one slot node | |
| - clock-names: tuple listing input clock names. | |
| Required elements: "mci_clk" | |
| - clocks: phandles to input clocks. | |
| The node contains child nodes for each slot that the platform uses | |
| Example MCI node: | |
| mmc0: mmc@f0008000 { | |
| compatible = "atmel,hsmci"; | |
| reg = <0xf0008000 0x600>; | |
| interrupts = <12 4>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| clock-names = "mci_clk"; | |
| clocks = <&mci0_clk>; | |
| [ child node definitions...] | |
| }; | |
| 2) slot nodes | |
| Required properties: | |
| - reg: should contain the slot id. | |
| - bus-width: number of data lines connected to the controller | |
| Optional properties: | |
| - cd-gpios: specify GPIOs for card detection | |
| - cd-inverted: invert the value of external card detect gpio line | |
| - wp-gpios: specify GPIOs for write protection | |
| Example slot node: | |
| slot@0 { | |
| reg = <0>; | |
| bus-width = <4>; | |
| cd-gpios = <&pioD 15 0> | |
| cd-inverted; | |
| }; | |
| Example full MCI node: | |
| mmc0: mmc@f0008000 { | |
| compatible = "atmel,hsmci"; | |
| reg = <0xf0008000 0x600>; | |
| interrupts = <12 4>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| slot@0 { | |
| reg = <0>; | |
| bus-width = <4>; | |
| cd-gpios = <&pioD 15 0> | |
| cd-inverted; | |
| }; | |
| slot@1 { | |
| reg = <1>; | |
| bus-width = <4>; | |
| }; | |
| }; |
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| * Atmel I2S controller | |
| Required properties: | |
| - compatible: Should be "atmel,sama5d2-i2s". | |
| - reg: Should be the physical base address of the controller and the | |
| length of memory mapped region. | |
| - interrupts: Should contain the interrupt for the controller. | |
| - dmas: Should be one per channel name listed in the dma-names property, | |
| as described in atmel-dma.txt and dma.txt files. | |
| - dma-names: Two dmas have to be defined, "tx" and "rx". | |
| This IP also supports one shared channel for both rx and tx; | |
| if this mode is used, one "rx-tx" name must be used. | |
| - clocks: Must contain an entry for each entry in clock-names. | |
| Please refer to clock-bindings.txt. | |
| - clock-names: Should be one of each entry matching the clocks phandles list: | |
| - "pclk" (peripheral clock) Required. | |
| - "gclk" (generated clock) Optional (1). | |
| - "muxclk" (I2S mux clock) Optional (1). | |
| Optional properties: | |
| - pinctrl-0: Should specify pin control groups used for this controller. | |
| - princtrl-names: Should contain only one value - "default". | |
| (1) : Only the peripheral clock is required. The generated clock and the I2S | |
| mux clock are optional and should only be set together, when Master Mode | |
| is required. | |
| Example: | |
| i2s@f8050000 { | |
| compatible = "atmel,sama5d2-i2s"; | |
| reg = <0xf8050000 0x300>; | |
| interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; | |
| dmas = <&dma0 | |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
| AT91_XDMAC_DT_PERID(31))>, | |
| <&dma0 | |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | | |
| AT91_XDMAC_DT_PERID(32))>; | |
| dma-names = "tx", "rx"; | |
| clocks = <&i2s0_clk>, <&i2s0_gclk>, <&i2s0muxck>; | |
| clock-names = "pclk", "gclk", "muxclk"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_i2s0_default>; | |
| }; |
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| Atmel Image Sensor Interface (ISI) | |
| ---------------------------------- | |
| Required properties for ISI: | |
| - compatible: must be "atmel,at91sam9g45-isi" or "microchip,sam9x60-isi". | |
| - reg: physical base address and length of the registers set for the device. | |
| - interrupts: should contain IRQ line for the ISI. | |
| - clocks: list of clock specifiers, corresponding to entries in the clock-names | |
| property; please refer to clock-bindings.txt. | |
| - clock-names: required elements: "isi_clk". | |
| - pinctrl-names, pinctrl-0: please refer to pinctrl-bindings.txt. | |
| ISI supports a single port node with parallel bus. It shall contain one | |
| 'port' child node with child 'endpoint' node. Please refer to the bindings | |
| defined in Documentation/devicetree/bindings/media/video-interfaces.txt. | |
| Endpoint node properties | |
| ------------------------ | |
| - bus-width: <8> or <10> (mandatory) | |
| - hsync-active (default: active high) | |
| - vsync-active (default: active high) | |
| - pclk-sample (default: sample on falling edge) | |
| - remote-endpoint: A phandle to the bus receiver's endpoint node (mandatory). | |
| Example: | |
| isi: isi@f0034000 { | |
| compatible = "atmel,at91sam9g45-isi"; | |
| reg = <0xf0034000 0x4000>; | |
| interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_isi_data_0_7>; | |
| clocks = <&isi_clk>; | |
| clock-names = "isi_clk"; | |
| port { | |
| isi_0: endpoint { | |
| remote-endpoint = <&ov2640_0>; | |
| bus-width = <8>; | |
| vsync-active = <1>; | |
| hsync-active = <1>; | |
| }; | |
| }; | |
| }; | |
| i2c1: i2c@f0018000 { | |
| ov2640: camera@30 { | |
| compatible = "ovti,ov2640"; | |
| reg = <0x30>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; | |
| resetb-gpios = <&pioE 11 GPIO_ACTIVE_LOW>; | |
| pwdn-gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; | |
| clocks = <&pck0>; | |
| clock-names = "xvclk"; | |
| assigned-clocks = <&pck0>; | |
| assigned-clock-rates = <25000000>; | |
| port { | |
| ov2640_0: endpoint { | |
| remote-endpoint = <&isi_0>; | |
| bus-width = <8>; | |
| }; | |
| }; | |
| }; | |
| }; |
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| * Device tree bindings for Atmel Bus Matrix | |
| The Bus Matrix registers are used to configure Atmel SoCs internal bus | |
| behavior (master/slave priorities, undefined burst length type, ...) | |
| Required properties: | |
| - compatible: Should be one of the following | |
| "atmel,at91sam9260-matrix", "syscon" | |
| "atmel,at91sam9261-matrix", "syscon" | |
| "atmel,at91sam9263-matrix", "syscon" | |
| "atmel,at91sam9rl-matrix", "syscon" | |
| "atmel,at91sam9g45-matrix", "syscon" | |
| "atmel,at91sam9n12-matrix", "syscon" | |
| "atmel,at91sam9x5-matrix", "syscon" | |
| "atmel,sama5d3-matrix", "syscon" | |
| "microchip,sam9x60-matrix", "syscon" | |
| - reg: Contains offset/length value of the Bus Matrix | |
| memory region. | |
| Example: | |
| matrix: matrix@ffffec00 { | |
| compatible = "atmel,sama5d3-matrix", "syscon"; | |
| reg = <0xffffec00 0x200>; | |
| }; |
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| Atmel NAND flash controller bindings | |
| The NAND flash controller node should be defined under the EBI bus (see | |
| Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt). | |
| One or several NAND devices can be defined under this NAND controller. | |
| The NAND controller might be connected to an ECC engine. | |
| * NAND controller bindings: | |
| Required properties: | |
| - compatible: should be one of the following | |
| "atmel,at91rm9200-nand-controller" | |
| "atmel,at91sam9260-nand-controller" | |
| "atmel,at91sam9261-nand-controller" | |
| "atmel,at91sam9g45-nand-controller" | |
| "atmel,sama5d3-nand-controller" | |
| "microchip,sam9x60-nand-controller" | |
| - ranges: empty ranges property to forward EBI ranges definitions. | |
| - #address-cells: should be set to 2. | |
| - #size-cells: should be set to 1. | |
| - atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3 | |
| controllers. | |
| - atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3 | |
| controllers. | |
| Optional properties: | |
| - ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds | |
| a PMECC engine. | |
| * NAND device/chip bindings: | |
| Required properties: | |
| - reg: describes the CS lines assigned to the NAND device. If the NAND device | |
| exposes multiple CS lines (multi-dies chips), your reg property will | |
| contain X tuples of 3 entries. | |
| 1st entry: the CS line this NAND chip is connected to | |
| 2nd entry: the base offset of the memory region assigned to this | |
| device (always 0) | |
| 3rd entry: the memory region size (always 0x800000) | |
| Optional properties: | |
| - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND. | |
| - cs-gpios: the GPIO(s) used to control the CS line. | |
| - det-gpios: the GPIO used to detect if a Smartmedia Card is present. | |
| - atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful | |
| on sama5 SoCs. | |
| All generic properties described in | |
| Documentation/devicetree/bindings/mtd/{common,nand}.txt also apply to the NAND | |
| device node, and NAND partitions should be defined under the NAND node as | |
| described in Documentation/devicetree/bindings/mtd/partition.txt. | |
| * ECC engine (PMECC) bindings: | |
| Required properties: | |
| - compatible: should be one of the following | |
| "atmel,at91sam9g45-pmecc" | |
| "atmel,sama5d4-pmecc" | |
| "atmel,sama5d2-pmecc" | |
| "microchip,sam9x60-pmecc" | |
| - reg: should contain 2 register ranges. The first one is pointing to the PMECC | |
| block, and the second one to the PMECC_ERRLOC block. | |
| * SAMA5 NFC I/O bindings: | |
| SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page | |
| operations. This interface to this logic is placed in a separate I/O range and | |
| should thus have its own DT node. | |
| - compatible: should be "atmel,sama5d3-nfc-io", "syscon". | |
| - reg: should contain the I/O range used to interact with the NFC logic. | |
| Example: | |
| nfc_io: nfc-io@70000000 { | |
| compatible = "atmel,sama5d3-nfc-io", "syscon"; | |
| reg = <0x70000000 0x8000000>; | |
| }; | |
| pmecc: ecc-engine@ffffc070 { | |
| compatible = "atmel,at91sam9g45-pmecc"; | |
| reg = <0xffffc070 0x490>, | |
| <0xffffc500 0x100>; | |
| }; | |
| ebi: ebi@10000000 { | |
| compatible = "atmel,sama5d3-ebi"; | |
| #address-cells = <2>; | |
| #size-cells = <1>; | |
| atmel,smc = <&hsmc>; | |
| reg = <0x10000000 0x10000000 | |
| 0x40000000 0x30000000>; | |
| ranges = <0x0 0x0 0x10000000 0x10000000 | |
| 0x1 0x0 0x40000000 0x10000000 | |
| 0x2 0x0 0x50000000 0x10000000 | |
| 0x3 0x0 0x60000000 0x10000000>; | |
| clocks = <&mck>; | |
| nand_controller: nand-controller { | |
| compatible = "atmel,sama5d3-nand-controller"; | |
| atmel,nfc-sram = <&nfc_sram>; | |
| atmel,nfc-io = <&nfc_io>; | |
| ecc-engine = <&pmecc>; | |
| #address-cells = <2>; | |
| #size-cells = <1>; | |
| ranges; | |
| nand@3 { | |
| reg = <0x3 0x0 0x800000>; | |
| atmel,rb = <0>; | |
| /* | |
| * Put generic NAND/MTD properties and | |
| * subnodes here. | |
| */ | |
| }; | |
| }; | |
| }; | |
| ----------------------------------------------------------------------- | |
| Deprecated bindings (should not be used in new device trees): | |
| Required properties: | |
| - compatible: The possible values are: | |
| "atmel,at91rm9200-nand" | |
| "atmel,sama5d2-nand" | |
| "atmel,sama5d4-nand" | |
| - reg : should specify localbus address and size used for the chip, | |
| and hardware ECC controller if available. | |
| If the hardware ECC is PMECC, it should contain address and size for | |
| PMECC and PMECC Error Location controller. | |
| The PMECC lookup table address and size in ROM is optional. If not | |
| specified, driver will build it in runtime. | |
| - atmel,nand-addr-offset : offset for the address latch. | |
| - atmel,nand-cmd-offset : offset for the command latch. | |
| - #address-cells, #size-cells : Must be present if the device has sub-nodes | |
| representing partitions. | |
| - gpios : specifies the gpio pins to control the NAND device. detect is an | |
| optional gpio and may be set to 0 if not present. | |
| Optional properties: | |
| - atmel,nand-has-dma : boolean to support dma transfer for nand read/write. | |
| - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default. | |
| Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first", | |
| "soft_bch". | |
| - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware, | |
| capable of BCH encoding and decoding, on devices where it is present. | |
| - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC | |
| Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string | |
| is "atmel,sama5d2-nand", 32 is also valid. | |
| - atmel,pmecc-sector-size : sector size for ECC computation. Supported values | |
| are: 512, 1024. | |
| - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM | |
| for different sector size. First one is for sector size 512, the next is for | |
| sector size 1024. If not specified, driver will build the table in runtime. | |
| - nand-bus-width : 8 or 16 bus width if not present 8 | |
| - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false | |
| Nand Flash Controller(NFC) is an optional sub-node | |
| Required properties: | |
| - compatible : "atmel,sama5d3-nfc". | |
| - reg : should specify the address and size used for NFC command registers, | |
| NFC registers and NFC SRAM. NFC SRAM address and size can be absent | |
| if don't want to use it. | |
| - clocks: phandle to the peripheral clock | |
| Optional properties: | |
| - atmel,write-by-sram: boolean to enable NFC write by SRAM. | |
| Examples: | |
| nand0: nand@40000000,0 { | |
| compatible = "atmel,at91rm9200-nand"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| reg = <0x40000000 0x10000000 | |
| 0xffffe800 0x200 | |
| >; | |
| atmel,nand-addr-offset = <21>; /* ale */ | |
| atmel,nand-cmd-offset = <22>; /* cle */ | |
| nand-on-flash-bbt; | |
| nand-ecc-mode = "soft"; | |
| gpios = <&pioC 13 0 /* rdy */ | |
| &pioC 14 0 /* nce */ | |
| 0 /* cd */ | |
| >; | |
| partition@0 { | |
| ... | |
| }; | |
| }; | |
| /* for PMECC supported chips */ | |
| nand0: nand@40000000 { | |
| compatible = "atmel,at91rm9200-nand"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| reg = < 0x40000000 0x10000000 /* bus addr & size */ | |
| 0xffffe000 0x00000600 /* PMECC addr & size */ | |
| 0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */ | |
| 0x00100000 0x00100000 /* ROM addr & size */ | |
| >; | |
| atmel,nand-addr-offset = <21>; /* ale */ | |
| atmel,nand-cmd-offset = <22>; /* cle */ | |
| nand-on-flash-bbt; | |
| nand-ecc-mode = "hw"; | |
| atmel,has-pmecc; /* enable PMECC */ | |
| atmel,pmecc-cap = <2>; | |
| atmel,pmecc-sector-size = <512>; | |
| atmel,pmecc-lookup-table-offset = <0x8000 0x10000>; | |
| gpios = <&pioD 5 0 /* rdy */ | |
| &pioD 4 0 /* nce */ | |
| 0 /* cd */ | |
| >; | |
| partition@0 { | |
| ... | |
| }; | |
| }; | |
| /* for NFC supported chips */ | |
| nand0: nand@40000000 { | |
| compatible = "atmel,at91rm9200-nand"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ranges; | |
| ... | |
| nfc@70000000 { | |
| compatible = "atmel,sama5d3-nfc"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| clocks = <&hsmc_clk> | |
| reg = < | |
| 0x70000000 0x10000000 /* NFC Command Registers */ | |
| 0xffffc000 0x00000070 /* NFC HSMC regs */ | |
| 0x00200000 0x00100000 /* NFC SRAM banks */ | |
| >; | |
| }; | |
| }; |
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| * Atmel PDMIC driver under ALSA SoC architecture | |
| Required properties: | |
| - compatible | |
| Should be "atmel,sama5d2-pdmic". | |
| - reg | |
| Should contain PDMIC registers location and length. | |
| - interrupts | |
| Should contain the IRQ line for the PDMIC. | |
| - dmas | |
| One DMA specifiers as described in atmel-dma.txt and dma.txt files. | |
| - dma-names | |
| Must be "rx". | |
| - clock-names | |
| Required elements: | |
| - "pclk" peripheral clock | |
| - "gclk" generated clock | |
| - clocks | |
| Must contain an entry for each required entry in clock-names. | |
| Please refer to clock-bindings.txt. | |
| - atmel,mic-min-freq | |
| The minimal frequency that the micphone supports. | |
| - atmel,mic-max-freq | |
| The maximal frequency that the micphone supports. | |
| Optional properties: | |
| - pinctrl-names, pinctrl-0 | |
| Please refer to pinctrl-bindings.txt. | |
| - atmel,model | |
| The user-visible name of this sound card. | |
| The default value is "PDMIC". | |
| - atmel,mic-offset | |
| The offset that should be added. | |
| The range is from -32768 to 32767. | |
| The default value is 0. | |
| Example: | |
| pdmic@f8018000 { | |
| compatible = "atmel,sama5d2-pdmic"; | |
| reg = <0xf8018000 0x124>; | |
| interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; | |
| dmas = <&dma0 | |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| | AT91_XDMAC_DT_PERID(50))>; | |
| dma-names = "rx"; | |
| clocks = <&pdmic_clk>, <&pdmic_gclk>; | |
| clock-names = "pclk", "gclk"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_pdmic_default>; | |
| atmel,model = "PDMIC @ sama5d2_xplained"; | |
| atmel,mic-min-freq = <1000000>; | |
| atmel,mic-max-freq = <3246000>; | |
| atmel,mic-offset = <0x0>; | |
| }; |
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| Atmel PWM controller | |
| Required properties: | |
| - compatible: should be one of: | |
| - "atmel,at91sam9rl-pwm" | |
| - "atmel,sama5d3-pwm" | |
| - "atmel,sama5d2-pwm" | |
| - "microchip,sam9x60-pwm" | |
| - reg: physical base address and length of the controller's registers | |
| - #pwm-cells: Should be 3. See pwm.yaml in this directory for a | |
| description of the cells format. | |
| Example: | |
| pwm0: pwm@f8034000 { | |
| compatible = "atmel,at91sam9rl-pwm"; | |
| reg = <0xf8034000 0x400>; | |
| #pwm-cells = <3>; | |
| }; | |
| pwmleds { | |
| compatible = "pwm-leds"; | |
| d1 { | |
| label = "d1"; | |
| pwms = <&pwm0 3 5000 0> | |
| max-brightness = <255>; | |
| }; | |
| d2 { | |
| label = "d2"; | |
| pwms = <&pwm0 1 5000 1> | |
| max-brightness = <255>; | |
| }; | |
| }; |
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| * Atmel at91sam9x5ek wm8731 audio complex | |
| Required properties: | |
| - compatible: "atmel,sam9x5-wm8731-audio" | |
| - atmel,model: The user-visible name of this sound complex. | |
| - atmel,ssc-controller: The phandle of the SSC controller | |
| - atmel,audio-codec: The phandle of the WM8731 audio codec | |
| - atmel,audio-routing: A list of the connections between audio components. | |
| Each entry is a pair of strings, the first being the connection's sink, | |
| the second being the connection's source. | |
| Available audio endpoints for the audio-routing table: | |
| Board connectors: | |
| * Headphone Jack | |
| * Line In Jack | |
| wm8731 pins: | |
| cf Documentation/devicetree/bindings/sound/wm8731.txt | |
| Example: | |
| sound { | |
| compatible = "atmel,sam9x5-wm8731-audio"; | |
| atmel,model = "wm8731 @ AT91SAM9X5EK"; | |
| atmel,audio-routing = | |
| "Headphone Jack", "RHPOUT", | |
| "Headphone Jack", "LHPOUT", | |
| "LLINEIN", "Line In Jack", | |
| "RLINEIN", "Line In Jack"; | |
| atmel,ssc-controller = <&ssc0>; | |
| atmel,audio-codec = <&wm8731>; | |
| }; |
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| * Device tree bindings for Atmel SMC (Static Memory Controller) | |
| The SMC registers are used to configure Atmel EBI (External Bus Interface) | |
| to interface with standard memory devices (NAND, NOR, SRAM or specialized | |
| devices like FPGAs). | |
| Required properties: | |
| - compatible: Should be one of the following | |
| "atmel,at91sam9260-smc", "syscon" | |
| "atmel,sama5d3-smc", "syscon" | |
| "atmel,sama5d2-smc", "syscon" | |
| "microchip,sam9x60-smc", "syscon" | |
| - reg: Contains offset/length value of the SMC memory | |
| region. | |
| Example: | |
| smc: smc@ffffc000 { | |
| compatible = "atmel,sama5d3-smc", "syscon"; | |
| reg = <0xffffc000 0x1000>; | |
| }; |
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| * Atmel SSC driver. | |
| Required properties: | |
| - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc" | |
| - atmel,at91rm9200-ssc: support pdc transfer | |
| - atmel,at91sam9g45-ssc: support dma transfer | |
| - reg: Should contain SSC registers location and length | |
| - interrupts: Should contain SSC interrupt | |
| - clock-names: tuple listing input clock names. | |
| Required elements: "pclk" | |
| - clocks: phandles to input clocks. | |
| Required properties for devices compatible with "atmel,at91sam9g45-ssc": | |
| - dmas: DMA specifier, consisting of a phandle to DMA controller node, | |
| the memory interface and SSC DMA channel ID (for tx and rx). | |
| See Documentation/devicetree/bindings/dma/atmel-dma.txt for details. | |
| - dma-names: Must be "tx", "rx". | |
| Optional properties: | |
| - atmel,clk-from-rk-pin: bool property. | |
| - When SSC works in slave mode, according to the hardware design, the | |
| clock can get from TK pin, and also can get from RK pin. So, add | |
| this parameter to choose where the clock from. | |
| - By default the clock is from TK pin, if the clock from RK pin, this | |
| property is needed. | |
| - #sound-dai-cells: Should contain <0>. | |
| - This property makes the SSC into an automatically registered DAI. | |
| Examples: | |
| - PDC transfer: | |
| ssc0: ssc@fffbc000 { | |
| compatible = "atmel,at91rm9200-ssc"; | |
| reg = <0xfffbc000 0x4000>; | |
| interrupts = <14 4 5>; | |
| clocks = <&ssc0_clk>; | |
| clock-names = "pclk"; | |
| }; | |
| - DMA transfer: | |
| ssc0: ssc@f0010000 { | |
| compatible = "atmel,at91sam9g45-ssc"; | |
| reg = <0xf0010000 0x4000>; | |
| interrupts = <28 4 5>; | |
| dmas = <&dma0 1 13>, | |
| <&dma0 1 14>; | |
| dma-names = "tx", "rx"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | |
| }; |
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| Atmel system registers | |
| Chipid required properties: | |
| - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" | |
| - reg : Should contain registers location and length | |
| PIT Timer required properties: | |
| - compatible: Should be "atmel,at91sam9260-pit" | |
| - reg: Should contain registers location and length | |
| - interrupts: Should contain interrupt for the PIT which is the IRQ line | |
| shared across all System Controller members. | |
| PIT64B Timer required properties: | |
| - compatible: Should be "microchip,sam9x60-pit64b" | |
| - reg: Should contain registers location and length | |
| - interrupts: Should contain interrupt for PIT64B timer | |
| - clocks: Should contain the available clock sources for PIT64B timer. | |
| System Timer (ST) required properties: | |
| - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" | |
| - reg: Should contain registers location and length | |
| - interrupts: Should contain interrupt for the ST which is the IRQ line | |
| shared across all System Controller members. | |
| - clocks: phandle to input clock. | |
| Its subnodes can be: | |
| - watchdog: compatible should be "atmel,at91rm9200-wdt" | |
| RSTC Reset Controller required properties: | |
| - compatible: Should be "atmel,<chip>-rstc". | |
| <chip> can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7" | |
| it also can be "microchip,sam9x60-rstc" | |
| - reg: Should contain registers location and length | |
| - clocks: phandle to input clock. | |
| Example: | |
| rstc@fffffd00 { | |
| compatible = "atmel,at91sam9260-rstc"; | |
| reg = <0xfffffd00 0x10>; | |
| clocks = <&clk32k>; | |
| }; | |
| RAMC SDRAM/DDR Controller required properties: | |
| - compatible: Should be "atmel,at91rm9200-sdramc", "syscon" | |
| "atmel,at91sam9260-sdramc", | |
| "atmel,at91sam9g45-ddramc", | |
| "atmel,sama5d3-ddramc", | |
| "microchip,sam9x60-ddramc", | |
| "microchip,sama7g5-uddrc" | |
| - reg: Should contain registers location and length | |
| Examples: | |
| ramc0: ramc@ffffe800 { | |
| compatible = "atmel,at91sam9g45-ddramc"; | |
| reg = <0xffffe800 0x200>; | |
| }; | |
| RAMC PHY Controller required properties: | |
| - compatible: Should be "microchip,sama7g5-ddr3phy", "syscon" | |
| - reg: Should contain registers location and length | |
| Example: | |
| ddr3phy: ddr3phy@e3804000 { | |
| compatible = "microchip,sama7g5-ddr3phy", "syscon"; | |
| reg = <0xe3804000 0x1000>; | |
| }; | |
| SHDWC Shutdown Controller | |
| required properties: | |
| - compatible: Should be "atmel,<chip>-shdwc". | |
| <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5". | |
| - reg: Should contain registers location and length | |
| - clocks: phandle to input clock. | |
| optional properties: | |
| - atmel,wakeup-mode: String, operation mode of the wakeup mode. | |
| Supported values are: "none", "high", "low", "any". | |
| - atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf). | |
| optional at91sam9260 properties: | |
| - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. | |
| optional at91sam9rl properties: | |
| - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. | |
| - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. | |
| optional at91sam9x5 properties: | |
| - atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. | |
| Example: | |
| shdwc@fffffd10 { | |
| compatible = "atmel,at91sam9260-shdwc"; | |
| reg = <0xfffffd10 0x10>; | |
| clocks = <&clk32k>; | |
| }; | |
| SHDWC SAMA5D2-Compatible Shutdown Controller | |
| 1) shdwc node | |
| required properties: | |
| - compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or | |
| "microchip,sama7g5-shdwc" | |
| - reg: should contain registers location and length | |
| - clocks: phandle to input clock. | |
| - #address-cells: should be one. The cell is the wake-up input index. | |
| - #size-cells: should be zero. | |
| optional properties: | |
| - debounce-delay-us: minimum wake-up inputs debouncer period in | |
| microseconds. It's usually a board-related property. | |
| - atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up. | |
| optional microchip,sam9x60-shdwc or microchip,sama7g5-shdwc properties: | |
| - atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. | |
| The node contains child nodes for each wake-up input that the platform uses. | |
| 2) input nodes | |
| Wake-up input nodes are usually described in the "board" part of the Device | |
| Tree. Note also that input 0 is linked to the wake-up pin and is frequently | |
| used. | |
| Required properties: | |
| - reg: should contain the wake-up input index [0 - 15]. | |
| Optional properties: | |
| - atmel,wakeup-active-high: boolean, the corresponding wake-up input described | |
| by the child, forces the wake-up of the core power supply on a high level. | |
| The default is to be active low. | |
| Example: | |
| On the SoC side: | |
| shdwc@f8048010 { | |
| compatible = "atmel,sama5d2-shdwc"; | |
| reg = <0xf8048010 0x10>; | |
| clocks = <&clk32k>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| atmel,wakeup-rtc-timer; | |
| }; | |
| On the board side: | |
| shdwc@f8048010 { | |
| debounce-delay-us = <976>; | |
| input@0 { | |
| reg = <0>; | |
| }; | |
| input@1 { | |
| reg = <1>; | |
| atmel,wakeup-active-high; | |
| }; | |
| }; | |
| Special Function Registers (SFR) | |
| Special Function Registers (SFR) manage specific aspects of the integrated | |
| memory, bridge implementations, processor and other functionality not controlled | |
| elsewhere. | |
| required properties: | |
| - compatible: Should be "atmel,<chip>-sfr", "syscon" or | |
| "atmel,<chip>-sfrbu", "syscon" | |
| <chip> can be "sama5d3", "sama5d4" or "sama5d2". | |
| It also can be "microchip,sam9x60-sfr", "syscon". | |
| - reg: Should contain registers location and length | |
| sfr@f0038000 { | |
| compatible = "atmel,sama5d3-sfr", "syscon"; | |
| reg = <0xf0038000 0x60>; | |
| }; | |
| Security Module (SECUMOD) | |
| The Security Module macrocell provides all necessary secure functions to avoid | |
| voltage, temperature, frequency and mechanical attacks on the chip. It also | |
| embeds secure memories that can be scrambled. | |
| The Security Module also offers the PIOBU pins which can be used as GPIO pins. | |
| Note that they maintain their voltage during Backup/Self-refresh. | |
| required properties: | |
| - compatible: Should be "atmel,<chip>-secumod", "syscon". | |
| <chip> can be "sama5d2". | |
| - reg: Should contain registers location and length | |
| - gpio-controller: Marks the port as GPIO controller. | |
| - #gpio-cells: There are 2. The pin number is the | |
| first, the second represents additional | |
| parameters such as GPIO_ACTIVE_HIGH/LOW. | |
| secumod@fc040000 { | |
| compatible = "atmel,sama5d2-secumod", "syscon"; | |
| reg = <0xfc040000 0x100>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| }; |
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| * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) | |
| Required properties for USART: | |
| - compatible: Should be one of the following: | |
| - "atmel,at91rm9200-usart" | |
| - "atmel,at91sam9260-usart" | |
| - "microchip,sam9x60-usart" | |
| - "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart" | |
| - "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart" | |
| - "microchip,sam9x60-dbgu", "microchip,sam9x60-usart" | |
| - reg: Should contain registers location and length | |
| - interrupts: Should contain interrupt | |
| - clock-names: tuple listing input clock names. | |
| Required elements: "usart" | |
| - clocks: phandles to input clocks. | |
| Required properties for USART in SPI mode: | |
| - #size-cells : Must be <0> | |
| - #address-cells : Must be <1> | |
| - cs-gpios: chipselects (internal cs not supported) | |
| - atmel,usart-mode : Must be <AT91_USART_MODE_SPI> (found in dt-bindings/mfd/at91-usart.h) | |
| Optional properties in serial and SPI mode: | |
| - dma bindings for dma transfer: | |
| - dmas: DMA specifier, consisting of a phandle to DMA controller node, | |
| memory peripheral interface and USART DMA channel ID, FIFO configuration. | |
| The order of DMA channels is fixed. The first DMA channel must be TX | |
| associated channel and the second one must be RX associated channel. | |
| Refer to dma.txt and atmel-dma.txt for details. | |
| - dma-names: "tx" for TX channel. | |
| "rx" for RX channel. | |
| The order of dma-names is also fixed. The first name must be "tx" | |
| and the second one must be "rx" as in the examples below. | |
| Optional properties in serial mode: | |
| - atmel,use-dma-rx: use of PDC or DMA for receiving data | |
| - atmel,use-dma-tx: use of PDC or DMA for transmitting data | |
| - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively. | |
| It will use specified PIO instead of the peripheral function pin for the USART feature. | |
| If unsure, don't specify this property. | |
| - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO | |
| capable USARTs. | |
| - rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt | |
| <chip> compatible description: | |
| - at91rm9200: legacy USART support | |
| - at91sam9260: generic USART implementation for SAM9 SoCs | |
| Example: | |
| - use PDC: | |
| usart0: serial@fff8c000 { | |
| compatible = "atmel,at91sam9260-usart"; | |
| reg = <0xfff8c000 0x4000>; | |
| interrupts = <7>; | |
| clocks = <&usart0_clk>; | |
| clock-names = "usart"; | |
| atmel,use-dma-rx; | |
| atmel,use-dma-tx; | |
| rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; | |
| cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; | |
| dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; | |
| dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; | |
| dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; | |
| rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; | |
| }; | |
| - use DMA: | |
| usart0: serial@f001c000 { | |
| compatible = "atmel,at91sam9260-usart"; | |
| reg = <0xf001c000 0x100>; | |
| interrupts = <12 4 5>; | |
| clocks = <&usart0_clk>; | |
| clock-names = "usart"; | |
| atmel,use-dma-rx; | |
| atmel,use-dma-tx; | |
| dmas = <&dma0 2 0x3>, | |
| <&dma0 2 0x204>; | |
| dma-names = "tx", "rx"; | |
| atmel,fifo-size = <32>; | |
| }; | |
| - SPI mode: | |
| #include <dt-bindings/mfd/at91-usart.h> | |
| spi0: spi@f001c000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "atmel,at91rm9200-usart", "atmel,at91sam9260-usart"; | |
| atmel,usart-mode = <AT91_USART_MODE_SPI>; | |
| reg = <0xf001c000 0x100>; | |
| interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; | |
| clocks = <&usart0_clk>; | |
| clock-names = "usart"; | |
| dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, | |
| <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; | |
| dma-names = "tx", "rx"; | |
| cs-gpios = <&pioB 3 0>; | |
| }; |
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| Atmel SOC USB controllers | |
| OHCI | |
| Required properties: | |
| - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers | |
| used in host mode. | |
| - reg: Address and length of the register set for the device | |
| - interrupts: Should contain ohci interrupt | |
| - clocks: Should reference the peripheral, host and system clocks | |
| - clock-names: Should contain three strings | |
| "ohci_clk" for the peripheral clock | |
| "hclk" for the host clock | |
| "uhpck" for the system clock | |
| - num-ports: Number of ports. | |
| - atmel,vbus-gpio: If present, specifies a gpio that needs to be | |
| activated for the bus to be powered. | |
| - atmel,oc-gpio: If present, specifies a gpio that needs to be | |
| activated for the overcurrent detection. | |
| usb0: ohci@500000 { | |
| compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
| reg = <0x00500000 0x100000>; | |
| clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; | |
| clock-names = "ohci_clk", "hclk", "uhpck"; | |
| interrupts = <20 4>; | |
| num-ports = <2>; | |
| }; | |
| EHCI | |
| Required properties: | |
| - compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers | |
| used in host mode. | |
| - reg: Address and length of the register set for the device | |
| - interrupts: Should contain ehci interrupt | |
| - clocks: Should reference the peripheral and the UTMI clocks | |
| - clock-names: Should contain two strings | |
| "ehci_clk" for the peripheral clock | |
| "usb_clk" for the UTMI clock | |
| Optional properties: | |
| - phy_type : For multi port host USB controllers, should be one of | |
| "utmi", or "hsic". | |
| usb1: ehci@800000 { | |
| compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
| reg = <0x00800000 0x100000>; | |
| interrupts = <22 4>; | |
| clocks = <&utmi>, <&uhphs_clk>; | |
| clock-names = "usb_clk", "ehci_clk"; | |
| }; | |
| AT91 USB device controller | |
| Required properties: | |
| - compatible: Should be one of the following | |
| "atmel,at91rm9200-udc" | |
| "atmel,at91sam9260-udc" | |
| "atmel,at91sam9261-udc" | |
| "atmel,at91sam9263-udc" | |
| - reg: Address and length of the register set for the device | |
| - interrupts: Should contain macb interrupt | |
| - clocks: Should reference the peripheral and the AHB clocks | |
| - clock-names: Should contain two strings | |
| "pclk" for the peripheral clock | |
| "hclk" for the AHB clock | |
| Optional properties: | |
| - atmel,vbus-gpio: If present, specifies a gpio that needs to be | |
| activated for the bus to be powered. | |
| usb1: gadget@fffa4000 { | |
| compatible = "atmel,at91rm9200-udc"; | |
| reg = <0xfffa4000 0x4000>; | |
| interrupts = <10 4>; | |
| clocks = <&udc_clk>, <&udpck>; | |
| clock-names = "pclk", "hclk"; | |
| atmel,vbus-gpio = <&pioC 5 0>; | |
| }; | |
| Atmel High-Speed USB device controller | |
| Required properties: | |
| - compatible: Should be one of the following | |
| "atmel,at91sam9rl-udc" | |
| "atmel,at91sam9g45-udc" | |
| "atmel,sama5d3-udc" | |
| "microchip,sam9x60-udc" | |
| - reg: Address and length of the register set for the device | |
| - interrupts: Should contain usba interrupt | |
| - clocks: Should reference the peripheral and host clocks | |
| - clock-names: Should contain two strings | |
| "pclk" for the peripheral clock | |
| "hclk" for the host clock | |
| Deprecated property: | |
| - ep childnode: To specify the number of endpoints and their properties. | |
| Optional properties: | |
| - atmel,vbus-gpio: If present, specifies a gpio that allows to detect whether | |
| vbus is present (USB is connected). | |
| Deprecated child node properties: | |
| - name: Name of the endpoint. | |
| - reg: Num of the endpoint. | |
| - atmel,fifo-size: Size of the fifo. | |
| - atmel,nb-banks: Number of banks. | |
| - atmel,can-dma: Boolean to specify if the endpoint support DMA. | |
| - atmel,can-isoc: Boolean to specify if the endpoint support ISOC. | |
| usb2: gadget@fff78000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "atmel,at91sam9rl-udc"; | |
| reg = <0x00600000 0x80000 | |
| 0xfff78000 0x400>; | |
| interrupts = <27 4 0>; | |
| clocks = <&utmi>, <&udphs_clk>; | |
| clock-names = "hclk", "pclk"; | |
| atmel,vbus-gpio = <&pioB 19 0>; | |
| }; |
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| * Atmel Watchdog Timers | |
| ** at91sam9-wdt | |
| Required properties: | |
| - compatible: must be "atmel,at91sam9260-wdt". | |
| - reg: physical base address of the controller and length of memory mapped | |
| region. | |
| - clocks: phandle to input clock. | |
| Optional properties: | |
| - timeout-sec: contains the watchdog timeout in seconds. | |
| - interrupts : Should contain WDT interrupt. | |
| - atmel,max-heartbeat-sec : Should contain the maximum heartbeat value in | |
| seconds. This value should be less or equal to 16. It is used to | |
| compute the WDV field. | |
| - atmel,min-heartbeat-sec : Should contain the minimum heartbeat value in | |
| seconds. This value must be smaller than the max-heartbeat-sec value. | |
| It is used to compute the WDD field. | |
| - atmel,watchdog-type : Should be "hardware" or "software". Hardware watchdog | |
| use the at91 watchdog reset. Software watchdog use the watchdog | |
| interrupt to trigger a software reset. | |
| - atmel,reset-type : Should be "proc" or "all". | |
| "all" : assert peripherals and processor reset signals | |
| "proc" : assert the processor reset signal | |
| This is valid only when using "hardware" watchdog. | |
| - atmel,disable : Should be present if you want to disable the watchdog. | |
| - atmel,idle-halt : Should be present if you want to stop the watchdog when | |
| entering idle state. | |
| CAUTION: This property should be used with care, it actually makes the | |
| watchdog not counting when the CPU is in idle state, therefore the | |
| watchdog reset time depends on mean CPU usage and will not reset at all | |
| if the CPU stop working while it is in idle state, which is probably | |
| not what you want. | |
| - atmel,dbg-halt : Should be present if you want to stop the watchdog when | |
| entering debug state. | |
| Example: | |
| watchdog@fffffd40 { | |
| compatible = "atmel,at91sam9260-wdt"; | |
| reg = <0xfffffd40 0x10>; | |
| interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
| clocks = <&clk32k>; | |
| timeout-sec = <15>; | |
| atmel,watchdog-type = "hardware"; | |
| atmel,reset-type = "all"; | |
| atmel,dbg-halt; | |
| atmel,idle-halt; | |
| atmel,max-heartbeat-sec = <16>; | |
| atmel,min-heartbeat-sec = <0>; | |
| }; |
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| Atmel ASoC driver with wm8904 audio codec complex | |
| Required properties: | |
| - compatible: "atmel,asoc-wm8904" | |
| - atmel,model: The user-visible name of this sound complex. | |
| - atmel,audio-routing: A list of the connections between audio components. | |
| Each entry is a pair of strings, the first being the connection's sink, | |
| the second being the connection's source. Valid names for sources and | |
| sinks are the WM8904's pins, and the jacks on the board: | |
| WM8904 pins: | |
| * IN1L | |
| * IN1R | |
| * IN2L | |
| * IN2R | |
| * IN3L | |
| * IN3R | |
| * HPOUTL | |
| * HPOUTR | |
| * LINEOUTL | |
| * LINEOUTR | |
| * MICBIAS | |
| Board connectors: | |
| * Headphone Jack | |
| * Line In Jack | |
| * Mic | |
| - atmel,ssc-controller: The phandle of the SSC controller | |
| - atmel,audio-codec: The phandle of the WM8904 audio codec | |
| Optional properties: | |
| - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt | |
| Example: | |
| sound { | |
| compatible = "atmel,asoc-wm8904"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_pck0_as_mck>; | |
| atmel,model = "wm8904 @ AT91SAM9N12EK"; | |
| atmel,audio-routing = | |
| "Headphone Jack", "HPOUTL", | |
| "Headphone Jack", "HPOUTR", | |
| "IN2L", "Line In Jack", | |
| "IN2R", "Line In Jack", | |
| "Mic", "MICBIAS", | |
| "IN1L", "Mic"; | |
| atmel,ssc-controller = <&ssc0>; | |
| atmel,audio-codec = <&wm8904>; | |
| }; |
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| * Atmel Extensible Direct Memory Access Controller (XDMAC) | |
| * XDMA Controller | |
| Required properties: | |
| - compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or | |
| "microchip,sama7g5-dma". | |
| - reg: Should contain DMA registers location and length. | |
| - interrupts: Should contain DMA interrupt. | |
| - #dma-cells: Must be <1>, used to represent the number of integer cells in | |
| the dmas property of client devices. | |
| - The 1st cell specifies the channel configuration register: | |
| - bit 13: SIF, source interface identifier, used to get the memory | |
| interface identifier, | |
| - bit 14: DIF, destination interface identifier, used to get the peripheral | |
| interface identifier, | |
| - bit 30-24: PERID, peripheral identifier. | |
| Example: | |
| dma1: dma-controller@f0004000 { | |
| compatible = "atmel,sama5d4-dma"; | |
| reg = <0xf0004000 0x200>; | |
| interrupts = <50 4 0>; | |
| #dma-cells = <1>; | |
| }; | |
| * DMA clients | |
| DMA clients connected to the Atmel XDMA controller must use the format | |
| described in the dma.txt file, using a one-cell specifier for each channel. | |
| The two cells in order are: | |
| 1. A phandle pointing to the DMA controller. | |
| 2. Channel configuration register. Configurable fields are: | |
| - bit 13: SIF, source interface identifier, used to get the memory | |
| interface identifier, | |
| - bit 14: DIF, destination interface identifier, used to get the peripheral | |
| interface identifier, | |
| - bit 30-24: PERID, peripheral identifier. | |
| Example: | |
| i2c2: i2c@f8024000 { | |
| compatible = "atmel,at91sam9x5-i2c"; | |
| reg = <0xf8024000 0x4000>; | |
| interrupts = <34 4 6>; | |
| dmas = <&dma1 | |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| | AT91_XDMAC_DT_PERID(6))>, | |
| <&dma1 | |
| (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| | AT91_XDMAC_DT_PERID(7))>; | |
| dma-names = "tx", "rx"; | |
| }; |
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| * Atmel AC97 controller | |
| Required properties: | |
| - compatible: "atmel,at91sam9263-ac97c" | |
| - reg: Address and length of the register set for the device | |
| - interrupts: Should contain AC97 interrupt | |
| - ac97-gpios: Please refer to soc-ac97link.txt, only ac97-reset is used | |
| Optional properties: | |
| - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt | |
| Example: | |
| sound@fffa0000 { | |
| compatible = "atmel,at91sam9263-ac97c"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_ac97>; | |
| reg = <0xfffa0000 0x4000>; | |
| interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>; | |
| ac97-gpios = <&pioB 0 0 &pioB 2 0 &pioC 29 GPIO_ACTIVE_LOW>; | |
| }; |
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| ============= | |
| Atomic bitops | |
| ============= | |
| While our bitmap_{}() functions are non-atomic, we have a number of operations | |
| operating on single bits in a bitmap that are atomic. | |
| API | |
| --- | |
| The single bit operations are: | |
| Non-RMW ops: | |
| test_bit() | |
| RMW atomic operations without return value: | |
| {set,clear,change}_bit() | |
| clear_bit_unlock() | |
| RMW atomic operations with return value: | |
| test_and_{set,clear,change}_bit() | |
| test_and_set_bit_lock() | |
| Barriers: | |
| smp_mb__{before,after}_atomic() | |
| All RMW atomic operations have a '__' prefixed variant which is non-atomic. | |
| SEMANTICS | |
| --------- | |
| Non-atomic ops: | |
| In particular __clear_bit_unlock() suffers the same issue as atomic_set(), | |
| which is why the generic version maps to clear_bit_unlock(), see atomic_t.txt. | |
| RMW ops: | |
| The test_and_{}_bit() operations return the original value of the bit. | |
| ORDERING | |
| -------- | |
| Like with atomic_t, the rule of thumb is: | |
| - non-RMW operations are unordered; | |
| - RMW operations that have no return value are unordered; | |
| - RMW operations that have a return value are fully ordered. | |
| - RMW operations that are conditional are unordered on FAILURE, | |
| otherwise the above rules apply. In the case of test_and_{}_bit() operations, | |
| if the bit in memory is unchanged by the operation then it is deemed to have | |
| failed. | |
| Except for a successful test_and_set_bit_lock() which has ACQUIRE semantics and | |
| clear_bit_unlock() which has RELEASE semantics. | |
| Since a platform only has a single means of achieving atomic operations | |
| the same barriers as for atomic_t are used, see atomic_t.txt. | |
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| On atomic types (atomic_t atomic64_t and atomic_long_t). | |
| The atomic type provides an interface to the architecture's means of atomic | |
| RMW operations between CPUs (atomic operations on MMIO are not supported and | |
| can lead to fatal traps on some platforms). | |
| API | |
| --- | |
| The 'full' API consists of (atomic64_ and atomic_long_ prefixes omitted for | |
| brevity): | |
| Non-RMW ops: | |
| atomic_read(), atomic_set() | |
| atomic_read_acquire(), atomic_set_release() | |
| RMW atomic operations: | |
| Arithmetic: | |
| atomic_{add,sub,inc,dec}() | |
| atomic_{add,sub,inc,dec}_return{,_relaxed,_acquire,_release}() | |
| atomic_fetch_{add,sub,inc,dec}{,_relaxed,_acquire,_release}() | |
| Bitwise: | |
| atomic_{and,or,xor,andnot}() | |
| atomic_fetch_{and,or,xor,andnot}{,_relaxed,_acquire,_release}() | |
| Swap: | |
| atomic_xchg{,_relaxed,_acquire,_release}() | |
| atomic_cmpxchg{,_relaxed,_acquire,_release}() | |
| atomic_try_cmpxchg{,_relaxed,_acquire,_release}() | |
| Reference count (but please see refcount_t): | |
| atomic_add_unless(), atomic_inc_not_zero() | |
| atomic_sub_and_test(), atomic_dec_and_test() | |
| Misc: | |
| atomic_inc_and_test(), atomic_add_negative() | |
| atomic_dec_unless_positive(), atomic_inc_unless_negative() | |
| Barriers: | |
| smp_mb__{before,after}_atomic() | |
| TYPES (signed vs unsigned) | |
| ----- | |
| While atomic_t, atomic_long_t and atomic64_t use int, long and s64 | |
| respectively (for hysterical raisins), the kernel uses -fno-strict-overflow | |
| (which implies -fwrapv) and defines signed overflow to behave like | |
| 2s-complement. | |
| Therefore, an explicitly unsigned variant of the atomic ops is strictly | |
| unnecessary and we can simply cast, there is no UB. | |
| There was a bug in UBSAN prior to GCC-8 that would generate UB warnings for | |
| signed types. | |
| With this we also conform to the C/C++ _Atomic behaviour and things like | |
| P1236R1. | |
| SEMANTICS | |
| --------- | |
| Non-RMW ops: | |
| The non-RMW ops are (typically) regular LOADs and STOREs and are canonically | |
| implemented using READ_ONCE(), WRITE_ONCE(), smp_load_acquire() and | |
| smp_store_release() respectively. Therefore, if you find yourself only using | |
| the Non-RMW operations of atomic_t, you do not in fact need atomic_t at all | |
| and are doing it wrong. | |
| A note for the implementation of atomic_set{}() is that it must not break the | |
| atomicity of the RMW ops. That is: | |
| C Atomic-RMW-ops-are-atomic-WRT-atomic_set | |
| { | |
| atomic_t v = ATOMIC_INIT(1); | |
| } | |
| P0(atomic_t *v) | |
| { | |
| (void)atomic_add_unless(v, 1, 0); | |
| } | |
| P1(atomic_t *v) | |
| { | |
| atomic_set(v, 0); | |
| } | |
| exists | |
| (v=2) | |
| In this case we would expect the atomic_set() from CPU1 to either happen | |
| before the atomic_add_unless(), in which case that latter one would no-op, or | |
| _after_ in which case we'd overwrite its result. In no case is "2" a valid | |
| outcome. | |
| This is typically true on 'normal' platforms, where a regular competing STORE | |
| will invalidate a LL/SC or fail a CMPXCHG. | |
| The obvious case where this is not so is when we need to implement atomic ops | |
| with a lock: | |
| CPU0 CPU1 | |
| atomic_add_unless(v, 1, 0); | |
| lock(); | |
| ret = READ_ONCE(v->counter); // == 1 | |
| atomic_set(v, 0); | |
| if (ret != u) WRITE_ONCE(v->counter, 0); | |
| WRITE_ONCE(v->counter, ret + 1); | |
| unlock(); | |
| the typical solution is to then implement atomic_set{}() with atomic_xchg(). | |
| RMW ops: | |
| These come in various forms: | |
| - plain operations without return value: atomic_{}() | |
| - operations which return the modified value: atomic_{}_return() | |
| these are limited to the arithmetic operations because those are | |
| reversible. Bitops are irreversible and therefore the modified value | |
| is of dubious utility. | |
| - operations which return the original value: atomic_fetch_{}() | |
| - swap operations: xchg(), cmpxchg() and try_cmpxchg() | |
| - misc; the special purpose operations that are commonly used and would, | |
| given the interface, normally be implemented using (try_)cmpxchg loops but | |
| are time critical and can, (typically) on LL/SC architectures, be more | |
| efficiently implemented. | |
| All these operations are SMP atomic; that is, the operations (for a single | |
| atomic variable) can be fully ordered and no intermediate state is lost or | |
| visible. | |
| ORDERING (go read memory-barriers.txt first) | |
| -------- | |
| The rule of thumb: | |
| - non-RMW operations are unordered; | |
| - RMW operations that have no return value are unordered; | |
| - RMW operations that have a return value are fully ordered; | |
| - RMW operations that are conditional are unordered on FAILURE, | |
| otherwise the above rules apply. | |
| Except of course when an operation has an explicit ordering like: | |
| {}_relaxed: unordered | |
| {}_acquire: the R of the RMW (or atomic_read) is an ACQUIRE | |
| {}_release: the W of the RMW (or atomic_set) is a RELEASE | |
| Where 'unordered' is against other memory locations. Address dependencies are | |
| not defeated. | |
| Fully ordered primitives are ordered against everything prior and everything | |
| subsequent. Therefore a fully ordered primitive is like having an smp_mb() | |
| before and an smp_mb() after the primitive. | |
| The barriers: | |
| smp_mb__{before,after}_atomic() | |
| only apply to the RMW atomic ops and can be used to augment/upgrade the | |
| ordering inherent to the op. These barriers act almost like a full smp_mb(): | |
| smp_mb__before_atomic() orders all earlier accesses against the RMW op | |
| itself and all accesses following it, and smp_mb__after_atomic() orders all | |
| later accesses against the RMW op and all accesses preceding it. However, | |
| accesses between the smp_mb__{before,after}_atomic() and the RMW op are not | |
| ordered, so it is advisable to place the barrier right next to the RMW atomic | |
| op whenever possible. | |
| These helper barriers exist because architectures have varying implicit | |
| ordering on their SMP atomic primitives. For example our TSO architectures | |
| provide full ordered atomics and these barriers are no-ops. | |
| NOTE: when the atomic RmW ops are fully ordered, they should also imply a | |
| compiler barrier. | |
| Thus: | |
| atomic_fetch_add(); | |
| is equivalent to: | |
| smp_mb__before_atomic(); | |
| atomic_fetch_add_relaxed(); | |
| smp_mb__after_atomic(); | |
| However the atomic_fetch_add() might be implemented more efficiently. | |
| Further, while something like: | |
| smp_mb__before_atomic(); | |
| atomic_dec(&X); | |
| is a 'typical' RELEASE pattern, the barrier is strictly stronger than | |
| a RELEASE because it orders preceding instructions against both the read | |
| and write parts of the atomic_dec(), and against all following instructions | |
| as well. Similarly, something like: | |
| atomic_inc(&X); | |
| smp_mb__after_atomic(); | |
| is an ACQUIRE pattern (though very much not typical), but again the barrier is | |
| strictly stronger than ACQUIRE. As illustrated: | |
| C Atomic-RMW+mb__after_atomic-is-stronger-than-acquire | |
| { | |
| } | |
| P0(int *x, atomic_t *y) | |
| { | |
| r0 = READ_ONCE(*x); | |
| smp_rmb(); | |
| r1 = atomic_read(y); | |
| } | |
| P1(int *x, atomic_t *y) | |
| { | |
| atomic_inc(y); | |
| smp_mb__after_atomic(); | |
| WRITE_ONCE(*x, 1); | |
| } | |
| exists | |
| (0:r0=1 /\ 0:r1=0) | |
| This should not happen; but a hypothetical atomic_inc_acquire() -- | |
| (void)atomic_fetch_inc_acquire() for instance -- would allow the outcome, | |
| because it would not order the W part of the RMW against the following | |
| WRITE_ONCE. Thus: | |
| P0 P1 | |
| t = LL.acq *y (0) | |
| t++; | |
| *x = 1; | |
| r0 = *x (1) | |
| RMB | |
| r1 = *y (0) | |
| SC *y, t; | |
| is allowed. | |
| CMPXCHG vs TRY_CMPXCHG | |
| ---------------------- | |
| int atomic_cmpxchg(atomic_t *ptr, int old, int new); | |
| bool atomic_try_cmpxchg(atomic_t *ptr, int *oldp, int new); | |
| Both provide the same functionality, but try_cmpxchg() can lead to more | |
| compact code. The functions relate like: | |
| bool atomic_try_cmpxchg(atomic_t *ptr, int *oldp, int new) | |
| { | |
| int ret, old = *oldp; | |
| ret = atomic_cmpxchg(ptr, old, new); | |
| if (ret != old) | |
| *oldp = ret; | |
| return ret == old; | |
| } | |
| and: | |
| int atomic_cmpxchg(atomic_t *ptr, int old, int new) | |
| { | |
| (void)atomic_try_cmpxchg(ptr, &old, new); | |
| return old; | |
| } | |
| Usage: | |
| old = atomic_read(&v); old = atomic_read(&v); | |
| for (;;) { do { | |
| new = func(old); new = func(old); | |
| tmp = atomic_cmpxchg(&v, old, new); } while (!atomic_try_cmpxchg(&v, &old, new)); | |
| if (tmp == old) | |
| break; | |
| old = tmp; | |
| } | |
| NB. try_cmpxchg() also generates better code on some platforms (notably x86) | |
| where the function more closely matches the hardware instruction. | |
| FORWARD PROGRESS | |
| ---------------- | |
| In general strong forward progress is expected of all unconditional atomic | |
| operations -- those in the Arithmetic and Bitwise classes and xchg(). However | |
| a fair amount of code also requires forward progress from the conditional | |
| atomic operations. | |
| Specifically 'simple' cmpxchg() loops are expected to not starve one another | |
| indefinitely. However, this is not evident on LL/SC architectures, because | |
| while an LL/SC architecure 'can/should/must' provide forward progress | |
| guarantees between competing LL/SC sections, such a guarantee does not | |
| transfer to cmpxchg() implemented using LL/SC. Consider: | |
| old = atomic_read(&v); | |
| do { | |
| new = func(old); | |
| } while (!atomic_try_cmpxchg(&v, &old, new)); | |
| which on LL/SC becomes something like: | |
| old = atomic_read(&v); | |
| do { | |
| new = func(old); | |
| } while (!({ | |
| volatile asm ("1: LL %[oldval], %[v]\n" | |
| " CMP %[oldval], %[old]\n" | |
| " BNE 2f\n" | |
| " SC %[new], %[v]\n" | |
| " BNE 1b\n" | |
| "2:\n" | |
| : [oldval] "=&r" (oldval), [v] "m" (v) | |
| : [old] "r" (old), [new] "r" (new) | |
| : "memory"); | |
| success = (oldval == old); | |
| if (!success) | |
| old = oldval; | |
| success; })); | |
| However, even the forward branch from the failed compare can cause the LL/SC | |
| to fail on some architectures, let alone whatever the compiler makes of the C | |
| loop body. As a result there is no guarantee what so ever the cacheline | |
| containing @v will stay on the local CPU and progress is made. | |
| Even native CAS architectures can fail to provide forward progress for their | |
| primitive (See Sparc64 for an example). | |
| Such implementations are strongly encouraged to add exponential backoff loops | |
| to a failed CAS in order to ensure some progress. Affected architectures are | |
| also strongly encouraged to inspect/audit the atomic fallbacks, refcount_t and | |
| their locking primitives. |
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| Android Goldfish Audio | |
| Android goldfish audio device generated by android emulator. | |
| Required properties: | |
| - compatible : should contain "google,goldfish-audio" to match emulator | |
| - reg : <registers mapping> | |
| - interrupts : <interrupt mapping> | |
| Example: | |
| goldfish_audio@9030000 { | |
| compatible = "google,goldfish-audio"; | |
| reg = <0x9030000 0x100>; | |
| interrupts = <0x4>; | |
| }; |
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| * AUO in-cell touchscreen controller using Pixcir sensors | |
| Required properties: | |
| - compatible: must be "auo,auo_pixcir_ts" | |
| - reg: I2C address of the chip | |
| - interrupts: interrupt to which the chip is connected | |
| - gpios: gpios the chip is connected to | |
| first one is the interrupt gpio and second one the reset gpio | |
| - x-size: horizontal resolution of touchscreen | |
| - y-size: vertical resolution of touchscreen | |
| Example: | |
| i2c@00000000 { | |
| /* ... */ | |
| auo_pixcir_ts@5c { | |
| compatible = "auo,auo_pixcir_ts"; | |
| reg = <0x5c>; | |
| interrupts = <2 0>; | |
| gpios = <&gpf 2 0 2>, /* INT */ | |
| <&gpf 5 1 0>; /* RST */ | |
| x-size = <800>; | |
| y-size = <600>; | |
| }; | |
| /* ... */ | |
| }; |
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| Binding for Texas Instruments autoidle clock. | |
| Binding status: Unstable - ABI compatibility may be broken in the future | |
| This binding uses the common clock binding[1]. It assumes a register mapped | |
| clock which can be put to idle automatically by hardware based on the usage | |
| and a configuration bit setting. Autoidle clock is never an individual | |
| clock, it is always a derivative of some basic clock like a gate, divider, | |
| or fixed-factor. | |
| [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| Required properties: | |
| - reg : offset for the register controlling the autoidle | |
| - ti,autoidle-shift : bit shift of the autoidle enable bit | |
| - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0 | |
| Examples: | |
| dpll_core_m4_ck: dpll_core_m4_ck { | |
| #clock-cells = <0>; | |
| compatible = "ti,divider-clock"; | |
| clocks = <&dpll_core_x2_ck>; | |
| ti,max-div = <31>; | |
| ti,autoidle-shift = <8>; | |
| reg = <0x2d38>; | |
| ti,index-starts-at-one; | |
| ti,invert-autoidle-bit; | |
| }; | |
| dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck { | |
| #clock-cells = <0>; | |
| compatible = "ti,fixed-factor-clock"; | |
| clocks = <&dpll_usb_ck>; | |
| ti,clock-div = <1>; | |
| ti,autoidle-shift = <8>; | |
| reg = <0x01b4>; | |
| ti,clock-mult = <1>; | |
| ti,invert-autoidle-bit; | |
| }; |
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| Devicetree bindings for the Axentia TSE-850 audio complex | |
| Required properties: | |
| - compatible: "axentia,tse850-pcm5142" | |
| - axentia,cpu-dai: The phandle of the cpu dai. | |
| - axentia,audio-codec: The phandle of the PCM5142 codec. | |
| - axentia,add-gpios: gpio specifier that controls the mixer. | |
| - axentia,loop1-gpios: gpio specifier that controls loop relays on channel 1. | |
| - axentia,loop2-gpios: gpio specifier that controls loop relays on channel 2. | |
| - axentia,ana-supply: Regulator that supplies the output amplifier. Must | |
| support voltages in the 2V - 20V range, in 1V steps. | |
| The schematics explaining the gpios are as follows: | |
| loop1 relays | |
| IN1 +---o +------------+ o---+ OUT1 | |
| \ / | |
| + + | |
| | / | | |
| +--o +--. | | |
| | add | | | |
| | V | | |
| | .---. | | |
| DAC +----------->|Sum|---+ | |
| | '---' | | |
| | | | |
| + + | |
| IN2 +---o--+------------+--o---+ OUT2 | |
| loop2 relays | |
| The 'loop1' gpio pin controlls two relays, which are either in loop position, | |
| meaning that input and output are directly connected, or they are in mixer | |
| position, meaning that the signal is passed through the 'Sum' mixer. Similarly | |
| for 'loop2'. | |
| In the above, the 'loop1' relays are inactive, thus feeding IN1 to the mixer | |
| (if 'add' is active) and feeding the mixer output to OUT1. The 'loop2' relays | |
| are active, short-cutting the TSE-850 from channel 2. IN1, IN2, OUT1 and OUT2 | |
| are TSE-850 connectors and DAC is the PCB name of the (filtered) output from | |
| the PCM5142 codec. | |
| Example: | |
| &ssc0 { | |
| #sound-dai-cells = <0>; | |
| }; | |
| &i2c { | |
| codec: pcm5142@4c { | |
| compatible = "ti,pcm5142"; | |
| reg = <0x4c>; | |
| AVDD-supply = <®_3v3>; | |
| DVDD-supply = <®_3v3>; | |
| CPVDD-supply = <®_3v3>; | |
| clocks = <&sck>; | |
| pll-in = <3>; | |
| pll-out = <6>; | |
| }; | |
| }; | |
| ana: ana-reg { | |
| compatible = "pwm-regulator"; | |
| regulator-name = "ANA"; | |
| pwms = <&pwm0 2 1000 PWM_POLARITY_INVERTED>; | |
| pwm-dutycycle-unit = <1000>; | |
| pwm-dutycycle-range = <100 1000>; | |
| regulator-min-microvolt = <2000000>; | |
| regulator-max-microvolt = <20000000>; | |
| regulator-ramp-delay = <1000>; | |
| }; | |
| sound { | |
| compatible = "axentia,tse850-pcm5142"; | |
| axentia,cpu-dai = <&ssc0>; | |
| axentia,audio-codec = <&codec>; | |
| axentia,add-gpios = <&pioA 8 GPIO_ACTIVE_LOW>; | |
| axentia,loop1-gpios = <&pioA 10 GPIO_ACTIVE_LOW>; | |
| axentia,loop2-gpios = <&pioA 11 GPIO_ACTIVE_LOW>; | |
| axentia,ana-supply = <&ana>; | |
| }; |
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| * Axis ARTPEC-6 PCIe interface | |
| This PCIe host controller is based on the Synopsys DesignWare PCIe IP | |
| and thus inherits all the common properties defined in snps,dw-pcie.yaml. | |
| Required properties: | |
| - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; | |
| "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode; | |
| "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode; | |
| "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode; | |
| - reg: base addresses and lengths of the PCIe controller (DBI), | |
| the PHY controller, and configuration address space. | |
| - reg-names: Must include the following entries: | |
| - "dbi" | |
| - "phy" | |
| - "config" | |
| - interrupts: A list of interrupt outputs of the controller. Must contain an | |
| entry for each entry in the interrupt-names property. | |
| - interrupt-names: Must include the following entries: | |
| - "msi": The interrupt that is asserted when an MSI is received | |
| - axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller, | |
| used to enable and control the Synopsys IP. | |
| Example: | |
| pcie@f8050000 { | |
| compatible = "axis,artpec6-pcie", "snps,dw-pcie"; | |
| reg = <0xf8050000 0x2000 | |
| 0xf8040000 0x1000 | |
| 0xc0000000 0x2000>; | |
| reg-names = "dbi", "phy", "config"; | |
| #address-cells = <3>; | |
| #size-cells = <2>; | |
| device_type = "pci"; | |
| /* downstream I/O */ | |
| ranges = <0x81000000 0 0 0xc0002000 0 0x00010000 | |
| /* non-prefetchable memory */ | |
| 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>; | |
| num-lanes = <2>; | |
| bus-range = <0x00 0xff>; | |
| interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-names = "msi"; | |
| #interrupt-cells = <1>; | |
| interrupt-map-mask = <0 0 0 0x7>; | |
| interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, | |
| <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, | |
| <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, | |
| <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; | |
| axis,syscon-pcie = <&syscon>; | |
| }; |
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| Axis ARTPEC-6 Pin Controller | |
| Required properties: | |
| - compatible: "axis,artpec6-pinctrl". | |
| - reg: Should contain the register physical address and length for the pin | |
| controller. | |
| A pinctrl node should contain at least one subnode representing the pinctrl | |
| groups available on the machine. Each subnode will list the mux function | |
| required and what pin group it will use. Each subnode will also configure the | |
| drive strength and bias pullup of the pin group. If either of these options is | |
| not set, its actual value will be unspecified. | |
| Required subnode-properties: | |
| - function: Function to mux. | |
| - groups: Name of the pin group to use for the function above. | |
| Available functions and groups (function: group0, group1...): | |
| gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0, | |
| i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0, | |
| spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2, | |
| uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2, | |
| uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1, | |
| uart5nocts | |
| cpuclkout: cpuclkoutgrp0 | |
| udlclkout: udlclkoutgrp0 | |
| i2c1: i2c1grp0 | |
| i2c2: i2c2grp0 | |
| i2c3: i2c3grp0 | |
| i2s0: i2s0grp0 | |
| i2s1: i2s1grp0 | |
| i2srefclk: i2srefclkgrp0 | |
| spi0: spi0grp0 | |
| spi1: spi1grp0 | |
| pciedebug: pciedebuggrp0 | |
| uart0: uart0grp0, uart0grp1, uart0grp2 | |
| uart1: uart1grp0, uart1grp1 | |
| uart2: uart2grp0, uart2grp1, uart2grp2 | |
| uart3: uart3grp0 | |
| uart4: uart4grp0, uart4grp1 | |
| uart5: uart5grp0, uart5grp1, uart5nocts | |
| nand: nandgrp0 | |
| sdio0: sdio0grp0 | |
| sdio1: sdio1grp0 | |
| ethernet: ethernetgrp0 | |
| Optional subnode-properties (see pinctrl-bindings.txt): | |
| - drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3. | |
| - bias-pull-up | |
| - bias-disable | |
| Examples: | |
| pinctrl@f801d000 { | |
| compatible = "axis,artpec6-pinctrl"; | |
| reg = <0xf801d000 0x400>; | |
| pinctrl_uart0: uart0grp { | |
| function = "uart0"; | |
| groups = "uart0grp0"; | |
| drive-strength = <4>; | |
| bias-pull-up; | |
| }; | |
| pinctrl_uart3: uart3grp { | |
| function = "uart3"; | |
| groups = "uart3grp0"; | |
| }; | |
| }; | |
| uart0: uart@f8036000 { | |
| compatible = "arm,pl011", "arm,primecell"; | |
| reg = <0xf8036000 0x1000>; | |
| interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&pll2div24>, <&apb_pclk>; | |
| clock-names = "uart_clk", "apb_pclk"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_uart0>; | |
| }; | |
| uart3: uart@f8039000 { | |
| compatible = "arm,pl011", "arm,primecell"; | |
| reg = <0xf8039000 0x1000>; | |
| interrupts = <0 128 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&pll2div24>, <&apb_pclk>; | |
| clock-names = "uart_clk", "apb_pclk"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&pinctrl_uart3>; | |
| }; |
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| Axis Communications AB | |
| ARTPEC series SoC Device Tree Bindings | |
| ARTPEC-6 ARM SoC | |
| ================ | |
| Required root node properties: | |
| - compatible = "axis,artpec6"; | |
| ARTPEC-6 System Controller | |
| -------------------------- | |
| The ARTPEC-6 has a system controller with mixed functions controlling DMA, PCIe | |
| and resets. | |
| Required properties: | |
| - compatible: "axis,artpec6-syscon", "syscon" | |
| - reg: Address and length of the register bank. | |
| Example: | |
| syscon { | |
| compatible = "axis,artpec6-syscon", "syscon"; | |
| reg = <0xf8000000 0x48>; | |
| }; | |
| ARTPEC-6 Development board: | |
| --------------------------- | |
| Required root node properties: | |
| - compatible = "axis,artpec6-dev-board", "axis,artpec6"; |
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| Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings | |
| --------------------------------------------------------------------------- | |
| SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon | |
| Required root node properties: | |
| - compatible = "snps,axs101", "snps,arc-sdp"; |
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| Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings | |
| --------------------------------------------------------------------------- | |
| SDP Main Board with an AXC003 FPGA Card which can contain various flavours of | |
| HS38x cores. | |
| Required root node properties: | |
| - compatible = "snps,axs103", "snps,arc-sdp"; |
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| Binding for the AXS10X I2S PLL clock | |
| This binding uses the common clock binding[1]. | |
| [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| Required properties: | |
| - compatible: shall be "snps,axs10x-i2s-pll-clock" | |
| - reg : address and length of the I2S PLL register set. | |
| - clocks: shall be the input parent clock phandle for the PLL. | |
| - #clock-cells: from common clock binding; Should always be set to 0. | |
| Example: | |
| pll_clock: pll_clock { | |
| compatible = "fixed-clock"; | |
| clock-frequency = <27000000>; | |
| #clock-cells = <0>; | |
| }; | |
| i2s_clock@100a0 { | |
| compatible = "snps,axs10x-i2s-pll-clock"; | |
| reg = <0x100a0 0x10>; | |
| clocks = <&pll_clock>; | |
| #clock-cells = <0>; | |
| }; |
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| Axxia Restart Driver | |
| This driver can do reset of the Axxia SoC. It uses the registers in the syscon | |
| block to initiate a chip reset. | |
| Required Properties: | |
| -compatible: "lsi,axm55xx-reset" | |
| -syscon: phandle to the syscon node. | |
| Example: | |
| syscon: syscon@2010030000 { | |
| compatible = "lsi,axxia-syscon", "syscon"; | |
| reg = <0x20 0x10030000 0 0x2000>; | |
| }; | |
| reset: reset@2010031000 { | |
| compatible = "lsi,axm55xx-reset"; | |
| syscon = <&syscon>; | |
| }; |
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| Android Goldfish Battery | |
| Android goldfish battery device generated by android emulator. | |
| Required properties: | |
| - compatible : should contain "google,goldfish-battery" to match emulator | |
| - reg : <registers mapping> | |
| - interrupts : <interrupt mapping> | |
| Example: | |
| goldfish_battery@9020000 { | |
| compatible = "google,goldfish-battery"; | |
| reg = <0x9020000 0x1000>; | |
| interrupts = <0x3>; | |
| }; |
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| * Pin-controller driver for the Marvell Berlin SoCs | |
| Pin control registers are part of both chip controller and system | |
| controller register sets. Pin controller nodes should be a sub-node of | |
| either the chip controller or system controller node. The pins | |
| controlled are organized in groups, so no actual pin information is | |
| needed. | |
| A pin-controller node should contain subnodes representing the pin group | |
| configurations, one per function. Each subnode has the group name and | |
| the muxing function used. | |
| Be aware the Marvell Berlin datasheets use the keyword 'mode' for what | |
| is called a 'function' in the pin-controller subsystem. | |
| Required properties: | |
| - compatible: should be one of: | |
| "marvell,berlin2-soc-pinctrl", | |
| "marvell,berlin2-system-pinctrl", | |
| "marvell,berlin2cd-soc-pinctrl", | |
| "marvell,berlin2cd-system-pinctrl", | |
| "marvell,berlin2q-soc-pinctrl", | |
| "marvell,berlin2q-system-pinctrl", | |
| "marvell,berlin4ct-avio-pinctrl", | |
| "marvell,berlin4ct-soc-pinctrl", | |
| "marvell,berlin4ct-system-pinctrl", | |
| "syna,as370-soc-pinctrl" | |
| Required subnode-properties: | |
| - groups: a list of strings describing the group names. | |
| - function: a string describing the function used to mux the groups. | |
| Example: | |
| sys_pinctrl: pin-controller { | |
| compatible = "marvell,berlin2q-system-pinctrl"; | |
| uart0_pmux: uart0-pmux { | |
| groups = "GSM12"; | |
| function = "uart0"; | |
| }; | |
| }; | |
| &uart0 { | |
| pinctrl-0 = <&uart0_pmux>; | |
| pinctrl-names = "default"; | |
| }; |
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| Marvell Berlin reset controller | |
| =============================== | |
| Please also refer to reset.txt in this directory for common reset | |
| controller binding usage. | |
| The reset controller node must be a sub-node of the chip controller | |
| node on Berlin SoCs. | |
| Required properties: | |
| - compatible: should be "marvell,berlin2-reset" | |
| - #reset-cells: must be set to 2 | |
| Example: | |
| chip_rst: reset { | |
| compatible = "marvell,berlin2-reset"; | |
| #reset-cells = <2>; | |
| }; | |
| &usb_phy0 { | |
| resets = <&chip_rst 0x104 12>; | |
| }; |
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| Berlin SATA PHY | |
| --------------- | |
| Required properties: | |
| - compatible: should be one of | |
| "marvell,berlin2-sata-phy" | |
| "marvell,berlin2q-sata-phy" | |
| - address-cells: should be 1 | |
| - size-cells: should be 0 | |
| - phy-cells: from the generic PHY bindings, must be 1 | |
| - reg: address and length of the register | |
| - clocks: reference to the clock entry | |
| Sub-nodes: | |
| Each PHY should be represented as a sub-node. | |
| Sub-nodes required properties: | |
| - reg: the PHY number | |
| Example: | |
| sata_phy: phy@f7e900a0 { | |
| compatible = "marvell,berlin2q-sata-phy"; | |
| reg = <0xf7e900a0 0x200>; | |
| clocks = <&chip CLKID_SATA>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| #phy-cells = <1>; | |
| sata-phy@0 { | |
| reg = <0>; | |
| }; | |
| sata-phy@1 { | |
| reg = <1>; | |
| }; | |
| }; |
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| * Marvell Berlin USB PHY | |
| Required properties: | |
| - compatible: "marvell,berlin2-usb-phy" or "marvell,berlin2cd-usb-phy" | |
| - reg: base address and length of the registers | |
| - #phys-cells: should be 0 | |
| - resets: reference to the reset controller | |
| Example: | |
| usb-phy@f774000 { | |
| compatible = "marvell,berlin2-usb-phy"; | |
| reg = <0xf774000 0x128>; | |
| #phy-cells = <0>; | |
| resets = <&chip 0x104 14>; | |
| }; |
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| KEYMILE bfticu Chassis Management FPGA | |
| The bfticu is a multifunction device that manages the whole chassis. | |
| Its main functionality is to collect IRQs from the whole chassis and signals | |
| them to a single controller. | |
| Required properties: | |
| - compatible: "keymile,bfticu" | |
| - interrupt-controller: the bfticu FPGA is an interrupt controller | |
| - interrupts: the main IRQ line to signal the collected IRQs | |
| - #interrupt-cells : is 2 and their usage is compliant to the 2 cells variant | |
| of Documentation/devicetree/bindings/interrupt-controller/interrupts.txt | |
| - reg: access on the parent local bus (chip select, offset in chip select, size) | |
| Example: | |
| chassis-mgmt@3,0 { | |
| compatible = "keymile,bfticu"; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| reg = <3 0 0x100>; | |
| interrupt-parent = <&mpic>; | |
| interrupts = <6 1 0 0>; | |
| }; |
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| Bitmain BM1880 Pin Controller | |
| This binding describes the pin controller found in the BM1880 SoC. | |
| Required Properties: | |
| - compatible: Should be "bitmain,bm1880-pinctrl" | |
| - reg: Offset and length of pinctrl space in SCTRL. | |
| Please refer to pinctrl-bindings.txt in this directory for details of the | |
| common pinctrl bindings used by client devices, including the meaning of the | |
| phrase "pin configuration node". | |
| The pin configuration nodes act as a container for an arbitrary number of | |
| subnodes. Each of these subnodes represents some desired configuration for a | |
| pin, a group, or a list of pins or groups. This configuration for BM1880 SoC | |
| includes pinmux and various pin configuration parameters, such as pull-up, | |
| slew rate etc... | |
| Each configuration node can consist of multiple nodes describing the pinmux | |
| options. The name of each subnode is not important; all subnodes should be | |
| enumerated and processed purely based on their content. | |
| The following generic properties as defined in pinctrl-bindings.txt are valid | |
| to specify in a pinmux subnode: | |
| Required Properties: | |
| - pins: An array of strings, each string containing the name of a pin. | |
| Valid values for pins are: | |
| MIO0 - MIO111 | |
| - groups: An array of strings, each string containing the name of a pin | |
| group. Valid values for groups are: | |
| nand_grp, spi_grp, emmc_grp, sdio_grp, eth0_grp, pwm0_grp, | |
| pwm1_grp, pwm2_grp, pwm3_grp, pwm4_grp, pwm5_grp, pwm6_grp, | |
| pwm7_grp, pwm8_grp, pwm9_grp, pwm10_grp, pwm11_grp, pwm12_grp, | |
| pwm13_grp, pwm14_grp, pwm15_grp, pwm16_grp, pwm17_grp, | |
| pwm18_grp, pwm19_grp, pwm20_grp, pwm21_grp, pwm22_grp, | |
| pwm23_grp, pwm24_grp, pwm25_grp, pwm26_grp, pwm27_grp, | |
| pwm28_grp, pwm29_grp, pwm30_grp, pwm31_grp, pwm32_grp, | |
| pwm33_grp, pwm34_grp, pwm35_grp, pwm36_grp, i2c0_grp, | |
| i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, uart0_grp, uart1_grp, | |
| uart2_grp, uart3_grp, uart4_grp, uart5_grp, uart6_grp, | |
| uart7_grp, uart8_grp, uart9_grp, uart10_grp, uart11_grp, | |
| uart12_grp, uart13_grp, uart14_grp, uart15_grp, gpio0_grp, | |
| gpio1_grp, gpio2_grp, gpio3_grp, gpio4_grp, gpio5_grp, | |
| gpio6_grp, gpio7_grp, gpio8_grp, gpio9_grp, gpio10_grp, | |
| gpio11_grp, gpio12_grp, gpio13_grp, gpio14_grp, gpio15_grp, | |
| gpio16_grp, gpio17_grp, gpio18_grp, gpio19_grp, gpio20_grp, | |
| gpio21_grp, gpio22_grp, gpio23_grp, gpio24_grp, gpio25_grp, | |
| gpio26_grp, gpio27_grp, gpio28_grp, gpio29_grp, gpio30_grp, | |
| gpio31_grp, gpio32_grp, gpio33_grp, gpio34_grp, gpio35_grp, | |
| gpio36_grp, gpio37_grp, gpio38_grp, gpio39_grp, gpio40_grp, | |
| gpio41_grp, gpio42_grp, gpio43_grp, gpio44_grp, gpio45_grp, | |
| gpio46_grp, gpio47_grp, gpio48_grp, gpio49_grp, gpio50_grp, | |
| gpio51_grp, gpio52_grp, gpio53_grp, gpio54_grp, gpio55_grp, | |
| gpio56_grp, gpio57_grp, gpio58_grp, gpio59_grp, gpio60_grp, | |
| gpio61_grp, gpio62_grp, gpio63_grp, gpio64_grp, gpio65_grp, | |
| gpio66_grp, gpio67_grp, eth1_grp, i2s0_grp, i2s0_mclkin_grp, | |
| i2s1_grp, i2s1_mclkin_grp, spi0_grp | |
| - function: An array of strings, each string containing the name of the | |
| pinmux functions. The following are the list of pinmux | |
| functions available: | |
| nand, spi, emmc, sdio, eth0, pwm0, pwm1, pwm2, pwm3, pwm4, | |
| pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, pwm12, pwm13, | |
| pwm14, pwm15, pwm16, pwm17, pwm18, pwm19, pwm20, pwm21, pwm22, | |
| pwm23, pwm24, pwm25, pwm26, pwm27, pwm28, pwm29, pwm30, pwm31, | |
| pwm32, pwm33, pwm34, pwm35, pwm36, i2c0, i2c1, i2c2, i2c3, | |
| i2c4, uart0, uart1, uart2, uart3, uart4, uart5, uart6, uart7, | |
| uart8, uart9, uart10, uart11, uart12, uart13, uart14, uart15, | |
| gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, | |
| gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, gpio16, | |
| gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23, | |
| gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, | |
| gpio31, gpio32, gpio33, gpio34, gpio35, gpio36, gpio37, | |
| gpio38, gpio39, gpio40, gpio41, gpio42, gpio43, gpio44, | |
| gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, gpio51, | |
| gpio52, gpio53, gpio54, gpio55, gpio56, gpio57, gpio58, | |
| gpio59, gpio60, gpio61, gpio62, gpio63, gpio64, gpio65, | |
| gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin, | |
| spi0 | |
| Optional Properties: | |
| - bias-disable: No arguments. Disable pin bias. | |
| - bias-pull-down: No arguments. The specified pins should be configured as | |
| pull down. | |
| - bias-pull-up: No arguments. The specified pins should be configured as | |
| pull up. | |
| - input-schmitt-enable: No arguments: Enable schmitt trigger for the specified | |
| pins | |
| - input-schmitt-disable: No arguments: Disable schmitt trigger for the specified | |
| pins | |
| - slew-rate: Integer. Sets slew rate for the specified pins. | |
| Valid values are: | |
| <0> - Slow | |
| <1> - Fast | |
| - drive-strength: Integer. Selects the drive strength for the specified | |
| pins in mA. | |
| Valid values are: | |
| <4> | |
| <8> | |
| <12> | |
| <16> | |
| <20> | |
| <24> | |
| <28> | |
| <32> | |
| Example: | |
| pinctrl: pinctrl@400 { | |
| compatible = "bitmain,bm1880-pinctrl"; | |
| reg = <0x400 0x120>; | |
| pinctrl_uart0_default: uart0-default { | |
| pinmux { | |
| groups = "uart0_grp"; | |
| function = "uart0"; | |
| }; | |
| }; | |
| }; |
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| Bitmain BM1880 SoC Reset Controller | |
| =================================== | |
| Please also refer to reset.txt in this directory for common reset | |
| controller binding usage. | |
| Required properties: | |
| - compatible: Should be "bitmain,bm1880-reset" | |
| - reg: Offset and length of reset controller space in SCTRL. | |
| - #reset-cells: Must be 1. | |
| Example: | |
| rst: reset-controller@c00 { | |
| compatible = "bitmain,bm1880-reset"; | |
| reg = <0xc00 0x8>; | |
| #reset-cells = <1>; | |
| }; |
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| * Mellanox Bluefield SoC specific extensions to the Synopsys Designware | |
| Mobile Storage Host Controller | |
| Read synopsys-dw-mshc.txt for more details | |
| The Synopsys designware mobile storage host controller is used to interface | |
| a SoC with storage medium such as eMMC or SD/MMC cards. This file documents | |
| differences between the core Synopsys dw mshc controller properties described | |
| by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC | |
| specific extensions to the Synopsys Designware Mobile Storage Host Controller. | |
| Required Properties: | |
| * compatible: should be one of the following. | |
| - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC | |
| specific extensions. | |
| Example: | |
| /* Mellanox Bluefield SoC MMC */ | |
| mmc@6008000 { | |
| compatible = "mellanox,bluefield-dw-mshc"; | |
| reg = <0x6008000 0x400>; | |
| interrupts = <32>; | |
| fifo-depth = <0x100>; | |
| clock-frequency = <24000000>; | |
| bus-width = <8>; | |
| cap-mmc-highspeed; | |
| }; |
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| The following properties are common to the Bluetooth controllers: | |
| - local-bd-address: array of 6 bytes, specifies the BD address that was | |
| uniquely assigned to the Bluetooth device, formatted with least significant | |
| byte first (little-endian). |
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| QorIQ DPAA Buffer Manager Portals Device Tree Binding | |
| Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. | |
| CONTENTS | |
| - BMan Portal | |
| - Example | |
| BMan Portal Node | |
| Portals are memory mapped interfaces to BMan that allow low-latency, lock-less | |
| interaction by software running on processor cores, accelerators and network | |
| interfaces with the BMan | |
| PROPERTIES | |
| - compatible | |
| Usage: Required | |
| Value type: <stringlist> | |
| Definition: Must include "fsl,bman-portal-<hardware revision>" | |
| May include "fsl,<SoC>-bman-portal" or "fsl,bman-portal" | |
| - reg | |
| Usage: Required | |
| Value type: <prop-encoded-array> | |
| Definition: Two regions. The first is the cache-enabled region of | |
| the portal. The second is the cache-inhibited region of | |
| the portal | |
| - interrupts | |
| Usage: Required | |
| Value type: <prop-encoded-array> | |
| Definition: Standard property | |
| EXAMPLE | |
| The example below shows a (P4080) BMan portals container/bus node with two portals | |
| bman-portals@ff4000000 { | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| compatible = "simple-bus"; | |
| ranges = <0 0xf 0xf4000000 0x200000>; | |
| bman-portal@0 { | |
| compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; | |
| reg = <0x0 0x4000>, <0x100000 0x1000>; | |
| interrupts = <105 2 0 0>; | |
| }; | |
| bman-portal@4000 { | |
| compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; | |
| reg = <0x4000 0x4000>, <0x101000 0x1000>; | |
| interrupts = <107 2 0 0>; | |
| }; | |
| }; |
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| QorIQ DPAA Buffer Manager Device Tree Bindings | |
| Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. | |
| CONTENTS | |
| - BMan Node | |
| - BMan Private Memory Node | |
| - Example | |
| BMan Node | |
| The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA). | |
| BMan supports hardware allocation and deallocation of buffers belonging to pools | |
| originally created by software with configurable depletion thresholds. This | |
| binding covers the CCSR space programming model | |
| PROPERTIES | |
| - compatible | |
| Usage: Required | |
| Value type: <stringlist> | |
| Definition: Must include "fsl,bman" | |
| May include "fsl,<SoC>-bman" | |
| - reg | |
| Usage: Required | |
| Value type: <prop-encoded-array> | |
| Definition: Registers region within the CCSR address space | |
| The BMan revision information is located in the BMAN_IP_REV_1/2 registers which | |
| are located at offsets 0xbf8 and 0xbfc | |
| - interrupts | |
| Usage: Required | |
| Value type: <prop-encoded-array> | |
| Definition: Standard property. The error interrupt | |
| - fsl,bman-portals | |
| Usage: Required | |
| Value type: <phandle> | |
| Definition: Phandle to this BMan instance's portals | |
| - fsl,liodn | |
| Usage: See pamu.txt | |
| Value type: <prop-encoded-array> | |
| Definition: PAMU property used for static LIODN assignment | |
| - fsl,iommu-parent | |
| Usage: See pamu.txt | |
| Value type: <phandle> | |
| Definition: PAMU property used for dynamic LIODN assignment | |
| For additional details about the PAMU/LIODN binding(s) see pamu.txt | |
| Devices connected to a BMan instance via Direct Connect Portals (DCP) must link | |
| to the respective BMan instance | |
| - fsl,bman | |
| Usage: Required | |
| Value type: <prop-encoded-array> | |
| Description: List of phandle and DCP index pairs, to the BMan instance | |
| to which this device is connected via the DCP | |
| BMan Private Memory Node | |
| BMan requires a contiguous range of physical memory used for the backing store | |
| for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as | |
| a node under the /reserved-memory node. | |
| The BMan FBPR memory node must be named "bman-fbpr" | |
| PROPERTIES | |
| - compatible | |
| Usage: required | |
| Value type: <stringlist> | |
| Definition: PPC platforms: Must include "fsl,bman-fbpr" | |
| ARM platforms: Must include "shared-dma-pool" | |
| as well as the "no-map" property | |
| The following constraints are relevant to the FBPR private memory: | |
| - The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to | |
| 16 GiB | |
| - The alignment must be a muliptle of the memory size | |
| The size of the FBPR must be chosen by observing the hardware features configured | |
| via the Reset Configuration Word (RCW) and that are relevant to a specific board | |
| (e.g. number of MAC(s) pinned-out, number of offline/host command FMan ports, | |
| etc.). The size configured in the DT must reflect the hardware capabilities and | |
| not the specific needs of an application | |
| For additional details about reserved memory regions see reserved-memory.txt | |
| EXAMPLE | |
| The example below shows a BMan FBPR dynamic allocation memory node | |
| reserved-memory { | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| ranges; | |
| bman_fbpr: bman-fbpr { | |
| compatible = "shared-mem-pool"; | |
| size = <0 0x1000000>; | |
| alignment = <0 0x1000000>; | |
| no-map; | |
| }; | |
| }; | |
| The example below shows a (P4080) BMan CCSR-space node | |
| bportals: bman-portals@ff4000000 { | |
| ... | |
| }; | |
| crypto@300000 { | |
| ... | |
| fsl,bman = <&bman, 2>; | |
| ... | |
| }; | |
| bman: bman@31a000 { | |
| compatible = "fsl,bman"; | |
| reg = <0x31a000 0x1000>; | |
| interrupts = <16 2 1 2>; | |
| fsl,liodn = <0x17>; | |
| fsl,bman-portals = <&bportals>; | |
| memory-region = <&bman_fbpr>; | |
| }; | |
| fman@400000 { | |
| ... | |
| fsl,bman = <&bman, 0>; | |
| ... | |
| }; |
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| ST-Ericsson Ux500 boards | |
| ------------------------ | |
| Required properties (in root node) one of these: | |
| compatible = "st-ericsson,mop500" (legacy) | |
| compatible = "st-ericsson,u8500" | |
| Required node (under root node): | |
| soc: represents the system-on-chip and contains the chip | |
| peripherals | |
| Required property of soc node, one of these: | |
| compatible = "stericsson,db8500" | |
| Required subnodes under soc node: | |
| backupram: (used for CPU spin tables and for storing data | |
| during retention, system won't boot without this): | |
| compatible = "ste,dbx500-backupram" | |
| scu: | |
| see binding for arm/arm,scu.yaml | |
| interrupt-controller: | |
| see binding for interrupt-controller/arm,gic.txt | |
| timer: | |
| see binding for timer/arm,twd-timer.yaml | |
| clocks: | |
| see binding for clocks/ux500.txt | |
| Example: | |
| /dts-v1/; | |
| / { | |
| model = "ST-Ericsson HREF (pre-v60) and ST UIB"; | |
| compatible = "st-ericsson,mop500", "st-ericsson,u8500"; | |
| soc { | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| compatible = "stericsson,db8500"; | |
| interrupt-parent = <&intc>; | |
| ranges; | |
| backupram@80150000 { | |
| compatible = "ste,dbx500-backupram"; | |
| reg = <0x80150000 0x2000>; | |
| }; | |
| intc: interrupt-controller@a0411000 { | |
| compatible = "arm,cortex-a9-gic"; | |
| #interrupt-cells = <3>; | |
| #address-cells = <1>; | |
| interrupt-controller; | |
| reg = <0xa0411000 0x1000>, | |
| <0xa0410100 0x100>; | |
| }; | |
| scu@a0410000 { | |
| compatible = "arm,cortex-a9-scu"; | |
| reg = <0xa0410000 0x100>; | |
| }; | |
| timer@a0410600 { | |
| compatible = "arm,cortex-a9-twd-timer"; | |
| reg = <0xa0410600 0x20>; | |
| interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ | |
| clocks = <&smp_twd_clk>; | |
| }; | |
| clocks { | |
| compatible = "stericsson,u8500-clks"; | |
| smp_twd_clk: smp-twd-clock { | |
| #clock-cells = <0>; | |
| }; | |
| }; | |
| }; | |
| }; |
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| * Boot Bus | |
| The Octeon Boot Bus is a configurable parallel bus with 8 chip | |
| selects. Each chip select is independently configurable. | |
| Properties: | |
| - compatible: "cavium,octeon-3860-bootbus" | |
| Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | |
| - reg: The base address of the Boot Bus' register bank. | |
| - #address-cells: Must be <2>. The first cell is the chip select | |
| within the bootbus. The second cell is the offset from the chip select. | |
| - #size-cells: Must be <1>. | |
| - ranges: There must be one one triplet of (child-bus-address, | |
| parent-bus-address, length) for each active chip select. If the | |
| length element for any triplet is zero, the chip select is disabled, | |
| making it inactive. | |
| The configuration parameters for each chip select are stored in child | |
| nodes. | |
| Configuration Properties: | |
| - compatible: "cavium,octeon-3860-bootbus-config" | |
| - cavium,cs-index: A single cell indicating the chip select that | |
| corresponds to this configuration. | |
| - cavium,t-adr: A cell specifying the ADR timing (in nS). | |
| - cavium,t-ce: A cell specifying the CE timing (in nS). | |
| - cavium,t-oe: A cell specifying the OE timing (in nS). | |
| - cavium,t-we: A cell specifying the WE timing (in nS). | |
| - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS). | |
| - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS). | |
| - cavium,t-pause: A cell specifying the PAUSE timing (in nS). | |
| - cavium,t-wait: A cell specifying the WAIT timing (in nS). | |
| - cavium,t-page: A cell specifying the PAGE timing (in nS). | |
| - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS). | |
| - cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1 | |
| = 2 bytes, 2 = 4 bytes, 3 = 8 bytes). | |
| - cavium,wait-mode: Optional. If present, wait mode (WAITM) is selected. | |
| - cavium,page-mode: Optional. If present, page mode (PAGEM) is selected. | |
| - cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of | |
| the bus for this chip select. | |
| - cavium,ale-mode: Optional. If present, ALE mode is selected. | |
| - cavium,sam-mode: Optional. If present, SAM mode is selected. | |
| - cavium,or-mode: Optional. If present, OR mode is selected. | |
| Example: | |
| bootbus: bootbus@1180000000000 { | |
| compatible = "cavium,octeon-3860-bootbus"; | |
| reg = <0x11800 0x00000000 0x0 0x200>; | |
| /* The chip select number and offset */ | |
| #address-cells = <2>; | |
| /* The size of the chip select region */ | |
| #size-cells = <1>; | |
| ranges = <0 0 0x0 0x1f400000 0xc00000>, | |
| <1 0 0x10000 0x30000000 0>, | |
| <2 0 0x10000 0x40000000 0>, | |
| <3 0 0x10000 0x50000000 0>, | |
| <4 0 0x0 0x1d020000 0x10000>, | |
| <5 0 0x0 0x1d040000 0x10000>, | |
| <6 0 0x0 0x1d050000 0x10000>, | |
| <7 0 0x10000 0x90000000 0>; | |
| cavium,cs-config@0 { | |
| compatible = "cavium,octeon-3860-bootbus-config"; | |
| cavium,cs-index = <0>; | |
| cavium,t-adr = <20>; | |
| cavium,t-ce = <60>; | |
| cavium,t-oe = <60>; | |
| cavium,t-we = <45>; | |
| cavium,t-rd-hld = <35>; | |
| cavium,t-wr-hld = <45>; | |
| cavium,t-pause = <0>; | |
| cavium,t-wait = <0>; | |
| cavium,t-page = <35>; | |
| cavium,t-rd-dly = <0>; | |
| cavium,pages = <0>; | |
| cavium,bus-width = <8>; | |
| }; | |
| . | |
| . | |
| . | |
| cavium,cs-config@6 { | |
| compatible = "cavium,octeon-3860-bootbus-config"; | |
| cavium,cs-index = <6>; | |
| cavium,t-adr = <5>; | |
| cavium,t-ce = <300>; | |
| cavium,t-oe = <270>; | |
| cavium,t-we = <150>; | |
| cavium,t-rd-hld = <100>; | |
| cavium,t-wr-hld = <70>; | |
| cavium,t-pause = <0>; | |
| cavium,t-wait = <0>; | |
| cavium,t-page = <320>; | |
| cavium,t-rd-dly = <0>; | |
| cavium,pages = <0>; | |
| cavium,wait-mode; | |
| cavium,bus-width = <16>; | |
| }; | |
| . | |
| . | |
| . | |
| }; |
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| SPDX-License-Identifier: GPL-2.0 | |
| Chinese translated version of Documentation/arm64/booting.rst | |
| If you have any comment or update to the content, please contact the | |
| original document maintainer directly. However, if you have a problem | |
| communicating in English you can also ask the Chinese maintainer for | |
| help. Contact the Chinese maintainer if this translation is outdated | |
| or if there is a problem with the translation. | |
| M: Will Deacon <will.deacon@arm.com> | |
| zh_CN: Fu Wei <wefu@redhat.com> | |
| zh_TW: Hu Haowen <src.res@email.cn> | |
| C: 55f058e7574c3615dea4615573a19bdb258696c6 | |
| --------------------------------------------------------------------- | |
| Documentation/arm64/booting.rst 的中文翻譯 | |
| 如果想評論或更新本文的內容，請直接聯繫原文檔的維護者。如果你使用英文 | |
| 交流有困難的話，也可以向中文版維護者求助。如果本翻譯更新不及時或者翻 | |
| 譯存在問題，請聯繫中文版維護者。 | |
| 英文版維護者： Will Deacon <will.deacon@arm.com> | |
| 中文版維護者： 傅煒 Fu Wei <wefu@redhat.com> | |
| 中文版翻譯者： 傅煒 Fu Wei <wefu@redhat.com> | |
| 中文版校譯者： 傅煒 Fu Wei <wefu@redhat.com> | |
| 繁體中文版校譯者： 胡皓文 Hu Haowen <src.res@email.cn> | |
| 本文翻譯提交時的 Git 檢出點爲： 55f058e7574c3615dea4615573a19bdb258696c6 | |
| 以下爲正文 | |
| --------------------------------------------------------------------- | |
| 啓動 AArch64 Linux | |
| ================== | |
| 作者: Will Deacon <will.deacon@arm.com> | |
| 日期: 2012 年 09 月 07 日 | |
| 本文檔基於 Russell King 的 ARM 啓動文檔，且適用於所有公開發布的 | |
| AArch64 Linux 內核代碼。 | |
| AArch64 異常模型由多個異常級（EL0 - EL3）組成，對於 EL0 和 EL1 異常級 | |
| 有對應的安全和非安全模式。EL2 是系統管理級，且僅存在於非安全模式下。 | |
| EL3 是最高特權級，且僅存在於安全模式下。 | |
| 基於本文檔的目的，我們將簡單地使用『引導裝載程序』（『boot loader』） | |
| 這個術語來定義在將控制權交給 Linux 內核前 CPU 上執行的所有軟體。 | |
| 這可能包含安全監控和系統管理代碼，或者它可能只是一些用於準備最小啓動 | |
| 環境的指令。 | |
| 基本上，引導裝載程序（至少）應實現以下操作： | |
| 1、設置和初始化 RAM | |
| 2、設置設備樹數據 | |
| 3、解壓內核映像 | |
| 4、調用內核映像 | |
| 1、設置和初始化 RAM | |
| ----------------- | |
| 必要性: 強制 | |
| 引導裝載程序應該找到並初始化系統中所有內核用於保持系統變量數據的 RAM。 | |
| 這個操作的執行方式因設備而異。（它可能使用內部算法來自動定位和計算所有 | |
| RAM，或可能使用對這個設備已知的 RAM 信息，還可能是引導裝載程序設計者 | |
| 想到的任何合適的方法。） | |
| 2、設置設備樹數據 | |
| --------------- | |
| 必要性: 強制 | |
| 設備樹數據塊（dtb）必須 8 字節對齊，且大小不能超過 2MB。由於設備樹 | |
| 數據塊將在使能緩存的情況下以 2MB 粒度被映射，故其不能被置於必須以特定 | |
| 屬性映射的2M區域內。 | |
| 註： v4.2 之前的版本同時要求設備樹數據塊被置於從內核映像以下 | |
| text_offset 字節處算起第一個 512MB 內。 | |
| 3、解壓內核映像 | |
| ------------- | |
| 必要性: 可選 | |
| AArch64 內核當前沒有提供自解壓代碼，因此如果使用了壓縮內核映像文件 | |
| （比如 Image.gz），則需要通過引導裝載程序（使用 gzip 等）來進行解壓。 | |
| 若引導裝載程序沒有實現這個功能，就要使用非壓縮內核映像文件。 | |
| 4、調用內核映像 | |
| ------------- | |
| 必要性: 強制 | |
| 已解壓的內核映像包含一個 64 字節的頭，內容如下： | |
| u32 code0; /* 可執行代碼 */ | |
| u32 code1; /* 可執行代碼 */ | |
| u64 text_offset; /* 映像裝載偏移，小端模式 */ | |
| u64 image_size; /* 映像實際大小, 小端模式 */ | |
| u64 flags; /* 內核旗標, 小端模式 * | |
| u64 res2 = 0; /* 保留 */ | |
| u64 res3 = 0; /* 保留 */ | |
| u64 res4 = 0; /* 保留 */ | |
| u32 magic = 0x644d5241; /* 魔數, 小端, "ARM\x64" */ | |
| u32 res5; /* 保留 （用於 PE COFF 偏移） */ | |
| 映像頭注釋： | |
| - 自 v3.17 起，除非另有說明，所有域都是小端模式。 | |
| - code0/code1 負責跳轉到 stext. | |
| - 當通過 EFI 啓動時， 最初 code0/code1 被跳過。 | |
| res5 是到 PE 文件頭的偏移，而 PE 文件頭含有 EFI 的啓動入口點 | |
| （efi_stub_entry）。當 stub 代碼完成了它的使命，它會跳轉到 code0 | |
| 繼續正常的啓動流程。 | |
| - v3.17 之前，未明確指定 text_offset 的字節序。此時，image_size 爲零， | |
| 且 text_offset 依照內核字節序爲 0x80000。 | |
| 當 image_size 非零，text_offset 爲小端模式且是有效值，應被引導加載 | |
| 程序使用。當 image_size 爲零，text_offset 可假定爲 0x80000。 | |
| - flags 域 (v3.17 引入) 爲 64 位小端模式，其編碼如下： | |
| 位 0: 內核字節序。 1 表示大端模式，0 表示小端模式。 | |
| 位 1-2: 內核頁大小。 | |
| 0 - 未指定。 | |
| 1 - 4K | |
| 2 - 16K | |
| 3 - 64K | |
| 位 3: 內核物理位置 | |
| 0 - 2MB 對齊基址應儘量靠近內存起始處，因爲 | |
| 其基址以下的內存無法通過線性映射訪問 | |
| 1 - 2MB 對齊基址可以在物理內存的任意位置 | |
| 位 4-63: 保留。 | |
| - 當 image_size 爲零時，引導裝載程序應試圖在內核映像末尾之後儘可能 | |
| 多地保留空閒內存供內核直接使用。對內存空間的需求量因所選定的內核 | |
| 特性而異, 並無實際限制。 | |
| 內核映像必須被放置在任意一個可用系統內存 2MB 對齊基址的 text_offset | |
| 字節處，並從該處被調用。2MB 對齊基址和內核映像起始地址之間的區域對於 | |
| 內核來說沒有特殊意義，且可能被用於其他目的。 | |
| 從映像起始地址算起，最少必須準備 image_size 字節的空閒內存供內核使用。 | |
| 註： v4.6 之前的版本無法使用內核映像物理偏移以下的內存，所以當時建議 | |
| 將映像儘量放置在靠近系統內存起始的地方。 | |
| 任何提供給內核的內存（甚至在映像起始地址之前），若未從內核中標記爲保留 | |
| (如在設備樹（dtb）的 memreserve 區域），都將被認爲對內核是可用。 | |
| 在跳轉入內核前，必須符合以下狀態： | |
| - 停止所有 DMA 設備，這樣內存數據就不會因爲虛假網絡包或磁碟數據而 | |
| 被破壞。這可能可以節省你許多的調試時間。 | |
| - 主 CPU 通用寄存器設置 | |
| x0 = 系統 RAM 中設備樹數據塊（dtb）的物理地址。 | |
| x1 = 0 (保留，將來可能使用) | |
| x2 = 0 (保留，將來可能使用) | |
| x3 = 0 (保留，將來可能使用) | |
| - CPU 模式 | |
| 所有形式的中斷必須在 PSTATE.DAIF 中被屏蔽（Debug、SError、IRQ | |
| 和 FIQ）。 | |
| CPU 必須處於 EL2（推薦，可訪問虛擬化擴展）或非安全 EL1 模式下。 | |
| - 高速緩存、MMU | |
| MMU 必須關閉。 | |
| 指令緩存開啓或關閉皆可。 | |
| 已載入的內核映像的相應內存區必須被清理，以達到緩存一致性點（PoC）。 | |
| 當存在系統緩存或其他使能緩存的一致性主控器時，通常需使用虛擬地址 | |
| 維護其緩存，而非 set/way 操作。 | |
| 遵從通過虛擬地址操作維護構架緩存的系統緩存必須被配置，並可以被使能。 | |
| 而不通過虛擬地址操作維護構架緩存的系統緩存（不推薦），必須被配置且 | |
| 禁用。 | |
| *譯者註：對於 PoC 以及緩存相關內容，請參考 ARMv8 構架參考手冊 | |
| ARM DDI 0487A | |
| - 架構計時器 | |
| CNTFRQ 必須設定爲計時器的頻率，且 CNTVOFF 必須設定爲對所有 CPU | |
| 都一致的值。如果在 EL1 模式下進入內核，則 CNTHCTL_EL2 中的 | |
| EL1PCTEN (bit 0) 必須置位。 | |
| - 一致性 | |
| 通過內核啓動的所有 CPU 在內核入口地址上必須處於相同的一致性域中。 | |
| 這可能要根據具體實現來定義初始化過程，以使能每個CPU上對維護操作的 | |
| 接收。 | |
| - 系統寄存器 | |
| 在進入內核映像的異常級中，所有構架中可寫的系統寄存器必須通過軟體 | |
| 在一個更高的異常級別下初始化，以防止在 未知 狀態下運行。 | |
| 對於擁有 GICv3 中斷控制器並以 v3 模式運行的系統： | |
| - 如果 EL3 存在： | |
| ICC_SRE_EL3.Enable (位 3) 必須初始化爲 0b1。 | |
| ICC_SRE_EL3.SRE (位 0) 必須初始化爲 0b1。 | |
| - 若內核運行在 EL1： | |
| ICC_SRE_EL2.Enable (位 3) 必須初始化爲 0b1。 | |
| ICC_SRE_EL2.SRE (位 0) 必須初始化爲 0b1。 | |
| - 設備樹（DT）或 ACPI 表必須描述一個 GICv3 中斷控制器。 | |
| 對於擁有 GICv3 中斷控制器並以兼容（v2）模式運行的系統： | |
| - 如果 EL3 存在： | |
| ICC_SRE_EL3.SRE (位 0) 必須初始化爲 0b0。 | |
| - 若內核運行在 EL1： | |
| ICC_SRE_EL2.SRE (位 0) 必須初始化爲 0b0。 | |
| - 設備樹（DT）或 ACPI 表必須描述一個 GICv2 中斷控制器。 | |
| 以上對於 CPU 模式、高速緩存、MMU、架構計時器、一致性、系統寄存器的 | |
| 必要條件描述適用於所有 CPU。所有 CPU 必須在同一異常級別跳入內核。 | |
| 引導裝載程序必須在每個 CPU 處於以下狀態時跳入內核入口： | |
| - 主 CPU 必須直接跳入內核映像的第一條指令。通過此 CPU 傳遞的設備樹 | |
| 數據塊必須在每個 CPU 節點中包含一個 『enable-method』 屬性，所 | |
| 支持的 enable-method 請見下文。 | |
| 引導裝載程序必須生成這些設備樹屬性，並在跳入內核入口之前將其插入 | |
| 數據塊。 | |
| - enable-method 爲 「spin-table」 的 CPU 必須在它們的 CPU | |
| 節點中包含一個 『cpu-release-addr』 屬性。這個屬性標識了一個 | |
| 64 位自然對齊且初始化爲零的內存位置。 | |
| 這些 CPU 必須在內存保留區（通過設備樹中的 /memreserve/ 域傳遞 | |
| 給內核）中自旋於內核之外，輪詢它們的 cpu-release-addr 位置（必須 | |
| 包含在保留區中）。可通過插入 wfe 指令來降低忙循環開銷，而主 CPU 將 | |
| 發出 sev 指令。當對 cpu-release-addr 所指位置的讀取操作返回非零值 | |
| 時，CPU 必須跳入此值所指向的地址。此值爲一個單獨的 64 位小端值， | |
| 因此 CPU 須在跳轉前將所讀取的值轉換爲其本身的端模式。 | |
| - enable-method 爲 「psci」 的 CPU 保持在內核外（比如，在 | |
| memory 節點中描述爲內核空間的內存區外，或在通過設備樹 /memreserve/ | |
| 域中描述爲內核保留區的空間中）。內核將會發起在 ARM 文檔（編號 | |
| ARM DEN 0022A：用於 ARM 上的電源狀態協調接口系統軟體）中描述的 | |
| CPU_ON 調用來將 CPU 帶入內核。 | |
| *譯者注: ARM DEN 0022A 已更新到 ARM DEN 0022C。 | |
| 設備樹必須包含一個 『psci』 節點，請參考以下文檔： | |
| Documentation/devicetree/bindings/arm/psci.yaml | |
| - 輔助 CPU 通用寄存器設置 | |
| x0 = 0 (保留，將來可能使用) | |
| x1 = 0 (保留，將來可能使用) | |
| x2 = 0 (保留，將來可能使用) | |
| x3 = 0 (保留，將來可能使用) | |
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| Amlogic Meson6/Meson8/Meson8b bootrom: | |
| -------------------------------------- | |
| The bootrom register area can be used to access SoC specific | |
| information, such as the "misc version". | |
| Required properties: | |
| - reg: the register range of the bootrom registers | |
| - compatible: should be "amlogic,meson-mx-bootrom" along with "syscon" | |
| Example: | |
| bootrom: bootrom@d9040000 { | |
| compatible = "amlogic,meson-mx-bootrom", "syscon"; | |
| reg = <0xd9040000 0x10000>; | |
| }; |
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| * Broadcom Keypad Controller device tree bindings | |
| Broadcom Keypad controller is used to interface a SoC with a matrix-type | |
| keypad device. The keypad controller supports multiple row and column lines. | |
| A key can be placed at each intersection of a unique row and a unique column. | |
| The keypad controller can sense a key-press and key-release and report the | |
| event using a interrupt to the cpu. | |
| This binding is based on the matrix-keymap binding with the following | |
| changes: | |
| keypad,num-rows and keypad,num-columns are required. | |
| Required SoC Specific Properties: | |
| - compatible: should be "brcm,bcm-keypad" | |
| - reg: physical base address of the controller and length of memory mapped | |
| region. | |
| - interrupts: The interrupt number to the cpu. | |
| Board Specific Properties: | |
| - keypad,num-rows: Number of row lines connected to the keypad | |
| controller. | |
| - keypad,num-columns: Number of column lines connected to the | |
| keypad controller. | |
| - col-debounce-filter-period: The debounce period for the Column filter. | |
| KEYPAD_DEBOUNCE_1_ms = 0 | |
| KEYPAD_DEBOUNCE_2_ms = 1 | |
| KEYPAD_DEBOUNCE_4_ms = 2 | |
| KEYPAD_DEBOUNCE_8_ms = 3 | |
| KEYPAD_DEBOUNCE_16_ms = 4 | |
| KEYPAD_DEBOUNCE_32_ms = 5 | |
| KEYPAD_DEBOUNCE_64_ms = 6 | |
| KEYPAD_DEBOUNCE_128_ms = 7 | |
| - status-debounce-filter-period: The debounce period for the Status filter. | |
| KEYPAD_DEBOUNCE_1_ms = 0 | |
| KEYPAD_DEBOUNCE_2_ms = 1 | |
| KEYPAD_DEBOUNCE_4_ms = 2 | |
| KEYPAD_DEBOUNCE_8_ms = 3 | |
| KEYPAD_DEBOUNCE_16_ms = 4 | |
| KEYPAD_DEBOUNCE_32_ms = 5 | |
| KEYPAD_DEBOUNCE_64_ms = 6 | |
| KEYPAD_DEBOUNCE_128_ms = 7 | |
| - row-output-enabled: An optional property indicating whether the row or | |
| column is being used as output. If specified the row is being used | |
| as the output. Else defaults to column. | |
| - pull-up-enabled: An optional property indicating the Keypad scan mode. | |
| If specified implies the keypad scan pull-up has been enabled. | |
| - autorepeat: Boolean, Enable auto repeat feature of Linux input | |
| subsystem (optional). | |
| - linux,keymap: The keymap for keys as described in the binding document | |
| devicetree/bindings/input/matrix-keymap.txt. | |
| Example: | |
| #include "dt-bindings/input/input.h" | |
| / { | |
| keypad: keypad@180ac000 { | |
| /* Required SoC specific properties */ | |
| compatible = "brcm,bcm-keypad"; | |
| /* Required Board specific properties */ | |
| keypad,num-rows = <5>; | |
| keypad,num-columns = <5>; | |
| linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_F) /* key_forward */ | |
| MATRIX_KEY(0x00, 0x03, KEY_HOME) /* key_home */ | |
| MATRIX_KEY(0x00, 0x04, KEY_M) /* key_message */ | |
| MATRIX_KEY(0x01, 0x00, KEY_A) /* key_contacts */ | |
| MATRIX_KEY(0x01, 0x01, KEY_1) /* key_1 */ | |
| MATRIX_KEY(0x01, 0x02, KEY_2) /* key_2 */ | |
| MATRIX_KEY(0x01, 0x03, KEY_3) /* key_3 */ | |
| MATRIX_KEY(0x01, 0x04, KEY_S) /* key_speaker */ | |
| MATRIX_KEY(0x02, 0x00, KEY_P) /* key_phone */ | |
| MATRIX_KEY(0x02, 0x01, KEY_4) /* key_4 */ | |
| MATRIX_KEY(0x02, 0x02, KEY_5) /* key_5 */ | |
| MATRIX_KEY(0x02, 0x03, KEY_6) /* key_6 */ | |
| MATRIX_KEY(0x02, 0x04, KEY_VOLUMEUP) /* key_vol_up */ | |
| MATRIX_KEY(0x03, 0x00, KEY_C) /* key_call_log */ | |
| MATRIX_KEY(0x03, 0x01, KEY_7) /* key_7 */ | |
| MATRIX_KEY(0x03, 0x02, KEY_8) /* key_8 */ | |
| MATRIX_KEY(0x03, 0x03, KEY_9) /* key_9 */ | |
| MATRIX_KEY(0x03, 0x04, KEY_VOLUMEDOWN) /* key_vol_down */ | |
| MATRIX_KEY(0x04, 0x00, KEY_H) /* key_headset */ | |
| MATRIX_KEY(0x04, 0x01, KEY_KPASTERISK) /* key_* */ | |
| MATRIX_KEY(0x04, 0x02, KEY_0) /* key_0 */ | |
| MATRIX_KEY(0x04, 0x03, KEY_GRAVE) /* key_# */ | |
| MATRIX_KEY(0x04, 0x04, KEY_MUTE) /* key_mute */ | |
| >; | |
| /* Optional board specific properties */ | |
| col-debounce-filter-period = <5>; | |
| row-output-enabled; | |
| pull-up-enabled; | |
| }; | |
| }; |
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| Broadcom BCM281xx Pin Controller | |
| This is a pin controller for the Broadcom BCM281xx SoC family, which includes | |
| BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs. | |
| === Pin Controller Node === | |
| Required Properties: | |
| - compatible: Must be "brcm,bcm11351-pinctrl" | |
| - reg: Base address of the PAD Controller register block and the size | |
| of the block. | |
| For example, the following is the bare minimum node: | |
| pinctrl@35004800 { | |
| compatible = "brcm,bcm11351-pinctrl"; | |
| reg = <0x35004800 0x430>; | |
| }; | |
| As a pin controller device, in addition to the required properties, this node | |
| should also contain the pin configuration nodes that client devices reference, | |
| if any. | |
| === Pin Configuration Node === | |
| Each pin configuration node is a sub-node of the pin controller node and is a | |
| container of an arbitrary number of subnodes, called pin group nodes in this | |
| document. | |
| Please refer to the pinctrl-bindings.txt in this directory for details of the | |
| common pinctrl bindings used by client devices, including the definition of a | |
| "pin configuration node". | |
| === Pin Group Node === | |
| A pin group node specifies the desired pin mux and/or pin configuration for an | |
| arbitrary number of pins. The name of the pin group node is optional and not | |
| used. | |
| A pin group node only affects the properties specified in the node, and has no | |
| effect on any properties that are omitted. | |
| The pin group node accepts a subset of the generic pin config properties. For | |
| details generic pin config properties, please refer to pinctrl-bindings.txt | |
| and <include/linux/pinctrl/pinconfig-generic.h>. | |
| Each pin controlled by this pin controller belong to one of three types: | |
| Standard, I2C, and HDMI. Each type accepts a different set of pin config | |
| properties. A list of pins and their types is provided below. | |
| Required Properties (applicable to all pins): | |
| - pins: Multiple strings. Specifies the name(s) of one or more pins to | |
| be configured by this node. | |
| Optional Properties (for standard pins): | |
| - function: String. Specifies the pin mux selection. Values | |
| must be one of: "alt1", "alt2", "alt3", "alt4" | |
| - input-schmitt-enable: No arguments. Enable schmitt-trigger mode. | |
| - input-schmitt-disable: No arguments. Disable schmitt-trigger mode. | |
| - bias-pull-up: No arguments. Pull up on pin. | |
| - bias-pull-down: No arguments. Pull down on pin. | |
| - bias-disable: No arguments. Disable pin bias. | |
| - slew-rate: Integer. Meaning depends on configured pin mux: | |
| *_SCL or *_SDA: | |
| 0: Standard(100kbps)& Fast(400kbps) mode | |
| 1: Highspeed (3.4Mbps) mode | |
| IC_DM or IC_DP: | |
| 0: normal slew rate | |
| 1: fast slew rate | |
| Otherwise: | |
| 0: fast slew rate | |
| 1: normal slew rate | |
| - input-enable: No arguments. Enable input (does not affect | |
| output.) | |
| - input-disable: No arguments. Disable input (does not affect | |
| output.) | |
| - drive-strength: Integer. Drive strength in mA. Valid values are | |
| 2, 4, 6, 8, 10, 12, 14, 16 mA. | |
| Optional Properties (for I2C pins): | |
| - function: String. Specifies the pin mux selection. Values | |
| must be one of: "alt1", "alt2", "alt3", "alt4" | |
| - bias-pull-up: Integer. Pull up strength in Ohm. There are 3 | |
| pull-up resisitors (1.2k, 1.8k, 2.7k) available | |
| in parallel for I2C pins, so the valid values | |
| are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm. | |
| - bias-disable: No arguments. Disable pin bias. | |
| - slew-rate: Integer. Meaning depends on configured pin mux: | |
| *_SCL or *_SDA: | |
| 0: Standard(100kbps)& Fast(400kbps) mode | |
| 1: Highspeed (3.4Mbps) mode | |
| IC_DM or IC_DP: | |
| 0: normal slew rate | |
| 1: fast slew rate | |
| Otherwise: | |
| 0: fast slew rate | |
| 1: normal slew rate | |
| - input-enable: No arguments. Enable input (does not affect | |
| output.) | |
| - input-disable: No arguments. Disable input (does not affect | |
| output.) | |
| Optional Properties (for HDMI pins): | |
| - function: String. Specifies the pin mux selection. Values | |
| must be one of: "alt1", "alt2", "alt3", "alt4" | |
| - slew-rate: Integer. Controls slew rate. | |
| 0: Standard(100kbps)& Fast(400kbps) mode | |
| 1: Highspeed (3.4Mbps) mode | |
| - input-enable: No arguments. Enable input (does not affect | |
| output.) | |
| - input-disable: No arguments. Disable input (does not affect | |
| output.) | |
| Example: | |
| // pin controller node | |
| pinctrl@35004800 { | |
| compatible = "brcm,bcm11351-pinctrl"; | |
| reg = <0x35004800 0x430>; | |
| // pin configuration node | |
| dev_a_default: dev_a_active { | |
| //group node defining 1 standard pin | |
| grp_1 { | |
| pins = "std_pin1"; | |
| function = "alt1"; | |
| input-schmitt-enable; | |
| bias-disable; | |
| slew-rate = <1>; | |
| drive-strength = <4>; | |
| }; | |
| // group node defining 2 I2C pins | |
| grp_2 { | |
| pins = "i2c_pin1", "i2c_pin2"; | |
| function = "alt2"; | |
| bias-pull-up = <720>; | |
| input-enable; | |
| }; | |
| // group node defining 2 HDMI pins | |
| grp_3 { | |
| pins = "hdmi_pin1", "hdmi_pin2"; | |
| function = "alt3"; | |
| slew-rate = <1>; | |
| }; | |
| // other pin group nodes | |
| ... | |
| }; | |
| // other pin configuration nodes | |
| ... | |
| }; | |
| In the example above, "dev_a_active" is a pin configuration node with a number | |
| of sub-nodes. In the pin group node "grp_1", one pin, "std_pin1", is defined in | |
| the "pins" property. Thus, the remaining properties in the "grp_1" node applies | |
| only to this pin, including the following settings: | |
| - setting pinmux to "alt1" | |
| - enabling schmitt-trigger (hystersis) mode | |
| - disabling pin bias | |
| - setting the slew-rate to 1 | |
| - setting the drive strength to 4 mA | |
| Note that neither "input-enable" nor "input-disable" was specified - the pinctrl | |
| subsystem will therefore leave this property unchanged from whatever state it | |
| was in before applying these changes. | |
| The "pins" property in the pin group node "grp_2" specifies two pins - | |
| "i2c_pin1" and "i2c_pin2"; the remaining properties in this pin group node, | |
| therefore, applies to both of these pins. The properties include: | |
| - setting pinmux to "alt2" | |
| - setting pull-up resistance to 720 Ohm (ie. enabling 1.2k and 1.8k resistors | |
| in parallel) | |
| - enabling both pins' input | |
| "slew-rate" is not specified in this pin group node, so the slew-rate for these | |
| pins are left as-is. | |
| Finally, "grp_3" defines two HDMI pins. The following properties are applied to | |
| both pins: | |
| - setting pinmux to "alt3" | |
| - setting slew-rate to 1; for HDMI pins, this corresponds to the 3.4 Mbps | |
| Highspeed mode | |
| The input is neither enabled or disabled, and is left untouched. | |
| === Pin Names and Type === | |
| The following are valid pin names and their pin types: | |
| "adcsync", Standard | |
| "bat_rm", Standard | |
| "bsc1_scl", I2C | |
| "bsc1_sda", I2C | |
| "bsc2_scl", I2C | |
| "bsc2_sda", I2C | |
| "classgpwr", Standard | |
| "clk_cx8", Standard | |
| "clkout_0", Standard | |
| "clkout_1", Standard | |
| "clkout_2", Standard | |
| "clkout_3", Standard | |
| "clkreq_in_0", Standard | |
| "clkreq_in_1", Standard | |
| "cws_sys_req1", Standard | |
| "cws_sys_req2", Standard | |
| "cws_sys_req3", Standard | |
| "digmic1_clk", Standard | |
| "digmic1_dq", Standard | |
| "digmic2_clk", Standard | |
| "digmic2_dq", Standard | |
| "gpen13", Standard | |
| "gpen14", Standard | |
| "gpen15", Standard | |
| "gpio00", Standard | |
| "gpio01", Standard | |
| "gpio02", Standard | |
| "gpio03", Standard | |
| "gpio04", Standard | |
| "gpio05", Standard | |
| "gpio06", Standard | |
| "gpio07", Standard | |
| "gpio08", Standard | |
| "gpio09", Standard | |
| "gpio10", Standard | |
| "gpio11", Standard | |
| "gpio12", Standard | |
| "gpio13", Standard | |
| "gpio14", Standard | |
| "gps_pablank", Standard | |
| "gps_tmark", Standard | |
| "hdmi_scl", HDMI | |
| "hdmi_sda", HDMI | |
| "ic_dm", Standard | |
| "ic_dp", Standard | |
| "kp_col_ip_0", Standard | |
| "kp_col_ip_1", Standard | |
| "kp_col_ip_2", Standard | |
| "kp_col_ip_3", Standard | |
| "kp_row_op_0", Standard | |
| "kp_row_op_1", Standard | |
| "kp_row_op_2", Standard | |
| "kp_row_op_3", Standard | |
| "lcd_b_0", Standard | |
| "lcd_b_1", Standard | |
| "lcd_b_2", Standard | |
| "lcd_b_3", Standard | |
| "lcd_b_4", Standard | |
| "lcd_b_5", Standard | |
| "lcd_b_6", Standard | |
| "lcd_b_7", Standard | |
| "lcd_g_0", Standard | |
| "lcd_g_1", Standard | |
| "lcd_g_2", Standard | |
| "lcd_g_3", Standard | |
| "lcd_g_4", Standard | |
| "lcd_g_5", Standard | |
| "lcd_g_6", Standard | |
| "lcd_g_7", Standard | |
| "lcd_hsync", Standard | |
| "lcd_oe", Standard | |
| "lcd_pclk", Standard | |
| "lcd_r_0", Standard | |
| "lcd_r_1", Standard | |
| "lcd_r_2", Standard | |
| "lcd_r_3", Standard | |
| "lcd_r_4", Standard | |
| "lcd_r_5", Standard | |
| "lcd_r_6", Standard | |
| "lcd_r_7", Standard | |
| "lcd_vsync", Standard | |
| "mdmgpio0", Standard | |
| "mdmgpio1", Standard | |
| "mdmgpio2", Standard | |
| "mdmgpio3", Standard | |
| "mdmgpio4", Standard | |
| "mdmgpio5", Standard | |
| "mdmgpio6", Standard | |
| "mdmgpio7", Standard | |
| "mdmgpio8", Standard | |
| "mphi_data_0", Standard | |
| "mphi_data_1", Standard | |
| "mphi_data_2", Standard | |
| "mphi_data_3", Standard | |
| "mphi_data_4", Standard | |
| "mphi_data_5", Standard | |
| "mphi_data_6", Standard | |
| "mphi_data_7", Standard | |
| "mphi_data_8", Standard | |
| "mphi_data_9", Standard | |
| "mphi_data_10", Standard | |
| "mphi_data_11", Standard | |
| "mphi_data_12", Standard | |
| "mphi_data_13", Standard | |
| "mphi_data_14", Standard | |
| "mphi_data_15", Standard | |
| "mphi_ha0", Standard | |
| "mphi_hat0", Standard | |
| "mphi_hat1", Standard | |
| "mphi_hce0_n", Standard | |
| "mphi_hce1_n", Standard | |
| "mphi_hrd_n", Standard | |
| "mphi_hwr_n", Standard | |
| "mphi_run0", Standard | |
| "mphi_run1", Standard | |
| "mtx_scan_clk", Standard | |
| "mtx_scan_data", Standard | |
| "nand_ad_0", Standard | |
| "nand_ad_1", Standard | |
| "nand_ad_2", Standard | |
| "nand_ad_3", Standard | |
| "nand_ad_4", Standard | |
| "nand_ad_5", Standard | |
| "nand_ad_6", Standard | |
| "nand_ad_7", Standard | |
| "nand_ale", Standard | |
| "nand_cen_0", Standard | |
| "nand_cen_1", Standard | |
| "nand_cle", Standard | |
| "nand_oen", Standard | |
| "nand_rdy_0", Standard | |
| "nand_rdy_1", Standard | |
| "nand_wen", Standard | |
| "nand_wp", Standard | |
| "pc1", Standard | |
| "pc2", Standard | |
| "pmu_int", Standard | |
| "pmu_scl", I2C | |
| "pmu_sda", I2C | |
| "rfst2g_mtsloten3g", Standard | |
| "rgmii_0_rx_ctl", Standard | |
| "rgmii_0_rxc", Standard | |
| "rgmii_0_rxd_0", Standard | |
| "rgmii_0_rxd_1", Standard | |
| "rgmii_0_rxd_2", Standard | |
| "rgmii_0_rxd_3", Standard | |
| "rgmii_0_tx_ctl", Standard | |
| "rgmii_0_txc", Standard | |
| "rgmii_0_txd_0", Standard | |
| "rgmii_0_txd_1", Standard | |
| "rgmii_0_txd_2", Standard | |
| "rgmii_0_txd_3", Standard | |
| "rgmii_1_rx_ctl", Standard | |
| "rgmii_1_rxc", Standard | |
| "rgmii_1_rxd_0", Standard | |
| "rgmii_1_rxd_1", Standard | |
| "rgmii_1_rxd_2", Standard | |
| "rgmii_1_rxd_3", Standard | |
| "rgmii_1_tx_ctl", Standard | |
| "rgmii_1_txc", Standard | |
| "rgmii_1_txd_0", Standard | |
| "rgmii_1_txd_1", Standard | |
| "rgmii_1_txd_2", Standard | |
| "rgmii_1_txd_3", Standard | |
| "rgmii_gpio_0", Standard | |
| "rgmii_gpio_1", Standard | |
| "rgmii_gpio_2", Standard | |
| "rgmii_gpio_3", Standard | |
| "rtxdata2g_txdata3g1", Standard | |
| "rtxen2g_txdata3g2", Standard | |
| "rxdata3g0", Standard | |
| "rxdata3g1", Standard | |
| "rxdata3g2", Standard | |
| "sdio1_clk", Standard | |
| "sdio1_cmd", Standard | |
| "sdio1_data_0", Standard | |
| "sdio1_data_1", Standard | |
| "sdio1_data_2", Standard | |
| "sdio1_data_3", Standard | |
| "sdio4_clk", Standard | |
| "sdio4_cmd", Standard | |
| "sdio4_data_0", Standard | |
| "sdio4_data_1", Standard | |
| "sdio4_data_2", Standard | |
| "sdio4_data_3", Standard | |
| "sim_clk", Standard | |
| "sim_data", Standard | |
| "sim_det", Standard | |
| "sim_resetn", Standard | |
| "sim2_clk", Standard | |
| "sim2_data", Standard | |
| "sim2_det", Standard | |
| "sim2_resetn", Standard | |
| "sri_c", Standard | |
| "sri_d", Standard | |
| "sri_e", Standard | |
| "ssp_extclk", Standard | |
| "ssp0_clk", Standard | |
| "ssp0_fs", Standard | |
| "ssp0_rxd", Standard | |
| "ssp0_txd", Standard | |
| "ssp2_clk", Standard | |
| "ssp2_fs_0", Standard | |
| "ssp2_fs_1", Standard | |
| "ssp2_fs_2", Standard | |
| "ssp2_fs_3", Standard | |
| "ssp2_rxd_0", Standard | |
| "ssp2_rxd_1", Standard | |
| "ssp2_txd_0", Standard | |
| "ssp2_txd_1", Standard | |
| "ssp3_clk", Standard | |
| "ssp3_fs", Standard | |
| "ssp3_rxd", Standard | |
| "ssp3_txd", Standard | |
| "ssp4_clk", Standard | |
| "ssp4_fs", Standard | |
| "ssp4_rxd", Standard | |
| "ssp4_txd", Standard | |
| "ssp5_clk", Standard | |
| "ssp5_fs", Standard | |
| "ssp5_rxd", Standard | |
| "ssp5_txd", Standard | |
| "ssp6_clk", Standard | |
| "ssp6_fs", Standard | |
| "ssp6_rxd", Standard | |
| "ssp6_txd", Standard | |
| "stat_1", Standard | |
| "stat_2", Standard | |
| "sysclken", Standard | |
| "traceclk", Standard | |
| "tracedt00", Standard | |
| "tracedt01", Standard | |
| "tracedt02", Standard | |
| "tracedt03", Standard | |
| "tracedt04", Standard | |
| "tracedt05", Standard | |
| "tracedt06", Standard | |
| "tracedt07", Standard | |
| "tracedt08", Standard | |
| "tracedt09", Standard | |
| "tracedt10", Standard | |
| "tracedt11", Standard | |
| "tracedt12", Standard | |
| "tracedt13", Standard | |
| "tracedt14", Standard | |
| "tracedt15", Standard | |
| "txdata3g0", Standard | |
| "txpwrind", Standard | |
| "uartb1_ucts", Standard | |
| "uartb1_urts", Standard | |
| "uartb1_urxd", Standard | |
| "uartb1_utxd", Standard | |
| "uartb2_urxd", Standard | |
| "uartb2_utxd", Standard | |
| "uartb3_ucts", Standard | |
| "uartb3_urts", Standard | |
| "uartb3_urxd", Standard | |
| "uartb3_utxd", Standard | |
| "uartb4_ucts", Standard | |
| "uartb4_urts", Standard | |
| "uartb4_urxd", Standard | |
| "uartb4_utxd", Standard | |
| "vc_cam1_scl", I2C | |
| "vc_cam1_sda", I2C | |
| "vc_cam2_scl", I2C | |
| "vc_cam2_sda", I2C | |
| "vc_cam3_scl", I2C | |
| "vc_cam3_sda", I2C |
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| Broadcom Kona Family Reset Manager | |
| ---------------------------------- | |
| The reset manager is used on the Broadcom BCM21664 SoC. | |
| Required properties: | |
| - compatible: brcm,bcm21664-resetmgr | |
| - reg: memory address & range | |
| Example: | |
| brcm,resetmgr@35001f00 { | |
| compatible = "brcm,bcm21664-resetmgr"; | |
| reg = <0x35001f00 0x24>; | |
| }; |
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| BCM2835 Top-Level ("ARMCTRL") Interrupt Controller | |
| The BCM2835 contains a custom top-level interrupt controller, which supports | |
| 72 interrupt sources using a 2-level register scheme. The interrupt | |
| controller, or the HW block containing it, is referred to occasionally | |
| as "armctrl" in the SoC documentation, hence naming of this binding. | |
| The BCM2836 contains the same interrupt controller with the same | |
| interrupts, but the per-CPU interrupt controller is the root, and an | |
| interrupt there indicates that the ARMCTRL has an interrupt to handle. | |
| Required properties: | |
| - compatible : should be "brcm,bcm2835-armctrl-ic" or | |
| "brcm,bcm2836-armctrl-ic" | |
| - reg : Specifies base physical address and size of the registers. | |
| - interrupt-controller : Identifies the node as an interrupt controller | |
| - #interrupt-cells : Specifies the number of cells needed to encode an | |
| interrupt source. The value shall be 2. | |
| The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic | |
| pending" register, or 1/2 respectively for interrupts in the "IRQ pending | |
| 1/2" register. | |
| The 2nd cell contains the interrupt number within the bank. Valid values | |
| are 0..7 for bank 0, and 0..31 for bank 1. | |
| Additional required properties for brcm,bcm2836-armctrl-ic: | |
| - interrupts : Specifies the interrupt on the parent for this interrupt | |
| controller to handle. | |
| The interrupt sources are as follows: | |
| Bank 0: | |
| 0: ARM_TIMER | |
| 1: ARM_MAILBOX | |
| 2: ARM_DOORBELL_0 | |
| 3: ARM_DOORBELL_1 | |
| 4: VPU0_HALTED | |
| 5: VPU1_HALTED | |
| 6: ILLEGAL_TYPE0 | |
| 7: ILLEGAL_TYPE1 | |
| Bank 1: | |
| 0: TIMER0 | |
| 1: TIMER1 | |
| 2: TIMER2 | |
| 3: TIMER3 | |
| 4: CODEC0 | |
| 5: CODEC1 | |
| 6: CODEC2 | |
| 7: VC_JPEG | |
| 8: ISP | |
| 9: VC_USB | |
| 10: VC_3D | |
| 11: TRANSPOSER | |
| 12: MULTICORESYNC0 | |
| 13: MULTICORESYNC1 | |
| 14: MULTICORESYNC2 | |
| 15: MULTICORESYNC3 | |
| 16: DMA0 | |
| 17: DMA1 | |
| 18: VC_DMA2 | |
| 19: VC_DMA3 | |
| 20: DMA4 | |
| 21: DMA5 | |
| 22: DMA6 | |
| 23: DMA7 | |
| 24: DMA8 | |
| 25: DMA9 | |
| 26: DMA10 | |
| 27: DMA11-14 - shared interrupt for DMA 11 to 14 | |
| 28: DMAALL - triggers on all dma interrupts (including chanel 15) | |
| 29: AUX | |
| 30: ARM | |
| 31: VPUDMA | |
| Bank 2: | |
| 0: HOSTPORT | |
| 1: VIDEOSCALER | |
| 2: CCP2TX | |
| 3: SDC | |
| 4: DSI0 | |
| 5: AVE | |
| 6: CAM0 | |
| 7: CAM1 | |
| 8: HDMI0 | |
| 9: HDMI1 | |
| 10: PIXELVALVE1 | |
| 11: I2CSPISLV | |
| 12: DSI1 | |
| 13: PWA0 | |
| 14: PWA1 | |
| 15: CPR | |
| 16: SMI | |
| 17: GPIO0 | |
| 18: GPIO1 | |
| 19: GPIO2 | |
| 20: GPIO3 | |
| 21: VC_I2C | |
| 22: VC_SPI | |
| 23: VC_I2SPCM | |
| 24: VC_SDIO | |
| 25: VC_UART | |
| 26: SLIMBUS | |
| 27: VEC | |
| 28: CPG | |
| 29: RNG | |
| 30: VC_ARASANSDIO | |
| 31: AVSPMON | |
| Example: | |
| /* BCM2835, first level */ | |
| intc: interrupt-controller { | |
| compatible = "brcm,bcm2835-armctrl-ic"; | |
| reg = <0x7e00b200 0x200>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| }; | |
| /* BCM2836, second level */ | |
| intc: interrupt-controller { | |
| compatible = "brcm,bcm2836-armctrl-ic"; | |
| reg = <0x7e00b200 0x200>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| interrupt-parent = <&local_intc>; | |
| interrupts = <8>; | |
| }; |
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| Broadcom BCM2835 auxiliary peripheral support | |
| This binding uses the common clock binding: | |
| Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| The auxiliary peripherals (UART, SPI1, and SPI2) have a small register | |
| area controlling clock gating to the peripherals, and providing an IRQ | |
| status register. | |
| Required properties: | |
| - compatible: Should be "brcm,bcm2835-aux" | |
| - #clock-cells: Should be <1>. The permitted clock-specifier values can be | |
| found in include/dt-bindings/clock/bcm2835-aux.h | |
| - reg: Specifies base physical address and size of the registers | |
| - clocks: The parent clock phandle | |
| Example: | |
| clocks: cprman@7e101000 { | |
| compatible = "brcm,bcm2835-cprman"; | |
| #clock-cells = <1>; | |
| reg = <0x7e101000 0x2000>; | |
| clocks = <&clk_osc>; | |
| }; | |
| aux: aux@7e215004 { | |
| compatible = "brcm,bcm2835-aux"; | |
| #clock-cells = <1>; | |
| reg = <0x7e215000 0x8>; | |
| clocks = <&clocks BCM2835_CLOCK_VPU>; | |
| }; |
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| Broadcom BCM2835 auxiliar SPI1/2 controller | |
| The BCM2835 contains two forms of SPI master controller, one known simply as | |
| SPI0, and the other known as the "Universal SPI Master"; part of the | |
| auxiliary block. This binding applies to the SPI1/2 controller. | |
| Required properties: | |
| - compatible: Should be "brcm,bcm2835-aux-spi". | |
| - reg: Should contain register location and length for the spi block | |
| - interrupts: Should contain shared interrupt of the aux block | |
| - clocks: The clock feeding the SPI controller - needs to | |
| point to the auxiliar clock driver of the bcm2835, | |
| as this clock will enable the output gate for the specific | |
| clock. | |
| - cs-gpios: the cs-gpios (native cs is NOT supported) | |
| see also spi-bus.txt | |
| Example: | |
| spi1@7e215080 { | |
| compatible = "brcm,bcm2835-aux-spi"; | |
| reg = <0x7e215080 0x40>; | |
| interrupts = <1 29>; | |
| clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI1>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| cs-gpios = <&gpio 18>, <&gpio 17>, <&gpio 16>; | |
| }; | |
| spi2@7e2150c0 { | |
| compatible = "brcm,bcm2835-aux-spi"; | |
| reg = <0x7e2150c0 0x40>; | |
| interrupts = <1 29>; | |
| clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI2>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| cs-gpios = <&gpio 43>, <&gpio 44>, <&gpio 45>; | |
| }; |
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| * BCM2835 AUXILIAR UART | |
| Required properties: | |
| - compatible: "brcm,bcm2835-aux-uart" | |
| - reg: The base address of the UART register bank. | |
| - interrupts: A single interrupt specifier. | |
| - clocks: Clock driving the hardware; used to figure out the baud rate | |
| divisor. | |
| Example: | |
| uart1: serial@7e215040 { | |
| compatible = "brcm,bcm2835-aux-uart"; | |
| reg = <0x7e215040 0x40>; | |
| interrupts = <1 29>; | |
| clocks = <&aux BCM2835_AUX_CLOCK_UART>; | |
| }; |
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| Broadcom BCM2835 CPRMAN clocks | |
| This binding uses the common clock binding: | |
| Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| The CPRMAN clock controller generates clocks in the audio power domain | |
| of the BCM2835. There is a level of PLLs deriving from an external | |
| oscillator, a level of PLL dividers that produce channels off of the | |
| few PLLs, and a level of mostly-generic clock generators sourcing from | |
| the PLL channels. Most other hardware components source from the | |
| clock generators, but a few (like the ARM or HDMI) will source from | |
| the PLL dividers directly. | |
| Required properties: | |
| - compatible: should be one of the following, | |
| "brcm,bcm2711-cprman" | |
| "brcm,bcm2835-cprman" | |
| - #clock-cells: Should be <1>. The permitted clock-specifier values can be | |
| found in include/dt-bindings/clock/bcm2835.h | |
| - reg: Specifies base physical address and size of the registers | |
| - clocks: phandles to the parent clocks used as input to the module, in | |
| the following order: | |
| - External oscillator | |
| - DSI0 byte clock | |
| - DSI0 DDR2 clock | |
| - DSI0 DDR clock | |
| - DSI1 byte clock | |
| - DSI1 DDR2 clock | |
| - DSI1 DDR clock | |
| Only external oscillator is required. The DSI clocks may | |
| not be present, in which case their children will be | |
| unusable. | |
| Example: | |
| clk_osc: clock@3 { | |
| compatible = "fixed-clock"; | |
| reg = <3>; | |
| #clock-cells = <0>; | |
| clock-output-names = "osc"; | |
| clock-frequency = <19200000>; | |
| }; | |
| clocks: cprman@7e101000 { | |
| compatible = "brcm,bcm2835-cprman"; | |
| #clock-cells = <1>; | |
| reg = <0x7e101000 0x2000>; | |
| clocks = <&clk_osc>; | |
| }; | |
| i2c0: i2c@7e205000 { | |
| compatible = "brcm,bcm2835-i2c"; | |
| reg = <0x7e205000 0x1000>; | |
| interrupts = <2 21>; | |
| clocks = <&clocks BCM2835_CLOCK_VPU>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| }; |
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| * BCM2835 DMA controller | |
| The BCM2835 DMA controller has 16 channels in total. | |
| Only the lower 13 channels have an associated IRQ. | |
| Some arbitrary channels are used by the firmware | |
| (1,3,6,7 in the current firmware version). | |
| The channels 0,2 and 3 have special functionality | |
| and should not be used by the driver. | |
| Required properties: | |
| - compatible: Should be "brcm,bcm2835-dma". | |
| - reg: Should contain DMA registers location and length. | |
| - interrupts: Should contain the DMA interrupts associated | |
| to the DMA channels in ascending order. | |
| - interrupt-names: Should contain the names of the interrupt | |
| in the form "dmaXX". | |
| Use "dma-shared-all" for the common interrupt line | |
| that is shared by all dma channels. | |
| - #dma-cells: Must be <1>, the cell in the dmas property of the | |
| client device represents the DREQ number. | |
| - brcm,dma-channel-mask: Bit mask representing the channels | |
| not used by the firmware in ascending order, | |
| i.e. first channel corresponds to LSB. | |
| Example: | |
| dma: dma@7e007000 { | |
| compatible = "brcm,bcm2835-dma"; | |
| reg = <0x7e007000 0xf00>; | |
| interrupts = <1 16>, | |
| <1 17>, | |
| <1 18>, | |
| <1 19>, | |
| <1 20>, | |
| <1 21>, | |
| <1 22>, | |
| <1 23>, | |
| <1 24>, | |
| <1 25>, | |
| <1 26>, | |
| /* dma channel 11-14 share one irq */ | |
| <1 27>, | |
| <1 27>, | |
| <1 27>, | |
| <1 27>, | |
| /* unused shared irq for all channels */ | |
| <1 28>; | |
| interrupt-names = "dma0", | |
| "dma1", | |
| "dma2", | |
| "dma3", | |
| "dma4", | |
| "dma5", | |
| "dma6", | |
| "dma7", | |
| "dma8", | |
| "dma9", | |
| "dma10", | |
| "dma11", | |
| "dma12", | |
| "dma13", | |
| "dma14", | |
| "dma-shared-all"; | |
| #dma-cells = <1>; | |
| brcm,dma-channel-mask = <0x7f35>; | |
| }; | |
| DMA clients connected to the BCM2835 DMA controller must use the format | |
| described in the dma.txt file, using a two-cell specifier for each channel. | |
| Example: | |
| bcm2835_i2s: i2s@7e203000 { | |
| compatible = "brcm,bcm2835-i2s"; | |
| reg = < 0x7e203000 0x24>; | |
| clocks = <&clocks BCM2835_CLOCK_PCM>; | |
| dmas = <&dma 2>, | |
| <&dma 3>; | |
| dma-names = "tx", "rx"; | |
| }; |
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| Broadcom BCM2835 GPIO (and pinmux) controller | |
| The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt | |
| controller, and pinmux/control device. | |
| Required properties: | |
| - compatible: "brcm,bcm2835-gpio" | |
| - compatible: should be one of: | |
| "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl | |
| "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl | |
| "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl | |
| "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl | |
| - reg: Should contain the physical address of the GPIO module's registers. | |
| - gpio-controller: Marks the device node as a GPIO controller. | |
| - #gpio-cells : Should be two. The first cell is the pin number and the | |
| second cell is used to specify optional parameters: | |
| - bit 0 specifies polarity (0 for normal, 1 for inverted) | |
| - interrupts : The interrupt outputs from the controller. One interrupt per | |
| individual bank followed by the "all banks" interrupt. For BCM7211, an | |
| additional set of per-bank interrupt line and an "all banks" wake-up | |
| interrupt may be specified. | |
| - interrupt-controller: Marks the device node as an interrupt controller. | |
| - #interrupt-cells : Should be 2. | |
| The first cell is the GPIO number. | |
| The second cell is used to specify flags: | |
| bits[3:0] trigger type and level flags: | |
| 1 = low-to-high edge triggered. | |
| 2 = high-to-low edge triggered. | |
| 4 = active high level-sensitive. | |
| 8 = active low level-sensitive. | |
| Valid combinations are 1, 2, 3, 4, 8. | |
| Please refer to ../gpio/gpio.txt for a general description of GPIO bindings. | |
| Please refer to pinctrl-bindings.txt in this directory for details of the | |
| common pinctrl bindings used by client devices, including the meaning of the | |
| phrase "pin configuration node". | |
| Each pin configuration node lists the pin(s) to which it applies, and one or | |
| more of the mux function to select on those pin(s), and pull-up/down | |
| configuration. Each subnode only affects those parameters that are explicitly | |
| listed. In other words, a subnode that lists only a mux function implies no | |
| information about any pull configuration. Similarly, a subnode that lists only | |
| a pul parameter implies no information about the mux function. | |
| The BCM2835 pin configuration and multiplexing supports the generic bindings. | |
| For details on each properties, you can refer to ./pinctrl-bindings.txt. | |
| Required sub-node properties: | |
| - pins | |
| - function | |
| Optional sub-node properties: | |
| - bias-disable | |
| - bias-pull-up | |
| - bias-pull-down | |
| - output-high | |
| - output-low | |
| Legacy pin configuration and multiplexing binding: | |
| *** (Its use is deprecated, use generic multiplexing and configuration | |
| bindings instead) | |
| Required subnode-properties: | |
| - brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs | |
| are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53. | |
| Optional subnode-properties: | |
| - brcm,function: Integer, containing the function to mux to the pin(s): | |
| 0: GPIO in | |
| 1: GPIO out | |
| 2: alt5 | |
| 3: alt4 | |
| 4: alt0 | |
| 5: alt1 | |
| 6: alt2 | |
| 7: alt3 | |
| - brcm,pull: Integer, representing the pull-down/up to apply to the pin(s): | |
| 0: none | |
| 1: down | |
| 2: up | |
| Each of brcm,function and brcm,pull may contain either a single value which | |
| will be applied to all pins in brcm,pins, or 1 value for each entry in | |
| brcm,pins. | |
| Example: | |
| gpio: gpio { | |
| compatible = "brcm,bcm2835-gpio"; | |
| reg = <0x2200000 0xb4>; | |
| interrupts = <2 17>, <2 19>, <2 18>, <2 20>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| }; |
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| * Broadcom BCM2835 SoC I2S/PCM module | |
| Required properties: | |
| - compatible: "brcm,bcm2835-i2s" | |
| - reg: Should contain PCM registers location and length. | |
| - clocks: the (PCM) clock to use | |
| - dmas: List of DMA controller phandle and DMA request line ordered pairs. | |
| - dma-names: Identifier string for each DMA request line in the dmas property. | |
| These strings correspond 1:1 with the ordered pairs in dmas. | |
| One of the DMA channels will be responsible for transmission (should be | |
| named "tx") and one for reception (should be named "rx"). | |
| Example: | |
| bcm2835_i2s: i2s@7e203000 { | |
| compatible = "brcm,bcm2835-i2s"; | |
| reg = <0x7e203000 0x24>; | |
| clocks = <&clocks BCM2835_CLOCK_PCM>; | |
| dmas = <&dma 2>, | |
| <&dma 3>; | |
| dma-names = "tx", "rx"; | |
| }; |
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| Broadcom BCM2835 VideoCore mailbox IPC | |
| Required properties: | |
| - compatible: Should be "brcm,bcm2835-mbox" | |
| - reg: Specifies base physical address and size of the registers | |
| - interrupts: The interrupt number | |
| See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt | |
| - #mbox-cells: Specifies the number of cells needed to encode a mailbox | |
| channel. The value shall be 0, since there is only one | |
| mailbox channel implemented by the device. | |
| Example: | |
| mailbox: mailbox@7e00b880 { | |
| compatible = "brcm,bcm2835-mbox"; | |
| reg = <0x7e00b880 0x40>; | |
| interrupts = <0 1>; | |
| #mbox-cells = <0>; | |
| }; | |
| firmware: firmware { | |
| compatible = "raspberrypi,firmware"; | |
| mboxes = <&mailbox>; | |
| #power-domain-cells = <1>; | |
| }; |
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| BCM2835 Watchdog timer | |
| Required properties: | |
| - compatible : should be "brcm,bcm2835-pm-wdt" | |
| - reg : Specifies base physical address and size of the registers. | |
| Optional properties: | |
| - timeout-sec : Contains the watchdog timeout in seconds | |
| Example: | |
| watchdog { | |
| compatible = "brcm,bcm2835-pm-wdt"; | |
| reg = <0x7e100000 0x28>; | |
| timeout-sec = <10>; | |
| }; |
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| BCM2835 PM (Power domains, watchdog) | |
| The PM block controls power domains and some reset lines, and includes | |
| a watchdog timer. This binding supersedes the brcm,bcm2835-pm-wdt | |
| binding which covered some of PM's register range and functionality. | |
| Required properties: | |
| - compatible: Should be "brcm,bcm2835-pm" | |
| - reg: Specifies base physical address and size of the two | |
| register ranges ("PM" and "ASYNC_BRIDGE" in that | |
| order) | |
| - clocks: a) v3d: The V3D clock from CPRMAN | |
| b) peri_image: The PERI_IMAGE clock from CPRMAN | |
| c) h264: The H264 clock from CPRMAN | |
| d) isp: The ISP clock from CPRMAN | |
| - #reset-cells: Should be 1. This property follows the reset controller | |
| bindings[1]. | |
| - #power-domain-cells: Should be 1. This property follows the power domain | |
| bindings[2]. | |
| Optional properties: | |
| - timeout-sec: Contains the watchdog timeout in seconds | |
| - system-power-controller: Whether the watchdog is controlling the | |
| system power. This node follows the power controller bindings[3]. | |
| [1] Documentation/devicetree/bindings/reset/reset.txt | |
| [2] Documentation/devicetree/bindings/power/power-domain.yaml | |
| [3] Documentation/devicetree/bindings/power/power-controller.txt | |
| Example: | |
| pm { | |
| compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; | |
| #power-domain-cells = <1>; | |
| #reset-cells = <1>; | |
| reg = <0x7e100000 0x114>, | |
| <0x7e00a000 0x24>; | |
| clocks = <&clocks BCM2835_CLOCK_V3D>, | |
| <&clocks BCM2835_CLOCK_PERI_IMAGE>, | |
| <&clocks BCM2835_CLOCK_H264>, | |
| <&clocks BCM2835_CLOCK_ISP>; | |
| clock-names = "v3d", "peri_image", "h264", "isp"; | |
| system-power-controller; | |
| }; |
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| Broadcom BCM2835 SDHOST controller | |
| This file documents differences between the core properties described | |
| by mmc.txt and the properties that represent the BCM2835 controller. | |
| Required properties: | |
| - compatible: Should be "brcm,bcm2835-sdhost". | |
| - clocks: The clock feeding the SDHOST controller. | |
| Optional properties: | |
| - dmas: DMA channel for read and write. | |
| See Documentation/devicetree/bindings/dma/dma.txt for details | |
| Example: | |
| sdhost: mmc@7e202000 { | |
| compatible = "brcm,bcm2835-sdhost"; | |
| reg = <0x7e202000 0x100>; | |
| interrupts = <2 24>; | |
| clocks = <&clocks BCM2835_CLOCK_VPU>; | |
| dmas = <&dma 13>; | |
| dma-names = "rx-tx"; | |
| }; |
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| Broadcom BCM2835 SPI0 controller | |
| The BCM2835 contains two forms of SPI master controller, one known simply as | |
| SPI0, and the other known as the "Universal SPI Master"; part of the | |
| auxiliary block. This binding applies to the SPI0 controller. | |
| Required properties: | |
| - compatible: Should be one of "brcm,bcm2835-spi" for BCM2835/2836/2837 or | |
| "brcm,bcm2711-spi" for BCM2711 or "brcm,bcm7211-spi" for BCM7211. | |
| - reg: Should contain register location and length. | |
| - interrupts: Should contain interrupt. | |
| - clocks: The clock feeding the SPI controller. | |
| Example: | |
| spi@20204000 { | |
| compatible = "brcm,bcm2835-spi"; | |
| reg = <0x7e204000 0x1000>; | |
| interrupts = <2 22>; | |
| clocks = <&clk_spi>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| }; |
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| BCM2835 System Timer | |
| The System Timer peripheral provides four 32-bit timer channels and a | |
| single 64-bit free running counter. Each channel has an output compare | |
| register, which is compared against the 32 least significant bits of the | |
| free running counter values, and generates an interrupt. | |
| Required properties: | |
| - compatible : should be "brcm,bcm2835-system-timer" | |
| - reg : Specifies base physical address and size of the registers. | |
| - interrupts : A list of 4 interrupt sinks; one per timer channel. | |
| - clock-frequency : The frequency of the clock that drives the counter, in Hz. | |
| Example: | |
| timer { | |
| compatible = "brcm,bcm2835-system-timer"; | |
| reg = <0x7e003000 0x1000>; | |
| interrupts = <1 0>, <1 1>, <1 2>, <1 3>; | |
| clock-frequency = <1000000>; | |
| }; |
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| Binding for Thermal Sensor driver for BCM2835 SoCs. | |
| Required parameters: | |
| ------------------- | |
| compatible: should be one of: "brcm,bcm2835-thermal", | |
| "brcm,bcm2836-thermal" or "brcm,bcm2837-thermal" | |
| reg: Address range of the thermal registers. | |
| clocks: Phandle of the clock used by the thermal sensor. | |
| #thermal-sensor-cells: should be 0 (see Documentation/devicetree/bindings/thermal/thermal-sensor.yaml) | |
| Example: | |
| thermal-zones { | |
| cpu_thermal: cpu-thermal { | |
| polling-delay-passive = <0>; | |
| polling-delay = <1000>; | |
| thermal-sensors = <&thermal>; | |
| trips { | |
| cpu-crit { | |
| temperature = <80000>; | |
| hysteresis = <0>; | |
| type = "critical"; | |
| }; | |
| }; | |
| coefficients = <(-538) 407000>; | |
| cooling-maps { | |
| }; | |
| }; | |
| }; | |
| thermal: thermal@7e212000 { | |
| compatible = "brcm,bcm2835-thermal"; | |
| reg = <0x7e212000 0x8>; | |
| clocks = <&clocks BCM2835_CLOCK_TSENS>; | |
| #thermal-sensor-cells = <0>; | |
| }; |
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| BCM2836 per-CPU interrupt controller | |
| The BCM2836 has a per-cpu interrupt controller for the timer, PMU | |
| events, and SMP IPIs. One of the CPUs may receive interrupts for the | |
| peripheral (GPU) events, which chain to the BCM2835-style interrupt | |
| controller. | |
| Required properties: | |
| - compatible: Should be "brcm,bcm2836-l1-intc" | |
| - reg: Specifies base physical address and size of the | |
| registers | |
| - interrupt-controller: Identifies the node as an interrupt controller | |
| - #interrupt-cells: Specifies the number of cells needed to encode an | |
| interrupt source. The value shall be 2 | |
| Please refer to interrupts.txt in this directory for details of the common | |
| Interrupt Controllers bindings used by client devices. | |
| The interrupt sources are as follows: | |
| 0: CNTPSIRQ | |
| 1: CNTPNSIRQ | |
| 2: CNTHPIRQ | |
| 3: CNTVIRQ | |
| 8: GPU_FAST | |
| 9: PMU_FAST | |
| Example: | |
| local_intc: local_intc { | |
| compatible = "brcm,bcm2836-l1-intc"; | |
| reg = <0x40000000 0x100>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| interrupt-parent = <&local_intc>; | |
| }; |
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| * Broadcom USB controllers | |
| Required properties: | |
| - compatible: "brcm,bcm3384-ohci", "brcm,bcm3384-ehci" | |
| These currently use the generic-ohci and generic-ehci drivers. On some | |
| systems, special handling may be needed in the following cases: | |
| - Restoring state after systemwide power save modes | |
| - Sharing PHYs with the USBD (UDC) hardware | |
| - Figuring out which controllers are disabled on ASIC bondout variants |
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| Broadcom BCM53573 ILP clock | |
| =========================== | |
| This binding uses the common clock binding: | |
| Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| This binding is used for ILP clock (sometimes referred as "slow clock") | |
| on Broadcom BCM53573 devices using Cortex-A7 CPU. | |
| ILP's rate has to be calculated on runtime and it depends on ALP clock | |
| which has to be referenced. | |
| This clock is part of PMU (Power Management Unit), a Broadcom's device | |
| handing power-related aspects. Its node must be sub-node of the PMU | |
| device. | |
| Required properties: | |
| - compatible: "brcm,bcm53573-ilp" | |
| - clocks: has to reference an ALP clock | |
| - #clock-cells: should be <0> | |
| - clock-output-names: from common clock bindings, should contain clock | |
| name | |
| Example: | |
| pmu@18012000 { | |
| compatible = "simple-mfd", "syscon"; | |
| reg = <0x18012000 0x00001000>; | |
| ilp { | |
| compatible = "brcm,bcm53573-ilp"; | |
| clocks = <&alp>; | |
| #clock-cells = <0>; | |
| clock-output-names = "ilp"; | |
| }; | |
| }; |
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| ------------------------------- | |
| BCM590xx Power Management Units | |
| ------------------------------- | |
| Required properties: | |
| - compatible: "brcm,bcm59056" | |
| - reg: I2C slave address | |
| - interrupts: interrupt for the PMU. Generic interrupt client node bindings | |
| are described in interrupt-controller/interrupts.txt | |
| ------------------ | |
| Voltage Regulators | |
| ------------------ | |
| Optional child nodes: | |
| - regulators: container node for regulators following the generic | |
| regulator binding in regulator/regulator.txt | |
| The valid regulator node names for BCM59056 are: | |
| rfldo, camldo1, camldo2, simldo1, simldo2, sdldo, sdxldo, | |
| mmcldo1, mmcldo2, audldo, micldo, usbldo, vibldo, | |
| csr, iosr1, iosr2, msr, sdsr1, sdsr2, vsr, | |
| gpldo1, gpldo2, gpldo3, gpldo4, gpldo5, gpldo6, | |
| vbus | |
| Example: | |
| pmu: bcm59056@8 { | |
| compatible = "brcm,bcm59056"; | |
| reg = <0x08>; | |
| interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; | |
| regulators { | |
| rfldo_reg: rfldo { | |
| regulator-min-microvolt = <1200000>; | |
| regulator-max-microvolt = <3300000>; | |
| }; | |
| ... | |
| }; | |
| }; |
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| Broadcom BCM63138 Processor Monitor Bus binding | |
| =============================================== | |
| Please also refer to reset.txt in this directory for common reset | |
| controller binding usage. | |
| Require properties: | |
| - compatible: must be "brcm,bcm63138-pmb" | |
| - reg: base register address and size for this bus controller | |
| - #reset-cells: must be 2 first cell is the address within the bus instance designated | |
| by the phandle, and the second is the number of zones for this peripheral | |
| Example: | |
| pmb0: reset-controller@4800c0 { | |
| compatible = "brcm,bcm63138-pmb"; | |
| reg = <0x4800c0 0x10>; | |
| #reset-cells = <2>; | |
| }; |
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| Broadcom BCM63138 DSL System-on-a-Chip device tree bindings | |
| ----------------------------------------------------------- | |
| Boards compatible with the BCM63138 DSL System-on-a-Chip should have the | |
| following properties: | |
| Required root node property: | |
| compatible: should be "brcm,bcm63138" | |
| An optional Boot lookup table Device Tree node is required for secondary CPU | |
| initialization as well as a 'resets' phandle to the correct PMB controller as | |
| defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an | |
| 'enable-method' property. | |
| Required properties for the Boot lookup table node: | |
| - compatible: should be "brcm,bcm63138-bootlut" | |
| - reg: register base address and length for the Boot Lookup table | |
| Optional properties for the primary CPU node: | |
| - enable-method: should be "brcm,bcm63138" | |
| Optional properties for the secondary CPU node: | |
| - enable-method: should be "brcm,bcm63138" | |
| - resets: phandle to the relevant PMB controller, one integer indicating the internal | |
| bus number, and a second integer indicating the address of the CPU in the PMB | |
| internal bus number. | |
| Example: | |
| cpus { | |
| cpu@0 { | |
| compatible = "arm,cotex-a9"; | |
| reg = <0>; | |
| ... | |
| enable-method = "brcm,bcm63138"; | |
| }; | |
| cpu@1 { | |
| compatible = "arm,cortex-a9"; | |
| reg = <1>; | |
| ... | |
| enable-method = "brcm,bcm63138"; | |
| resets = <&pmb0 4 1>; | |
| }; | |
| }; | |
| bootlut: bootlut@8000 { | |
| compatible = "brcm,bcm63138-bootlut"; | |
| reg = <0x8000 0x50>; | |
| }; | |
| ======= | |
| reboot | |
| ------ | |
| Two nodes are required for software reboot: a timer node and a syscon-reboot node. | |
| Timer node: | |
| - compatible: Must be "brcm,bcm6328-timer", "syscon" | |
| - reg: Register base address and length | |
| Syscon reboot node: | |
| See Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml for the | |
| detailed list of properties, the two values defined below are specific to the | |
| BCM6328-style timer: | |
| - offset: Should be 0x34 to denote the offset of the TIMER_WD_TIMER_RESET register | |
| from the beginning of the TIMER block | |
| - mask: Should be 1 for the SoftRst bit. | |
| Example: | |
| timer: timer@80 { | |
| compatible = "brcm,bcm6328-timer", "syscon"; | |
| reg = <0x80 0x3c>; | |
| }; | |
| reboot { | |
| compatible = "syscon-reboot"; | |
| regmap = <&timer>; | |
| offset = <0x34>; | |
| mask = <0x1>; | |
| }; |
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| Broadcom BCM6345-style Level 1 interrupt controller | |
| This block is a first level interrupt controller that is typically connected | |
| directly to one of the HW INT lines on each CPU. | |
| Key elements of the hardware design include: | |
| - 32, 64 or 128 incoming level IRQ lines | |
| - Most onchip peripherals are wired directly to an L1 input | |
| - A separate instance of the register set for each CPU, allowing individual | |
| peripheral IRQs to be routed to any CPU | |
| - Contains one or more enable/status word pairs per CPU | |
| - No atomic set/clear operations | |
| - No polarity/level/edge settings | |
| - No FIFO or priority encoder logic; software is expected to read all | |
| 2-4 status words to determine which IRQs are pending | |
| Required properties: | |
| - compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc" | |
| - reg: specifies the base physical address and size of the registers; | |
| the number of supported IRQs is inferred from the size argument | |
| - interrupt-controller: identifies the node as an interrupt controller | |
| - #interrupt-cells: specifies the number of cells needed to encode an interrupt | |
| source, should be 1. | |
| - interrupts: specifies the interrupt line(s) in the interrupt-parent controller | |
| node; valid values depend on the type of parent interrupt controller | |
| If multiple reg ranges and interrupt-parent entries are present on an SMP | |
| system, the driver will allow IRQ SMP affinity to be set up through the | |
| /proc/irq/ interface. In the simplest possible configuration, only one | |
| reg range and one interrupt-parent is needed. | |
| The driver operates in native CPU endian by default, there is no support for | |
| specifying an alternative endianness. | |
| Example: | |
| periph_intc: interrupt-controller@10000000 { | |
| compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc"; | |
| reg = <0x10000020 0x20>, | |
| <0x10000040 0x20>; | |
| interrupt-controller; | |
| #interrupt-cells = <1>; | |
| interrupt-parent = <&cpu_intc>; | |
| interrupts = <2>, <3>; | |
| }; |
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| Broadcom DSL/PON BCM63xx Audio I2S controller | |
| Required properties: | |
| - compatible: Should be "brcm,bcm63xx-i2s". | |
| - #address-cells: 32bit valued, 1 cell. | |
| - #size-cells: 32bit valued, 0 cell. | |
| - reg: Should contain audio registers location and length | |
| - interrupts: Should contain the interrupt for the controller. | |
| - clocks: Must contain an entry for each entry in clock-names. | |
| Please refer to clock-bindings.txt. | |
| - clock-names: One of each entry matching the clocks phandles list: | |
| - "i2sclk" (generated clock) Required. | |
| - "i2sosc" (fixed 200MHz clock) Required. | |
| (1) : The generated clock is required only when any of TX and RX | |
| works on Master Mode. | |
| (2) : The fixed 200MHz clock is from internal chip and always on | |
| Example: | |
| i2s: bcm63xx-i2s { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "brcm,bcm63xx-i2s"; | |
| reg = <0xFF802080 0xFF>; | |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&i2sclk>, <&osc>; | |
| clock-names = "i2sclk","i2sosc"; | |
| }; |
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| Gated Clock Controller Bindings for MIPS based BCM63XX SoCs | |
| Required properties: | |
| - compatible: must be one of: | |
| "brcm,bcm3368-clocks" | |
| "brcm,bcm6318-clocks" | |
| "brcm,bcm6318-ubus-clocks" | |
| "brcm,bcm6328-clocks" | |
| "brcm,bcm6358-clocks" | |
| "brcm,bcm6362-clocks" | |
| "brcm,bcm6368-clocks" | |
| "brcm,bcm63268-clocks" | |
| - reg: Address and length of the register set | |
| - #clock-cells: must be <1> | |
| Example: | |
| clkctl: clock-controller@10000004 { | |
| compatible = "brcm,bcm6328-clocks"; | |
| reg = <0x10000004 0x4>; | |
| #clock-cells = <1>; | |
| }; |
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| * Broadcom Starfighter 2 integrated swich | |
| See dsa/brcm,bcm7445-switch-v4.0.yaml for the documentation. | |
| *Deprecated* binding required properties: | |
| - dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt | |
| - dsa,ethernet: phandle to the CPU network interface controller, see dsa/dsa.txt | |
| - #address-cells: must be 2, see dsa/dsa.txt | |
| Example using the old DSA DeviceTree binding: | |
| switch_top@f0b00000 { | |
| compatible = "simple-bus"; | |
| #size-cells = <1>; | |
| #address-cells = <1>; | |
| ranges = <0 0xf0b00000 0x40804>; | |
| ethernet_switch@0 { | |
| compatible = "brcm,bcm7445-switch-v4.0"; | |
| #size-cells = <0>; | |
| #address-cells = <2>; | |
| reg = <0x0 0x40000 | |
| 0x40000 0x110 | |
| 0x40340 0x30 | |
| 0x40380 0x30 | |
| 0x40400 0x34 | |
| 0x40600 0x208>; | |
| interrupts = <0 0x18 0 | |
| 0 0x19 0>; | |
| brcm,num-gphy = <1>; | |
| brcm,num-rgmii-ports = <2>; | |
| brcm,fcb-pause-override; | |
| brcm,acb-packets-inflight; | |
| ... | |
| switch@0 { | |
| reg = <0 0>; | |
| #size-cells = <0>; | |
| #address-cells = <1>; | |
| port@0 { | |
| label = "gphy"; | |
| reg = <0>; | |
| brcm,use-bcm-hdr; | |
| }; | |
| ... | |
| }; | |
| }; | |
| }; |
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| Broadcom BCM47xx Partitions | |
| =========================== | |
| Broadcom is one of hardware manufacturers providing SoCs (BCM47xx) used in | |
| home routers. Their BCM947xx boards using CFE bootloader have several partitions | |
| without any on-flash partition table. On some devices their sizes and/or | |
| meanings can also vary so fixed partitioning can't be used. | |
| Discovering partitions on these devices is possible thanks to having a special | |
| header and/or magic signature at the beginning of each of them. They are also | |
| block aligned which is important for determinig a size. | |
| Most of partitions use ASCII text based magic for determining a type. More | |
| complex partitions (like TRX with its HDR0 magic) may include extra header | |
| containing some details, including a length. | |
| A list of supported partitions includes: | |
| 1) Bootloader with Broadcom's CFE (Common Firmware Environment) | |
| 2) NVRAM with configuration/calibration data | |
| 3) Device manufacturer's data with some default values (e.g. SSIDs) | |
| 4) TRX firmware container which can hold up to 4 subpartitions | |
| 5) Backup TRX firmware used after failed upgrade | |
| As mentioned earlier, role of some partitions may depend on extra configuration. | |
| For example both: main firmware and backup firmware use the same TRX format with | |
| the same header. To distinguish currently used firmware a CFE's environment | |
| variable "bootpartition" is used. | |
| Devices using Broadcom partitions described above should should have flash node | |
| with a subnode named "partitions" using following properties: | |
| Required properties: | |
| - compatible : (required) must be "brcm,bcm947xx-cfe-partitions" | |
| Example: | |
| flash@0 { | |
| partitions { | |
| compatible = "brcm,bcm947xx-cfe-partitions"; | |
| }; | |
| }; |
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| Broadcom BCM963XX CFE Loader NOR Flash Partitions | |
| ================================================= | |
| Most Broadcom BCM63XX SoC based devices follow the Broadcom reference layout for | |
| NOR. The first erase block used for the CFE bootloader, the last for an | |
| NVRAM partition, and the remainder in-between for one to two firmware partitions | |
| at fixed offsets. A valid firmware partition is identified by the ImageTag | |
| header found at beginning of the second erase block, containing the rootfs and | |
| kernel offsets and sizes within the firmware partition. | |
| Required properties: | |
| - compatible : must be "brcm,bcm963xx-cfe-nor-partitions" | |
| Example: | |
| flash@1fc00000 { | |
| compatible = "cfi-flash"; | |
| reg = <0x1fc00000 0x400000>; | |
| bank-width = <2>; | |
| partitions { | |
| compatible = "brcm,bcm963xx-cfe-nor-partitions"; | |
| }; | |
| }; |
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| Broadcom BCM963XX ImageTag Partition Container | |
| ============================================== | |
| Some Broadcom BCM63XX SoC based devices contain additional, non discoverable | |
| partitions or non standard bootloader partition sizes. For these a mixed layout | |
| needs to be used with an explicit firmware partition. | |
| The BCM963XX ImageTag is a simple firmware header describing the offsets and | |
| sizes of the rootfs and kernel parts contained in the firmware. | |
| Required properties: | |
| - compatible : must be "brcm,bcm963xx-imagetag" | |
| Example: | |
| flash@1e000000 { | |
| compatible = "cfi-flash"; | |
| reg = <0x1e000000 0x2000000>; | |
| bank-width = <2>; | |
| partitions { | |
| compatible = "fixed-partitions"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| cfe@0 { | |
| reg = <0x0 0x10000>; | |
| read-only; | |
| }; | |
| firmware@10000 { | |
| reg = <0x10000 0x7d0000>; | |
| compatible = "brcm,bcm963xx-imagetag"; | |
| }; | |
| caldata@7e0000 { | |
| reg = <0x7e0000 0x10000>; | |
| read-only; | |
| }; | |
| nvram@7f0000 { | |
| reg = <0x7f0000 0x10000>; | |
| }; | |
| }; | |
| }; |
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| * Broadcom MIPS (BMIPS) CPUs | |
| Required properties: | |
| - compatible: "brcm,bmips3300", "brcm,bmips4350", "brcm,bmips4380", | |
| "brcm,bmips5000" | |
| - mips-hpt-frequency: This is common to all CPUs in the system so it lives | |
| under the "cpus" node. |
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| ARM Broadcom STB platforms Device Tree Bindings | |
| ----------------------------------------------- | |
| Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants) | |
| SoC shall have the following DT organization: | |
| Required root node properties: | |
| - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb" | |
| example: | |
| / { | |
| #address-cells = <2>; | |
| #size-cells = <2>; | |
| model = "Broadcom STB (bcm7445)"; | |
| compatible = "brcm,bcm7445", "brcm,brcmstb"; | |
| Further, syscon nodes that map platform-specific registers used for general | |
| system control is required: | |
| - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon" | |
| - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl", | |
| "brcm,brcmstb-cpu-biu-ctrl", | |
| "syscon" | |
| - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon" | |
| cpu-biu-ctrl node | |
| ------------------- | |
| SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a | |
| specific Bus Interface Unit (BIU) block which controls and interfaces the CPU | |
| complex to the different Memory Controller Ports (MCP), one per memory | |
| controller (MEMC). This BIU block offers a feature called Write Pairing which | |
| consists in collapsing two adjacent cache lines into a single (bursted) write | |
| transaction towards the memory controller (MEMC) to maximize write bandwidth. | |
| Required properties: | |
| - compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon" | |
| Optional properties: | |
| - brcm,write-pairing: | |
| Boolean property, which when present indicates that the chip | |
| supports write-pairing. | |
| example: | |
| rdb { | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| compatible = "simple-bus"; | |
| ranges = <0 0x00 0xf0000000 0x1000000>; | |
| sun_top_ctrl: syscon@404000 { | |
| compatible = "brcm,bcm7445-sun-top-ctrl", "syscon"; | |
| reg = <0x404000 0x51c>; | |
| }; | |
| hif_cpubiuctrl: syscon@3e2400 { | |
| compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"; | |
| reg = <0x3e2400 0x5b4>; | |
| brcm,write-pairing; | |
| }; | |
| hif_continuation: syscon@452000 { | |
| compatible = "brcm,bcm7445-hif-continuation", "syscon"; | |
| reg = <0x452000 0x100>; | |
| }; | |
| }; | |
| Nodes that allow for support of SMP initialization and reboot are required: | |
| smpboot | |
| ------- | |
| Required properties: | |
| - compatible | |
| The string "brcm,brcmstb-smpboot". | |
| - syscon-cpu | |
| A phandle / integer array property which lets the BSP know the location | |
| of certain CPU power-on registers. | |
| The layout of the property is as follows: | |
| o a phandle to the "hif_cpubiuctrl" syscon node | |
| o offset to the base CPU power zone register | |
| o offset to the base CPU reset register | |
| - syscon-cont | |
| A phandle pointing to the syscon node which describes the CPU boot | |
| continuation registers. | |
| o a phandle to the "hif_continuation" syscon node | |
| example: | |
| smpboot { | |
| compatible = "brcm,brcmstb-smpboot"; | |
| syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>; | |
| syscon-cont = <&hif_continuation>; | |
| }; | |
| reboot | |
| ------- | |
| Required properties | |
| - compatible | |
| The string property "brcm,brcmstb-reboot" for 40nm/28nm chips with | |
| the new SYS_CTRL interface, or "brcm,bcm7038-reboot" for 65nm | |
| chips with the old SUN_TOP_CTRL interface. | |
| - syscon | |
| A phandle / integer array that points to the syscon node which describes | |
| the general system reset registers. | |
| o a phandle to "sun_top_ctrl" | |
| o offset to the "reset source enable" register | |
| o offset to the "software master reset" register | |
| example: | |
| reboot { | |
| compatible = "brcm,brcmstb-reboot"; | |
| syscon = <&sun_top_ctrl 0x304 0x308>; | |
| }; | |
| Power management | |
| ---------------- | |
| For power management (particularly, S2/S3/S5 system suspend), the following SoC | |
| components are needed: | |
| = Always-On control block (AON CTRL) | |
| This hardware provides control registers for the "always-on" (even in low-power | |
| modes) hardware, such as the Power Management State Machine (PMSM). | |
| Required properties: | |
| - compatible : should contain "brcm,brcmstb-aon-ctrl" | |
| - reg : the register start and length for the AON CTRL block | |
| Example: | |
| aon-ctrl@410000 { | |
| compatible = "brcm,brcmstb-aon-ctrl"; | |
| reg = <0x410000 0x400>; | |
| }; | |
| = Memory controllers | |
| A Broadcom STB SoC typically has a number of independent memory controllers, | |
| each of which may have several associated hardware blocks, which are versioned | |
| independently (control registers, DDR PHYs, etc.). One might consider | |
| describing these controllers as a parent "memory controllers" block, which | |
| contains N sub-nodes (one for each controller in the system), each of which is | |
| associated with a number of hardware register resources (e.g., its PHY). See | |
| the example device tree snippet below. | |
| == MEMC (MEMory Controller) | |
| Represents a single memory controller instance. | |
| Required properties: | |
| - compatible : should contain "brcm,brcmstb-memc" and "simple-bus" | |
| Should contain subnodes for any of the following relevant hardware resources: | |
| == DDR PHY control | |
| Control registers for this memory controller's DDR PHY. | |
| Required properties: | |
| - compatible : should contain one of these | |
| "brcm,brcmstb-ddr-phy-v71.1" | |
| "brcm,brcmstb-ddr-phy-v72.0" | |
| "brcm,brcmstb-ddr-phy-v225.1" | |
| "brcm,brcmstb-ddr-phy-v240.1" | |
| "brcm,brcmstb-ddr-phy-v240.2" | |
| - reg : the DDR PHY register range | |
| == DDR SHIMPHY | |
| Control registers for this memory controller's DDR SHIMPHY. | |
| Required properties: | |
| - compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0" | |
| - reg : the DDR SHIMPHY register range | |
| == MEMC DDR control | |
| Sequencer DRAM parameters and control registers. Used for Self-Refresh | |
| Power-Down (SRPD), among other things. | |
| Required properties: | |
| - compatible : should contain one of these | |
| "brcm,brcmstb-memc-ddr-rev-b.2.1" | |
| "brcm,brcmstb-memc-ddr-rev-b.2.2" | |
| "brcm,brcmstb-memc-ddr-rev-b.2.3" | |
| "brcm,brcmstb-memc-ddr-rev-b.3.0" | |
| "brcm,brcmstb-memc-ddr-rev-b.3.1" | |
| "brcm,brcmstb-memc-ddr" | |
| - reg : the MEMC DDR register range | |
| Example: | |
| memory_controllers { | |
| ranges; | |
| compatible = "simple-bus"; | |
| memc@0 { | |
| compatible = "brcm,brcmstb-memc", "simple-bus"; | |
| ranges; | |
| ddr-phy@f1106000 { | |
| compatible = "brcm,brcmstb-ddr-phy-v240.1"; | |
| reg = <0xf1106000 0x21c>; | |
| }; | |
| shimphy@f1108000 { | |
| compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; | |
| reg = <0xf1108000 0xe4>; | |
| }; | |
| memc-ddr@f1102000 { | |
| reg = <0xf1102000 0x800>; | |
| compatible = "brcm,brcmstb-memc-ddr"; | |
| }; | |
| }; | |
| memc@1 { | |
| compatible = "brcm,brcmstb-memc", "simple-bus"; | |
| ranges; | |
| ddr-phy@f1186000 { | |
| compatible = "brcm,brcmstb-ddr-phy-v240.1"; | |
| reg = <0xf1186000 0x21c>; | |
| }; | |
| shimphy@f1188000 { | |
| compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; | |
| reg = <0xf1188000 0xe4>; | |
| }; | |
| memc-ddr@f1182000 { | |
| reg = <0xf1182000 0x800>; | |
| compatible = "brcm,brcmstb-memc-ddr"; | |
| }; | |
| }; | |
| memc@2 { | |
| compatible = "brcm,brcmstb-memc", "simple-bus"; | |
| ranges; | |
| ddr-phy@f1206000 { | |
| compatible = "brcm,brcmstb-ddr-phy-v240.1"; | |
| reg = <0xf1206000 0x21c>; | |
| }; | |
| shimphy@f1208000 { | |
| compatible = "brcm,brcmstb-ddr-shimphy-v1.0"; | |
| reg = <0xf1208000 0xe4>; | |
| }; | |
| memc-ddr@f1202000 { | |
| reg = <0xf1202000 0x800>; | |
| compatible = "brcm,brcmstb-memc-ddr"; | |
| }; | |
| }; | |
| }; |
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| Driver for ARM AXI Bus with Broadcom Plugins (bcma) | |
| Required properties: | |
| - compatible : brcm,bus-axi | |
| - reg : iomem address range of chipcommon core | |
| The cores on the AXI bus are automatically detected by bcma with the | |
| memory ranges they are using and they get registered afterwards. | |
| Automatic detection of the IRQ number is not working on | |
| BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide | |
| them manually through device tree. Use an interrupt-map to specify the | |
| IRQ used by the devices on the bus. The first address is just an index, | |
| because we do not have any special register. | |
| The top-level axi bus may contain children representing attached cores | |
| (devices). This is needed since some hardware details can't be auto | |
| detected (e.g. IRQ numbers). Also some of the cores may be responsible | |
| for extra things, e.g. ChipCommon providing access to the GPIO chip. | |
| Example: | |
| axi@18000000 { | |
| compatible = "brcm,bus-axi"; | |
| reg = <0x18000000 0x1000>; | |
| ranges = <0x00000000 0x18000000 0x00100000>; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| #interrupt-cells = <1>; | |
| interrupt-map-mask = <0x000fffff 0xffff>; | |
| interrupt-map = | |
| /* Ethernet Controller 0 */ | |
| <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, | |
| /* Ethernet Controller 1 */ | |
| <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | |
| /* PCIe Controller 0 */ | |
| <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, | |
| <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, | |
| <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
| <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
| <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
| <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; | |
| chipcommon { | |
| reg = <0x00000000 0x1000>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| }; | |
| }; |
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| BROADCOM Cygnus Audio I2S/TDM/SPDIF controller | |
| Required properties: | |
| - compatible : "brcm,cygnus-audio" | |
| - #address-cells: 32bit valued, 1 cell. | |
| - #size-cells: 32bit valued, 0 cell. | |
| - reg : Should contain audio registers location and length | |
| - reg-names: names of the registers listed in "reg" property | |
| Valid names are "aud" and "i2s_in". "aud" contains a | |
| set of DMA, I2S_OUT and SPDIF registers. "i2s_in" contains | |
| a set of I2S_IN registers. | |
| - clocks: PLL and leaf clocks used by audio ports | |
| - assigned-clocks: PLL and leaf clocks | |
| - assigned-clock-parents: parent clocks of the assigned clocks | |
| (usually the PLL) | |
| - assigned-clock-rates: List of clock frequencies of the | |
| assigned clocks | |
| - clock-names: names of 3 leaf clocks used by audio ports | |
| Valid names are "ch0_audio", "ch1_audio", "ch2_audio" | |
| - interrupts: audio DMA interrupt number | |
| SSP Subnode properties: | |
| - reg: The index of ssp port interface to use | |
| Valid value are 0, 1, 2, or 3 (for spdif) | |
| Example: | |
| cygnus_audio: audio@180ae000 { | |
| compatible = "brcm,cygnus-audio"; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| reg = <0x180ae000 0xafd>, <0x180aec00 0x1f8>; | |
| reg-names = "aud", "i2s_in"; | |
| clocks = <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>, | |
| <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>, | |
| <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>; | |
| assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>, | |
| <&audiopll BCM_CYGNUS_AUDIOPLL_CH0>, | |
| <&audiopll BCM_CYGNUS_AUDIOPLL_CH1>, | |
| <&audiopll BCM_CYGNUS_AUDIOPLL_CH2>; | |
| assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>; | |
| assigned-clock-rates = <1769470191>, | |
| <0>, | |
| <0>, | |
| <0>; | |
| clock-names = "ch0_audio", "ch1_audio", "ch2_audio"; | |
| interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
| ssp0: ssp_port@0 { | |
| reg = <0>; | |
| }; | |
| ssp1: ssp_port@1 { | |
| reg = <1>; | |
| }; | |
| ssp2: ssp_port@2 { | |
| reg = <2>; | |
| }; | |
| spdif: spdif_port@3 { | |
| reg = <3>; | |
| }; | |
| }; |
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| Broadcom Cygnus IOMUX Controller | |
| The Cygnus IOMUX controller supports group based mux configuration. In | |
| addition, certain pins can be muxed to GPIO function individually. | |
| Required properties: | |
| - compatible: | |
| Must be "brcm,cygnus-pinmux" | |
| - reg: | |
| Define the base and range of the I/O address space that contains the Cygnus | |
| IOMUX registers | |
| Properties in subnodes: | |
| - function: | |
| The mux function to select | |
| - groups: | |
| The list of groups to select with a given function | |
| For more details, refer to | |
| Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt | |
| For example: | |
| pinmux: pinmux@0301d0c8 { | |
| compatible = "brcm,cygnus-pinmux"; | |
| reg = <0x0301d0c8 0x1b0>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <&i2s0_default>; | |
| i2s0_default: i2s0_default { | |
| mux { | |
| function = "i2s0"; | |
| groups = "i2s0_0_grp", "i2s0_1_grp"; | |
| }; | |
| }; | |
| }; | |
| List of supported functions and groups in Cygnus: | |
| "i2s0": "i2s0_0_grp", "i2s0_1_grp" | |
| "i2s1": "i2s1_0_grp", "i2s1_1_grp" | |
| "i2s2": "i2s2_0_grp", "i2s2_1_grp", "i2s2_2_grp", "i2s2_3_grp", "i2s2_4_grp" | |
| "spdif": "spdif_grp" | |
| "pwm0": "pwm0_grp" | |
| "pwm1": "pwm1_grp" | |
| "pwm2": "pwm2_grp" | |
| "pwm3": "pwm3_grp" | |
| "pwm4": "pwm4_grp" | |
| "pwm5": "pwm5_grp" | |
| "key": "key0_grp", "key1_grp", "key2_grp", "key3_grp", "key4_grp", "key5_grp", | |
| "key6_grp", "key7_grp", "key8_grp", "key9_grp", "key10_grp", "key11_grp", | |
| "key12_grp", "key13_grp", "key14_grp", "key15_grp" | |
| "audio_dte": "audio_dte0_grp", "audio_dte1_grp", "audio_dte2_grp", "audio_dte3_grp" | |
| "smart_card0": "smart_card0_grp", "smart_card0_fcb_grp" | |
| "smart_card1": "smart_card1_grp", "smart_card1_fcb_grp" | |
| "spi0": "spi0_grp" | |
| "spi1": "spi1_grp" | |
| "spi2": "spi2_grp" | |
| "spi3": "spi3_grp" | |
| "spi4": "spi4_0_grp", "spi4_1_grp" | |
| "spi5": "spi5_grp" | |
| "sw_led0": "sw_led0_0_grp", "sw_led0_1_grp" | |
| "sw_led1": "sw_led1_grp" | |
| "sw_led2": "sw_led2_0_grp", "sw_led2_1_grp" | |
| "d1w": "d1w_grp" | |
| "lcd": "lcd_grp" | |
| "sram": "sram_0_grp", "sram_1_grp" | |
| "uart0": "uart0_grp" | |
| "uart1": "uart1_grp", "uart1_dte_grp" | |
| "uart2": "uart2_grp" | |
| "uart3": "uart3_grp" | |
| "uart4": "uart4_grp" | |
| "qspi": "qspi_0_grp", "qspi_1_grp" | |
| "nand": "nand_grp" | |
| "sdio0": "sdio0_grp", "sdio0_cd_grp", "sdio0_mmc_grp" | |
| "sdio1": "sdio1_data_0_grp", "sdio1_data_1_grp", "sdio1_cd_grp", | |
| "sdio1_led_grp", "sdio1_mmc_grp" | |
| "can0": "can0_grp" | |
| "can1": "can1_grp" | |
| "cam": "cam_led_grp", "cam_0_grp", "cam_1_grp" | |
| "bsc1": "bsc1_grp" | |
| "pcie_clkreq": "pcie_clkreq_grp" | |
| "usb0_oc": "usb0_oc_grp" | |
| "usb1_oc": "usb1_oc_grp" | |
| "usb2_oc": "usb2_oc_grp" |
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| Broadcom iProc Chip Device Resource Unit (CDRU) | |
| Various Broadcom iProc SoCs have a set of registers that provide various | |
| chip specific device and resource configurations. This node allows access to | |
| these CDRU registers via syscon. | |
| Required properties: | |
| - compatible: should contain: | |
| "brcm,sr-cdru", "syscon" for Stingray | |
| - reg: base address and range of the CDRU registers | |
| Example: | |
| cdru: syscon@6641d000 { | |
| compatible = "brcm,sr-cdru", "syscon"; | |
| reg = <0 0x6641d000 0 0x400>; | |
| }; |
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| Broadcom FlexRM Ring Manager | |
| ============================ | |
| The Broadcom FlexRM ring manager provides a set of rings which can be | |
| used to submit work to offload engines. An SoC may have multiple FlexRM | |
| hardware blocks. There is one device tree entry per FlexRM block. The | |
| FlexRM driver will create a mailbox-controller instance for given FlexRM | |
| hardware block where each mailbox channel is a separate FlexRM ring. | |
| Required properties: | |
| -------------------- | |
| - compatible: Should be "brcm,iproc-flexrm-mbox" | |
| - reg: Specifies base physical address and size of the FlexRM | |
| ring registers | |
| - msi-parent: Phandles (and potential Device IDs) to MSI controllers | |
| The FlexRM engine will send MSIs (instead of wired | |
| interrupts) to CPU. There is one MSI for each FlexRM ring. | |
| Refer devicetree/bindings/interrupt-controller/msi.txt | |
| - #mbox-cells: Specifies the number of cells needed to encode a mailbox | |
| channel. This should be 3. | |
| The 1st cell is the mailbox channel number. | |
| The 2nd cell contains MSI completion threshold. This is the | |
| number of completion messages for which FlexRM will inject | |
| one MSI interrupt to CPU. | |
| The 3nd cell contains MSI timer value representing time for | |
| which FlexRM will wait to accumulate N completion messages | |
| where N is the value specified by 2nd cell above. If FlexRM | |
| does not get required number of completion messages in time | |
| specified by this cell then it will inject one MSI interrupt | |
| to CPU provided atleast one completion message is available. | |
| Optional properties: | |
| -------------------- | |
| - dma-coherent: Present if DMA operations made by the FlexRM engine (such | |
| as DMA descriptor access, access to buffers pointed by DMA | |
| descriptors and read/write pointer updates to DDR) are | |
| cache coherent with the CPU. | |
| Example: | |
| -------- | |
| crypto_mbox: mbox@67000000 { | |
| compatible = "brcm,iproc-flexrm-mbox"; | |
| reg = <0x67000000 0x200000>; | |
| msi-parent = <&gic_its 0x7f00>; | |
| #mbox-cells = <3>; | |
| }; | |
| crypto@672c0000 { | |
| compatible = "brcm,spu2-v2-crypto"; | |
| reg = <0x672c0000 0x1000>; | |
| mboxes = <&crypto_mbox 0 0x1 0xffff>, | |
| <&crypto_mbox 1 0x1 0xffff>, | |
| <&crypto_mbox 16 0x1 0xffff>, | |
| <&crypto_mbox 17 0x1 0xffff>, | |
| <&crypto_mbox 30 0x1 0xffff>, | |
| <&crypto_mbox 31 0x1 0xffff>; | |
| }; |
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| Broadcom iProc GPIO/PINCONF Controller | |
| Required properties: | |
| - compatible: | |
| "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that | |
| supports full-featured pinctrl and GPIO functions used in various iProc | |
| based SoCs | |
| May contain an SoC-specific compatibility string to accommodate any | |
| SoC-specific features | |
| "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or | |
| "brcm,cygnus-crmu-gpio" for Cygnus SoCs | |
| "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support | |
| disabled | |
| "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general | |
| pinctrl support completely disabled in this IP block. In Stingray, a | |
| different IP block is used to handle pinctrl related functions | |
| - reg: | |
| Define the base and range of the I/O address space that contains SoC | |
| GPIO/PINCONF controller registers | |
| - ngpios: | |
| Total number of in-use slots in GPIO controller | |
| - #gpio-cells: | |
| Must be two. The first cell is the GPIO pin number (within the | |
| controller's pin space) and the second cell is used for the following: | |
| bit[0]: polarity (0 for active high and 1 for active low) | |
| - gpio-controller: | |
| Specifies that the node is a GPIO controller | |
| Optional properties: | |
| - interrupts: | |
| Interrupt ID | |
| - interrupt-controller: | |
| Specifies that the node is an interrupt controller | |
| - gpio-ranges: | |
| Specifies the mapping between gpio controller and pin-controllers pins. | |
| This requires 4 fields in cells defined as - | |
| 1. Phandle of pin-controller. | |
| 2. GPIO base pin offset. | |
| 3 Pin-control base pin offset. | |
| 4. number of gpio pins which are linearly mapped from pin base. | |
| Supported generic PINCONF properties in child nodes: | |
| - pins: | |
| The list of pins (within the controller's own pin space) that properties | |
| in the node apply to. Pin names are "gpio-<pin>" | |
| - bias-disable: | |
| Disable pin bias | |
| - bias-pull-up: | |
| Enable internal pull up resistor | |
| - bias-pull-down: | |
| Enable internal pull down resistor | |
| - drive-strength: | |
| Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) | |
| Example: | |
| gpio_ccm: gpio@1800a000 { | |
| compatible = "brcm,cygnus-ccm-gpio"; | |
| reg = <0x1800a000 0x50>, | |
| <0x0301d164 0x20>; | |
| ngpios = <24>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-controller; | |
| touch_pins: touch_pins { | |
| pwr: pwr { | |
| pins = "gpio-0"; | |
| drive-strength = <16>; | |
| }; | |
| event: event { | |
| pins = "gpio-1"; | |
| bias-pull-up; | |
| }; | |
| }; | |
| }; | |
| gpio_asiu: gpio@180a5000 { | |
| compatible = "brcm,cygnus-asiu-gpio"; | |
| reg = <0x180a5000 0x668>; | |
| ngpios = <146>; | |
| #gpio-cells = <2>; | |
| gpio-controller; | |
| interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-controller; | |
| gpio-ranges = <&pinctrl 0 42 1>, | |
| <&pinctrl 1 44 3>; | |
| }; | |
| /* | |
| * Touchscreen that uses the CCM GPIO 0 and 1 | |
| */ | |
| tsc { | |
| ... | |
| ... | |
| gpio-pwr = <&gpio_ccm 0 0>; | |
| gpio-event = <&gpio_ccm 1 0>; | |
| }; | |
| /* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */ | |
| bluetooth { | |
| ... | |
| ... | |
| bcm,rfkill-bank-sel = <&gpio_asiu 5 1> | |
| } |
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| Broadcom iProc Multi Host Bridge (MHB) | |
| Certain Broadcom iProc SoCs have a multi host bridge (MHB) block that controls | |
| the connection and configuration of 1) internal PCIe serdes; 2) PCIe endpoint | |
| interface; 3) access to the Nitro (network processing) engine | |
| This node allows access to these MHB registers via syscon. | |
| Required properties: | |
| - compatible: should contain: | |
| "brcm,sr-mhb", "syscon" for Stingray | |
| - reg: base address and range of the MHB registers | |
| Example: | |
| mhb: syscon@60401000 { | |
| compatible = "brcm,sr-mhb", "syscon"; | |
| reg = <0 0x60401000 0 0x38c>; | |
| }; |
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| The PDC driver manages data transfer to and from various offload engines | |
| on some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is | |
| one device tree entry per block. On some chips, the PDC functionality is | |
| handled by the FA2 (Northstar Plus). | |
| Required properties: | |
| - compatible : Should be "brcm,iproc-pdc-mbox" or "brcm,iproc-fa2-mbox" for | |
| FA2/Northstar Plus. | |
| - reg: Should contain PDC registers location and length. | |
| - interrupts: Should contain the IRQ line for the PDC. | |
| - #mbox-cells: 1 | |
| - brcm,rx-status-len: Length of metadata preceding received frames, in bytes. | |
| Optional properties: | |
| - brcm,use-bcm-hdr: present if a BCM header precedes each frame. | |
| Example: | |
| pdc0: iproc-pdc0@612c0000 { | |
| compatible = "brcm,iproc-pdc-mbox"; | |
| reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */ | |
| interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | |
| #mbox-cells = <1>; /* one cell per mailbox channel */ | |
| brcm,rx-status-len = <32>; | |
| brcm,use-bcm-hdr; | |
| }; |
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| * Broadcom SBA RAID engine | |
| Required properties: | |
| - compatible: Should be one of the following | |
| "brcm,iproc-sba" | |
| "brcm,iproc-sba-v2" | |
| The "brcm,iproc-sba" has support for only 6 PQ coefficients | |
| The "brcm,iproc-sba-v2" has support for only 30 PQ coefficients | |
| - mboxes: List of phandle and mailbox channel specifiers | |
| Example: | |
| raid_mbox: mbox@67400000 { | |
| ... | |
| #mbox-cells = <3>; | |
| ... | |
| }; | |
| raid0 { | |
| compatible = "brcm,iproc-sba-v2"; | |
| mboxes = <&raid_mbox 0 0x1 0xffff>, | |
| <&raid_mbox 1 0x1 0xffff>, | |
| <&raid_mbox 2 0x1 0xffff>, | |
| <&raid_mbox 3 0x1 0xffff>, | |
| <&raid_mbox 4 0x1 0xffff>, | |
| <&raid_mbox 5 0x1 0xffff>, | |
| <&raid_mbox 6 0x1 0xffff>, | |
| <&raid_mbox 7 0x1 0xffff>; | |
| }; |
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| * Broadcom's IPROC Touchscreen Controller | |
| Required properties: | |
| - compatible: must be "brcm,iproc-touchscreen" | |
| - ts_syscon: handler of syscon node defining physical base | |
| address of the controller and length of memory mapped region. | |
| If this property is selected please make sure MFD_SYSCON config | |
| is enabled in the defconfig file. | |
| - clocks: The clock provided by the SOC to driver the tsc | |
| - clock-names: name for the clock | |
| - interrupts: The touchscreen controller's interrupt | |
| - address-cells: Specify the number of u32 entries needed in child nodes. | |
| Should set to 1. | |
| - size-cells: Specify number of u32 entries needed to specify child nodes size | |
| in reg property. Should set to 1. | |
| Optional properties: | |
| - scanning_period: Time between scans. Each step is 1024 us. Valid 1-256. | |
| - debounce_timeout: Each step is 512 us. Valid 0-255 | |
| - settling_timeout: The settling duration (in ms) is the amount of time | |
| the tsc waits to allow the voltage to settle after | |
| turning on the drivers in detection mode. | |
| Valid values: 0-11 | |
| 0 = 0.008 ms | |
| 1 = 0.01 ms | |
| 2 = 0.02 ms | |
| 3 = 0.04 ms | |
| 4 = 0.08 ms | |
| 5 = 0.16 ms | |
| 6 = 0.32 ms | |
| 7 = 0.64 ms | |
| 8 = 1.28 ms | |
| 9 = 2.56 ms | |
| 10 = 5.12 ms | |
| 11 = 10.24 ms | |
| - touch_timeout: The continuous number of scan periods in which touch is | |
| not detected before the controller returns to idle state. | |
| Valid values 0-255. | |
| - average_data: Number of data samples which are averaged before a final | |
| data point is placed into the FIFO | |
| Valid values 0-7 | |
| 0 = 1 sample | |
| 1 = 2 samples | |
| 2 = 4 samples | |
| 3 = 8 samples | |
| 4 = 16 samples | |
| 5 = 32 samples | |
| 6 = 64 samples | |
| 7 = 128 samples | |
| - fifo_threshold: Interrupt is generated whenever the number of fifo | |
| entries exceeds this value | |
| Valid values 0-31 | |
| - touchscreen-size-x: horizontal resolution of touchscreen (in pixels) | |
| - touchscreen-size-y: vertical resolution of touchscreen (in pixels) | |
| - touchscreen-fuzz-x: horizontal noise value of the absolute input | |
| device (in pixels) | |
| - touchscreen-fuzz-y: vertical noise value of the absolute input | |
| device (in pixels) | |
| - touchscreen-inverted-x: X axis is inverted (boolean) | |
| - touchscreen-inverted-y: Y axis is inverted (boolean) | |
| Example: An example of touchscreen node | |
| ts_adc_syscon: ts_adc_syscon@180a6000 { | |
| compatible = "brcm,iproc-ts-adc-syscon","syscon"; | |
| reg = <0x180a6000 0xc30>; | |
| }; | |
| touchscreen: touchscreen@180a6000 { | |
| compatible = "brcm,iproc-touchscreen"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| ts_syscon = <&ts_adc_syscon>; | |
| clocks = <&adc_clk>; | |
| clock-names = "tsc_clk"; | |
| interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
| scanning_period = <5>; | |
| debounce_timeout = <40>; | |
| settling_timeout = <7>; | |
| touch_timeout = <10>; | |
| average_data = <5>; | |
| fifo_threshold = <1>; | |
| /* Touchscreen is rotated 180 degrees. */ | |
| touchscreen-inverted-x; | |
| touchscreen-inverted-y; | |
| }; |
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| Broadcom Kona Family Clocks | |
| This binding is associated with Broadcom SoCs having "Kona" style | |
| clock control units (CCUs). A CCU is a clock provider that manages | |
| a set of clock signals. Each CCU is represented by a node in the | |
| device tree. | |
| This binding uses the common clock binding: | |
| Documentation/devicetree/bindings/clock/clock-bindings.txt | |
| Required properties: | |
| - compatible | |
| Shall have a value of the form "brcm,<model>-<which>-ccu", | |
| where <model> is a Broadcom SoC model number and <which> is | |
| the name of a defined CCU. For example: | |
| "brcm,bcm11351-root-ccu" | |
| The compatible strings used for each supported SoC family | |
| are defined below. | |
| - reg | |
| Shall define the base and range of the address space | |
| containing clock control registers | |
| - #clock-cells | |
| Shall have value <1>. The permitted clock-specifier values | |
| are defined below. | |
| - clock-output-names | |
| Shall be an ordered list of strings defining the names of | |
| the clocks provided by the CCU. | |
| Device tree example: | |
| slave_ccu: slave_ccu { | |
| compatible = "brcm,bcm11351-slave-ccu"; | |
| reg = <0x3e011000 0x0f00>; | |
| #clock-cells = <1>; | |
| clock-output-names = "uartb", | |
| "uartb2", | |
| "uartb3", | |
| "uartb4"; | |
| }; | |
| ref_crystal_clk: ref_crystal { | |
| #clock-cells = <0>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <26000000>; | |
| }; | |
| uart@3e002000 { | |
| compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; | |
| reg = <0x3e002000 0x1000>; | |
| clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; | |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
| reg-shift = <2>; | |
| reg-io-width = <4>; | |
| }; | |
| BCM281XX family | |
| --------------- | |
| CCU compatible string values for SoCs in the BCM281XX family are: | |
| "brcm,bcm11351-root-ccu" | |
| "brcm,bcm11351-aon-ccu" | |
| "brcm,bcm11351-hub-ccu" | |
| "brcm,bcm11351-master-ccu" | |
| "brcm,bcm11351-slave-ccu" | |
| The following table defines the set of CCUs and clock specifiers for | |
| BCM281XX family clocks. When a clock consumer references a clocks, | |
| its symbolic specifier (rather than its numeric index value) should | |
| be used. These specifiers are defined in: | |
| "include/dt-bindings/clock/bcm281xx.h" | |
| CCU Clock Type Index Specifier | |
| --- ----- ---- ----- --------- | |
| root frac_1m peri 0 BCM281XX_ROOT_CCU_FRAC_1M | |
| aon hub_timer peri 0 BCM281XX_AON_CCU_HUB_TIMER | |
| aon pmu_bsc peri 1 BCM281XX_AON_CCU_PMU_BSC | |
| aon pmu_bsc_var peri 2 BCM281XX_AON_CCU_PMU_BSC_VAR | |
| hub tmon_1m peri 0 BCM281XX_HUB_CCU_TMON_1M | |
| master sdio1 peri 0 BCM281XX_MASTER_CCU_SDIO1 | |
| master sdio2 peri 1 BCM281XX_MASTER_CCU_SDIO2 | |
| master sdio3 peri 2 BCM281XX_MASTER_CCU_SDIO3 | |
| master sdio4 peri 3 BCM281XX_MASTER_CCU_SDIO4 | |
| master dmac peri 4 BCM281XX_MASTER_CCU_DMAC | |
| master usb_ic peri 5 BCM281XX_MASTER_CCU_USB_IC | |
| master hsic2_48m peri 6 BCM281XX_MASTER_CCU_HSIC_48M | |
| master hsic2_12m peri 7 BCM281XX_MASTER_CCU_HSIC_12M | |
| slave uartb peri 0 BCM281XX_SLAVE_CCU_UARTB | |
| slave uartb2 peri 1 BCM281XX_SLAVE_CCU_UARTB2 | |
| slave uartb3 peri 2 BCM281XX_SLAVE_CCU_UARTB3 | |
| slave uartb4 peri 3 BCM281XX_SLAVE_CCU_UARTB4 | |
| slave ssp0 peri 4 BCM281XX_SLAVE_CCU_SSP0 | |
| slave ssp2 peri 5 BCM281XX_SLAVE_CCU_SSP2 | |
| slave bsc1 peri 6 BCM281XX_SLAVE_CCU_BSC1 | |
| slave bsc2 peri 7 BCM281XX_SLAVE_CCU_BSC2 | |
| slave bsc3 peri 8 BCM281XX_SLAVE_CCU_BSC3 | |
| slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM | |
| BCM21664 family | |
| --------------- | |
| CCU compatible string values for SoCs in the BCM21664 family are: | |
| "brcm,bcm21664-root-ccu" | |
| "brcm,bcm21664-aon-ccu" | |
| "brcm,bcm21664-master-ccu" | |
| "brcm,bcm21664-slave-ccu" | |
| The following table defines the set of CCUs and clock specifiers for | |
| BCM21664 family clocks. When a clock consumer references a clocks, | |
| its symbolic specifier (rather than its numeric index value) should | |
| be used. These specifiers are defined in: | |
| "include/dt-bindings/clock/bcm21664.h" | |
| CCU Clock Type Index Specifier | |
| --- ----- ---- ----- --------- | |
| root frac_1m peri 0 BCM21664_ROOT_CCU_FRAC_1M | |
| aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER | |
| master sdio1 peri 0 BCM21664_MASTER_CCU_SDIO1 | |
| master sdio2 peri 1 BCM21664_MASTER_CCU_SDIO2 | |
| master sdio3 peri 2 BCM21664_MASTER_CCU_SDIO3 | |
| master sdio4 peri 3 BCM21664_MASTER_CCU_SDIO4 | |
| master sdio1_sleep peri 4 BCM21664_MASTER_CCU_SDIO1_SLEEP | |
| master sdio2_sleep peri 5 BCM21664_MASTER_CCU_SDIO2_SLEEP | |
| master sdio3_sleep peri 6 BCM21664_MASTER_CCU_SDIO3_SLEEP | |
| master sdio4_sleep peri 7 BCM21664_MASTER_CCU_SDIO4_SLEEP | |
| slave uartb peri 0 BCM21664_SLAVE_CCU_UARTB | |
| slave uartb2 peri 1 BCM21664_SLAVE_CCU_UARTB2 | |
| slave uartb3 peri 2 BCM21664_SLAVE_CCU_UARTB3 | |
| slave uartb4 peri 3 BCM21664_SLAVE_CCU_UARTB4 | |
| slave bsc1 peri 4 BCM21664_SLAVE_CCU_BSC1 | |
| slave bsc2 peri 5 BCM21664_SLAVE_CCU_BSC2 | |
| slave bsc3 peri 6 BCM21664_SLAVE_CCU_BSC3 | |
| slave bsc4 peri 7 BCM21664_SLAVE_CCU_BSC4 |
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| Broadcom Kona Family GPIO | |
| ========================= | |
| This GPIO driver is used in the following Broadcom SoCs: | |
| BCM11130, BCM11140, BCM11351, BCM28145, BCM28155 | |
| The Broadcom GPIO Controller IP can be configured prior to synthesis to | |
| support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The | |
| GPIO controller only supports edge, not level, triggering of interrupts. | |
| Required properties | |
| ------------------- | |
| - compatible: "brcm,bcm11351-gpio", "brcm,kona-gpio" | |
| - reg: Physical base address and length of the controller's registers. | |
| - interrupts: The interrupt outputs from the controller. There is one GPIO | |
| interrupt per GPIO bank. The number of interrupts listed depends on the | |
| number of GPIO banks on the SoC. The interrupts must be ordered by bank, | |
| starting with bank 0. There is always a 1:1 mapping between banks and | |
| IRQs. | |
| - #gpio-cells: Should be <2>. The first cell is the pin number, the second | |
| cell is used to specify optional parameters: | |
| - bit 0 specifies polarity (0 for normal, 1 for inverted) | |
| See also "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt. | |
| - #interrupt-cells: Should be <2>. The first cell is the GPIO number. The | |
| second cell is used to specify flags. The following subset of flags is | |
| supported: | |
| - trigger type (bits[1:0]): | |
| 1 = low-to-high edge triggered. | |
| 2 = high-to-low edge triggered. | |
| 3 = low-to-high or high-to-low edge triggered | |
| Valid values are 1, 2, 3 | |
| See also .../devicetree/bindings/interrupt-controller/interrupts.txt. | |
| - gpio-controller: Marks the device node as a GPIO controller. | |
| - interrupt-controller: Marks the device node as an interrupt controller. | |
| Example: | |
| gpio: gpio@35003000 { | |
| compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio"; | |
| reg = <0x35003000 0x800>; | |
| interrupts = | |
| <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH | |
| GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
| #gpio-cells = <2>; | |
| #interrupt-cells = <2>; | |
| gpio-controller; | |
| interrupt-controller; | |
| }; |
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| Broadcom Kona Family I2C | |
| ========================= | |
| This I2C controller is used in the following Broadcom SoCs: | |
| BCM11130 | |
| BCM11140 | |
| BCM11351 | |
| BCM28145 | |
| BCM28155 | |
| Required Properties | |
| ------------------- | |
| - compatible: "brcm,bcm11351-i2c", "brcm,kona-i2c" | |
| - reg: Physical base address and length of controller registers | |
| - interrupts: The interrupt number used by the controller | |
| - clocks: clock specifier for the kona i2c external clock | |
| - clock-frequency: The I2C bus frequency in Hz | |
| - #address-cells: Should be <1> | |
| - #size-cells: Should be <0> | |
| Refer to clocks/clock-bindings.txt for generic clock consumer | |
| properties. | |
| Example: | |
| i2c@3e016000 { | |
| compatible = "brcm,bcm11351-i2c","brcm,kona-i2c"; | |
| reg = <0x3e016000 0x80>; | |
| interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&bsc1_clk>; | |
| clock-frequency = <400000>; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| }; |
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| Broadcom Kona PWM controller device tree bindings | |
| This controller has 6 channels. | |
| Required Properties : | |
| - compatible: should contain "brcm,kona-pwm" | |
| - reg: physical base address and length of the controller's registers | |
| - clocks: phandle + clock specifier pair for the external clock | |
| - #pwm-cells: Should be 3. See pwm.yaml in this directory for a | |
| description of the cells format. | |
| Refer to clocks/clock-bindings.txt for generic clock consumer properties. | |
| Example: | |
| pwm: pwm@3e01a000 { | |
| compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm"; | |
| reg = <0x3e01a000 0xc4>; | |
| clocks = <&pwm_clk>; | |
| #pwm-cells = <3>; | |
| }; |
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