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Register Definitions for EPSON C17 MCU
Raw
c17_regs.h
#define REG(addr) (*(volatile unsigned int *)(addr))
#define REG32(addr) (*(volatile unsigned long int *)(addr))
typedef union {
unsigned int reg;
struct {
unsigned b0:1;
unsigned b1:1;
unsigned b2:1;
unsigned b3:1;
unsigned b4:1;
unsigned b5:1;
unsigned b6:1;
unsigned b7:1;
} bit;
} RegBit;
typedef union {
unsigned int reg;
struct {
unsigned lower:3;
const unsigned margin:5;
unsigned upper:3;
} bits;
} ILV_RegBit;
// MISC
#define MSCPROT REG(0x4000)
#define MSCIRAMSZ REG(0x4002)
#define MSCTTBRL REG(0x4004)
#define MSCTTBRH REG(0x4006)
#define MSTTBR REG32(0x4004)
#define MSCPSR REG(0x4008)
// PWG2
#define PWGCTL REG(0x4020)
#define PWGTIM REG(0x4022)
#define PWGINTF REG(0x4024)
#define PWGINTE REG(0x4026)
// CLG
#define CLGSCLK REG(0x4040)
#define CLGOSC REG(0x4042)
#define CLGIOSC REG(0x4044)
#define CLGOSC1 REG(0x4046)
#define CLGOSC3 REG(0x4048)
#define CLGINTF REG(0x404c)
#define CLGINTE REG(0x404e)
#define CLGFOUT REG(0x4050)
#define CLGTRIM REG(0x4052)
// ITC
#define ITCLV0 REG(0x4080)
#define ITCLV1 REG(0x4082)
#define ITCLV2 REG(0x4084)
#define ITCLV3 REG(0x4086)
#define ITCLV4 REG(0x4088)
#define ITCLV5 REG(0x408a)
#define ITCLV6 REG(0x408c)
#define ITCLV7 REG(0x408e)
#define ITCLV8 REG(0x4090)
#define ITCLV9 REG(0x4082)
#define ITCLV10 REG(0x4084)
#define ITCLV11 REG(0x4086)
#define ILV_SVD (((volatile ILV_RegBit *)&ITCLV0)->bits.lower)
#define ILV_PPORT (((volatile ILV_RegBit *)&ITCLV0)->bits.upper)
#define ILV_PWG2 (((volatile ILV_RegBit *)&ITCLV1)->bits.lower)
#define ILV_CLG (((volatile ILV_RegBit *)&ITCLV1)->bits.upper)
#define ILV_RTCA_0 (((volatile ILV_RegBit *)&ITCLV2)->bits.lower)
#define ILV_T16_0 (((volatile ILV_RegBit *)&ITCLV2)->bits.upper)
#define ILV_UART_0 (((volatile ILV_RegBit *)&ITCLV3)->bits.lower)
#define ILV_T16_1 (((volatile ILV_RegBit *)&ITCLV3)->bits.upper)
#define ILV_SPIA_0 (((volatile ILV_RegBit *)&ITCLV4)->bits.lower)
#define ILV_I2C_0 (((volatile ILV_RegBit *)&ITCLV4)->bits.upper)
#define ILV_T16B_0 (((volatile ILV_RegBit *)&ITCLV5)->bits.lower)
#define ILV_T16B_1 (((volatile ILV_RegBit *)&ITCLV5)->bits.upper)
#define ILV_UART_1 (((volatile ILV_RegBit *)&ITCLV6)->bits.lower)
#define ILV_SNDA_0 (((volatile ILV_RegBit *)&ITCLV6)->bits.upper)
#define ILV_REMC2_0 (((volatile ILV_RegBit *)&ITCLV7)->bits.lower)
#define ILV_LCD8B (((volatile ILV_RegBit *)&ITCLV7)->bits.upper)
#define ILV_RFC_0 (((volatile ILV_RegBit *)&ITCLV8)->bits.lower)
#define ILV_RFC_1 (((volatile ILV_RegBit *)&ITCLV8)->bits.upper)
#define ILV_T16_2 (((volatile ILV_RegBit *)&ITCLV9)->bits.lower)
#define ILV_SPIA_1 (((volatile ILV_RegBit *)&ITCLV9)->bits.upper)
#define ILV_T16_3 (((volatile ILV_RegBit *)&ITCLV10)->bits.lower)
#define ILV_ADC12_0 (((volatile ILV_RegBit *)&ITCLV10)->bits.upper)
#define ILV_T16B_2 (((volatile ILV_RegBit *)&ITCLV11)->bits.lower)
// WDT
#define WDTCLK REG(0x40a0)
#define WDTCTL REG(0x40a2)
// RTCA
#define RTCCTL REG(0x40c0)
#define RTCALM1 REG(0x40c2)
#define RTCALM2 REG(0x40c4)
#define RTCSWCTL REG(0x40c6)
#define RTCSEC REG(0x40c8)
#define RTCHUR REG(0x49ca)
#define RTCMON REG(0x40cc)
#define RTCYAR REG(0x40ce)
#define RTCINTF REG(0x40d0)
#define RTCINTE REG(0x40d2)
// SVD
#define SVDCLK REG(0x4100)
#define SVDCTL REG(0x4102)
#define SVDINTF REG(0x4104)
#define SVDINTE REG(0x4016)
// T16_0
#define T16_0CLK REG(0x4160)
#define T16_0MOD REG(0x4162)
#define T16_0CTL REG(0x4164)
#define T16_0TR REG(0x4166)
#define T16_0TC REG(0x4168)
#define T16_0INTF REG(0x416a)
#define T16_0INTE REG(0x416c)
// FLASHC
#define FLASHCWAIT REG(0x41b0)
// PPORT
#define P0DAT REG(0x4200)
#define P0IOEN REG(0x4202)
#define P0RCTL REG(0x4204)
#define P0INTF REG(0x4206)
#define P0INTCTL REG(0x4208)
#define P0CHATEN REG(0x420a)
#define P0MODSEL REG(0x420c)
#define P0FNCSEL REG(0x420e)
#define P1DAT REG(0x4210)
#define P1IOEN REG(0x4212)
#define P1RCTL REG(0x4214)
#define P1INTF REG(0x4216)
#define P1INTCTL REG(0x4218)
#define P1CHATEN REG(0x421a)
#define P1MODSEL REG(0x421c)
#define P1FNCSEL REG(0x421e)
#define P2DAT REG(0x4220)
#define P2IOEN REG(0x4222)
#define P2RCTL REG(0x4224)
#define P2INTF REG(0x4226)
#define P2INTCTL REG(0x4228)
#define P2CHATEN REG(0x422a)
#define P2MODSEL REG(0x422c)
#define P2FNCSEL REG(0x422e)
#define P3DAT REG(0x4230)
#define P3IOEN REG(0x4232)
#define P3RCTL REG(0x4234)
#define P3INTF REG(0x4236)
#define P3INTCTL REG(0x4238)
#define P3CHATEN REG(0x423a)
#define P3MODSEL REG(0x423c)
#define P3FNCSEL REG(0x423e)
#define P4DAT REG(0x4240)
#define P4IOEN REG(0x4242)
#define P4RCTL REG(0x4244)
#define P4INTF REG(0x4246)
#define P4INTCTL REG(0x4248)
#define P4CHATEN REG(0x424a)
#define P4MODSEL REG(0x424c)
#define P4FNCSEL REG(0x424e)
#define P5DAT REG(0x4250)
#define P5IOEN REG(0x4252)
#define P5RCTL REG(0x4254)
#define P5INTF REG(0x4256)
#define P5INTCTL REG(0x4258)
#define P5CHATEN REG(0x425a)
#define P5MODSEL REG(0x425c)
#define P5FNCSEL REG(0x425e)
#define P6DAT REG(0x4260)
#define P6IOEN REG(0x4262)
#define P6RCTL REG(0x4264)
#define P6INTF REG(0x4266)
#define P6INTCTL REG(0x4268)
#define P6CHATEN REG(0x426a)
#define P6MODSEL REG(0x426c)
#define P6FNCSEL REG(0x426e)
#define P7DAT REG(0x4270)
#define P7IOEN REG(0x4272)
#define P7RCTL REG(0x4274)
#define P7INTF REG(0x4276)
#define P7INTCTL REG(0x4278)
#define P7CHATEN REG(0x427a)
#define P7MODSEL REG(0x427c)
#define P7FNCSEL REG(0x427e)
#define P8DAT REG(0x4280)
#define P8IOEN REG(0x4282)
#define P8RCTL REG(0x4284)
#define P8INTF REG(0x4286)
#define P8INTCTL REG(0x4288)
#define P8CHATEN REG(0x428a)
#define P8MODSEL REG(0x428c)
#define P8FNCSEL REG(0x428e)
#define PDDAT REG(0x42d0)
#define PDIOEN REG(0x42d2)
#define PDRCTL REG(0x42d4)
#define PDMODSEL REG(0x42dc)
#define PDFNCSEL REG(0x42de)
#define PCLK REG(0x42e0)
#define PINTFGRP REG(0x42e2)
// UPMUX
#define P0UPMUX0 REG(0x4300)
#define P0UPMUX1 REG(0x4302)
#define P0UPMUX2 REG(0x4304)
#define P0UPMUX3 REG(0x4306)
#define P1UPMUX0 REG(0x4308)
#define P1UPMUX1 REG(0x430a)
#define P1UPMUX2 REG(0x430c)
#define P1UPMUX3 REG(0x430e)
#define P2UPMUX0 REG(0x4310)
#define P2UPMUX1 REG(0x4312)
#define P2UPMUX2 REG(0x4314)
#define P2UPMUX3 REG(0x4316)
#define P3UPMUX0 REG(0x4318)
#define P3UPMUX1 REG(0x431a)
#define P3UPMUX2 REG(0x431c)
#define P3UPMUX3 REG(0x431e)
// UART0
#define UA0CLK REG(0x4380)
#define UA0MOD REG(0x4382)
#define UA0BR REG(0x4384)
#define UA0CTL REG(0x4386)
#define UA0TXD REG(0x4388)
#define UA0RXD REG(0x438a)
#define UA0INTF REG(0x438c)
#define UA0INTE REG(0x438e)
// T16_1
#define T16_1CLK REG(0x43a0)
#define T16_1MOD REG(0x43a2)
#define T16_1CTL REG(0x43a4)
#define T16_1TR REG(0x43a6)
#define T16_1TC REG(0x43a8)
#define T16_1INTF REG(0x43aa)
#define T16_1INTE REG(0x43ac)
// SPIA0
#define SPI0MOD REG(0x43b0)
#define SPI0CTL REG(0x43b2)
#define SPI0TXD REG(0x43b4)
#define SPI0RXD REG(0x43b6)
#define SPI0INTF REG(0x43b8)
#define SPI0INTE REG(0x43ba)
// I2C
#define I2C0CLK REG(0x43c0)
#define I2C0MOD REG(0x43c2)
#define I2C0BR REG(0x43c4)
#define I2C0OADR REG(0x43c8)
#define I2C0CTL REG(0x43ca)
#define I2C0TXD REG(0x43cc)
#define I2C0RXD REG(0x43ce)
#define I2C0INTF REG(0x43d0)
#define I2C0INTE REG(0x43d2)
// T16B0
#define T16B0CLK REG(0x5000)
#define T16B0CTL REG(0x5002)
#define T16B0MC REG(0x5004)
#define T16B0TC REG(0x5006)
#define T16B0CS REG(0x5008)
#define T16B0INTF REG(0x500a)
#define T16B0INTE REG(0x500c)
#define T16B0CCCTL0 REG(0x5010)
#define T16B0CCR0 REG(0x5012)
#define T16B0CCCTL1 REG(0x5018)
#define T16B0CCR1 REG(0x501a)
// T16B1
#define T16B1CLK REG(0x5040)
#define T16B1CTL REG(0x5042)
#define T16B1MC REG(0x5044)
#define T16B1TC REG(0x5046)
#define T16B1CS REG(0x5048)
#define T16B1INTF REG(0x504a)
#define T16B1INTE REG(0x504c)
#define T16B1CCCTL0 REG(0x5050)
#define T16B1CCR0 REG(0x5052)
#define T16B1CCCTL1 REG(0x5058)
#define T16B1CCR1 REG(0x505a)
// T16B2
#define T16B2CLK REG(0x5080)
#define T16B2CTL REG(0x5082)
#define T16B2MC REG(0x5084)
#define T16B2TC REG(0x5086)
#define T16B2CS REG(0x5088)
#define T16B2INTF REG(0x508a)
#define T16B2INTE REG(0x508c)
#define T16B2CCCTL0 REG(0x5090)
#define T16B2CCR0 REG(0x5092)
#define T16B2CCCTL1 REG(0x5098)
#define T16B2CCR1 REG(0x509a)
// UART1
#define UA1CLK REG(0x5200)
#define UA1MOD REG(0x5202)
#define UA1BR REG(0x5204)
#define UA1CTL REG(0x5206)
#define UA1TXD REG(0x5208)
#define UA1RXD REG(0x520a)
#define UA1INTF REG(0x520c)
#define UA1INTE REG(0x520e)
// T16_2
#define T16_2CLK REG(0x5260)
#define T16_2MOD REG(0x5262)
#define T16_2CTL REG(0x5264)
#define T16_2TR REG(0x5266)
#define T16_2TC REG(0x5268)
#define T16_2INTF REG(0x526a)
#define T16_2INTE REG(0x526c)
// SPIA1
#define SPI1MOD REG(0x5270)
#define SPI1CTL REG(0x5272)
#define SPI1TXD REG(0x5274)
#define SPI1RXD REG(0x5276)
#define SPI1INTF REG(0x5278)
#define SPI1INTE REG(0x527a)
// SNDA
#define SNDCLK REG(0x5300)
#define SNDSEL REG(0x5302)
#define SNDCTL REG(0x5304)
#define SNDDAT REG(0x5306)
#define SNDINTF REG(0x5308)
#define SNDINTE REG(0x530a)
// REMC2
#define REMCLK REG(0x5320)
#define REMDBCTL REG(0x5322)
#define REMDBCNT REG(0x5324)
#define REMAPLEN REG(0x5326)
#define REMDBLEN REG(0x5328)
#define REMINTF REG(0x532a)
#define REMINTE REG(0x532c)
#define REMCARR REG(0x5330)
#define REMCCTL REG(0x5332)
// LCD8B
#define LCD8CLK REG(0x5400)
#define LCD8CTL REG(0x5402)
#define LCD8TIM1 REG(0x5404)
#define LCD8TIM2 REG(0x5406)
#define LCD8PWR REG(0x5408)
#define LCD8DSP REG(0x540a)
#define LCD8COMC0 REG(0x540c)
#define LCD8INTF REG(0x5410)
#define LCD8INTE REG(0x5412)
// RFC0
#define RFC0CLK REG(0x5440)
#define RFC0CTL REG(0x5442)
#define RFC0TRG REG(0x5444)
#define RFC0MCL REG(0x5446)
#define RFC0MCH REG(0x5448)
#define RFC0MC REG32(0x5446)
#define RFC0TCL REG(0x544a)
#define RFC0TCH REG(0x544c)
#define RFC0TC REG32(0x544a)
#define RFC0INTF REG(0x544e)
#define RFC0INTE REG(0x5450)
// RFC1
#define RFC1CLK REG(0x5460)
#define RFC1CTL REG(0x5462)
#define RFC1TRG REG(0x5464)
#define RFC1MCL REG(0x5466)
#define RFC1MCH REG(0x5468)
#define RFC1MC REG32(0x5466)
#define RFC1TCL REG(0x546a)
#define RFC1TCH REG(0x546c)
#define RFC1TC REG32(0x546a)
#define RFC1INTF REG(0x546e)
#define RFC1INTE REG(0x5470)
// T16_3
#define T16_3CLK REG(0x5480)
#define T16_3MOD REG(0x5482)
#define T16_3CTL REG(0x5484)
#define T16_3TR REG(0x5486)
#define T16_3TC REG(0x5488)
#define T16_3INTF REG(0x548a)
#define T16_3INTE REG(0x548c)
// ADC12A
#define ADC12_0CTL REG(0x54a2)
#define ADC12_0TRG REG(0x54a4)
#define ADC12_0CFG REG(0x54a6)
#define ADC12_0INTF REG(0x54a8)
#define ADC12_0INTE REG(0x54aa)
#define ADC12_0AD0D REG(0x54ac)
#define ADC12_0AD1D REG(0x54ae)
#define ADC12_0AD2D REG(0x54b0)
#define ADC12_0AD3D REG(0x54b2)
#define ADC12_0AD4D REG(0x54b4)
#define ADC12_0AD5D REG(0x54b6)
#define ADC12_0AD6D REG(0x54b8)
#define ADC12_0AD7D REG(0x54ba)
// TSRVR
#define TSRVR0TCTL REG(0x54c0)
#define TSRVR0VCTL REG(0x54c2)
// DBG
#define DBRAM REG(0xffff90)
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