Tegra X1 T210 OpenOCD JTAG config for Jetson Nano/TX1

t210.cfg

#
# OpenOCD configuration for Tegra X1 (T210)
# by shinyquagsire23
# For use on Jetson Nano/TX1 and similar
#
transport select jtag
adapter speed 3000

reset_config trst_and_srst
jtag_ntrst_delay 500

set _CHIPNAME t210
set _CCPLEX_TARGETNAME $_CHIPNAME.ccplex
set _CCPLEX_CTINAME $_CCPLEX_TARGETNAME.cti
set _BPMP_TARGETNAME $_CHIPNAME.bpmp

#init_reset run
#jtag arp_init

#jtag newtap $_CHIPNAME tap -irlen 2 -expected-id 0x221173d7 -enable

# CCPLEX AND BPMP
jtag newtap $_CCPLEX_TARGETNAME tap -irlen 4 -expected-id 0x5ba00477 -enable
jtag newtap $_BPMP_TARGETNAME tap -irlen 4 -expected-id 0x4f1f0f0f

# CCPLEX DAP
dap create $_CCPLEX_TARGETNAME.dap -chain-position $_CCPLEX_TARGETNAME.tap

# Give AXI-AP a name
target create $_CHIPNAME.axi mem_ap -dap $_CCPLEX_TARGETNAME.dap -ap-num 1

# and APB-AP
target create $_CHIPNAME.apb mem_ap -dap $_CCPLEX_TARGETNAME.dap -ap-num 0

# Coresight Major
cti create $_CHIPNAME.coresight -dap $_CCPLEX_TARGETNAME.dap -ap-num 0 -baseaddr 0x72020000

# TODO: APE

# Cortex-A57/A53 cluster (A53s ignored)
set DBGBASE {0x81410000 0x81510000 0x81610000 0x81710000}
set CTIBASE {0x81420000 0x81520000 0x81620000 0x81720000}
set ATIDS {0x40 0x41 0x42 0x43}
set _cores 4
 
for { set _core 0 } { $_core < $_cores } { incr _core } {

    cti create $_CCPLEX_CTINAME.$_core -dap $_CCPLEX_TARGETNAME.dap -ap-num 0 \
        -baseaddr [lindex $CTIBASE $_core]

    target create $_CCPLEX_TARGETNAME.$_core aarch64 -dap $_CCPLEX_TARGETNAME.dap \
        -dbgbase [lindex $DBGBASE $_core] -cti $_CCPLEX_CTINAME.$_core -coreid [lindex $ATIDS $_core]
}

target smp $_CCPLEX_TARGETNAME.0 $_CCPLEX_TARGETNAME.1 $_CCPLEX_TARGETNAME.2 $_CCPLEX_TARGETNAME.3

# BPMP ARM7TDMI
target create $_BPMP_TARGETNAME arm7tdmi -endian little -chain-position 1

# default target is BPMP ARM7TDMI
targets $_BPMP_TARGETNAME