FickleAI

Compiler Output

[info] Running jp.ac.kyotou.kansai.fickleAI 
func_entryPoint:
LDC 0
LDC 0
LDC 0
LDC 0
LDF body_entryPoint
TAP 4
body_entryPoint:
LDC 0
ST 0 0
LDC 0
ST 0 1
LDC 0
ST 0 2
LDC 0
ST 0 3
LD 0 0
LD 0 1
LD 0 2
LD 0 3
CONS
CONS
CONS
LDF func_step
CONS
RTN
func_step:
LDC 0
LDC 0
LDC 0
LDC 0
LDC 0
LDC 0
LDF body_step
TAP 6
body_step:
LD 1 0
CAR
ST 0 1
LD 1 0
CDR
CAR
ST 0 5
LD 1 0
CDR
CDR
CAR
ST 0 0
LD 1 0
CDR
CDR
CDR
CDR
ST 0 2
LD 0 1
ST 0 4
LDC 0
ST 0 3
if1:
LD 0 4
LD 0 5
CGT
TSEL true2 false3
true2:
LD 0 5
ST 0 4
LDC 1
ST 0 3
LDC 0
LDC 0
CEQ
TSEL after4 terminate
false3:
after4:
if5:
LD 0 4
LD 0 0
CGT
TSEL true6 false7
true6:
LD 0 0
ST 0 4
LDC 2
ST 0 3
LDC 0
LDC 0
CEQ
TSEL after8 terminate
false7:
after8:
if9:
LD 0 4
LD 0 2
CGT
TSEL true10 false11
true10:
LD 0 2
ST 0 4
LDC 3
ST 0 3
LDC 0
LDC 0
CEQ
TSEL after12 terminate
false11:
after12:
if13:
LD 0 3
LDC 0
CEQ
TSEL true14 false15
true14:
LD 0 1
LDC 1
ADD
ST 0 1
LDC 0
LDC 0
CEQ
TSEL after16 terminate
false15:
if17:
LD 0 3
LDC 1
CEQ
TSEL true18 false19
true18:
LD 0 5
LDC 1
ADD
ST 0 5
LDC 0
LDC 0
CEQ
TSEL after20 terminate
false19:
if21:
LD 0 3
LDC 2
CEQ
TSEL true22 false23
true22:
LD 0 0
LDC 1
ADD
ST 0 0
LDC 0
LDC 0
CEQ
TSEL after24 terminate
false23:
LD 0 2
LDC 1
ADD
ST 0 2
after24:
after20:
after16:
LD 0 1
LD 0 5
LD 0 0
LD 0 2
CONS
CONS
CONS
LD 0 3
CONS
RTN
terminate:
-----
LDC 0
LDC 0
LDC 0
LDC 0
LDF 6
TAP 4
LDC 0
ST 0 0
LDC 0
ST 0 1
LDC 0
ST 0 2
LDC 0
ST 0 3
LD 0 0
LD 0 1
LD 0 2
LD 0 3
CONS
CONS
CONS
LDF 24
CONS
RTN
LDC 0
LDC 0
LDC 0
LDC 0
LDC 0
LDC 0
LDF 32
TAP 6
LD 1 0
CAR
ST 0 1
LD 1 0
CDR
CAR
ST 0 5
LD 1 0
CDR
CDR
CAR
ST 0 0
LD 1 0
CDR
CDR
CDR
CDR
ST 0 2
LD 0 1
ST 0 4
LDC 0
ST 0 3
LD 0 4
LD 0 5
CGT
TSEL 58 66
LD 0 5
ST 0 4
LDC 1
ST 0 3
LDC 0
LDC 0
CEQ
TSEL 66 140
LD 0 4
LD 0 0
CGT
TSEL 70 78
LD 0 0
ST 0 4
LDC 2
ST 0 3
LDC 0
LDC 0
CEQ
TSEL 78 140
LD 0 4
LD 0 2
CGT
TSEL 82 90
LD 0 2
ST 0 4
LDC 3
ST 0 3
LDC 0
LDC 0
CEQ
TSEL 90 140
LD 0 3
LDC 0
CEQ
TSEL 94 102
LD 0 1
LDC 1
ADD
ST 0 1
LDC 0
LDC 0
CEQ
TSEL 130 140
LD 0 3
LDC 1
CEQ
TSEL 106 114
LD 0 5
LDC 1
ADD
ST 0 5
LDC 0
LDC 0
CEQ
TSEL 130 140
LD 0 3
LDC 2
CEQ
TSEL 118 126
LD 0 0
LDC 1
ADD
ST 0 0
LDC 0
LDC 0
CEQ
TSEL 130 140
LD 0 2
LDC 1
ADD
ST 0 2
LD 0 1
LD 0 5
LD 0 0
LD 0 2
CONS
CONS
CONS
LD 0 3
CONS
RTN

fickleAI.scala

package jp.ac.kyotou.kansai

@gccCode
class fickleAI extends Support {
  def step(state : (Int, Int, Int, Int), world : Int) : (((Int, Int, Int, Int)), Int) = {
    var up = state._1
    var right = state._2
    var down = state._3
    var left = state._4

    var minv = up
    var mind = 0

    if (minv > right) {
      minv = right
      mind = 1
    }

    if (minv > down) {
      minv = down
      mind = 2
    }

    if (minv > left) {
      minv = left
      mind = 3
    }

    if (mind == 0) {
      up = up + 1      
    } else {
      if (mind == 1) {
        right = right + 1
      } else {
        if (mind == 2) {
            down = down + 1
        } else {
            left = left + 1
        }
      }
    }

    return (((up, right, down, left)), mind)
  }

  def entryPoint(world: Int, undoc: Int): ((Int, Int, Int, Int), ((Int, Int, Int, Int), Int) => ((Int, Int, Int, Int), Int)) = {
    var up = 0
    var right = 0
    var down = 0
    var left = 0
    return ((up, right, down, left), step)
  }
}

object fickleAI extends AstCleanup {
  val asts = ???

  def main(args: Array[String]) {
    var gen = NameGen()
  	var codeList = CodeGen.emitStructure(cleanAsts.get("entryPoint").get, gen)
        codeList ++= CodeGen.emitStructure(cleanAsts.get("step").get, gen)
        codeList ++= List(Label("terminate"))
    println(codeList.map(CodeGen.show).mkString("", "\n", ""))
    println("-----")
    println(CodeGen.dereferenceLabels(codeList).map(CodeGen.show).mkString("", "\n", ""))
  }
}