Created
April 30, 2016 15:38
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from myhdl import * | |
coram_obj_count = 0 | |
def MyhdlCoramMemory1P(CLK, ADDR, D, WE, Q, | |
CORAM_THREAD_NAME="undefined", | |
CORAM_THREAD_ID=0, | |
CORAM_ID=0, | |
CORAM_SUB_ID=0, | |
CORAM_ADDR_LEN=10, | |
CORAM_DATA_WIDTH=32): | |
@always(CLK.posedge) | |
def logic(): | |
pass # do nothing | |
Q.driven = "wire" | |
MyhdlCoramMemory1P.verilog_code=\ | |
""" | |
CoramMemory1P | |
#( | |
.CORAM_THREAD_NAME( "$CORAM_THREAD_NAME" ), | |
.CORAM_ID( $CORAM_ID ), | |
.CORAM_SUB_ID( $CORAM_SUB_ID ), | |
.CORAM_ADDR_LEN( $CORAM_ADDR_LEN ), | |
.CORAM_DATA_WIDTH( $CORAM_DATA_WIDTH ) | |
) | |
obj_$coram_obj_count | |
(.CLK( $CLK ), | |
.ADDR( $ADDR ), | |
.D( $D ), | |
.WE( $WE ), | |
.Q( $Q ) | |
); | |
""" | |
global coram_obj_count | |
coram_obj_count += 1 | |
return logic | |
def sub(CLK, RST, LED): | |
ADDR = Signal(intbv()[16:]) | |
D = Signal(intbv()[32:]) | |
WE = Signal(bool(0)) | |
Q = Signal(intbv()[32:]) | |
coram_memory = MyhdlCoramMemory1P(CLK, ADDR, D, WE, Q, | |
"cthread_test", 0, 0, 0, 16, 32) | |
@always(CLK.posedge) | |
def logic(): | |
if RST == 1: | |
WE.next = 0 | |
ADDR.next = 0 | |
D.next = 0 | |
LED.next = 0 | |
else: | |
WE.next = 1 | |
ADDR.next = ADDR + 1 | |
D.next = D + 4 | |
LED.next = Q | |
return instances() | |
def main(CLK, RST, LED0, LED1): | |
s0 = sub(CLK, RST, LED0) | |
s1 = sub(CLK, RST, LED1) | |
return instances() | |
def convert(): | |
CLK = Signal(bool(0)) | |
RST = Signal(bool(0)) | |
LED0 = Signal(intbv()[8:]) | |
LED1 = Signal(intbv()[8:]) | |
toVerilog(main, | |
CLK, RST, LED0, LED1) | |
convert() |
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