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machine-readable powerpc ISA (32bit, espresso / nintendo)
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| ''' | |
| example of consuming insns.xml | |
| ''' | |
| from xml.etree.ElementTree import ElementTree | |
| class Instructions: | |
| def __init__(s): | |
| s.root = ElementTree(file = 'insns.xml') | |
| def dump(s): | |
| for e in s.root.findall('.//insn'): | |
| print('%-16s %08x' % (e.attrib['mnem'], int(e.attrib['opcode'], 16))) | |
| if __name__ == '__main__': | |
| insns = Instructions() | |
| insns.dump() |
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| # Generate C macro table from the xml table (which was generated from a pdf...) | |
| import sys | |
| from xml.etree.ElementTree import ElementTree, Element, SubElement, tostring, dump | |
| class Insn: | |
| pass | |
| def bit_extract(x, leftmost, rightmost): | |
| return (x >> (32 - 1 - rightmost)) & ((1 << (rightmost - leftmost + 1)) - 1) | |
| def opcode_primary(insn): | |
| return bit_extract(insn, 0, 5) | |
| def opcode_extended(insn, form): | |
| if form in ('X', 'XL', 'XFX', 'XFL'): | |
| return bit_extract(insn, 21, 30) | |
| elif form == 'XO': | |
| return bit_extract(insn, 22, 30) | |
| elif form == 'XW': | |
| return bit_extract(insn, 25, 30) | |
| elif form == 'A': | |
| return bit_extract(insn, 26, 30) | |
| else: return -1 | |
| def form_bitlen(): return 10 | |
| def parse_insns(filename): | |
| root = ElementTree(file = filename) | |
| insns = [] | |
| # Convert to python types | |
| for e in root.findall('.//insn'): | |
| i = Insn() | |
| i.level = e.attrib['arch-level'] | |
| i.desc = e.attrib['desc'] | |
| i.form = e.attrib['form'] | |
| i.group = e.attrib['group'] | |
| i.mnem = e.attrib['mnem'] | |
| i.opcode = int(e.attrib['opcode'], 16) | |
| i.optional = e.attrib['optional'] | |
| i.subform = e.attrib['sub-form'] | |
| i.supervisor = e.attrib['supervisor'] == 'True' | |
| i.op_primary = opcode_primary(i.opcode) | |
| i.op_extended = opcode_extended(i.opcode, i.form) | |
| insns.append(i) | |
| return insns | |
| def gen_c(insns): | |
| # Convert to pretty C | |
| def c_mnem(x): return x.replace('.', 'x') | |
| def c_subform(x): | |
| x = x.replace('-', '_') | |
| if x[0] >= '0' and x[0] <= '9': | |
| x = '_' + x | |
| return x | |
| def c_bool(x): return 'true' if x else 'false' | |
| def c_group(x): | |
| return { | |
| 'Integer Arithmetic Instructions' : 'int', | |
| 'Integer Compare Instructions' : 'int', | |
| 'Integer Logical Instructions' : 'int', | |
| 'Integer Rotate Instructions' : 'int', | |
| 'Integer Shift Instructions' : 'int', | |
| 'Floating-Point Arithmetic Instructions' : 'fp', | |
| 'Floating-Point Multiply-Add Instructions' : 'fp', | |
| 'Floating-Point Rounding and Conversion Instructions' : 'fp', | |
| 'Floating-Point Compare Instructions' : 'fp', | |
| 'Floating-Point Status and Control Register Instructions' : 'fp', | |
| 'Integer Load Instructions' : 'int', | |
| 'Integer Store Instructions' : 'int', | |
| 'Integer Load and Store with Byte Reverse Instructions' : 'int', | |
| 'Integer Load and Store Multiple Instructions' : 'int', | |
| 'Integer Load and Store String Instructions' : 'int', | |
| 'Memory Synchronization Instructions' : 'int', | |
| 'Floating-Point Load Instructions' : 'fp', | |
| 'Floating-Point Store Instructions' : 'fp', | |
| 'Floating-Point Move Instructions' : 'fp', | |
| 'Branch Instructions' : 'int', | |
| 'Condition Register Logical Instructions' : 'int', | |
| 'System Linkage Instructions' : 'int', | |
| 'Trap Instructions' : 'int', | |
| 'Processor Control Instructions' : 'int', | |
| 'Cache Management Instructions' : 'int', | |
| 'Segment Register Manipulation Instructions' : 'int', | |
| 'Lookaside Buffer Management Instructions' : 'int', | |
| 'External Control Instructions' : 'int', | |
| 'Paired-Single Load and Store Instructions' : 'int', | |
| 'Paired-Single Floating-Point Arithmetic Instructions' : 'int', | |
| 'Miscellaneous Paired-Single Instructions' : 'int', | |
| }[x] | |
| l = [] | |
| l.append('// This file was autogenerated by %s. Do not modify!' % (sys.argv[0])) | |
| l.append('#ifndef INSTRUCTION') | |
| l.append('static_assert(false, "you need to #define INSTRUCTION(opcode, mnemonic, form, subform, description, group, supervisor)");') | |
| l.append('#else') | |
| for i in insns: | |
| i.mnem = c_mnem(i.mnem) | |
| i.subform = c_subform(i.subform) | |
| i.group = c_group(i.group) | |
| mnem_len = len(max(insns, key = lambda i: len(i.mnem)).mnem) | |
| form_len = len(max(insns, key = lambda i: len(i.form)).form) | |
| subform_len = len(max(insns, key = lambda i: len(i.subform)).subform) | |
| desc_len = len(max(insns, key = lambda i: len(i.desc)).desc) | |
| group_len = len(max(insns, key = lambda i: len(i.group)).group) | |
| insns = sorted(insns, key = lambda i: i.mnem) | |
| fmt = 'INSTRUCTION(0x%08x, %-' + str(mnem_len) + 's, %-' + str(form_len) + 's, %-' + str(subform_len) + 's, %-' + str(desc_len) + 's, %-' + str(group_len) + 's, %s)' | |
| [l.append(fmt % (i.opcode, i.mnem, i.form, i.subform, i.desc, i.group, c_bool(i.supervisor))) for i in insns] | |
| l.append('#endif') | |
| return ' \\\n'.join(l) | |
| def gen_switch(insns): | |
| l = [] | |
| TAB = ' ' * 2 | |
| def w0(x): l.append(x) | |
| def w1(x): w0(TAB * 1 + x) | |
| def w2(x): w0(TAB * 2 + x) | |
| def w3(x): w0(TAB * 3 + x) | |
| def w4(x): w0(TAB * 4 + x) | |
| def c_mnem(x): return x.replace('.', 'x') | |
| for i in insns: | |
| i.mnem = c_mnem(i.mnem) | |
| def decode_form(pri, ext): | |
| for i in insns: | |
| if i.op_primary == pri and i.op_extended == ext: | |
| return i.form | |
| def decode_mnem(pri, ext): | |
| for i in insns: | |
| if i.op_primary == pri and i.op_extended == ext: | |
| return i.mnem | |
| def form_bitlen(pri, ext): | |
| # others not here purposefully, so it will blow up | |
| return { | |
| 'X' : 10, 'XL' : 10, 'XFX' : 10, 'XFL' : 10, | |
| 'XO' : 9, | |
| 'XW' : 6, | |
| 'A' : 5, | |
| }[decode_form(pri, ext)] | |
| def bitlen_to_form(bitlen): | |
| return { 10 : 'X', 9 : 'XO', 6 : 'XW', 5 : 'A' }[bitlen] | |
| w0('#define PPC_DECODER(name)') | |
| w1('PPC_DECODER_RET_TYPE ppc_decode_##name(u32 insn) {') | |
| w2('switch (opcode_primary(insn)) {') | |
| subtables = {} | |
| for i in sorted(insns, key = lambda i: i.op_primary): | |
| if i.op_extended == -1: | |
| # the primary opcode field fully identifies the opcode | |
| w2('case %i: PPC_DECODER_HIT(%s);' % (i.op_primary, i.mnem)) | |
| else: | |
| if i.op_primary not in subtables: subtables[i.op_primary] = [] | |
| subtables[i.op_primary].append(i.op_extended) | |
| for pri in sorted(subtables.iterkeys()): | |
| # all the extended encodings (which we care about) end with bit 30. So we want to | |
| # do the rest of the seach by bitscanning left from bit 30. This is simulated | |
| # in the C switch-statement by creating leafs for each extended opcode, | |
| # sorted by bitlength shortest to longest. | |
| bitstrings = {} | |
| for ext in subtables[pri]: | |
| bs_len = form_bitlen(pri, ext) | |
| bs = ('{:0'+str(bs_len)+'b}').format(ext) | |
| if bs_len not in bitstrings: bitstrings[bs_len] = [] | |
| bitstrings[bs_len].append(bs) | |
| w2('case %i:' % (pri)) | |
| for bs in sorted(bitstrings.iterkeys()): | |
| # this could be replaced with opcode_extended() or something... | |
| #w3('switch ((insn >> 1) & %#x) {' % ((1 << bs) - 1)) | |
| w3('switch (opcode_extended<k%s>(insn)) {' % (bitlen_to_form(bs))) | |
| for ext in sorted(bitstrings[bs]): | |
| w4('case 0b%s: PPC_DECODER_HIT(%s);' % (ext, decode_mnem(pri, int(ext, 2)))) | |
| w3('}') | |
| w3('PPC_DECODER_MISS;') | |
| w2('default: PPC_DECODER_MISS;') | |
| w2('}') | |
| w1('}') | |
| ''' | |
| for pri in subtables.iterkeys(): | |
| print('PRI %3i' % (pri)) | |
| bitstrings = [] | |
| for ext in subtables[pri]: | |
| bitstrings.append(('{:0'+str(form_bitlen(pri, ext))+'b}').format(ext)) | |
| for bitstring in sorted(bitstrings, key = lambda bs: bs[::-1]): | |
| print('%20s' % (bitstring)) | |
| #''' | |
| # from this we can see some tables have bits which can be used to determine extended opcoded size: | |
| # primary opcode 31: | |
| # 01... = 9 bits (XO form), else 10 bits (X/XFX forms) | |
| # primary opcode 63: | |
| # 1.... = 7 bits (A form), else 10 bits (X/XFL forms) | |
| # primary opcode 4: | |
| # does not have small bit range to determine size, but you can just use the | |
| # low 7 bits in order to "guess" the opcode. if you assume no invalid | |
| # encodings are input, only the sequence ...0001000 actually *needs* the upper | |
| # bits in order to differentiate the opcode (0100001000 = ps_abs, 0010001000 = ps_nabs) | |
| # otherwise, the low 7bits can be used as the determinant, and a second comparison | |
| # can be used against the real length of bits to fully match the extended opcode | |
| # | |
| # this approach can be generalized for all primary opcodes with extended opcodes of varying lengths: | |
| # compare bits of smallest length, fall through to comparing larger sizes until found or failure | |
| # with the optional optimization of discarding further compares for extended opcodes which | |
| # share top bits with any other extended opcode (at the price of failing to detect invalid opcodes) | |
| macro = ' \\\n'.join(l) | |
| l = [] | |
| l.append('// This macro was autogenerated by %s. Do not modify!' % (sys.argv[0])) | |
| l.append(macro) | |
| return '\n'.join(l) | |
| def gen_emitters(insns): | |
| def c_mnem(x): return x.replace('.', 'x') | |
| def c_subform(x): | |
| x = x.replace('-', '_') | |
| if x[0] >= '0' and x[0] <= '9': | |
| x = '_' + x | |
| return x | |
| TAB = ' ' * 2 | |
| for i in insns: | |
| i.mnem = c_mnem(i.mnem) | |
| i.subform = c_subform(i.subform) | |
| fields, funcs = [], [] | |
| group = '' | |
| subforms = {} | |
| fields.append('union PpcInsn {') | |
| for i in sorted(insns, key = lambda i: i.group): | |
| if i.subform not in subforms: | |
| subforms[i.subform] = i.form | |
| fields.append('%sstruct %s {};' % (TAB * 1, i.subform)) | |
| elif subforms[i.subform] != i.form: | |
| pass #print('subform %s shared by multiple forms (%s and %s) insn: %s' % (i.subform, subforms[i.subform], i.form, i.mnem)) | |
| if i.group != group: | |
| group = i.group | |
| funcs.append('// %s' % (i.group)) | |
| funcs.append('') | |
| funcs.append('EMITTER(%s) {' % (i.mnem)) | |
| funcs.append('EMITTER_UNIMPLEMENTED(%s);' % (i.mnem)) | |
| funcs.append('}') | |
| funcs.append('') | |
| fields.append('};') | |
| fields.append('') | |
| return '\n'.join(fields) + '\n' + '\n'.join(funcs) | |
| if __name__ == '__main__': | |
| insns = parse_insns('insns.xml') | |
| #print(gen_c(insns)) | |
| print(gen_switch(insns)) | |
| #print(gen_emitters(insns)) |
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| <?xml version="1.0" encoding="UTF-8"?> | |
| <root> | |
| <ppc-isa name="6xx_pem"> | |
| <insn arch-level="U" desc="Add" form="XO" group="Integer Arithmetic Instructions" mnem="addx" opcode="7c000214" optional="False" sub-form="D-A-B-OE-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Add Carrying" form="XO" group="Integer Arithmetic Instructions" mnem="addcx" opcode="7c000014" optional="False" sub-form="D-A-B-OE-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Add Extended" form="XO" group="Integer Arithmetic Instructions" mnem="addex" opcode="7c000114" optional="False" sub-form="D-A-B-OE-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Add Immediate" form="D" group="Integer Arithmetic Instructions" mnem="addi" opcode="38000000" optional="False" sub-form="D-A-SIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="Add Immediate Carrying" form="D" group="Integer Arithmetic Instructions" mnem="addic" opcode="30000000" optional="False" sub-form="D-A-SIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="Add Immediate Carrying and Record" form="D" group="Integer Arithmetic Instructions" mnem="addic." opcode="34000000" optional="False" sub-form="D-A-SIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="Add Immediate Shifted" form="D" group="Integer Arithmetic Instructions" mnem="addis" opcode="3c000000" optional="False" sub-form="D-A-SIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="Add to Minus One Extended" form="XO" group="Integer Arithmetic Instructions" mnem="addmex" opcode="7c0001d4" optional="False" sub-form="D-A-0-OE-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Add to Zero Extended" form="XO" group="Integer Arithmetic Instructions" mnem="addzex" opcode="7c000194" optional="False" sub-form="D-A-0-OE-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Divide Word" form="XO" group="Integer Arithmetic Instructions" mnem="divwx" opcode="7c0003d6" optional="False" sub-form="D-A-B-OE-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Divide Word Unsigned" form="XO" group="Integer Arithmetic Instructions" mnem="divwux" opcode="7c000396" optional="False" sub-form="D-A-B-OE-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Multiply High Word" form="XO" group="Integer Arithmetic Instructions" mnem="mulhwx" opcode="7c000096" optional="False" sub-form="D-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Multiply High Word Unsigned" form="XO" group="Integer Arithmetic Instructions" mnem="mulhwux" opcode="7c000016" optional="False" sub-form="D-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Multiply Low Immediate" form="D" group="Integer Arithmetic Instructions" mnem="mulli" opcode="1c000000" optional="False" sub-form="D-A-SIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="Multiply Low Word" form="XO" group="Integer Arithmetic Instructions" mnem="mullwx" opcode="7c0001d6" optional="False" sub-form="D-A-B-OE-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Negate" form="XO" group="Integer Arithmetic Instructions" mnem="negx" opcode="7c0000d0" optional="False" sub-form="D-A-0-OE-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Subtract From" form="XO" group="Integer Arithmetic Instructions" mnem="subfx" opcode="7c000050" optional="False" sub-form="D-A-B-OE-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Subtract from Carrying" form="XO" group="Integer Arithmetic Instructions" mnem="subfcx" opcode="7c000010" optional="False" sub-form="D-A-B-OE-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Subtract from Immediate Carrying" form="D" group="Integer Arithmetic Instructions" mnem="subfic" opcode="20000000" optional="False" sub-form="D-A-SIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="Subtract from Extended" form="XO" group="Integer Arithmetic Instructions" mnem="subfex" opcode="7c000110" optional="False" sub-form="D-A-B-OE-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Subtract from Minus One Extended" form="XO" group="Integer Arithmetic Instructions" mnem="subfmex" opcode="7c0001d0" optional="False" sub-form="D-A-0-OE-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Subtract from Zero Extended" form="XO" group="Integer Arithmetic Instructions" mnem="subfzex" opcode="7c000190" optional="False" sub-form="D-A-0-OE-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Compare" form="X" group="Integer Compare Instructions" mnem="cmp" opcode="7c000000" optional="False" sub-form="crfD-L-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Compare Immediate" form="D" group="Integer Compare Instructions" mnem="cmpi" opcode="2c000000" optional="False" sub-form="crfD-L-A-SIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="Compare Logical" form="X" group="Integer Compare Instructions" mnem="cmpl" opcode="7c000040" optional="False" sub-form="crfD-L-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Compare Logical Immediate" form="D" group="Integer Compare Instructions" mnem="cmpli" opcode="28000000" optional="False" sub-form="crfD-L-A-UIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="AND" form="X" group="Integer Logical Instructions" mnem="andx" opcode="7c000038" optional="False" sub-form="S-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="AND with Complement" form="X" group="Integer Logical Instructions" mnem="andcx" opcode="7c000078" optional="False" sub-form="S-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="AND Immediate" form="D" group="Integer Logical Instructions" mnem="andi." opcode="70000000" optional="False" sub-form="S-A-UIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="AND Immediate Shifted" form="D" group="Integer Logical Instructions" mnem="andis." opcode="74000000" optional="False" sub-form="S-A-UIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="Count Leading Zeros Word" form="X" group="Integer Logical Instructions" mnem="cntlzwx" opcode="7c000034" optional="False" sub-form="S-A-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Equivalent" form="X" group="Integer Logical Instructions" mnem="eqvx" opcode="7c000238" optional="False" sub-form="S-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Extend Sign Byte" form="X" group="Integer Logical Instructions" mnem="extsbx" opcode="7c000774" optional="False" sub-form="S-A-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Extend Sign Half Word" form="X" group="Integer Logical Instructions" mnem="extshx" opcode="7c000734" optional="False" sub-form="S-A-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="NAND" form="X" group="Integer Logical Instructions" mnem="nandx" opcode="7c0003b8" optional="False" sub-form="S-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="NOR" form="X" group="Integer Logical Instructions" mnem="norx" opcode="7c0000f8" optional="False" sub-form="S-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="OR" form="X" group="Integer Logical Instructions" mnem="orx" opcode="7c000378" optional="False" sub-form="S-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="OR with Complement" form="X" group="Integer Logical Instructions" mnem="orcx" opcode="7c000338" optional="False" sub-form="S-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="OR Immediate" form="D" group="Integer Logical Instructions" mnem="ori" opcode="60000000" optional="False" sub-form="S-A-UIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="OR Immediate Shifted" form="D" group="Integer Logical Instructions" mnem="oris" opcode="64000000" optional="False" sub-form="S-A-UIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="XOR" form="X" group="Integer Logical Instructions" mnem="xorx" opcode="7c000278" optional="False" sub-form="S-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="XOR Immediate" form="D" group="Integer Logical Instructions" mnem="xori" opcode="68000000" optional="False" sub-form="S-A-UIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="XOR Immediate Shifted" form="D" group="Integer Logical Instructions" mnem="xoris" opcode="6c000000" optional="False" sub-form="S-A-UIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="Rotate Left Word Immediate then Mask Insert" form="M" group="Integer Rotate Instructions" mnem="rlwimix" opcode="50000000" optional="False" sub-form="S-A-SH-MB-ME-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Rotate Left Word Immediate then AND with Mask" form="M" group="Integer Rotate Instructions" mnem="rlwinmx" opcode="54000000" optional="False" sub-form="S-A-SH-MB-ME-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Rotate Left Word then AND with Mask" form="M" group="Integer Rotate Instructions" mnem="rlwnmx" opcode="5c000000" optional="False" sub-form="S-A-SH-MB-ME-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Shift Left Word" form="X" group="Integer Shift Instructions" mnem="slwx" opcode="7c000030" optional="False" sub-form="S-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Shift Right Algebraic Word" form="X" group="Integer Shift Instructions" mnem="srawx" opcode="7c000630" optional="False" sub-form="S-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Shift Right Algebraic Word Immediate" form="X" group="Integer Shift Instructions" mnem="srawix" opcode="7c000670" optional="False" sub-form="S-A-SH-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Shift Right Word" form="X" group="Integer Shift Instructions" mnem="srwx" opcode="7c000430" optional="False" sub-form="S-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Add (Double-Precision)" form="A" group="Floating-Point Arithmetic Instructions" mnem="faddx" opcode="fc00002a" optional="False" sub-form="D-A-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Add Single" form="A" group="Floating-Point Arithmetic Instructions" mnem="faddsx" opcode="ec00002a" optional="False" sub-form="D-A-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Divide (Double-Precision)" form="A" group="Floating-Point Arithmetic Instructions" mnem="fdivx" opcode="fc000024" optional="False" sub-form="D-A-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Divide Single" form="A" group="Floating-Point Arithmetic Instructions" mnem="fdivsx" opcode="ec000024" optional="False" sub-form="D-A-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Multiply (Double-Precision)" form="A" group="Floating-Point Arithmetic Instructions" mnem="fmulx" opcode="fc000032" optional="False" sub-form="D-A-0-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Multiply Single" form="A" group="Floating-Point Arithmetic Instructions" mnem="fmulsx" opcode="ec000032" optional="False" sub-form="D-A-0-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Reciprocal Estimate Single" form="A" group="Floating-Point Arithmetic Instructions" mnem="fresx" opcode="ec000030" optional="True" sub-form="D-0-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Reciprocal Square Root Estimate" form="A" group="Floating-Point Arithmetic Instructions" mnem="frsqrtex" opcode="fc000034" optional="True" sub-form="D-0-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Subtract (Double-Precision)" form="A" group="Floating-Point Arithmetic Instructions" mnem="fsubx" opcode="fc000028" optional="False" sub-form="D-A-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Subtract Single" form="A" group="Floating-Point Arithmetic Instructions" mnem="fsubsx" opcode="ec000028" optional="False" sub-form="D-A-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Select" form="A" group="Floating-Point Arithmetic Instructions" mnem="fselx" opcode="fc00002e" optional="True" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Square Root(Double-Precision)" form="A" group="Floating-Point Arithmetic Instructions" mnem="fsqrtx" opcode="fc00002c" optional="True" sub-form="D-0-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Square Root(Single-Precision)" form="A" group="Floating-Point Arithmetic Instructions" mnem="fsqrtsx" opcode="ec00002c" optional="True" sub-form="D-0-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Multiply-Add (Double-Precision)" form="A" group="Floating-Point Multiply-Add Instructions" mnem="fmaddx" opcode="fc00003a" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Multiply-Add Single" form="A" group="Floating-Point Multiply-Add Instructions" mnem="fmaddsx" opcode="ec00003a" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Multiply-Subtract (Double-Precision)" form="A" group="Floating-Point Multiply-Add Instructions" mnem="fmsubx" opcode="fc000038" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Multiply-Subtract Single" form="A" group="Floating-Point Multiply-Add Instructions" mnem="fmsubsx" opcode="ec000038" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Negative Multiply-Add (Double-Precision)" form="A" group="Floating-Point Multiply-Add Instructions" mnem="fnmaddx" opcode="fc00003e" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Negative Multiply-Add Single" form="A" group="Floating-Point Multiply-Add Instructions" mnem="fnmaddsx" opcode="ec00003e" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Negative Multiply-Subtract (Double-Precision)" form="A" group="Floating-Point Multiply-Add Instructions" mnem="fnmsubx" opcode="fc00003c" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Negative Multiply-Subtract Single" form="A" group="Floating-Point Multiply-Add Instructions" mnem="fnmsubsx" opcode="ec00003c" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Convert to Integer Word" form="X" group="Floating-Point Rounding and Conversion Instructions" mnem="fctiwx" opcode="fc00001c" optional="False" sub-form="D-0-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Convert to Integer Word with Round toward Zero" form="X" group="Floating-Point Rounding and Conversion Instructions" mnem="fctiwzx" opcode="fc00001e" optional="True" sub-form="D-0-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Round to Single" form="X" group="Floating-Point Rounding and Conversion Instructions" mnem="frspx" opcode="fc000018" optional="False" sub-form="D-0-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Compare Ordered" form="X" group="Floating-Point Compare Instructions" mnem="fcmpo" opcode="fc000040" optional="False" sub-form="crfD-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Compare Unordered" form="X" group="Floating-Point Compare Instructions" mnem="fcmpu" opcode="fc000000" optional="False" sub-form="crfD-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Move to Condition Register from FPSCR" form="X" group="Floating-Point Status and Control Register Instructions" mnem="mcrfs" opcode="fc000080" optional="False" sub-form="crfD-crfS-0" supervisor="False" /> | |
| <insn arch-level="U" desc="Move from FPSCR" form="X" group="Floating-Point Status and Control Register Instructions" mnem="mffsx" opcode="fc00048e" optional="False" sub-form="D-0-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Move to FPSCR Bit 0" form="X" group="Floating-Point Status and Control Register Instructions" mnem="mtfsb0x" opcode="fc00008c" optional="False" sub-form="crbD-0-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Move to FPSCR Bit 1" form="X" group="Floating-Point Status and Control Register Instructions" mnem="mtfsb1x" opcode="fc00004c" optional="False" sub-form="crbD-0-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Move to FPSCR Fields" form="XFL" group="Floating-Point Status and Control Register Instructions" mnem="mtfsfx" opcode="fc00058e" optional="False" sub-form="FM-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Move to FPSCR Field Immediate" form="X" group="Floating-Point Status and Control Register Instructions" mnem="mtfsfix" opcode="fc00010c" optional="False" sub-form="crfD-0-IMM-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Byte and Zero" form="D" group="Integer Load Instructions" mnem="lbz" opcode="88000000" optional="False" sub-form="D-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Byte and Zero with Update" form="D" group="Integer Load Instructions" mnem="lbzu" opcode="8c000000" optional="False" sub-form="D-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Byte and Zero with Update Indexed" form="X" group="Integer Load Instructions" mnem="lbzux" opcode="7c0000ee" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Byte and Zero Indexed" form="X" group="Integer Load Instructions" mnem="lbzx" opcode="7c0000ae" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Half Word Algebraic" form="D" group="Integer Load Instructions" mnem="lha" opcode="a8000000" optional="False" sub-form="D-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Half Word Algebraic with Update" form="D" group="Integer Load Instructions" mnem="lhau" opcode="ac000000" optional="False" sub-form="D-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Half Word Algebraic with Update Indexed" form="X" group="Integer Load Instructions" mnem="lhaux" opcode="7c0002ee" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Half Word Algebraic Indexed" form="X" group="Integer Load Instructions" mnem="lhax" opcode="7c0002ae" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Half Word and Zero" form="D" group="Integer Load Instructions" mnem="lhz" opcode="a0000000" optional="False" sub-form="D-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Half Word and Zero with Update" form="D" group="Integer Load Instructions" mnem="lhzu" opcode="a4000000" optional="False" sub-form="D-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Half Word and Zero with Update Indexed" form="X" group="Integer Load Instructions" mnem="lhzux" opcode="7c00026e" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Half Word and Zero Indexed" form="X" group="Integer Load Instructions" mnem="lhzx" opcode="7c00022e" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Word and Zero" form="D" group="Integer Load Instructions" mnem="lwz" opcode="80000000" optional="False" sub-form="D-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Word and Zero with Update" form="D" group="Integer Load Instructions" mnem="lwzu" opcode="84000000" optional="False" sub-form="D-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Word and Zero with Update Indexed" form="X" group="Integer Load Instructions" mnem="lwzux" opcode="7c00006e" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Word and Zero Indexed" form="X" group="Integer Load Instructions" mnem="lwzx" opcode="7c00002e" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Byte" form="D" group="Integer Store Instructions" mnem="stb" opcode="98000000" optional="False" sub-form="S-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Byte with Update" form="D" group="Integer Store Instructions" mnem="stbu" opcode="9c000000" optional="False" sub-form="S-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Byte with Update Indexed" form="X" group="Integer Store Instructions" mnem="stbux" opcode="7c0001ee" optional="False" sub-form="S-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Byte Indexed" form="X" group="Integer Store Instructions" mnem="stbx" opcode="7c0001ae" optional="False" sub-form="S-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Half Word" form="D" group="Integer Store Instructions" mnem="sth" opcode="b0000000" optional="False" sub-form="S-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Half Word with Update" form="D" group="Integer Store Instructions" mnem="sthu" opcode="b4000000" optional="False" sub-form="S-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Half Word with Update Indexed" form="X" group="Integer Store Instructions" mnem="sthux" opcode="7c00036e" optional="False" sub-form="S-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Half Word Indexed" form="X" group="Integer Store Instructions" mnem="sthx" opcode="7c00032e" optional="False" sub-form="S-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Word" form="D" group="Integer Store Instructions" mnem="stw" opcode="90000000" optional="False" sub-form="S-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Word with Update" form="D" group="Integer Store Instructions" mnem="stwu" opcode="94000000" optional="False" sub-form="S-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Word with Update Indexed" form="X" group="Integer Store Instructions" mnem="stwux" opcode="7c00016e" optional="False" sub-form="S-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Word Indexed" form="X" group="Integer Store Instructions" mnem="stwx" opcode="7c00012e" optional="False" sub-form="S-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Half Word Byte-Reverse Indexed" form="X" group="Integer Load and Store with Byte Reverse Instructions" mnem="lhbrx" opcode="7c00062c" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Word Byte-Reverse Indexed" form="X" group="Integer Load and Store with Byte Reverse Instructions" mnem="lwbrx" opcode="7c00042c" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Half Word Byte-Reverse Indexed" form="X" group="Integer Load and Store with Byte Reverse Instructions" mnem="sthbrx" opcode="7c00072c" optional="False" sub-form="S-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Word Byte-Reverse Indexed" form="X" group="Integer Load and Store with Byte Reverse Instructions" mnem="stwbrx" opcode="7c00052c" optional="False" sub-form="S-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Multiple Word" form="D" group="Integer Load and Store Multiple Instructions" mnem="lmw" opcode="b8000000" optional="False" sub-form="D-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Multiple Word" form="D" group="Integer Load and Store Multiple Instructions" mnem="stmw" opcode="bc000000" optional="False" sub-form="S-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Load String Word Immediate" form="X" group="Integer Load and Store String Instructions" mnem="lswi" opcode="7c0004aa" optional="False" sub-form="D-A-NB" supervisor="False" /> | |
| <insn arch-level="U" desc="Load String Word Indexed" form="X" group="Integer Load and Store String Instructions" mnem="lswx" opcode="7c00042a" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store String Word Immediate" form="X" group="Integer Load and Store String Instructions" mnem="stswi" opcode="7c0005aa" optional="False" sub-form="S-A-NB" supervisor="False" /> | |
| <insn arch-level="U" desc="Store String Word Indexed" form="X" group="Integer Load and Store String Instructions" mnem="stswx" opcode="7c00052a" optional="False" sub-form="S-A-B" supervisor="False" /> | |
| <insn arch-level="V" desc="Enforce In-Order Execution of I/O" form="X" group="Memory Synchronization Instructions" mnem="eieio" opcode="7c0006ac" optional="True" sub-form="0-0-0" supervisor="False" /> | |
| <insn arch-level="V" desc="Instruction Synchronize" form="XL" group="Memory Synchronization Instructions" mnem="isync" opcode="4c00012c" optional="False" sub-form="0-0-0" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Word and Reserve Indexed" form="X" group="Memory Synchronization Instructions" mnem="lwarx" opcode="7c000028" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Word Conditional Indexed" form="X" group="Memory Synchronization Instructions" mnem="stwcx." opcode="7c00012d" optional="False" sub-form="S-A-B-1" supervisor="False" /> | |
| <insn arch-level="U" desc="Synchronize" form="X" group="Memory Synchronization Instructions" mnem="sync" opcode="7c0004ac" optional="False" sub-form="0-0-0" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Floating-Point Double" form="D" group="Floating-Point Load Instructions" mnem="lfd" opcode="c8000000" optional="False" sub-form="D-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Floating-Point Double with Update" form="D" group="Floating-Point Load Instructions" mnem="lfdu" opcode="cc000000" optional="False" sub-form="D-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Floating-Point Double with Update Indexed" form="X" group="Floating-Point Load Instructions" mnem="lfdux" opcode="7c0004ee" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Floating-Point Double Indexed" form="X" group="Floating-Point Load Instructions" mnem="lfdx" opcode="7c0004ae" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Floating-Point Single" form="D" group="Floating-Point Load Instructions" mnem="lfs" opcode="c0000000" optional="False" sub-form="D-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Floating-Point Single with Update" form="D" group="Floating-Point Load Instructions" mnem="lfsu" opcode="c4000000" optional="False" sub-form="D-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Floating-Point Single with Update Indexed" form="X" group="Floating-Point Load Instructions" mnem="lfsux" opcode="7c00046e" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Load Floating-Point Single Indexed" form="X" group="Floating-Point Load Instructions" mnem="lfsx" opcode="7c00042e" optional="False" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Floating-Point Double" form="D" group="Floating-Point Store Instructions" mnem="stfd" opcode="d8000000" optional="False" sub-form="S-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Floating-Point Double with Update" form="D" group="Floating-Point Store Instructions" mnem="stfdu" opcode="dc000000" optional="False" sub-form="S-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Floating-Point Double with Update Indexed" form="X" group="Floating-Point Store Instructions" mnem="stfdux" opcode="7c0005ee" optional="False" sub-form="S-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Floating-Point Double Indexed" form="X" group="Floating-Point Store Instructions" mnem="stfdx" opcode="7c0005ae" optional="False" sub-form="S-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Floating-Point as Integer Word Indexed" form="X" group="Floating-Point Store Instructions" mnem="stfiwx" opcode="7c0007ae" optional="True" sub-form="S-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Floating-Point Single" form="D" group="Floating-Point Store Instructions" mnem="stfs" opcode="d0000000" optional="False" sub-form="S-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Floating-Point Single with Update" form="D" group="Floating-Point Store Instructions" mnem="stfsu" opcode="d4000000" optional="False" sub-form="S-A-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Floating-Point Single with Update Indexed" form="X" group="Floating-Point Store Instructions" mnem="stfsux" opcode="7c00056e" optional="False" sub-form="S-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Store Floating-Point Single Indexed" form="X" group="Floating-Point Store Instructions" mnem="stfsx" opcode="7c00052e" optional="False" sub-form="S-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Absolute Value" form="X" group="Floating-Point Move Instructions" mnem="fabsx" opcode="fc000210" optional="False" sub-form="D-0-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Move Register(Double-Precision)" form="X" group="Floating-Point Move Instructions" mnem="fmrx" opcode="fc000090" optional="False" sub-form="D-0-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Negative Absolute Value" form="X" group="Floating-Point Move Instructions" mnem="fnabsx" opcode="fc000110" optional="False" sub-form="D-0-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Floating Negate" form="X" group="Floating-Point Move Instructions" mnem="fnegx" opcode="fc000050" optional="False" sub-form="D-0-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Branch" form="I" group="Branch Instructions" mnem="bx" opcode="48000000" optional="False" sub-form="LI-AA-LK" supervisor="False" /> | |
| <insn arch-level="U" desc="Branch Conditional" form="B" group="Branch Instructions" mnem="bcx" opcode="40000000" optional="False" sub-form="BO-BI-BD-AA-LK" supervisor="False" /> | |
| <insn arch-level="U" desc="Branch Conditional to Count Register" form="XL" group="Branch Instructions" mnem="bcctrx" opcode="4c000420" optional="False" sub-form="BO-BI-0-LK" supervisor="False" /> | |
| <insn arch-level="U" desc="Branch Conditional to Link Register" form="XL" group="Branch Instructions" mnem="bclrx" opcode="4c000020" optional="False" sub-form="BO-BI-0-LK" supervisor="False" /> | |
| <insn arch-level="U" desc="Condition Register AND" form="XL" group="Condition Register Logical Instructions" mnem="crand" opcode="4c000202" optional="False" sub-form="crbD-crbA-crbB" supervisor="False" /> | |
| <insn arch-level="U" desc="Condition Register AND with Complement" form="XL" group="Condition Register Logical Instructions" mnem="crandc" opcode="4c000102" optional="False" sub-form="crbD-crbA-crbB" supervisor="False" /> | |
| <insn arch-level="U" desc="Condition Register Equivalent" form="XL" group="Condition Register Logical Instructions" mnem="creqv" opcode="4c000242" optional="False" sub-form="crbD-crbA-crbB" supervisor="False" /> | |
| <insn arch-level="U" desc="Condition Register NAND" form="XL" group="Condition Register Logical Instructions" mnem="crnand" opcode="4c0001c2" optional="False" sub-form="crbD-crbA-crbB" supervisor="False" /> | |
| <insn arch-level="U" desc="Condition Register NOR" form="XL" group="Condition Register Logical Instructions" mnem="crnor" opcode="4c000042" optional="False" sub-form="crbD-crbA-crbB" supervisor="False" /> | |
| <insn arch-level="U" desc="Condition Register OR" form="XL" group="Condition Register Logical Instructions" mnem="cror" opcode="4c000382" optional="False" sub-form="crbD-crbA-crbB" supervisor="False" /> | |
| <insn arch-level="U" desc="Condition Register OR with Complement" form="XL" group="Condition Register Logical Instructions" mnem="crorc" opcode="4c000342" optional="False" sub-form="crbD-crbA-crbB" supervisor="False" /> | |
| <insn arch-level="U" desc="Condition Register XOR" form="XL" group="Condition Register Logical Instructions" mnem="crxor" opcode="4c000182" optional="False" sub-form="crbD-crbA-crbB" supervisor="False" /> | |
| <insn arch-level="U" desc="Move Condition Register Field" form="XL" group="Condition Register Logical Instructions" mnem="mcrf" opcode="4c000000" optional="False" sub-form="crfD-crfS-0" supervisor="False" /> | |
| <insn arch-level="O" desc="Return from Interrupt" form="XL" group="System Linkage Instructions" mnem="rfi" opcode="4c000064" optional="False" sub-form="0-0-0" supervisor="True" /> | |
| <insn arch-level="UO" desc="System Call" form="SC" group="System Linkage Instructions" mnem="sc" opcode="44000002" optional="False" sub-form="sc" supervisor="False" /> | |
| <insn arch-level="U" desc="Trap Word" form="X" group="Trap Instructions" mnem="tw" opcode="7c000008" optional="False" sub-form="TO-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Trap Word Immediate" form="D" group="Trap Instructions" mnem="twi" opcode="0c000000" optional="False" sub-form="TO-A-SIMM" supervisor="False" /> | |
| <insn arch-level="U" desc="Move to Condition Register from XER" form="X" group="Processor Control Instructions" mnem="mcrxr" opcode="7c000400" optional="False" sub-form="crfD-0-0" supervisor="False" /> | |
| <insn arch-level="U" desc="Move from Condition Register" form="X" group="Processor Control Instructions" mnem="mfcr" opcode="7c000026" optional="False" sub-form="D-0-0" supervisor="False" /> | |
| <insn arch-level="O" desc="Move from Machine State Register" form="X" group="Processor Control Instructions" mnem="mfmsr" opcode="7c0000a6" optional="False" sub-form="D-0-0" supervisor="True" /> | |
| <insn arch-level="UO" desc="Move from Special-Purpose Register" form="XFX" group="Processor Control Instructions" mnem="mfspr" opcode="7c0002a6" optional="False" sub-form="D-spr" supervisor="True" /> | |
| <insn arch-level="V" desc="Move from Time Base" form="XFX" group="Processor Control Instructions" mnem="mftb" opcode="7c0002e6" optional="False" sub-form="D-tbr" supervisor="False" /> | |
| <insn arch-level="U" desc="Move to Condition Register Fields" form="XFX" group="Processor Control Instructions" mnem="mtcrf" opcode="7c000120" optional="False" sub-form="S-CRM" supervisor="False" /> | |
| <insn arch-level="O" desc="Move to Machine State Register" form="X" group="Processor Control Instructions" mnem="mtmsr" opcode="7c000124" optional="False" sub-form="S-0-0" supervisor="True" /> | |
| <insn arch-level="UO" desc="Move to Special-Purpose Register" form="XFX" group="Processor Control Instructions" mnem="mtspr" opcode="7c0003a6" optional="False" sub-form="S-spr" supervisor="True" /> | |
| <insn arch-level="V" desc="Data Cache Block Allocate" form="X" group="Cache Management Instructions" mnem="dcba" opcode="7c0005ec" optional="True" sub-form="0-A-B" supervisor="False" /> | |
| <insn arch-level="V" desc="Data Cache Block Flush" form="X" group="Cache Management Instructions" mnem="dcbf" opcode="7c0000ac" optional="False" sub-form="0-A-B" supervisor="False" /> | |
| <insn arch-level="O" desc="Data Cache Block Invalidate" form="X" group="Cache Management Instructions" mnem="dcbi" opcode="7c0003ac" optional="False" sub-form="0-A-B" supervisor="True" /> | |
| <insn arch-level="V" desc="Data Cache Block Store" form="X" group="Cache Management Instructions" mnem="dcbst" opcode="7c00006c" optional="False" sub-form="0-A-B" supervisor="False" /> | |
| <insn arch-level="V" desc="Data Cache Block Touch" form="X" group="Cache Management Instructions" mnem="dcbt" opcode="7c00022c" optional="False" sub-form="0-A-B" supervisor="False" /> | |
| <insn arch-level="V" desc="Data Cache Block Touch for Store" form="X" group="Cache Management Instructions" mnem="dcbtst" opcode="7c0001ec" optional="False" sub-form="0-A-B" supervisor="False" /> | |
| <insn arch-level="V" desc="Data Cache Block Clear to Zero" form="X" group="Cache Management Instructions" mnem="dcbz" opcode="7c0007ec" optional="False" sub-form="0-A-B" supervisor="False" /> | |
| <insn arch-level="V" desc="Instruction Cache Block Invalidate" form="X" group="Cache Management Instructions" mnem="icbi" opcode="7c0007ac" optional="False" sub-form="0-A-B" supervisor="False" /> | |
| <insn arch-level="O" desc="Move from Segment Register" form="X" group="Segment Register Manipulation Instructions" mnem="mfsr" opcode="7c0004a6" optional="False" sub-form="D-SR-0" supervisor="True" /> | |
| <insn arch-level="O" desc="Move from Segment Register Indirect" form="X" group="Segment Register Manipulation Instructions" mnem="mfsrin" opcode="7c000526" optional="False" sub-form="D-0-B" supervisor="True" /> | |
| <insn arch-level="O" desc="Move to Segment Register" form="X" group="Segment Register Manipulation Instructions" mnem="mtsr" opcode="7c0001a4" optional="False" sub-form="S-SR-0" supervisor="True" /> | |
| <insn arch-level="O" desc="Move to Segment Register Indirect" form="X" group="Segment Register Manipulation Instructions" mnem="mtsrin" opcode="7c0001e4" optional="True" sub-form="S-0-B" supervisor="True" /> | |
| <insn arch-level="O" desc="Translation Lookaside Buffer Invalidate All" form="X" group="Lookaside Buffer Management Instructions" mnem="tlbia" opcode="7c0002e4" optional="True" sub-form="0-0-0" supervisor="True" /> | |
| <insn arch-level="O" desc="Translation Lookaside Buffer Invalidate Entry" form="X" group="Lookaside Buffer Management Instructions" mnem="tlbie" opcode="7c000264" optional="True" sub-form="0-0-B" supervisor="True" /> | |
| <insn arch-level="O" desc="TLB Synchronize" form="X" group="Lookaside Buffer Management Instructions" mnem="tlbsync" opcode="7c00046c" optional="False" sub-form="0-0-0" supervisor="True" /> | |
| <insn arch-level="V" desc="External Control In Word Indexed" form="X" group="External Control Instructions" mnem="eciwx" opcode="7c00026c" optional="True" sub-form="D-A-B" supervisor="False" /> | |
| <insn arch-level="V" desc="External Control Out Word Indexed" form="X" group="External Control Instructions" mnem="ecowx" opcode="7c00036c" optional="True" sub-form="S-A-B" supervisor="False" /> | |
| </ppc-isa> | |
| <ppc-isa name="Espresso"> | |
| <insn arch-level="U" desc="Paired Single Quantized Load Indexed" form="XW" group="Paired-Single Load and Store Instructions" mnem="psq_lx" opcode="1000000c" optional="False" sub-form="D-A-B-w-i" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Quantized Store Indexed" form="XW" group="Paired-Single Load and Store Instructions" mnem="psq_stx" opcode="1000000e" optional="False" sub-form="S-A-B-w-i" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Quantized Load with update Indexed" form="XW" group="Paired-Single Load and Store Instructions" mnem="psq_lux" opcode="1000004c" optional="False" sub-form="D-A-B-w-i" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Quantized Store with Update Indexed" form="XW" group="Paired-Single Load and Store Instructions" mnem="psq_stux" opcode="1000004e" optional="False" sub-form="S-A-B-w-i" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Quantized Load" form="DW" group="Paired-Single Load and Store Instructions" mnem="psq_l" opcode="e0000000" optional="False" sub-form="D-A-w-i-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Quantized Load with Update" form="DW" group="Paired-Single Load and Store Instructions" mnem="psq_lu" opcode="e4000000" optional="False" sub-form="D-A-w-i-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Quantized Store" form="DW" group="Paired-Single Load and Store Instructions" mnem="psq_st" opcode="f0000000" optional="False" sub-form="S-A-w-i-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Quantized Store with update" form="DW" group="Paired-Single Load and Store Instructions" mnem="psq_stu" opcode="f4000000" optional="False" sub-form="S-A-w-i-d" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Divide" form="A" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_divx" opcode="10000024" optional="False" sub-form="D-A-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Subtract" form="A" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_subx" opcode="10000028" optional="False" sub-form="D-A-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Add" form="A" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_addx" opcode="1000002a" optional="False" sub-form="D-A-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Select" form="A" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_selx" opcode="1000002e" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Reciprocal Estimate" form="A" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_resx" opcode="10000030" optional="False" sub-form="D-0-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Multiply" form="A" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_mulx" opcode="10000032" optional="False" sub-form="D-A-0-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Reciprocal Square Root Estimate" form="A" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_rsqrtex" opcode="10000034" optional="False" sub-form="D-0-B-0-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Multiply-Subtract" form="A" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_msubx" opcode="10000038" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Multiply-Add" form="A" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_maddx" opcode="1000003a" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Negative Multiply-Subtract" form="A" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_nmsubx" opcode="1000003c" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Negative Multiply-Add" form="A" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_nmaddx" opcode="1000003e" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Negate" form="X" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_negx" opcode="10000050" optional="False" sub-form="D-0-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Move Register" form="X" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_mrx" opcode="10000090" optional="False" sub-form="D-0-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Negative Absolute Value" form="X" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_nabsx" opcode="10000110" optional="False" sub-form="D-0-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Absolute Value" form="X" group="Paired-Single Floating-Point Arithmetic Instructions" mnem="ps_absx" opcode="10000210" optional="False" sub-form="D-0-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single vector SUM high" form="A" group="Miscellaneous Paired-Single Instructions" mnem="ps_sum0x" opcode="10000014" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single vector SUM low" form="A" group="Miscellaneous Paired-Single Instructions" mnem="ps_sum1x" opcode="10000016" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Multiply Scalar High" form="A" group="Miscellaneous Paired-Single Instructions" mnem="ps_muls0x" opcode="10000018" optional="False" sub-form="D-A-0-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Multiply Scalar Low" form="A" group="Miscellaneous Paired-Single Instructions" mnem="ps_muls1x" opcode="1000001a" optional="False" sub-form="D-A-0-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Multiply-Add Scalar high" form="A" group="Miscellaneous Paired-Single Instructions" mnem="ps_madds0x" opcode="1000001c" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single Multiply-Add Scalar low" form="A" group="Miscellaneous Paired-Single Instructions" mnem="ps_madds1x" opcode="1000001e" optional="False" sub-form="D-A-B-C-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Singles Compare Unordered High" form="X" group="Miscellaneous Paired-Single Instructions" mnem="ps_cmpu0" opcode="10000000" optional="False" sub-form="crfD-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Singles Compare Ordered High" form="X" group="Miscellaneous Paired-Single Instructions" mnem="ps_cmpo0" opcode="10000040" optional="False" sub-form="crfD-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Singles Compare Unordered Low" form="X" group="Miscellaneous Paired-Single Instructions" mnem="ps_cmpu1" opcode="10000080" optional="False" sub-form="crfD-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Singles Compare Ordered Low" form="X" group="Miscellaneous Paired-Single Instructions" mnem="ps_cmpo1" opcode="100000c0" optional="False" sub-form="crfD-A-B" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single MERGE high" form="X" group="Miscellaneous Paired-Single Instructions" mnem="ps_merge00x" opcode="10000420" optional="False" sub-form="D-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single MERGE direct" form="X" group="Miscellaneous Paired-Single Instructions" mnem="ps_merge01x" opcode="10000460" optional="False" sub-form="D-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single MERGE swapped" form="X" group="Miscellaneous Paired-Single Instructions" mnem="ps_merge10x" opcode="100004a0" optional="False" sub-form="D-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="U" desc="Paired Single MERGE low" form="X" group="Miscellaneous Paired-Single Instructions" mnem="ps_merge11x" opcode="100004e0" optional="False" sub-form="D-A-B-Rc" supervisor="False" /> | |
| <insn arch-level="V" desc="Data Cache Block Set to Zero Locked" form="X" group="Miscellaneous Paired-Single Instructions" mnem="dcbz_l" opcode="100007ec" optional="False" sub-form="0-A-B" supervisor="False" /> | |
| </ppc-isa> | |
| </root> |
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