rgmii_phy_status.diff

diff --git a/liteeth/phy/ecp5rgmii.py b/liteeth/phy/ecp5rgmii.py
index 9bb1999..8899aaa 100644
--- a/liteeth/phy/ecp5rgmii.py
+++ b/liteeth/phy/ecp5rgmii.py
@@ -66,8 +66,10 @@ class LiteEthPHYRGMIIRX(Module):
         assert rx_delay_taps < 128

         rx_ctl_delayf  = Signal()
-        rx_ctl         = Signal()
-        rx_ctl_reg     = Signal()
+        rx_ctl_r       = Signal()
+        rx_ctl_f       = Signal()
+        rx_ctl_r_reg   = Signal()
+        rx_ctl_f_reg   = Signal()
         rx_data_delayf = Signal(4)
         rx_data        = Signal(8)
         rx_data_reg    = Signal(8)
@@ -84,11 +86,15 @@ class LiteEthPHYRGMIIRX(Module):
             DDRInput(
                 clk = ClockSignal("eth_rx"),
                 i   = rx_ctl_delayf,
-                o1  = rx_ctl,
-                o2  = Signal()
+                o1  = rx_ctl_r,
+                o2  = rx_ctl_f
             )
         ]
-        self.sync += rx_ctl_reg.eq(rx_ctl)
+        self.sync += [
+            rx_ctl_r_reg.eq(rx_ctl_r),
+            rx_ctl_f_reg.eq(rx_ctl_f)
+        ]
+
         for i in range(4):
             self.specials += [
                 Instance("DELAYF",
@@ -108,17 +114,29 @@ class LiteEthPHYRGMIIRX(Module):
             ]
         self.sync += rx_data_reg.eq(rx_data)

-        rx_ctl_reg_d = Signal()
-        self.sync += rx_ctl_reg_d.eq(rx_ctl_reg)
+        rx_ctl_r_reg_d = Signal()
+        self.sync += rx_ctl_r_reg_d.eq(rx_ctl_r_reg)

         last = Signal()
-        self.comb += last.eq(~rx_ctl_reg & rx_ctl_reg_d)
+        self.comb += last.eq(~rx_ctl_r_reg & rx_ctl_r_reg_d)
         self.sync += [
-            source.valid.eq(rx_ctl_reg),
-            source.data.eq(Cat(rx_data_reg[:4], rx_data_reg[4:]))
+            source.valid.eq(rx_ctl_r_reg),
+            source.data.eq(rx_data_reg)
         ]
         self.comb += source.last.eq(last)

+        inter_frame = Signal()
+        self.comb += inter_frame.eq(~(rx_ctl_r_reg | rx_ctl_f_reg))
+
+        # phy_status signals optionally sent during inter-frame
+        self.link_up = Signal()
+        self.rxc_speed = Signal(2)
+        self.full_duplex = Signal()
+        self.sync += If(inter_frame,
+            self.link_up.eq(rx_data_reg[0]),
+            self.rxc_speed.eq(rx_data_reg[1:3]),
+            self.full_duplex.eq(rx_data_reg[3]))
+