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May 5, 2020 11:37
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This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters. Learn more about bidirectional Unicode charactersOriginal file line number Diff line number Diff line change @@ -0,0 +1,104 @@ // attempting to create 100mhz ->pll-> 125mhz // note clarity seems to suggest buffering clk100 since it's coming from pads, and // various parameters differ from litex (besides defaulted ones) // litex (* FREQUENCY_PIN_CLKI = "100.0", ICP_CURRENT = "6", LPF_RESISTOR = "16", MFG_ENABLE_FILTEROPAMP = "1", MFG_GMCREF_SEL = "2" *) EHXPLLL #( .CLKFB_DIV(3'd5), .CLKI_DIV(1'd1), .CLKOP_CPHASE(3'd4), .CLKOP_DIV(3'd4), .CLKOP_ENABLE("ENABLED"), .CLKOP_FPHASE(1'd0), .CLKOS3_DIV(1'd1), .CLKOS3_ENABLE("ENABLED"), .FEEDBK_PATH("INT_OS3") ) EHXPLLL ( .CLKI(crg_clkin), .RST(crg_reset), .CLKOP(crg_clkout), .LOCK(crg_locked) ); // clarity `timescale 1 ns / 1 ps module pll_inst (CLKI, RST, CLKOP, LOCK)/* synthesis NGD_DRC_MASK=1 */; input wire CLKI; input wire RST; output wire CLKOP; output wire LOCK; wire REFCLK; wire CLKOP_t; wire CLKFB_t; wire buf_CLKI; wire scuba_vhi; wire scuba_vlo; IB Inst1_IB (.I(CLKI), .O(buf_CLKI)) /* synthesis IO_TYPE="LVDS" */; VHI scuba_vhi_inst (.Z(scuba_vhi)); VLO scuba_vlo_inst (.Z(scuba_vlo)); defparam PLLInst_0.PLLRST_ENA = "ENABLED" ; defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; defparam PLLInst_0.CLKOS3_FPHASE = 0 ; defparam PLLInst_0.CLKOS3_CPHASE = 0 ; defparam PLLInst_0.CLKOS2_FPHASE = 0 ; defparam PLLInst_0.CLKOS2_CPHASE = 0 ; defparam PLLInst_0.CLKOS_FPHASE = 0 ; defparam PLLInst_0.CLKOS_CPHASE = 0 ; defparam PLLInst_0.CLKOP_FPHASE = 0 ; defparam PLLInst_0.CLKOP_CPHASE = 4 ; defparam PLLInst_0.PLL_LOCK_MODE = 0 ; defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; defparam PLLInst_0.CLKOS3_DIV = 1 ; defparam PLLInst_0.CLKOS2_DIV = 1 ; defparam PLLInst_0.CLKOS_DIV = 1 ; defparam PLLInst_0.CLKOP_DIV = 5 ; defparam PLLInst_0.CLKFB_DIV = 5 ; defparam PLLInst_0.CLKI_DIV = 4 ; defparam PLLInst_0.FEEDBK_PATH = "INT_OP" ; EHXPLLL PLLInst_0 (.CLKI(buf_CLKI), .CLKFB(CLKFB_t), .PHASESEL1(scuba_vlo), .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), .RST(RST), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB(CLKFB_t)) /* synthesis FREQUENCY_PIN_CLKOP="125.000000" */ /* synthesis FREQUENCY_PIN_CLKI="100.000000" */ /* synthesis ICP_CURRENT="5" */ /* synthesis LPF_RESISTOR="16" */; assign CLKOP = CLKOP_t; // exemplar begin // exemplar attribute Inst1_IB IO_TYPE LVDS // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 125.000000 // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 100.000000 // exemplar attribute PLLInst_0 ICP_CURRENT 5 // exemplar attribute PLLInst_0 LPF_RESISTOR 16 // exemplar end endmodule