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Last active October 7, 2023 19:20
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CGA and VGA signal timings for converter project

Clock and timing info for CGA and VGA signal

CGA Params

https://www.vogons.org/viewtopic.php?f=9&t=47052

  • Resolution: 320x200x60 (/2)
  • Vertical: 15.750Khz
  • Pixel: 14.318Mhz (315 / 22)

Horizontal

  • Visible: 320
  • Sync pos: 360
  • Sync wid: 80
  • Total: 448
  • Polarity: P

errata The actual hsync pulse sent to the monitor starts 32 hdots after the hsync pulse from the CRTC, and is 64 hdots wide (if not truncated).

Vertical

  • Visible: 200
  • Adjust: 6
  • SyncStart: 226 errata 224
  • Sync: 16 (226 - 242) errata 3 (224 - 227)
  • Back: 242 - 262?
  • Total: 256
  • Polarity: P

errata The vsync pulse generated by the CRTC (and reflected in port 0x3da) is 16 scanlines long (fixed by the CRTC), but the vsync pulse sent to the monitor is only 3 scanlines long (adjusted by the CGA to match NTSC specifications). Ah yes, the same can also be said for hsync I suppose. If you set a hsync width of 16, that is not the hsync pulse alone, but the whole period of horizontal blank, front porch, hsync pulse, back porch, and the colorburst. Right. The actual hsync pulse sent to the monitor starts 32 hdots after the hsync pulse from the CRTC, and is 64 hdots wide (if not truncated).

VGA Output 640x400x70

http://tinyvga.com/vga-timing/640x400@70Hz https://www.digikey.com/eewiki/pages/viewpage.action?pageId=15925278

  • Resolution: 640x400x70
  • Vertical: 31.46875 kHz
  • Pixel: 25.175 MHz

Horizontal

  • Visible: 640
  • Front: 16
  • Sync: 96
  • Back: 48
  • Total: 800
  • Polarity: N

Vertical

  • Visible: 400
  • Front: 12
  • Sync: 2
  • Back: 35
  • Total: 449
  • Polarity: P

Ref

Scheme

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