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@sigmaris
Created Feb 17, 2020
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ATF compiled with GCC 9.2.0 suspend exception
This file has been truncated, but you can view the full file.
build/rk3399/debug/bl31/bl31.elf: file format elf64-littleaarch64
build/rk3399/debug/bl31/bl31.elf
architecture: aarch64, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x0000000000040000
Program Header:
LOAD off 0x0000000000010000 vaddr 0x0000000000040000 paddr 0x0000000000040000 align 2**16
filesz 0x0000000000027072 memsz 0x0000000000057000 flags rwx
LOAD off 0x0000000000040000 vaddr 0x00000000ff3b0000 paddr 0x00000000ff3b0000 align 2**16
filesz 0x0000000000001f54 memsz 0x0000000000001f54 flags rwx
LOAD off 0x0000000000050000 vaddr 0x00000000ff8c0000 paddr 0x00000000ff8c0000 align 2**16
filesz 0x0000000000002000 memsz 0x0000000000003000 flags rwx
STACK off 0x0000000000000000 vaddr 0x0000000000000000 paddr 0x0000000000000000 align 2**4
filesz 0x0000000000000000 memsz 0x0000000000000000 flags rw-
private flags = 0:
Sections:
Idx Name Size VMA LMA File off Algn
0 .incbin_sram 00001000 00000000ff8c0000 00000000ff8c0000 00050000 2**12
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text_sram 00001000 00000000ff8c1000 00000000ff8c1000 00051000 2**12
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .data_sram 00000000 00000000ff8c2000 00000000ff8c2000 00052000 2**12
CONTENTS
3 .stack_sram 00001000 00000000ff8c2000 00000000ff8c2000 00052000 2**12
ALLOC
4 .pmusram 00001f54 00000000ff3b0000 00000000ff3b0000 00040000 2**4
CONTENTS, ALLOC, LOAD, CODE
5 ro 00027000 0000000000040000 0000000000040000 00010000 2**16
CONTENTS, ALLOC, LOAD, CODE
6 .data 00000072 0000000000067000 0000000000067000 00037000 2**3
CONTENTS, ALLOC, LOAD, DATA
7 stacks 00003000 0000000000067080 0000000000067080 00037072 2**6
ALLOC
8 .bss 00017c95 000000000006a080 000000000006a080 00037072 2**6
ALLOC
9 xlat_table 00014000 0000000000082000 0000000000082000 00037072 2**12
ALLOC
10 coherent_ram 00001000 0000000000096000 0000000000096000 00037072 2**12
ALLOC
11 .debug_info 00054740 0000000000000000 0000000000000000 00052000 2**0
CONTENTS, READONLY, DEBUGGING
12 .debug_abbrev 0000b328 0000000000000000 0000000000000000 000a6740 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_aranges 00003360 0000000000000000 0000000000000000 000b1a70 2**4
CONTENTS, READONLY, DEBUGGING
14 .debug_line 00025b7d 0000000000000000 0000000000000000 000b4dd0 2**0
CONTENTS, READONLY, DEBUGGING
15 .debug_str 000093f4 0000000000000000 0000000000000000 000da94d 2**0
CONTENTS, READONLY, DEBUGGING
16 .comment 00000011 0000000000000000 0000000000000000 000e3d41 2**0
CONTENTS, READONLY
17 .debug_loc 00058f39 0000000000000000 0000000000000000 000e3d52 2**0
CONTENTS, READONLY, DEBUGGING
18 .debug_ranges 00012bd0 0000000000000000 0000000000000000 0013cc90 2**4
CONTENTS, READONLY, DEBUGGING
19 .debug_frame 00001010 0000000000000000 0000000000000000 0014f860 2**3
CONTENTS, READONLY, DEBUGGING
SYMBOL TABLE:
00000000ff8c0000 l d .incbin_sram 0000000000000000 .incbin_sram
00000000ff8c1000 l d .text_sram 0000000000000000 .text_sram
00000000ff8c2000 l d .data_sram 0000000000000000 .data_sram
00000000ff8c2000 l d .stack_sram 0000000000000000 .stack_sram
00000000ff3b0000 l d .pmusram 0000000000000000 .pmusram
0000000000040000 l d ro 0000000000000000 ro
0000000000067000 l d .data 0000000000000000 .data
0000000000067080 l d stacks 0000000000000000 stacks
000000000006a080 l d .bss 0000000000000000 .bss
0000000000082000 l d xlat_table 0000000000000000 xlat_table
0000000000096000 l d coherent_ram 0000000000000000 coherent_ram
0000000000000000 l d .debug_info 0000000000000000 .debug_info
0000000000000000 l d .debug_abbrev 0000000000000000 .debug_abbrev
0000000000000000 l d .debug_aranges 0000000000000000 .debug_aranges
0000000000000000 l d .debug_line 0000000000000000 .debug_line
0000000000000000 l d .debug_str 0000000000000000 .debug_str
0000000000000000 l d .comment 0000000000000000 .comment
0000000000000000 l d .debug_loc 0000000000000000 .debug_loc
0000000000000000 l d .debug_ranges 0000000000000000 .debug_ranges
0000000000000000 l d .debug_frame 0000000000000000 .debug_frame
0000000000000000 l df *ABS* 0000000000000000 pmu_fw.c
0000000000000000 l df *ABS* 0000000000000000 ./build/rk3399/debug/bl31/plat_helpers.o
00000000ff8c102c l .text_sram 0000000000000000 check_ddrc0_1_sref_enter
00000000ff8c1068 l .text_sram 0000000000000000 check_ddrc0_1_sref_exit
000000000005febc l ro 0000000000000000 handler_a72
000000000005fec8 l ro 0000000000000000 handler_end
0000000000050038 l ro 0000000000000000 clst_warmboot_end
0000000000050060 l ro 0000000000000000 boot_entry
0000000000050058 l ro 0000000000000000 wfe_loop
0000000000000000 l df *ABS* 0000000000000000 ./build/rk3399/debug/bl31/pmu_sram_cpus_on.o
00000000ff3b0000 l .pmusram 0000000000000000 ddr_resume
00000000ff3b0010 l .pmusram 0000000000000000 sys_resume
0000000000000000 l df *ABS* 0000000000000000 secure.c
0000000000000000 l df *ABS* 0000000000000000 soc.c
00000000000568f8 l F ro 0000000000000078 restore_pll.constprop.0
000000000006ea4c l O .bss 0000000000000158 slp_data
0000000000000000 l df *ABS* 0000000000000000 suspend.c
00000000ff3b00e4 l F .pmusram 0000000000000024 sram_regcpy
000000000005ba94 l F ro 0000000000000024 dram_regcpy
00000000ff3b0108 l F .pmusram 0000000000000030 sram_udelay
00000000ff3b0138 l F .pmusram 0000000000000048 rkclk_ddr_reset
00000000ff3b0180 l F .pmusram 0000000000000054 select_per_cs_training_index
00000000ff3b01d4 l F .pmusram 00000000000004f8 data_training.constprop.0
0000000000000000 l df *ABS* 0000000000000000 dram.c
0000000000000000 l df *ABS* 0000000000000000 ./build/rk3399/debug/bl31/bl31_entrypoint.o
0000000000000000 l df *ABS* 0000000000000000 gic_common.c
0000000000000000 l df *ABS* 0000000000000000 arm_gicv3_common.c
0000000000000000 l df *ABS* 0000000000000000 gic500.c
0000000000000000 l df *ABS* 0000000000000000 gicv3_main.c
0000000000050388 l F ro 000000000000000c gicr_wait_for_pending_write
0000000000000000 l df *ABS* 0000000000000000 gicv3_helpers.c
0000000000000000 l df *ABS* 0000000000000000 plat_gicv3.c
0000000000062b41 l O ro 0000000000000004 CSWTCH.12
0000000000000000 l df *ABS* 0000000000000000 rockchip_gicv3.c
00000000000516ec l F ro 0000000000000004 plat_rockchip_mpidr_to_core_pos
00000000000622f8 l O ro 0000000000000008 g01s_interrupt_props
0000000000000000 l df *ABS* 0000000000000000 cci.c
000000000006b098 l O .bss 0000000000000008 cci_base
000000000006dd70 l O .bss 0000000000000004 cci_num_slave_ports
000000000006b0a0 l O .bss 0000000000000008 cci_slave_if_map
000000000006dd74 l O .bss 0000000000000004 max_master_id
0000000000062c82 l O ro 0000000000000004 CSWTCH.22
0000000000000000 l df *ABS* 0000000000000000 delay_timer.c
000000000006b0a8 l O .bss 0000000000000008 timer_ops
0000000000000000 l df *ABS* 0000000000000000 generic_delay_timer.c
0000000000051acc l F ro 000000000000000c get_timer_value
000000000006b0b0 l O .bss 0000000000000010 ops
0000000000000000 l df *ABS* 0000000000000000 gpio.c
000000000006b0c0 l O .bss 0000000000000008 ops
0000000000000000 l df *ABS* 0000000000000000 bl31_plat_setup.c
000000000006b0c8 l O .bss 0000000000000058 bl32_ep_info
000000000006b120 l O .bss 0000000000000058 bl33_ep_info
000000000006b178 l O .bss 0000000000000030 console.1964
0000000000000000 l df *ABS* 0000000000000000 params_setup.c
0000000000051de4 l F ro 00000000000000d8 rk_aux_param_handler
000000000006ec88 l O .bss 0000000000010000 fdt_buffer
000000000007ec88 l O .bss 0000000000000001 suspend_apio
000000000006dd78 l O .bss 0000000000000050 suspend_gpio
0000000000067028 l O .data 0000000000000008 poweroff_gpio
0000000000067030 l O .data 0000000000000004 rk_uart_base
0000000000067034 l O .data 0000000000000004 rk_uart_baudrate
0000000000067038 l O .data 0000000000000008 rst_gpio
0000000000000000 l df *ABS* 0000000000000000 plat_pm.c
0000000000052338 l F ro 000000000000000c rockchip_system_reset
0000000000052344 l F ro 000000000000000c rockchip_system_poweroff
0000000000052368 l F ro 000000000000001c rockchip_pd_pwr_down_wfi
000000000006b1a8 l O .bss 0000000000000008 rockchip_sec_entrypoint
0000000000000000 l df *ABS* 0000000000000000 plat_topology.c
0000000000000000 l df *ABS* 0000000000000000 platform_common.c
0000000000062304 l O ro 0000000000000008 cci_map
0000000000000000 l df *ABS* 0000000000000000 rockchip_sip_svc.c
0000000000065138 l O ro 0000000000000020 __svc_desc_rockchip_sip_svc
0000000000000000 l df *ABS* 0000000000000000 plat_sip_calls.c
00000000000630b3 l O ro 000000000000001a __func__.1837
0000000000000000 l df *ABS* 0000000000000000 rk3399_gpio.c
0000000000052604 l F ro 00000000000000b8 gpio_get_clock
0000000000052730 l F ro 00000000000000f8 get_pull
0000000000052828 l F ro 000000000000012c set_pull
0000000000052954 l F ro 00000000000000a0 set_value
00000000000529f4 l F ro 000000000000008c get_value
0000000000052a80 l F ro 0000000000000098 set_direction
0000000000052b18 l F ro 0000000000000090 get_direction
000000000006de2c l O .bss 0000000000000190 store_grf_gpio
0000000000000000 l df *ABS* 0000000000000000 pmu.c
0000000000052d90 l F ro 0000000000000020 pmu_power_domain_st
0000000000052db0 l F ro 00000000000000cc pmu_power_domain_ctr
0000000000052e7c l F ro 00000000000000c4 clst_pwr_domain_suspend
0000000000052f40 l F ro 000000000000009c clst_pwr_domain_resume
0000000000052fdc l F ro 0000000000000108 pmu_bus_idle_req
00000000000530e4 l F ro 0000000000000138 pmu_set_power_domain
000000000005321c l F ro 000000000000015c cpus_power_domain_off
000000000007ec89 l O .bss 0000000000003000 store_sram
000000000006b1b0 l O .bss 0000000000002720 dist_ctx
000000000006dfbc l O .bss 0000000000000004 clk_ddrc_save
000000000006dfc0 l O .bss 0000000000000004 cpu_warm_boot_addr
000000000006dfc4 l O .bss 0000000000000004 gpio_2_4_clk_gate
000000000006dfc8 l O .bss 000000000000000c gpio_direction
000000000006dfd4 l O .bss 0000000000000030 iomux_status
000000000006e004 l O .bss 0000000000000004 pmu_powerdomain_state
000000000006e3f8 l O .bss 0000000000000030 pull_mode_status
000000000006d8d0 l O .bss 0000000000000058 rdist_ctx
000000000006e428 l O .bss 0000000000000590 store_cru
000000000006e9b8 l O .bss 0000000000000010 store_grf_ddrc_con
000000000006e9c8 l O .bss 0000000000000004 store_grf_io_vsel
000000000006e9cc l O .bss 0000000000000004 store_grf_soc_con0
000000000006e9d0 l O .bss 0000000000000004 store_grf_soc_con1
000000000006e9d4 l O .bss 0000000000000004 store_grf_soc_con2
000000000006e9d8 l O .bss 0000000000000004 store_grf_soc_con3
000000000006e9dc l O .bss 0000000000000004 store_grf_soc_con4
000000000006e9e0 l O .bss 0000000000000004 store_grf_soc_con7
000000000006e9e4 l O .bss 000000000000001c store_usbphy0
000000000006ea00 l O .bss 000000000000001c store_usbphy1
000000000006ea1c l O .bss 0000000000000008 store_wdt0
000000000006ea24 l O .bss 0000000000000008 store_wdt1
000000000006ea2c l O .bss 0000000000000018 uart_save
00000000000632b0 l O ro 0000000000000015 __func__.3889
00000000000632c5 l O ro 000000000000000f __func__.3899
00000000000632d4 l O ro 0000000000000011 __func__.4057
00000000000632e5 l O ro 0000000000000010 __func__.4115
00000000000632f5 l O ro 0000000000000015 __func__.4134
000000000006330a l O ro 0000000000000017 __func__.4155
0000000000063321 l O ro 0000000000000020 __func__.4337
0000000000063341 l O ro 000000000000001f __func__.4346
0000000000063360 l O ro 0000000000000017 __func__.4374
0000000000096054 l O coherent_ram 0000000000000018 core_pm_cfg_info
0000000000000000 l df *ABS* 0000000000000000 m0_ctl.c
0000000000000000 l df *ABS* 0000000000000000 pwm.c
000000000006ea44 l O .bss 0000000000000008 pwm_data
0000000000000000 l df *ABS* 0000000000000000 dfs.c
0000000000056d58 l F ro 0000000000000068 get_rdlat_adj
0000000000056dc0 l F ro 0000000000000068 get_wrlat_adj
0000000000056e28 l F ro 0000000000000074 get_pi_rdlat_adj
0000000000056e9c l F ro 00000000000000d8 gen_rk3399_set_odt
0000000000056f74 l F ro 000000000000003c to_get_clk_index
0000000000056fb0 l F ro 0000000000000050 get_pi_wrlat.isra.0.part.0
0000000000057000 l F ro 000000000000003c get_pi_todtoff_min.isra.0
000000000005703c l F ro 0000000000000030 get_pi_todtoff_max.isra.0
000000000005706c l F ro 00000000000000c8 get_pi_tdfi_phy_rdlat.isra.0
0000000000057134 l F ro 0000000000000038 get_pi_wrlat_adj.constprop.0
000000000005716c l F ro 0000000000002630 prepare_ddr_timing
000000000006eba4 l O .bss 0000000000000004 rddqs_delay_ps
000000000006eba8 l O .bss 0000000000000088 rk3399_dram_status
000000000006ec30 l O .bss 000000000000000c rk3399_suspend_status
000000000006ec3c l O .bss 0000000000000040 wrdqs_delay_val
000000000006239c l O ro 00000000000000fc dpll_rates_table
0000000000000000 l df *ABS* 0000000000000000 dram_spec_timing.c
000000000005a52c l F ro 000000000000004c get_max_die_capability
00000000000633d1 l O ro 000000000000009a ddr3_cl_cwl
0000000000062636 l O ro 000000000000002c ddr3_trc_tfaw
0000000000000000 l df *ABS* 0000000000000000 bl31_main.c
000000000006d928 l O .bss 0000000000000008 bl32_init
0000000000067054 l O .data 0000000000000004 next_image_type
00000000000635fd l O ro 000000000000001e __func__.2976
0000000000062290 l O ro 0000000000000010 psci_args.2951
0000000000000000 l df *ABS* 0000000000000000 interrupt_mgmt.c
000000000006d930 l O .bss 0000000000000060 intr_type_descs
0000000000000000 l df *ABS* 0000000000000000 bl31_context_mgmt.c
0000000000000000 l df *ABS* 0000000000000000 runtime_svc.c
000000000006375f l O ro 0000000000000011 __func__.1385
0000000000000000 l df *ABS* 0000000000000000 arm_arch_svc_setup.c
000000000005c138 l F ro 00000000000000c8 arm_arch_svc_smc_handler
0000000000065158 l O ro 0000000000000020 __svc_desc_arm_arch_svc
0000000000000000 l df *ABS* 0000000000000000 std_svc_setup.c
000000000005c200 l F ro 00000000000000bc std_svc_smc_handler
000000000005c2bc l F ro 0000000000000040 std_svc_setup
0000000000065178 l O ro 0000000000000020 __svc_desc_std_svc
0000000000000000 l df *ABS* 0000000000000000 context_mgmt.c
0000000000063898 l O ro 0000000000000011 __func__.2495
0000000000000000 l df *ABS* 0000000000000000 errata_report.c
00000000000622a0 l O ro 0000000000000018 errata_status_str.2554
0000000000000000 l df *ABS* 0000000000000000 psci_off.c
0000000000000000 l df *ABS* 0000000000000000 psci_on.c
0000000000000000 l df *ABS* 0000000000000000 psci_suspend.c
0000000000000000 l df *ABS* 0000000000000000 psci_common.c
000000000005cee4 l F ro 000000000000005c psci_set_req_local_pwr_state
0000000000081d09 l O .bss 000000000000000c psci_req_local_pwr_states
0000000000063e72 l O ro 0000000000000019 __func__.3216
00000000000622b8 l O ro 0000000000000018 psci_state_type_str.3230
0000000000000000 l df *ABS* 0000000000000000 psci_main.c
00000000000640d8 l O ro 0000000000000011 __func__.2994
0000000000000000 l df *ABS* 0000000000000000 psci_setup.c
000000000006a3a0 l O .bss 0000000000000cc0 psci_ns_context
0000000000000000 l df *ABS* 0000000000000000 psci_system_off.c
0000000000000000 l df *ABS* 0000000000000000 psci_mem_protect.c
0000000000000000 l df *ABS* 0000000000000000 bakery_lock_coherent.c
0000000000000000 l df *ABS* 0000000000000000 spe.c
000000000005e758 l F ro 0000000000000030 spe_drain_buffers_hook
0000000000000000 l df *ABS* 0000000000000000 bl_common.c
0000000000000000 l df *ABS* 0000000000000000 tf_log.c
0000000000067058 l O .data 0000000000000004 max_log_level
0000000000000000 l df *ABS* 0000000000000000 multi_console.c
0000000000000000 l df *ABS* 0000000000000000 plat_log_common.c
00000000000622d0 l O ro 0000000000000028 plat_prefix_str
0000000000000000 l df *ABS* 0000000000000000 plat_common.c
00000000000645b3 l O ro 0000000000000010 __func__.2717
0000000000000000 l df *ABS* 0000000000000000 backtrace.c
000000000005ebc0 l F ro 0000000000000040 is_address_readable
000000000005ec00 l F ro 0000000000000054 is_valid_object.constprop.0
0000000000000000 l df *ABS* 0000000000000000 desc_image_load.c
0000000000000000 l df *ABS* 0000000000000000 bl_aux_params.c
0000000000000000 l df *ABS* 0000000000000000 xlat_tables_common.c
000000000005ef04 l F ro 000000000000038c init_xlation_table_inner
0000000000082000 l O xlat_table 0000000000014000 xlat_tables
000000000006da08 l O .bss 0000000000000008 ap1_mask
000000000006da10 l O .bss 0000000000000008 execute_never_mask
000000000006da18 l O .bss 0000000000000340 mmap
000000000006ec84 l O .bss 0000000000000004 next_xlat
000000000006dd58 l O .bss 0000000000000008 xlat_max_pa
000000000006dd60 l O .bss 0000000000000008 xlat_max_va
0000000000000000 l df *ABS* 0000000000000000 xlat_tables.c
000000000006a380 l O .bss 0000000000000020 base_xlation_table
000000000006dd68 l O .bss 0000000000000008 tcr_ps_bits
00000000000625e0 l O ro 000000000000001c pa_range_bits_arr
0000000000000000 l df *ABS* 0000000000000000 plat_psci_common.c
0000000000000000 l df *ABS* 0000000000000000 ./build/rk3399/debug/bl31/16550_console.o
000000000005f938 l ro 0000000000000000 init_fail
000000000005f994 l ro 0000000000000000 register_fail
000000000005f95c l ro 0000000000000000 register_16550
000000000005fa24 l ro 0000000000000000 no_char
0000000000000000 l df *ABS* 0000000000000000 ./build/rk3399/debug/bl31/cortex_a53.o
0000000000000008 l *ABS* 0000000000000000 CPU_MIDR_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_EXTRA1_FUNC_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_EXTRA2_FUNC_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_E_HANDLER_FUNC_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_RESET_FUNC_SIZE
0000000000000010 l *ABS* 0000000000000000 CPU_PWR_DWN_OPS_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_ERRATA_FUNC_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_ERRATA_LOCK_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_ERRATA_PRINTED_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_REG_DUMP_SIZE
0000000000000000 l *ABS* 0000000000000000 CPU_MIDR
0000000000000008 l *ABS* 0000000000000000 CPU_RESET_FUNC
0000000000000010 l *ABS* 0000000000000000 CPU_EXTRA1_FUNC
0000000000000018 l *ABS* 0000000000000000 CPU_EXTRA2_FUNC
0000000000000020 l *ABS* 0000000000000000 CPU_E_HANDLER_FUNC
0000000000000028 l *ABS* 0000000000000000 CPU_PWR_DWN_OPS
0000000000000038 l *ABS* 0000000000000000 CPU_ERRATA_FUNC
0000000000000040 l *ABS* 0000000000000000 CPU_ERRATA_LOCK
0000000000000048 l *ABS* 0000000000000000 CPU_ERRATA_PRINTED
0000000000000050 l *ABS* 0000000000000000 CPU_REG_DUMP
0000000000000058 l *ABS* 0000000000000000 CPU_OPS_SIZE
000000000005fa90 l F ro 0000000000000014 cortex_a53_disable_dcache
000000000005faa4 l F ro 0000000000000018 cortex_a53_disable_smp
000000000005fabc l F ro 0000000000000008 check_errata_819472
000000000005fac4 l F ro 0000000000000008 check_errata_824069
000000000005facc l F ro 0000000000000008 check_errata_826319
000000000005fad4 l F ro 0000000000000008 check_errata_827319
000000000005fadc l F ro 000000000000001c a53_disable_non_temporal_hint
000000000005faf8 l F ro 0000000000000008 check_errata_disable_non_temporal_hint
000000000005fb00 l F ro 000000000000001c errata_a53_855873_wa
000000000005fb1c l F ro 0000000000000008 check_errata_855873
000000000005fb24 l F ro 0000000000000024 check_errata_835769
000000000005fb40 l ro 0000000000000000 errata_not_applies
000000000005fb44 l ro 0000000000000000 exit_check_errata_835769
000000000005fb48 l F ro 0000000000000024 check_errata_843419
000000000005fb68 l ro 0000000000000000 exit_check_errata_843419
000000000005fb6c l F ro 0000000000000030 cortex_a53_reset_func
000000000005fb9c l F ro 0000000000000018 cortex_a53_core_pwr_dwn
000000000005fbb4 l F ro 0000000000000024 cortex_a53_cluster_pwr_dwn
000000000005fbd8 l F ro 00000000000000e4 cortex_a53_errata_report
0000000000064be7 l ro 0000000000000000 cortex_a53_errata_819472_str
0000000000064c32 l ro 0000000000000000 cortex_a53_cpu_str
0000000000064bee l ro 0000000000000000 cortex_a53_errata_824069_str
0000000000064bf5 l ro 0000000000000000 cortex_a53_errata_826319_str
0000000000064bfc l ro 0000000000000000 cortex_a53_errata_827319_str
0000000000064c03 l ro 0000000000000000 cortex_a53_errata_835769_str
0000000000064c0a l ro 0000000000000000 cortex_a53_errata_disable_non_temporal_hint_str
0000000000064c24 l ro 0000000000000000 cortex_a53_errata_843419_str
0000000000064c2b l ro 0000000000000000 cortex_a53_errata_855873_str
0000000000064c3d l ro 0000000000000000 cortex_a53_regs
000000000005fcbc l F ro 0000000000000018 cortex_a53_cpu_reg_dump
000000000006705c l .data 0000000000000000 cortex_a53_errata_lock
0000000000067060 l .data 0000000000000000 cortex_a53_errata_reported
0000000000000000 l df *ABS* 0000000000000000 ./build/rk3399/debug/bl31/cortex_a72.o
0000000000000008 l *ABS* 0000000000000000 CPU_MIDR_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_EXTRA1_FUNC_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_EXTRA2_FUNC_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_E_HANDLER_FUNC_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_RESET_FUNC_SIZE
0000000000000010 l *ABS* 0000000000000000 CPU_PWR_DWN_OPS_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_ERRATA_FUNC_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_ERRATA_LOCK_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_ERRATA_PRINTED_SIZE
0000000000000008 l *ABS* 0000000000000000 CPU_REG_DUMP_SIZE
0000000000000000 l *ABS* 0000000000000000 CPU_MIDR
0000000000000008 l *ABS* 0000000000000000 CPU_RESET_FUNC
0000000000000010 l *ABS* 0000000000000000 CPU_EXTRA1_FUNC
0000000000000018 l *ABS* 0000000000000000 CPU_EXTRA2_FUNC
0000000000000020 l *ABS* 0000000000000000 CPU_E_HANDLER_FUNC
0000000000000028 l *ABS* 0000000000000000 CPU_PWR_DWN_OPS
0000000000000038 l *ABS* 0000000000000000 CPU_ERRATA_FUNC
0000000000000040 l *ABS* 0000000000000000 CPU_ERRATA_LOCK
0000000000000048 l *ABS* 0000000000000000 CPU_ERRATA_PRINTED
0000000000000050 l *ABS* 0000000000000000 CPU_REG_DUMP
0000000000000058 l *ABS* 0000000000000000 CPU_OPS_SIZE
000000000005fcd4 l F ro 0000000000000014 cortex_a72_disable_dcache
000000000005fce8 l F ro 0000000000000020 cortex_a72_disable_l2_prefetch
000000000005fd08 l F ro 0000000000000018 cortex_a72_disable_hw_prefetcher
000000000005fd20 l F ro 0000000000000010 cortex_a72_disable_smp
000000000005fd30 l F ro 0000000000000014 cortex_a72_disable_ext_debug
000000000005fd44 l F ro 0000000000000008 check_errata_859971
000000000005fd4c l F ro 0000000000000034 check_errata_cve_2017_5715
000000000005fd80 l F ro 0000000000000008 check_errata_cve_2018_3639
000000000005fd88 l F ro 0000000000000060 cortex_a72_reset_func
000000000005fde8 l F ro 0000000000000024 cortex_a72_core_pwr_dwn
000000000005fe0c l F ro 0000000000000030 cortex_a72_cluster_pwr_dwn
000000000005fe3c l F ro 0000000000000058 cortex_a72_errata_report
0000000000064c99 l ro 0000000000000000 cortex_a72_errata_859971_str
0000000000064cbc l ro 0000000000000000 cortex_a72_cpu_str
0000000000064ca0 l ro 0000000000000000 cortex_a72_errata_cve_2017_5715_str
0000000000064cae l ro 0000000000000000 cortex_a72_errata_cve_2018_3639_str
0000000000064cc7 l ro 0000000000000000 cortex_a72_regs
000000000005fe94 l F ro 0000000000000014 cortex_a72_cpu_reg_dump
0000000000067064 l .data 0000000000000000 cortex_a72_errata_lock
0000000000067068 l .data 0000000000000000 cortex_a72_errata_reported
0000000000000000 l df *ABS* 0000000000000000 ./build/rk3399/debug/bl31/crash_reporting.o
0000000000064cf0 l ro 0000000000000000 gicc_regs
0000000000064d12 l ro 0000000000000000 icc_regs
0000000000064d3e l ro 0000000000000000 gicd_pend_reg
0000000000064d7b l ro 0000000000000000 newline
0000000000064d7d l ro 0000000000000000 spacer
0000000000064d83 l ro 0000000000000000 cci_iface_regs
0000000000064db4 l ro 0000000000000000 print_spacer
0000000000064dc6 l ro 0000000000000000 gp_regs
0000000000064e35 l ro 0000000000000000 el3_sys_regs
0000000000064e92 l ro 0000000000000000 non_el3_sys_regs
0000000000064fde l ro 0000000000000000 aarch32_regs
0000000000064ff5 l ro 0000000000000000 panic_msg
0000000000065007 l ro 0000000000000000 excpt_msg
0000000000065027 l ro 0000000000000000 intr_excpt_msg
000000000005feec l F ro 000000000000004c size_controlled_print
000000000005fef4 l ro 0000000000000000 test_size_list
000000000005ff30 l ro 0000000000000000 exit_size_print
000000000005ff38 l F ro 000000000000000c print_alignment
000000000005ff44 l F ro 0000000000000018 str_in_crash_buf_print
000000000005ffd8 l F ro 0000000000000218 do_crash_reporting
00000000000601f0 l F ro 0000000000000008 crash_panic
0000000000060178 l ro 0000000000000000 print_gicv2
000000000006018c l ro 0000000000000000 print_gic_common
0000000000060198 l ro 0000000000000000 gicd_ispendr_loop
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0000000000052038 g F ro 0000000000000014 rockchip_get_sys_suspend_power_state
0000000000056d2c g F ro 000000000000002c plat_rockchip_soc_init
00000000000500e0 g F ro 0000000000000014 gicd_read_icfgr
0000000000051214 g F ro 0000000000000020 gicr_clr_igrpmodr0
00000000000500d0 g F ro 0000000000000010 gicd_read_ipriorityr
000000000005e744 g F ro 0000000000000014 spe_supported
000000000005c7cc g F ro 000000000000012c psci_do_cpu_off
000000000006ec80 g O .bss 0000000000000004 psci_caps
00000000000604c0 g F ro 0000000000000020 do_cpu_reg_dump
000000000005c300 g F ro 0000000000000178 cm_setup_context
0000000000040000 g ro 0000000000000000 __BL31_START__
0000000000065a80 g F ro 0000000000000000 irq_sp_elx
0000000000065900 g F ro 0000000000000000 fiq_sp_el0
00000000000620c8 g F ro 0000000000000038 strncmp
0000000000067072 g .data 0000000000000000 __DATA_END__
00000000000608b8 g ro 0000000000000000 asm_print_hex_bits
000000000005114c g F ro 0000000000000030 gicd_set_igrpmodr
0000000000065198 g ro 0000000000000000 __CPU_OPS_START__
0000000000051be4 g F ro 000000000000007c gpio_set_value
00000000000519cc g F ro 00000000000000b8 udelay
0000000000056524 g F ro 0000000000000054 m0_init
00000000ff3b1f54 g .pmusram 0000000000000000 __bl31_pmusram_data_end
00000000ff8c0310 g .incbin_sram 0000000000000000 __sram_incbin_real_end
00000000000618e0 g F ro 0000000000000040 fdt_check_prop_offset_
000000000005153c g F ro 0000000000000058 gicv3_ppi_sgi_config_defaults
00000000000609a0 g F ro 0000000000000038 inv_dcache_range
0000000000067070 g O .data 0000000000000001 console_state
00000000000535e0 g F ro 0000000000000030 rockchip_soc_hlvl_pwr_dm_off
00000000ff3b1240 g .pmusram 0000000000000000 __bl31_pmusram_data_start
000000000005eea4 g F ro 0000000000000060 bl_aux_params_parse
000000000005dde8 g F ro 000000000000015c psci_smc_handler
0000000000051744 w F ro 0000000000000014 plat_rockchip_gic_pcpu_init
0000000000051b24 g F ro 0000000000000044 generic_delay_timer_init
000000000005cc1c g F ro 00000000000001dc psci_cpu_suspend_start
0000000000053378 g F ro 00000000000000b8 pmu_power_domains_on
000000000005d058 g F ro 0000000000000058 psci_init_req_local_pwr_states
0000000000056c68 g F ro 0000000000000020 enable_nodvfs_plls
0000000000065250 g ro 0000000000000000 __pubsub_cm_entering_secure_world_end
0000000000051ad8 g F ro 000000000000004c generic_delay_timer_init_args
0000000000061a8c g F ro 0000000000000034 memcmp
00000000ff3b1f3c g O .pmusram 0000000000000018 dpll_data
000000000006051c g F ro 0000000000000010 cpu_get_rev_var
000000000005c8f8 g F ro 0000000000000224 psci_cpu_on_start
000000000005d3b0 g F ro 000000000000003c psci_find_max_off_lvl
0000000000061254 g F ro 00000000000000f8 fdt_path_offset_namelen
000000000006102c g F ro 0000000000000038 fdt_next_property_offset
0000000000051ef8 g F ro 0000000000000018 plat_get_rockchip_gpio_poweroff
00000000000501e0 g F ro 0000000000000040 gicd_set_icfgr
000000000005629c g F ro 0000000000000038 rockchip_soc_soft_reset
000000000009606c g O coherent_ram 0000000000000060 psci_non_cpu_pd_nodes
00000000000537e4 g F ro 0000000000000088 sram_restore
0000000000081d15 g .bss 0000000000000000 __BSS_END__
0000000000065248 g ro 0000000000000000 __CPU_OPS_END__
00000000000536a0 g F ro 0000000000000030 rockchip_soc_hlvl_pwr_dm_suspend
00000000000524ac g F ro 000000000000008c sip_smc_handler
000000000005d91c g F ro 0000000000000004 psci_do_pwrdown_sequence
00000000000605e8 g F ro 000000000000003c psci_do_pwrdown_cache_maintenance
0000000000051124 g F ro 0000000000000014 gicd_read_igrpmodr
000000000005386c g F ro 0000000000000064 suspend_uart
000000000005c568 g F ro 000000000000005c cm_set_next_eret_context
0000000000065248 g ro 0000000000000000 __pubsub_cm_entering_secure_world_start
00000000ff3b006c g F .pmusram 0000000000000030 sram_secure_timer_init
0000000000050094 g F ro 0000000000000014 gicd_read_isenabler
000000000005d920 g F ro 000000000000005c psci_cpu_on
000000000005f5b8 g F ro 00000000000000bc init_xlation_table
000000000005bd20 g F ro 00000000000000d8 bl31_prepare_next_image_entry
000000000005d420 g F ro 00000000000000a0 psci_validate_suspend_req
0000000000096000 g coherent_ram 0000000000000000 __COHERENT_RAM_START__
0000000000056c18 g F ro 0000000000000050 enable_dvfs_plls
000000000006ec7c g O .bss 0000000000000004 psci_plat_core_count
00000000000516fc w F ro 0000000000000020 plat_rockchip_gic_init
000000000005dd80 g F ro 0000000000000068 psci_features
0000000000065248 g ro 0000000000000000 __GOT_END__
0000000000052ba8 g F ro 00000000000000e0 plat_rockchip_save_gpio
00000000ff3b1000 g .pmusram 0000000000000000 __pmusram_incbin_start
0000000000061b14 g F ro 000000000000001c memset
000000000005f940 g F ro 0000000000000058 console_16550_register
0000000000059a0c g F ro 0000000000000504 dram_dfs_init
000000000005c70c g F ro 00000000000000c0 errata_print_msg
000000000005d0b0 g F ro 0000000000000090 psci_get_target_local_pwr_states
0000000000056970 g F ro 000000000000004c disable_dvfs_plls
000000000005372c g F ro 0000000000000030 rockchip_soc_hlvl_pwr_dm_resume
0000000000065250 g ro 0000000000000000 __pubsub_cm_exited_normal_world_end
0000000000051f28 g F ro 000000000000000c plat_get_rockchip_suspend_apio
0000000000060274 g F ro 000000000000001c enter_lower_el_async_ea
000000000006d9f0 g O .bss 0000000000000008 psci_plat_pm_ops
000000000005686c g F ro 0000000000000060 secure_sgrf_init
000000000005bd0c g F ro 0000000000000014 bl31_setup
00000000ff3b1f38 g O .pmusram 0000000000000004 cru_clksel_con6
0000000000065248 g ro 0000000000000000 __pubsub_psci_suspend_pwrdown_start_start
0000000000062230 g O ro 0000000000000060 plat_rk_mmap
00000000ff8c0000 g .incbin_sram 0000000000000000 __sram_incbin_start
000000000005124c g F ro 0000000000000030 gicr_set_icfgr1
0000000000065248 g ro 0000000000000000 __GOT_START__
000000000006e008 g O .bss 00000000000003f0 pmu_slpdata
0000000000056c88 g F ro 0000000000000028 soc_global_soft_reset_init
000000000005bcd4 g F ro 0000000000000038 get_arm_std_svc_args
0000000000065250 g ro 0000000000000000 __pubsub_cm_entering_normal_world_start
000000000005e5bc g F ro 0000000000000108 bakery_lock_get
000000000005e4d0 g F ro 0000000000000090 psci_mem_protect
00000000000614d8 g F ro 00000000000001b4 fdt_open_into
000000000005e6c4 g F ro 0000000000000080 bakery_lock_release
0000000000062200 g O ro 0000000000000030 rk3399_gpio_ops
00000000000569d8 g F ro 00000000000000d0 prepare_abpll_for_ddrctrl
000000000005bee0 g F ro 0000000000000024 get_interrupt_type_handler
00000000000523f4 g F ro 0000000000000080 plat_configure_mmu_el3
00000000000523d0 g F ro 000000000000000c plat_get_power_domain_tree_desc
0000000000050158 g F ro 0000000000000010 gicd_write_ipriorityr
0000000000056b5c g F ro 0000000000000068 clk_gate_con_restore
0000000000052350 w F ro 000000000000000c rockchip_soc_cores_pd_pwr_dn_wfi
000000000005dcf4 g F ro 000000000000008c psci_node_hw_state
0000000000059f10 g F ro 0000000000000128 dram_set_odt_pd
0000000000061694 g F ro 0000000000000088 fdt_check_header
0000000000050144 g F ro 0000000000000014 gicd_write_isactiver
0000000000060ac4 g F ro 0000000000000010 dcsw_op_level2
000000000006048c g F ro 0000000000000034 init_cpu_ops
000000000005eacc g F ro 0000000000000070 console_flush
0000000000065b00 g F ro 0000000000000000 fiq_sp_elx
0000000000067000 g ro 0000000000000000 __RO_END__
0000000000060e64 g F ro 00000000000000a8 fdt_get_name
0000000000065c00 g F ro 0000000000000000 sync_exception_aarch64
0000000000065d00 g F ro 0000000000000000 fiq_aarch64
0000000000050080 g F ro 0000000000000014 gicd_read_igroupr
000000000005ea24 g F ro 000000000000000c console_switch_state
0000000000051ed4 g F ro 000000000000000c rockchip_get_uart_clock
0000000000060554 g F ro 0000000000000038 print_errata_status
00000000000605e0 g F ro 0000000000000008 spin_unlock
00000000000526bc g F ro 0000000000000074 gpio_put_clock
000000000006a080 g .bss 0000000000000000 __BSS_START__
0000000000040000 g ro 0000000000000000 __RO_START__
00000000ff3b00b0 g F .pmusram 0000000000000034 restore_pmu_rsthold
0000000000063377 g O ro 0000000000000004 rockchip_power_domain_tree_desc
000000000005e788 g F ro 0000000000000044 spe_enable
0000000000060c48 g F ro 0000000000000084 plat_crash_console_putc
00000000ff8c0310 g .incbin_sram 0000000000000000 rk3399m0_bin_end
000000000006a080 g O .bss 0000000000000300 percpu_data
0000000000060540 g F ro 0000000000000014 cpu_rev_var_hs
0000000000061920 g F ro 00000000000000b0 fdt_next_node
00000000000505d4 w F ro 0000000000000004 gicv3_rdistif_on
00000000000605c0 g F ro 0000000000000020 spin_lock
000000000005e95c g F ro 0000000000000050 console_is_registered
00000000000508cc g F ro 000000000000003c gicv3_get_pending_interrupt_type
0000000000053b1c g F ro 00000000000000d8 grf_register_save
000000000005cf8c g F ro 0000000000000038 psci_query_sys_suspend_pwrstate
00000000ff8c2000 g .data_sram 0000000000000000 __bl31_sram_data_end
000000000005e884 g F ro 00000000000000d8 tf_log
000000000005a2a8 g F ro 0000000000000094 ddr_prepare_for_sys_resume
0000000000065248 g ro 0000000000000000 __pubsub_psci_cpu_on_finish_start
0000000000056674 g F ro 00000000000000fc disable_pwms
0000000000053bf4 g F ro 00000000000000c4 grf_register_restore
00000000000597f0 g F ro 0000000000000170 exit_low_power
000000000006052c g F ro 0000000000000014 cpu_rev_var_ls
000000000005be88 g F ro 0000000000000058 get_scr_el3_from_routing_model
0000000000097000 g coherent_ram 0000000000000000 __RW_END__
000000000005f6a8 g F ro 0000000000000040 xlat_arch_get_xn_desc
0000000000096120 g coherent_ram 0000000000000000 __COHERENT_RAM_END_UNALIGNED__
0000000000051d84 g F ro 0000000000000020 bl31_platform_setup
0000000000060dfc g F ro 0000000000000028 fdt_string
000000000005375c g F ro 0000000000000088 sram_save
000000000005fa2c g F ro 000000000000001c console_16550_getc
0000000000067080 g stacks 0000000000000000 __STACKS_START__
0000000000050e98 g F ro 000000000000028c gicv3_distif_init_restore
000000000005d228 g F ro 0000000000000188 psci_do_state_coordination
000000000005e40c g F ro 00000000000000c4 psci_system_reset2
000000000005f7bc g F ro 00000000000000c4 enable_mmu_el3
0000000000061798 g F ro 0000000000000108 fdt_next_tag
0000000000065f80 g F ro 0000000000000000 serror_aarch32
0000000000060bf8 w F ro 0000000000000004 plat_handle_double_fault
000000000005bab8 g F ro 000000000000021c dmc_suspend
0000000000050220 g F ro 00000000000000c4 arm_gicv3_distif_pre_save
0000000000065248 g ro 0000000000000000 __pubsub_psci_suspend_pwrdown_finish_start
0000000000051364 g F ro 000000000000009c gicv3_spis_config_defaults
000000000005117c g F ro 0000000000000030 gicd_clr_igrpmodr
000000000005fecc g F ro 0000000000000014 plat_my_core_pos
0000000000096118 g coherent_ram 0000000000000000 clst_warmboot_data
00000000000611f0 g F ro 0000000000000064 fdt_get_alias_namelen
0000000000051594 g F ro 00000000000000fc gicv3_secure_ppi_sgi_config_props
000000000005213c g F ro 0000000000000080 rockchip_pwr_domain_off
000000000005bfc4 g F ro 0000000000000174 runtime_svc_init
00000000000960d0 g coherent_ram 0000000000000000 cpuson_entry_point
00000000000500a8 g F ro 0000000000000014 gicd_read_ispendr
00000000000620ac g F ro 000000000000001c strlen
00000000000511d4 g F ro 0000000000000020 gicr_clr_igroupr0
0000000000065c80 g F ro 0000000000000000 irq_aarch64
000000000005dcb4 g F ro 0000000000000018 psci_migrate_info_type
0000000000051ebc g F ro 000000000000000c rockchip_get_uart_base
0000000000051ee0 g F ro 0000000000000018 plat_get_rockchip_gpio_reset
0000000000050380 g F ro 0000000000000004 gicv3_distif_pre_save
0000000000061a2c g F ro 0000000000000034 __assert
00000000ff3b1240 g O .pmusram 0000000000000008 pmu_slp_data
000000000005e560 g F ro 000000000000005c psci_mem_chk_range
000000000005ffac g F ro 000000000000002c el3_panic
0000000000050190 g F ro 0000000000000030 gicd_clr_igroupr
0000000000062498 g O ro 0000000000000090 lpddr3_lat_adj
0000000000062088 g F ro 0000000000000024 strchr
0000000000051f10 g F ro 0000000000000018 plat_get_rockchip_suspend_gpio
000000000006b060 g O .bss 0000000000000008 gicv3_driver_data
0000000000051c60 g F ro 0000000000000050 gpio_init
00000000ff8c2000 g .stack_sram 0000000000000000 __bl31_sram_stack_start
000000000005f8d0 g F ro 0000000000000070 console_16550_core_init
0000000000062528 g O ro 0000000000000080 lpddr4_lat_adj
00000000000536d0 g F ro 0000000000000028 rockchip_soc_cores_pwr_dm_on_finish
0000000000052494 g F ro 000000000000000c plat_cci_enable
0000000000052538 g F ro 000000000000005c ddr_smc_handler
000000000005d4c0 g F ro 0000000000000070 psci_acquire_pwr_domain_locks
0000000000065248 g ro 0000000000000000 __pubsub_psci_cpu_on_finish_end
0000000000060668 g F ro 00000000000000ac el1_sysregs_context_restore
000000000005eda0 g F ro 0000000000000104 bl31_params_parse_helper
000000000006da00 g O .bss 0000000000000008 console_list
000000000005d188 g F ro 00000000000000a0 psci_set_pwr_domains_to_run
0000000000050708 g F ro 00000000000000f4 gicv3_cpuif_enable
00000000000502e4 g F ro 000000000000009c arm_gicv3_distif_post_restore
00000000000562d4 g F ro 0000000000000060 rockchip_soc_system_off
0000000000050108 g F ro 0000000000000014 gicd_write_igroupr
000000000005ff84 g F ro 0000000000000028 report_unhandled_interrupt
0000000000053954 g F ro 00000000000000f4 save_usbphy
0000000000065f00 g F ro 0000000000000000 fiq_aarch32
000000000005a578 g F ro 000000000000151c dram_get_parameter
0000000000053610 g F ro 0000000000000090 rockchip_soc_cores_pwr_dm_suspend
00000000000603c8 w F ro 000000000000001c plat_get_my_stack
000000000005f2ec g F ro 0000000000000290 mmap_add_region
000000000005c6ac g F ro 0000000000000060 errata_needs_reporting
00000000000500bc g F ro 0000000000000014 gicd_read_isactiver
0000000000050908 g F ro 0000000000000184 gicv3_rdistif_save
000000000006d9f8 g O .bss 0000000000000008 psci_spd_pm
00000000000520e4 g F ro 000000000000004c rockchip_cpu_standby
00000000ff3b1240 g .pmusram 0000000000000000 rk3399m0pmu_bin_end
Disassembly of section .text_sram:
00000000ff8c1000 <sram_func_set_ddrctl_pll>:
ff8c1000: aa0003e8 mov x8, x0
ff8c1004: d53e1009 mrs x9, sctlr_el3
ff8c1008: 927ff92a and x10, x9, #0xfffffffffffffffe
ff8c100c: d51e100a msr sctlr_el3, x10
ff8c1010: d5033fdf isb
ff8c1014: d5033f9f dsb sy
ff8c1018: d2bfe625 mov x5, #0xff310000 // #4281401344
ff8c101c: b94024a0 ldr w0, [x5, #36]
ff8c1020: 32180000 orr w0, w0, #0x100
ff8c1024: 32140000 orr w0, w0, #0x1000
ff8c1028: b90024a0 str w0, [x5, #36]
00000000ff8c102c <check_ddrc0_1_sref_enter>:
ff8c102c: b94098a1 ldr w1, [x5, #152]
ff8c1030: 12000022 and w2, w1, #0x1
ff8c1034: 121e0023 and w3, w1, #0x4
ff8c1038: 2a030042 orr w2, w2, w3
ff8c103c: 7100145f cmp w2, #0x5
ff8c1040: 54ffff60 b.eq ff8c102c <check_ddrc0_1_sref_enter> // b.none
ff8c1044: d2bfeec5 mov x5, #0xff760000 // #4285923328
ff8c1048: 531c6d00 lsl w0, w8, #4
ff8c104c: 320c0400 orr w0, w0, #0x300000
ff8c1050: b90118a0 str w0, [x5, #280]
ff8c1054: d2bfe625 mov x5, #0xff310000 // #4281401344
ff8c1058: b94024a0 ldr w0, [x5, #36]
ff8c105c: 12177800 and w0, w0, #0xfffffeff
ff8c1060: 12137800 and w0, w0, #0xffffefff
ff8c1064: b90024a0 str w0, [x5, #36]
00000000ff8c1068 <check_ddrc0_1_sref_exit>:
ff8c1068: b94098a1 ldr w1, [x5, #152]
ff8c106c: 12000022 and w2, w1, #0x1
ff8c1070: 121e0023 and w3, w1, #0x4
ff8c1074: 2a030042 orr w2, w2, w3
ff8c1078: 7100005f cmp w2, #0x0
ff8c107c: 54ffff60 b.eq ff8c1068 <check_ddrc0_1_sref_exit> // b.none
ff8c1080: d51e1009 msr sctlr_el3, x9
ff8c1084: d5033fdf isb
ff8c1088: d5033f9f dsb sy
ff8c108c: d65f03c0 ret
00000000ff8c1090 <__bl31_sram_text_real_end>:
...
Disassembly of section .pmusram:
00000000ff3b0000 <pmu_cpuson_entrypoint>:
ff3b0000: 580000c2 ldr x2, ff3b0018 <sys_resume+0x8>
ff3b0004: 9100005f mov sp, x2
ff3b0008: 940001b1 bl ff3b06cc <dmc_resume>
ff3b000c: 9400000b bl ff3b0038 <__sram_restore_veneer>
00000000ff3b0010 <sys_resume>:
ff3b0010: 94000006 bl ff3b0028 <__bl31_warm_entrypoint_veneer>
ff3b0014: 00000000 .inst 0x00000000 ; undefined
ff3b0018: ff8c3000 .word 0xff8c3000
ff3b001c: 00000000 .word 0x00000000
ff3b0020: 1400000e b ff3b0058 <secure_watchdog_ungate>
ff3b0024: d503201f nop
00000000ff3b0028 <__bl31_warm_entrypoint_veneer>:
ff3b0028: 90806490 adrp x16, 40000 <bl31_entrypoint>
ff3b002c: 9104e210 add x16, x16, #0x138
ff3b0030: d61f0200 br x16
ff3b0034: 00000000 .inst 0x00000000 ; undefined
00000000ff3b0038 <__sram_restore_veneer>:
ff3b0038: f0806510 adrp x16, 53000 <pmu_bus_idle_req+0x24>
ff3b003c: 911f9210 add x16, x16, #0x7e4
ff3b0040: d61f0200 br x16
...
00000000ff3b0058 <secure_watchdog_ungate>:
ff3b0058: d29c0180 mov x0, #0xe00c // #57356
ff3b005c: 52a0a001 mov w1, #0x5000000 // #83886080
ff3b0060: f2bfe660 movk x0, #0xff33, lsl #16
ff3b0064: b9000001 str w1, [x0]
ff3b0068: d65f03c0 ret
00000000ff3b006c <sram_secure_timer_init>:
ff3b006c: d2901401 mov x1, #0x80a0 // #32928
ff3b0070: 12800000 mov w0, #0xffffffff // #-1
ff3b0074: f2bff0c1 movk x1, #0xff86, lsl #16
ff3b0078: b9000020 str w0, [x1]
ff3b007c: b9000420 str w0, [x1, #4]
ff3b0080: d2901600 mov x0, #0x80b0 // #32944
ff3b0084: f2bff0c0 movk x0, #0xff86, lsl #16
ff3b0088: 52800021 mov w1, #0x1 // #1
ff3b008c: b900001f str wzr, [x0]
ff3b0090: b900001f str wzr, [x0]
ff3b0094: b9000c01 str w1, [x0, #12]
ff3b0098: d65f03c0 ret
00000000ff3b009c <pmu_sgrf_rst_hld_release>:
ff3b009c: d2802480 mov x0, #0x124 // #292
ff3b00a0: 52a00801 mov w1, #0x400000 // #4194304
ff3b00a4: f2bfeea0 movk x0, #0xff75, lsl #16
ff3b00a8: b9000001 str w1, [x0]
ff3b00ac: d65f03c0 ret
00000000ff3b00b0 <restore_pmu_rsthold>:
ff3b00b0: b0000000 adrp x0, ff3b1000 <rk3399m0pmu_bin>
ff3b00b4: d2802402 mov x2, #0x120 // #288
ff3b00b8: 91090001 add x1, x0, #0x240
ff3b00bc: f2bfeea2 movk x2, #0xff75, lsl #16
ff3b00c0: b9424000 ldr w0, [x0, #576]
ff3b00c4: 32103c00 orr w0, w0, #0xffff0000
ff3b00c8: b9000040 str w0, [x2]
ff3b00cc: b9400420 ldr w0, [x1, #4]
ff3b00d0: d2802481 mov x1, #0x124 // #292
ff3b00d4: f2bfeea1 movk x1, #0xff75, lsl #16
ff3b00d8: 32103c00 orr w0, w0, #0xffff0000
ff3b00dc: b9000020 str w0, [x1]
ff3b00e0: d65f03c0 ret
00000000ff3b00e4 <sram_regcpy>:
ff3b00e4: cb010000 sub x0, x0, x1
ff3b00e8: 51000442 sub w2, w2, #0x1
ff3b00ec: 3100045f cmn w2, #0x1
ff3b00f0: 54000041 b.ne ff3b00f8 <sram_regcpy+0x14> // b.any
ff3b00f4: d65f03c0 ret
ff3b00f8: b9400023 ldr w3, [x1]
ff3b00fc: b8216803 str w3, [x0, x1]
ff3b0100: 91001021 add x1, x1, #0x4
ff3b0104: 17fffff9 b ff3b00e8 <sram_regcpy+0x4>
00000000ff3b0108 <sram_udelay>:
ff3b0108: d53be021 mrs x1, cntpct_el0
ff3b010c: 52800302 mov w2, #0x18 // #24
ff3b0110: 2a2103e1 mvn w1, w1
ff3b0114: 1b027c00 mul w0, w0, w2
ff3b0118: d53be022 mrs x2, cntpct_el0
ff3b011c: 2a2203e4 mvn w4, w2
ff3b0120: 0b020022 add w2, w1, w2
ff3b0124: 6b040023 subs w3, w1, w4
ff3b0128: 1a822062 csel w2, w3, w2, cs // cs = hs, nlast
ff3b012c: 6b00005f cmp w2, w0
ff3b0130: 54ffff49 b.ls ff3b0118 <sram_udelay+0x10> // b.plast
ff3b0134: d65f03c0 ret
00000000ff3b0138 <rkclk_ddr_reset>:
ff3b0138: 12000000 and w0, w0, #0x1
ff3b013c: 11001800 add w0, w0, #0x6
ff3b0140: 531e7400 lsl w0, w0, #2
ff3b0144: 51004003 sub w3, w0, #0x10
ff3b0148: 1ac32021 lsl w1, w1, w3
ff3b014c: 51003c03 sub w3, w0, #0xf
ff3b0150: 1ac32042 lsl w2, w2, w3
ff3b0154: 2a020021 orr w1, w1, w2
ff3b0158: 11000402 add w2, w0, #0x1
ff3b015c: 52800023 mov w3, #0x1 // #1
ff3b0160: 1ac02060 lsl w0, w3, w0
ff3b0164: 1ac22062 lsl w2, w3, w2
ff3b0168: 2a000040 orr w0, w2, w0
ff3b016c: 2a000021 orr w1, w1, w0
ff3b0170: d2808200 mov x0, #0x410 // #1040
ff3b0174: f2bfeec0 movk x0, #0xff76, lsl #16
ff3b0178: b9000001 str w1, [x0]
ff3b017c: d65f03c0 ret
00000000ff3b0180 <select_per_cs_training_index>:
ff3b0180: 11407c00 add w0, w0, #0x1f, lsl #12
ff3b0184: 52842a03 mov w3, #0x2150 // #8528
ff3b0188: 113d4000 add w0, w0, #0xf50
ff3b018c: 53114002 lsl w2, w0, #15
ff3b0190: 0b003c60 add w0, w3, w0, lsl #15
ff3b0194: b9400000 ldr w0, [x0]
ff3b0198: 368001c0 tbz w0, #16, ff3b01d0 <select_per_cs_training_index+0x50>
ff3b019c: 52840400 mov w0, #0x2020 // #8224
ff3b01a0: 52850404 mov w4, #0x2820 // #10272
ff3b01a4: 0b000043 add w3, w2, w0
ff3b01a8: 53081c21 lsl w1, w1, #24
ff3b01ac: 0b040042 add w2, w2, w4
ff3b01b0: 2a0303e4 mov w4, w3
ff3b01b4: 11080063 add w3, w3, #0x200
ff3b01b8: 6b02007f cmp w3, w2
ff3b01bc: b9400080 ldr w0, [x4]
ff3b01c0: 12077800 and w0, w0, #0xfeffffff
ff3b01c4: 2a010000 orr w0, w0, w1
ff3b01c8: b9000080 str w0, [x4]
ff3b01cc: 54ffff21 b.ne ff3b01b0 <select_per_cs_training_index+0x30> // b.any
ff3b01d0: d65f03c0 ret
00000000ff3b01d4 <data_training.constprop.0>:
ff3b01d4: 2a0003e1 mov w1, w0
ff3b01d8: d2800482 mov x2, #0x24 // #36
ff3b01dc: a9be7bfd stp x29, x30, [sp, #-32]!
ff3b01e0: aa0103e8 mov x8, x1
ff3b01e4: b0000000 adrp x0, ff3b1000 <rk3399m0pmu_bin>
ff3b01e8: 9b027c21 mul x1, x1, x2
ff3b01ec: 91092000 add x0, x0, #0x248
ff3b01f0: 910003fd mov x29, sp
ff3b01f4: a90153f3 stp x19, x20, [sp, #16]
ff3b01f8: 3861680b ldrb w11, [x0, x1]
ff3b01fc: 39413001 ldrb w1, [x0, #76]
ff3b0200: 71001c3f cmp w1, #0x7
ff3b0204: 540008a1 b.ne ff3b0318 <data_training.constprop.0+0x144> // b.any
ff3b0208: 7100057f cmp w11, #0x1
ff3b020c: 528000a9 mov w9, #0x5 // #5
ff3b0210: 528001e1 mov w1, #0xf // #15
ff3b0214: 1a810129 csel w9, w9, w1, eq // eq = none
ff3b0218: 11407d07 add w7, w8, #0x1f, lsl #12
ff3b021c: 5285cf81 mov w1, #0x2e7c // #11900
ff3b0220: 113d40e7 add w7, w7, #0xf50
ff3b0224: 531140e5 lsl w5, w7, #15
ff3b0228: 0b073c27 add w7, w1, w7, lsl #15
ff3b022c: b94000e1 ldr w1, [x7]
ff3b0230: 320a0021 orr w1, w1, #0x400000
ff3b0234: b90000e1 str w1, [x7]
ff3b0238: 39413000 ldrb w0, [x0, #76]
ff3b023c: 71001c1f cmp w0, #0x7
ff3b0240: 54000740 b.eq ff3b0328 <data_training.constprop.0+0x154> // b.none
ff3b0244: 7100181f cmp w0, #0x6
ff3b0248: 54000740 b.eq ff3b0330 <data_training.constprop.0+0x15c> // b.none
ff3b024c: 71000c1f cmp w0, #0x3
ff3b0250: 52801fea mov w10, #0xff // #255
ff3b0254: 528001c0 mov w0, #0xe // #14
ff3b0258: 1a80114a csel w10, w10, w0, ne // ne = any
ff3b025c: 3600084a tbz w10, #0, ff3b0364 <data_training.constprop.0+0x190>
ff3b0260: 52850a0d mov w13, #0x2850 // #10320
ff3b0264: 112640a6 add w6, w5, #0x990
ff3b0268: 0b0d00ad add w13, w5, w13
ff3b026c: 5280000c mov w12, #0x0 // #0
ff3b0270: 5280002e mov w14, #0x1 // #1
ff3b0274: 1acc21c0 lsl w0, w14, w12
ff3b0278: 6a09001f tst w0, w9
ff3b027c: 54000680 b.eq ff3b034c <data_training.constprop.0+0x178> // b.none
ff3b0280: 2a0803e0 mov w0, w8
ff3b0284: 2a0c03e1 mov w1, w12
ff3b0288: 97ffffbe bl ff3b0180 <select_per_cs_training_index>
ff3b028c: b94000c0 ldr w0, [x6]
ff3b0290: 1125c0a1 add w1, w5, #0x970
ff3b0294: 12a06022 mov w2, #0xfcfeffff // #-50397185
ff3b0298: 12167400 and w0, w0, #0xfffffcff
ff3b029c: 52854a03 mov w3, #0x2a50 // #10832
ff3b02a0: 32170000 orr w0, w0, #0x200
ff3b02a4: b90000c0 str w0, [x6]
ff3b02a8: 52858a04 mov w4, #0x2c50 // #11344
ff3b02ac: 0b0300a3 add w3, w5, w3
ff3b02b0: b9400020 ldr w0, [x1]
ff3b02b4: 0b0400a4 add w4, w5, w4
ff3b02b8: 52850411 mov w17, #0x2820 // #10272
ff3b02bc: 52850012 mov w18, #0x2800 // #10240
ff3b02c0: 0a020000 and w0, w0, w2
ff3b02c4: 112ae0a2 add w2, w5, #0xab8
ff3b02c8: 2a0c6000 orr w0, w0, w12, lsl #24
ff3b02cc: 32100000 orr w0, w0, #0x10000
ff3b02d0: b9000020 str w0, [x1]
ff3b02d4: b9400041 ldr w1, [x2]
ff3b02d8: b94001af ldr w15, [x13]
ff3b02dc: b9400070 ldr w16, [x3]
ff3b02e0: b9400080 ldr w0, [x4]
ff3b02e4: 53087c33 lsr w19, w1, #8
ff3b02e8: 0a412221 and w1, w17, w1, lsr #8
ff3b02ec: 531e7e10 lsr w16, w16, #30
ff3b02f0: 6b12003f cmp w1, w18
ff3b02f4: 2a4f7a0f orr w15, w16, w15, lsr #30
ff3b02f8: 2a4079e0 orr w0, w15, w0, lsr #30
ff3b02fc: 54000041 b.ne ff3b0304 <data_training.constprop.0+0x130> // b.any
ff3b0300: 34000200 cbz w0, ff3b0340 <data_training.constprop.0+0x16c>
ff3b0304: 362801b3 tbz w19, #5, ff3b0338 <data_training.constprop.0+0x164>
ff3b0308: 12800000 mov w0, #0xffffffff // #-1
ff3b030c: a94153f3 ldp x19, x20, [sp, #16]
ff3b0310: a8c27bfd ldp x29, x30, [sp], #32
ff3b0314: d65f03c0 ret
ff3b0318: 7100057f cmp w11, #0x1
ff3b031c: 52800069 mov w9, #0x3 // #3
ff3b0320: 1a9f1529 csinc w9, w9, wzr, ne // ne = any
ff3b0324: 17ffffbd b ff3b0218 <data_training.constprop.0+0x44>
ff3b0328: 528003ca mov w10, #0x1e // #30
ff3b032c: 17ffffcc b ff3b025c <data_training.constprop.0+0x88>
ff3b0330: 528000ea mov w10, #0x7 // #7
ff3b0334: 17ffffca b ff3b025c <data_training.constprop.0+0x88>
ff3b0338: 34fffce0 cbz w0, ff3b02d4 <data_training.constprop.0+0x100>
ff3b033c: 17fffff3 b ff3b0308 <data_training.constprop.0+0x134>
ff3b0340: 112af0a0 add w0, w5, #0xabc
ff3b0344: 5287ef81 mov w1, #0x3f7c // #16252
ff3b0348: b9000001 str w1, [x0]
ff3b034c: 1100058c add w12, w12, #0x1
ff3b0350: 7100119f cmp w12, #0x4
ff3b0354: 54fff901 b.ne ff3b0274 <data_training.constprop.0+0xa0> // b.any
ff3b0358: b94000c0 ldr w0, [x6]
ff3b035c: 12167400 and w0, w0, #0xfffffcff
ff3b0360: b90000c0 str w0, [x6]
ff3b0364: 529fdfee mov w14, #0xfeff // #65279
ff3b0368: 52841400 mov w0, #0x20a0 // #8352
ff3b036c: 1123c0a6 add w6, w5, #0x8f0
ff3b0370: 0b0000ad add w13, w5, w0
ff3b0374: 5280000c mov w12, #0x0 // #0
ff3b0378: 72bfff8e movk w14, #0xfffc, lsl #16
ff3b037c: 6b0c017f cmp w11, w12
ff3b0380: 540008c8 b.hi ff3b0498 <data_training.constprop.0+0x2c4> // b.pmore
ff3b0384: 52840411 mov w17, #0x2020 // #8224
ff3b0388: 52850412 mov w18, #0x2820 // #10272
ff3b038c: 0b1100a0 add w0, w5, w17
ff3b0390: 0b1200a3 add w3, w5, w18
ff3b0394: 2a0003e2 mov w2, w0
ff3b0398: b9400041 ldr w1, [x2]
ff3b039c: 32100021 orr w1, w1, #0x10000
ff3b03a0: b9000041 str w1, [x2]
ff3b03a4: 11037002 add w2, w0, #0xdc
ff3b03a8: 11080000 add w0, w0, #0x200
ff3b03ac: 6b00007f cmp w3, w0
ff3b03b0: b9400041 ldr w1, [x2]
ff3b03b4: 12003c21 and w1, w1, #0xffff
ff3b03b8: 32070021 orr w1, w1, #0x2000000
ff3b03bc: b9000041 str w1, [x2]
ff3b03c0: 54fffea1 b.ne ff3b0394 <data_training.constprop.0+0x1c0> // b.any
ff3b03c4: 110c80a0 add w0, w5, #0x320
ff3b03c8: 52841590 mov w16, #0x20ac // #8364
ff3b03cc: 1124a0ae add w14, w5, #0x928
ff3b03d0: 0b1000ad add w13, w5, w16
ff3b03d4: 5280000c mov w12, #0x0 // #0
ff3b03d8: b9400001 ldr w1, [x0]
ff3b03dc: 32180021 orr w1, w1, #0x100
ff3b03e0: b9000001 str w1, [x0]
ff3b03e4: b94000c0 ldr w0, [x6]
ff3b03e8: 12167400 and w0, w0, #0xfffffcff
ff3b03ec: b90000c0 str w0, [x6]
ff3b03f0: 112500a6 add w6, w5, #0x940
ff3b03f4: 6b0c017f cmp w11, w12
ff3b03f8: 54000a88 b.hi ff3b0548 <data_training.constprop.0+0x374> // b.pmore
ff3b03fc: b94000c0 ldr w0, [x6]
ff3b0400: 12067400 and w0, w0, #0xfcffffff
ff3b0404: b90000c0 str w0, [x6]
ff3b0408: 371813aa tbnz w10, #3, ff3b067c <data_training.constprop.0+0x4a8>
ff3b040c: 3620156a tbz w10, #4, ff3b06b8 <data_training.constprop.0+0x4e4>
ff3b0410: 1127c0a6 add w6, w5, #0x9f0
ff3b0414: 112b50ab add w11, w5, #0xad4
ff3b0418: 112790ac add w12, w5, #0x9e4
ff3b041c: 5280000a mov w10, #0x0 // #0
ff3b0420: 52800020 mov w0, #0x1 // #1
ff3b0424: 1aca2000 lsl w0, w0, w10
ff3b0428: 6a09001f tst w0, w9
ff3b042c: 540013a0 b.eq ff3b06a0 <data_training.constprop.0+0x4cc> // b.none
ff3b0430: 2a0803e0 mov w0, w8
ff3b0434: 2a0a03e1 mov w1, w10
ff3b0438: 97ffff52 bl ff3b0180 <select_per_cs_training_index>
ff3b043c: b9400160 ldr w0, [x11]
ff3b0440: 529fdfe1 mov w1, #0xfeff // #65279
ff3b0444: 52860803 mov w3, #0x3040 // #12352
ff3b0448: 12177800 and w0, w0, #0xfffffeff
ff3b044c: b9000160 str w0, [x11]
ff3b0450: 72bfff81 movk w1, #0xfffc, lsl #16
ff3b0454: b94000c0 ldr w0, [x6]
ff3b0458: 120e7400 and w0, w0, #0xfffcffff
ff3b045c: 320f0000 orr w0, w0, #0x20000
ff3b0460: b90000c0 str w0, [x6]
ff3b0464: b9400180 ldr w0, [x12]
ff3b0468: 0a010000 and w0, w0, w1
ff3b046c: 112ae0a1 add w1, w5, #0xab8
ff3b0470: 2a0a4000 orr w0, w0, w10, lsl #16
ff3b0474: 32180000 orr w0, w0, #0x100
ff3b0478: b9000180 str w0, [x12]
ff3b047c: b9400020 ldr w0, [x1]
ff3b0480: 53087c02 lsr w2, w0, #8
ff3b0484: 0a402060 and w0, w3, w0, lsr #8
ff3b0488: 71400c1f cmp w0, #0x3, lsl #12
ff3b048c: 54001040 b.eq ff3b0694 <data_training.constprop.0+0x4c0> // b.none
ff3b0490: 3637ff62 tbz w2, #6, ff3b047c <data_training.constprop.0+0x2a8>
ff3b0494: 17ffff9d b ff3b0308 <data_training.constprop.0+0x134>
ff3b0498: 2a0803e0 mov w0, w8
ff3b049c: 2a0c03e1 mov w1, w12
ff3b04a0: 97ffff38 bl ff3b0180 <select_per_cs_training_index>
ff3b04a4: b94000c0 ldr w0, [x6]
ff3b04a8: 1123b0a1 add w1, w5, #0x8ec
ff3b04ac: 52845413 mov w19, #0x22a0 // #8864
ff3b04b0: 12167400 and w0, w0, #0xfffffcff
ff3b04b4: 52849414 mov w20, #0x24a0 // #9376
ff3b04b8: 32170000 orr w0, w0, #0x200
ff3b04bc: b90000c0 str w0, [x6]
ff3b04c0: 5284d41e mov w30, #0x26a0 // #9888
ff3b04c4: 112ae0a2 add w2, w5, #0xab8
ff3b04c8: b9400020 ldr w0, [x1]
ff3b04cc: 0b1300a3 add w3, w5, w19
ff3b04d0: 0b1400a4 add w4, w5, w20
ff3b04d4: 0b1e00af add w15, w5, w30
ff3b04d8: 0a0e0000 and w0, w0, w14
ff3b04dc: 52848211 mov w17, #0x2410 // #9232
ff3b04e0: 2a0c4000 orr w0, w0, w12, lsl #16
ff3b04e4: 52848012 mov w18, #0x2400 // #9216
ff3b04e8: 32180000 orr w0, w0, #0x100
ff3b04ec: b9000020 str w0, [x1]
ff3b04f0: b9400041 ldr w1, [x2]
ff3b04f4: b94001a0 ldr w0, [x13]
ff3b04f8: b940007e ldr w30, [x3]
ff3b04fc: b9400090 ldr w16, [x4]
ff3b0500: 53087c33 lsr w19, w1, #8
ff3b0504: b94001f4 ldr w20, [x15]
ff3b0508: 2a1e0000 orr w0, w0, w30
ff3b050c: 0a412221 and w1, w17, w1, lsr #8
ff3b0510: 2a140210 orr w16, w16, w20
ff3b0514: 6b12003f cmp w1, w18
ff3b0518: 2a100000 orr w0, w0, w16
ff3b051c: 12140000 and w0, w0, #0x1000
ff3b0520: 54000041 b.ne ff3b0528 <data_training.constprop.0+0x354> // b.any
ff3b0524: 34000080 cbz w0, ff3b0534 <data_training.constprop.0+0x360>
ff3b0528: 3727ef13 tbnz w19, #4, ff3b0308 <data_training.constprop.0+0x134>
ff3b052c: 34fffe20 cbz w0, ff3b04f0 <data_training.constprop.0+0x31c>
ff3b0530: 17ffff76 b ff3b0308 <data_training.constprop.0+0x134>
ff3b0534: 112af0a0 add w0, w5, #0xabc
ff3b0538: 5287ef81 mov w1, #0x3f7c // #16252
ff3b053c: 1100058c add w12, w12, #0x1
ff3b0540: b9000001 str w1, [x0]
ff3b0544: 17ffff8e b ff3b037c <data_training.constprop.0+0x1a8>
ff3b0548: 2a0c03e1 mov w1, w12
ff3b054c: 2a0803e0 mov w0, w8
ff3b0550: 97ffff0c bl ff3b0180 <select_per_cs_training_index>
ff3b0554: 2a0e03e1 mov w1, w14
ff3b0558: 52845580 mov w0, #0x22ac // #8876
ff3b055c: 0b0000a3 add w3, w5, w0
ff3b0560: b94000c0 ldr w0, [x6]
ff3b0564: 12a06022 mov w2, #0xfcfeffff // #-50397185
ff3b0568: 52849584 mov w4, #0x24ac // #9388
ff3b056c: 5284d58f mov w15, #0x26ac // #9900
ff3b0570: 12067400 and w0, w0, #0xfcffffff
ff3b0574: 0b0400a4 add w4, w5, w4
ff3b0578: 32070000 orr w0, w0, #0x2000000
ff3b057c: b90000c0 str w0, [x6]
ff3b0580: 0b0f00af add w15, w5, w15
ff3b0584: 52844112 mov w18, #0x2208 // #8712
ff3b0588: b9400020 ldr w0, [x1]
ff3b058c: 5284401e mov w30, #0x2200 // #8704
ff3b0590: 0a020000 and w0, w0, w2
ff3b0594: 112ae0a2 add w2, w5, #0xab8
ff3b0598: 2a0c6000 orr w0, w0, w12, lsl #24
ff3b059c: 32100000 orr w0, w0, #0x10000
ff3b05a0: b9000020 str w0, [x1]
ff3b05a4: b9400041 ldr w1, [x2]
ff3b05a8: b94001a0 ldr w0, [x13]
ff3b05ac: b9400074 ldr w20, [x3]
ff3b05b0: b9400090 ldr w16, [x4]
ff3b05b4: 53087c33 lsr w19, w1, #8
ff3b05b8: b94001f1 ldr w17, [x15]
ff3b05bc: 2a140000 orr w0, w0, w20
ff3b05c0: 0a412241 and w1, w18, w1, lsr #8
ff3b05c4: 6b1e003f cmp w1, w30
ff3b05c8: 53167e31 lsr w17, w17, #22
ff3b05cc: 2a505a30 orr w16, w17, w16, lsr #22
ff3b05d0: 2a405a00 orr w0, w16, w0, lsr #22
ff3b05d4: 12000400 and w0, w0, #0x3
ff3b05d8: 54000041 b.ne ff3b05e0 <data_training.constprop.0+0x40c> // b.any
ff3b05dc: 34000080 cbz w0, ff3b05ec <data_training.constprop.0+0x418>
ff3b05e0: 371fe953 tbnz w19, #3, ff3b0308 <data_training.constprop.0+0x134>
ff3b05e4: 34fffe00 cbz w0, ff3b05a4 <data_training.constprop.0+0x3d0>
ff3b05e8: 17ffff48 b ff3b0308 <data_training.constprop.0+0x134>
ff3b05ec: 112af0a0 add w0, w5, #0xabc
ff3b05f0: 5287ef81 mov w1, #0x3f7c // #16252
ff3b05f4: 1100058c add w12, w12, #0x1
ff3b05f8: b9000001 str w1, [x0]
ff3b05fc: 17ffff7e b ff3b03f4 <data_training.constprop.0+0x220>
ff3b0600: 2a0803e0 mov w0, w8
ff3b0604: 2a0c03e1 mov w1, w12
ff3b0608: 97fffede bl ff3b0180 <select_per_cs_training_index>
ff3b060c: b94000c0 ldr w0, [x6]
ff3b0610: 52842082 mov w2, #0x2104 // #8452
ff3b0614: 52842003 mov w3, #0x2100 // #8448
ff3b0618: 120e7400 and w0, w0, #0xfffcffff
ff3b061c: 320f0000 orr w0, w0, #0x20000
ff3b0620: b90000c0 str w0, [x6]
ff3b0624: b94001a0 ldr w0, [x13]
ff3b0628: 0a0f0000 and w0, w0, w15
ff3b062c: 2a0c6000 orr w0, w0, w12, lsl #24
ff3b0630: 32180000 orr w0, w0, #0x100
ff3b0634: b90001a0 str w0, [x13]
ff3b0638: b94001c0 ldr w0, [x14]
ff3b063c: 53087c01 lsr w1, w0, #8
ff3b0640: 0a402040 and w0, w2, w0, lsr #8
ff3b0644: 6b03001f cmp w0, w3
ff3b0648: 54000060 b.eq ff3b0654 <data_training.constprop.0+0x480> // b.none
ff3b064c: 3617ff61 tbz w1, #2, ff3b0638 <data_training.constprop.0+0x464>
ff3b0650: 17ffff2e b ff3b0308 <data_training.constprop.0+0x134>
ff3b0654: 112af0a0 add w0, w5, #0xabc
ff3b0658: 1100058c add w12, w12, #0x1
ff3b065c: 5287ef81 mov w1, #0x3f7c // #16252
ff3b0660: b9000001 str w1, [x0]
ff3b0664: 6b0c017f cmp w11, w12
ff3b0668: 54fffcc8 b.hi ff3b0600 <data_training.constprop.0+0x42c> // b.pmore
ff3b066c: b94000c0 ldr w0, [x6]
ff3b0670: 120e7400 and w0, w0, #0xfffcffff
ff3b0674: b90000c0 str w0, [x6]
ff3b0678: 17ffff65 b ff3b040c <data_training.constprop.0+0x238>
ff3b067c: 529fdfef mov w15, #0xfeff // #65279
ff3b0680: 1124a0ad add w13, w5, #0x928
ff3b0684: 112ae0ae add w14, w5, #0xab8
ff3b0688: 5280000c mov w12, #0x0 // #0
ff3b068c: 72bf9fef movk w15, #0xfcff, lsl #16
ff3b0690: 17fffff5 b ff3b0664 <data_training.constprop.0+0x490>
ff3b0694: 112af0a0 add w0, w5, #0xabc
ff3b0698: 5287ef81 mov w1, #0x3f7c // #16252
ff3b069c: b9000001 str w1, [x0]
ff3b06a0: 1100054a add w10, w10, #0x1
ff3b06a4: 7100115f cmp w10, #0x4
ff3b06a8: 54ffebc1 b.ne ff3b0420 <data_training.constprop.0+0x24c> // b.any
ff3b06ac: b94000c0 ldr w0, [x6]
ff3b06b0: 120e7400 and w0, w0, #0xfffcffff
ff3b06b4: b90000c0 str w0, [x6]
ff3b06b8: b94000e0 ldr w0, [x7]
ff3b06bc: 12097800 and w0, w0, #0xffbfffff
ff3b06c0: b90000e0 str w0, [x7]
ff3b06c4: 52800000 mov w0, #0x0 // #0
ff3b06c8: 17ffff11 b ff3b030c <data_training.constprop.0+0x138>
00000000ff3b06cc <dmc_resume>:
ff3b06cc: a9ba7bfd stp x29, x30, [sp, #-96]!
ff3b06d0: d280a200 mov x0, #0x510 // #1296
ff3b06d4: f2bfeec0 movk x0, #0xff76, lsl #16
ff3b06d8: 910003fd mov x29, sp
ff3b06dc: a90153f3 stp x19, x20, [sp, #16]
ff3b06e0: 52800041 mov w1, #0x2 // #2
ff3b06e4: a9025bf5 stp x21, x22, [sp, #32]
ff3b06e8: a90363f7 stp x23, x24, [sp, #48]
ff3b06ec: a9046bf9 stp x25, x26, [sp, #64]
ff3b06f0: f9002bfb str x27, [sp, #80]
ff3b06f4: b9000001 str w1, [x0]
ff3b06f8: d2900080 mov x0, #0x8004 // #32772
ff3b06fc: f2bff080 movk x0, #0xff84, lsl #16
ff3b0700: 52800121 mov w1, #0x9 // #9
ff3b0704: b9000001 str w1, [x0]
ff3b0708: d2900001 mov x1, #0x8000 // #32768
ff3b070c: f2bff081 movk x1, #0xff84, lsl #16
ff3b0710: b9400020 ldr w0, [x1]
ff3b0714: 32000000 orr w0, w0, #0x1
ff3b0718: b9000020 str w0, [x1]
ff3b071c: d2900180 mov x0, #0x800c // #32780
ff3b0720: 52800ec1 mov w1, #0x76 // #118
ff3b0724: f2bff080 movk x0, #0xff84, lsl #16
ff3b0728: b9000001 str w1, [x0]
ff3b072c: 97fffe4b bl ff3b0058 <secure_watchdog_ungate>
ff3b0730: d2800b81 mov x1, #0x5c // #92
ff3b0734: 12800282 mov w2, #0xffffffeb // #-21
ff3b0738: f2bfe621 movk x1, #0xff31, lsl #16
ff3b073c: b9400020 ldr w0, [x1]
ff3b0740: 0a020000 and w0, w0, w2
ff3b0744: b9000020 str w0, [x1]
ff3b0748: 97fffe55 bl ff3b009c <pmu_sgrf_rst_hld_release>
ff3b074c: 97fffe59 bl ff3b00b0 <restore_pmu_rsthold>
ff3b0750: 97fffe47 bl ff3b006c <sram_secure_timer_init>
ff3b0754: b0000000 adrp x0, ff3b1000 <rk3399m0pmu_bin>
ff3b0758: d2802302 mov x2, #0x118 // #280
ff3b075c: 913ce001 add x1, x0, #0xf38
ff3b0760: f2bfeec2 movk x2, #0xff76, lsl #16
ff3b0764: b94f3800 ldr w0, [x0, #3896]
ff3b0768: d2800983 mov x3, #0x4c // #76
ff3b076c: f2bfeec3 movk x3, #0xff76, lsl #16
ff3b0770: d2800a04 mov x4, #0x50 // #80
ff3b0774: 32103c00 orr w0, w0, #0xffff0000
ff3b0778: b9000040 str w0, [x2]
ff3b077c: 52a06000 mov w0, #0x3000000 // #50331648
ff3b0780: b9000060 str w0, [x3]
ff3b0784: d2800802 mov x2, #0x40 // #64
ff3b0788: 91001020 add x0, x1, #0x4
ff3b078c: f2bfeec2 movk x2, #0xff76, lsl #16
ff3b0790: b9400421 ldr w1, [x1, #4]
ff3b0794: f2bfeec4 movk x4, #0xff76, lsl #16
ff3b0798: 32103c21 orr w1, w1, #0xffff0000
ff3b079c: b9000041 str w1, [x2]
ff3b07a0: b9400401 ldr w1, [x0, #4]
ff3b07a4: 32103c21 orr w1, w1, #0xffff0000
ff3b07a8: b9000441 str w1, [x2, #4]
ff3b07ac: d2800901 mov x1, #0x48 // #72
ff3b07b0: f2bfeec1 movk x1, #0xff76, lsl #16
ff3b07b4: b9400802 ldr w2, [x0, #8]
ff3b07b8: b9000022 str w2, [x1]
ff3b07bc: b9401002 ldr w2, [x0, #16]
ff3b07c0: 32103c42 orr w2, w2, #0xffff0000
ff3b07c4: b9000082 str w2, [x4]
ff3b07c8: b9401402 ldr w2, [x0, #20]
ff3b07cc: 32103c42 orr w2, w2, #0xffff0000
ff3b07d0: b9000482 str w2, [x4, #4]
ff3b07d4: b9400c00 ldr w0, [x0, #12]
ff3b07d8: 32103c00 orr w0, w0, #0xffff0000
ff3b07dc: b9000060 str w0, [x3]
ff3b07e0: b9400020 ldr w0, [x1]
ff3b07e4: 36ffffe0 tbz w0, #31, ff3b07e0 <dmc_resume+0x114>
ff3b07e8: d2800800 mov x0, #0x40 // #64
ff3b07ec: 52984001 mov w1, #0xc200 // #49664
ff3b07f0: f2bfe660 movk x0, #0xff33, lsl #16
ff3b07f4: b0000013 adrp x19, ff3b1000 <rk3399m0pmu_bin>
ff3b07f8: b0000016 adrp x22, ff3b1000 <rk3399m0pmu_bin>
ff3b07fc: d2802215 mov x21, #0x110 // #272
ff3b0800: 91092273 add x19, x19, #0x248
ff3b0804: 910a72d6 add x22, x22, #0x29c
ff3b0808: 72b84001 movk w1, #0xc200, lsl #16
ff3b080c: 52800014 mov w20, #0x0 // #0
ff3b0810: f2bff515 movk x21, #0xffa8, lsl #16
ff3b0814: b9000001 str w1, [x0]
ff3b0818: 52850005 mov w5, #0x2800 // #10240
ff3b081c: 52800006 mov w6, #0x0 // #0
ff3b0820: 72bff505 movk w5, #0xffa8, lsl #16
ff3b0824: 39413660 ldrb w0, [x19, #77]
ff3b0828: 6b06001f cmp w0, w6
ff3b082c: 54000528 b.hi ff3b08d0 <dmc_resume+0x204> // b.pmore
ff3b0830: 39400660 ldrb w0, [x19, #1]
ff3b0834: 34000040 cbz w0, ff3b083c <dmc_resume+0x170>
ff3b0838: 32000294 orr w20, w20, #0x1
ff3b083c: 39409660 ldrb w0, [x19, #37]
ff3b0840: 34000040 cbz w0, ff3b0848 <dmc_resume+0x17c>
ff3b0844: 321f0294 orr w20, w20, #0x2
ff3b0848: b94002a0 ldr w0, [x21]
ff3b084c: d2902201 mov x1, #0x8110 // #33040
ff3b0850: f2bff501 movk x1, #0xffa8, lsl #16
ff3b0854: 32100000 orr w0, w0, #0x10000
ff3b0858: b90002a0 str w0, [x21]
ff3b085c: b9400020 ldr w0, [x1]
ff3b0860: 32100000 orr w0, w0, #0x10000
ff3b0864: b9000020 str w0, [x1]
ff3b0868: 12000281 and w1, w20, #0x1
ff3b086c: 360000d4 tbz w20, #0, ff3b0884 <dmc_resume+0x1b8>
ff3b0870: d2800402 mov x2, #0x20 // #32
ff3b0874: f2bfe622 movk x2, #0xff31, lsl #16
ff3b0878: b9400040 ldr w0, [x2]
ff3b087c: 320d0000 orr w0, w0, #0x80000
ff3b0880: b9000040 str w0, [x2]
ff3b0884: 121f0286 and w6, w20, #0x2
ff3b0888: 36080f34 tbz w20, #1, ff3b0a6c <dmc_resume+0x3a0>
ff3b088c: d2800402 mov x2, #0x20 // #32
ff3b0890: f2bfe622 movk x2, #0xff31, lsl #16
ff3b0894: b9400040 ldr w0, [x2]
ff3b0898: 32090000 orr w0, w0, #0x800000
ff3b089c: b9000040 str w0, [x2]
ff3b08a0: 35000e81 cbnz w1, ff3b0a70 <dmc_resume+0x3a4>
ff3b08a4: d295de82 mov x2, #0xaef4 // #44788
ff3b08a8: f2bff502 movk x2, #0xffa8, lsl #16
ff3b08ac: b9400040 ldr w0, [x2]
ff3b08b0: 12067400 and w0, w0, #0xfcffffff
ff3b08b4: 32070000 orr w0, w0, #0x2000000
ff3b08b8: b9000040 str w0, [x2]
ff3b08bc: 35000e81 cbnz w1, ff3b0a8c <dmc_resume+0x3c0>
ff3b08c0: d2906586 mov x6, #0x832c // #33580
ff3b08c4: 52800cc5 mov w5, #0x66 // #102
ff3b08c8: f2bff506 movk x6, #0xffa8, lsl #16
ff3b08cc: 140000fa b ff3b0cb4 <dmc_resume+0x5e8>
ff3b08d0: 52800022 mov w2, #0x1 // #1
ff3b08d4: 2a0203e1 mov w1, w2
ff3b08d8: 2a0603e0 mov w0, w6
ff3b08dc: 97fffe17 bl ff3b0138 <rkclk_ddr_reset>
ff3b08e0: 52800140 mov w0, #0xa // #10
ff3b08e4: 97fffe09 bl ff3b0108 <sram_udelay>
ff3b08e8: 2a0603e0 mov w0, w6
ff3b08ec: 52800002 mov w2, #0x0 // #0
ff3b08f0: 52800021 mov w1, #0x1 // #1
ff3b08f4: 97fffe11 bl ff3b0138 <rkclk_ddr_reset>
ff3b08f8: 52800140 mov w0, #0xa // #10
ff3b08fc: 97fffe03 bl ff3b0108 <sram_udelay>
ff3b0900: 52800002 mov w2, #0x0 // #0
ff3b0904: 52800001 mov w1, #0x0 // #0
ff3b0908: 2a0603e0 mov w0, w6
ff3b090c: 97fffe0b bl ff3b0138 <rkclk_ddr_reset>
ff3b0910: 52800140 mov w0, #0xa // #10
ff3b0914: 97fffdfd bl ff3b0108 <sram_udelay>
ff3b0918: aa1603e1 mov x1, x22
ff3b091c: 52802962 mov w2, #0x14b // #331
ff3b0920: 1284ff60 mov w0, #0xffffd804 // #-10236
ff3b0924: 0b0000a0 add w0, w5, w0
ff3b0928: 97fffdef bl ff3b00e4 <sram_regcpy>
ff3b092c: 514008a4 sub w4, w5, #0x2, lsl #12
ff3b0930: 1284ffe1 mov w1, #0xffffd800 // #-10240
ff3b0934: 0b0100a7 add w7, w5, w1
ff3b0938: b9405260 ldr w0, [x19, #80]
ff3b093c: 52801902 mov w2, #0xc8 // #200
ff3b0940: b0000001 adrp x1, ff3b1000 <rk3399m0pmu_bin>
ff3b0944: 911f2021 add x1, x1, #0x7c8
ff3b0948: b90000e0 str w0, [x7]
ff3b094c: aa0403e0 mov x0, x4
ff3b0950: 97fffde5 bl ff3b00e4 <sram_regcpy>
ff3b0954: 1118e0a0 add w0, w5, #0x638
ff3b0958: 52800062 mov w2, #0x3 // #3
ff3b095c: b0000001 adrp x1, ff3b1000 <rk3399m0pmu_bin>
ff3b0960: 91395021 add x1, x1, #0xe54
ff3b0964: 97fffde0 bl ff3b00e4 <sram_regcpy>
ff3b0968: 1284dde2 mov w2, #0xffffd910 // #-9968
ff3b096c: 0b0200a1 add w1, w5, w2
ff3b0970: b9400020 ldr w0, [x1]
ff3b0974: 32100000 orr w0, w0, #0x10000
ff3b0978: b9000020 str w0, [x1]
ff3b097c: 111bd0a1 add w1, w5, #0x6f4
ff3b0980: b9400020 ldr w0, [x1]
ff3b0984: 12067400 and w0, w0, #0xfcffffff
ff3b0988: 32080000 orr w0, w0, #0x1000000
ff3b098c: b9000020 str w0, [x1]
ff3b0990: d5033ebf dmb st
ff3b0994: b9400080 ldr w0, [x4]
ff3b0998: 111980a2 add w2, w5, #0x660
ff3b099c: 111990a3 add w3, w5, #0x664
ff3b09a0: 1118f0a1 add w1, w5, #0x63c
ff3b09a4: 32000000 orr w0, w0, #0x1
ff3b09a8: b9000080 str w0, [x4]
ff3b09ac: 1119a0a4 add w4, w5, #0x668
ff3b09b0: b94000e0 ldr w0, [x7]
ff3b09b4: 32000000 orr w0, w0, #0x1
ff3b09b8: b90000e0 str w0, [x7]
ff3b09bc: 320083e7 mov w7, #0x10001 // #65537
ff3b09c0: b9400049 ldr w9, [x2]
ff3b09c4: b9400060 ldr w0, [x3]
ff3b09c8: b9400088 ldr w8, [x4]
ff3b09cc: 368000a9 tbz w9, #16, ff3b09e0 <dmc_resume+0x314>
ff3b09d0: 12008000 and w0, w0, #0x10001
ff3b09d4: 6b07001f cmp w0, w7
ff3b09d8: 54000041 b.ne ff3b09e0 <dmc_resume+0x314> // b.any
ff3b09dc: 37000068 tbnz w8, #0, ff3b09e8 <dmc_resume+0x31c>
ff3b09e0: b9400020 ldr w0, [x1]
ff3b09e4: 3607fee0 tbz w0, #0, ff3b09c0 <dmc_resume+0x2f4>
ff3b09e8: 111800a0 add w0, w5, #0x600
ff3b09ec: 528007e2 mov w2, #0x3f // #63
ff3b09f0: b0000001 adrp x1, ff3b1000 <rk3399m0pmu_bin>
ff3b09f4: 91387021 add x1, x1, #0xe1c
ff3b09f8: 97fffdbb bl ff3b00e4 <sram_regcpy>
ff3b09fc: 512000a4 sub w4, w5, #0x800
ff3b0a00: b0000007 adrp x7, ff3b1000 <rk3399m0pmu_bin>
ff3b0a04: 912ba0e7 add x7, x7, #0xae8
ff3b0a08: 2a0403e0 mov w0, w4
ff3b0a0c: aa0703e1 mov x1, x7
ff3b0a10: 52800b62 mov w2, #0x5b // #91
ff3b0a14: 97fffdb4 bl ff3b00e4 <sram_regcpy>
ff3b0a18: 11080084 add w4, w4, #0x200
ff3b0a1c: 6b0400bf cmp w5, w4
ff3b0a20: 54ffff41 b.ne ff3b0a08 <dmc_resume+0x33c> // b.any
ff3b0a24: 2a0503e0 mov w0, w5
ff3b0a28: 528004c2 mov w2, #0x26 // #38
ff3b0a2c: b0000001 adrp x1, ff3b1000 <rk3399m0pmu_bin>
ff3b0a30: 91315021 add x1, x1, #0xc54
ff3b0a34: 97fffdac bl ff3b00e4 <sram_regcpy>
ff3b0a38: 110800a0 add w0, w5, #0x200
ff3b0a3c: 528004c2 mov w2, #0x26 // #38
ff3b0a40: b0000001 adrp x1, ff3b1000 <rk3399m0pmu_bin>
ff3b0a44: 9133b021 add x1, x1, #0xcec
ff3b0a48: 97fffda7 bl ff3b00e4 <sram_regcpy>
ff3b0a4c: 528004c2 mov w2, #0x26 // #38
ff3b0a50: 111000a0 add w0, w5, #0x400
ff3b0a54: b0000001 adrp x1, ff3b1000 <rk3399m0pmu_bin>
ff3b0a58: 91361021 add x1, x1, #0xd84
ff3b0a5c: 97fffda2 bl ff3b00e4 <sram_regcpy>
ff3b0a60: 110004c6 add w6, w6, #0x1
ff3b0a64: 114020a5 add w5, w5, #0x8, lsl #12
ff3b0a68: 17ffff6f b ff3b0824 <dmc_resume+0x158>
ff3b0a6c: 340003e1 cbz w1, ff3b0ae8 <dmc_resume+0x41c>
ff3b0a70: d285de82 mov x2, #0x2ef4 // #12020
ff3b0a74: f2bff502 movk x2, #0xffa8, lsl #16
ff3b0a78: b9400040 ldr w0, [x2]
ff3b0a7c: 12067400 and w0, w0, #0xfcffffff
ff3b0a80: 32070000 orr w0, w0, #0x2000000
ff3b0a84: b9000040 str w0, [x2]
ff3b0a88: 35fff0e6 cbnz w6, ff3b08a4 <dmc_resume+0x1d8>
ff3b0a8c: d2806587 mov x7, #0x32c // #812
ff3b0a90: 52800cc5 mov w5, #0x66 // #102
ff3b0a94: f2bff507 movk x7, #0xffa8, lsl #16
ff3b0a98: b94000e0 ldr w0, [x7]
ff3b0a9c: 36180fa0 tbz w0, #3, ff3b0c90 <dmc_resume+0x5c4>
ff3b0aa0: b94002a0 ldr w0, [x21]
ff3b0aa4: b0000002 adrp x2, ff3b1000 <rk3399m0pmu_bin>
ff3b0aa8: d2851c83 mov x3, #0x28e4 // #10468
ff3b0aac: 913c6042 add x2, x2, #0xf18
ff3b0ab0: 120f7800 and w0, w0, #0xfffeffff
ff3b0ab4: b90002a0 str w0, [x21]
ff3b0ab8: d2841c80 mov x0, #0x20e4 // #8420
ff3b0abc: f2bff503 movk x3, #0xffa8, lsl #16
ff3b0ac0: f2bff500 movk x0, #0xffa8, lsl #16
ff3b0ac4: b9400001 ldr w1, [x0]
ff3b0ac8: b8404444 ldr w4, [x2], #4
ff3b0acc: 12044c21 and w1, w1, #0xf000ffff
ff3b0ad0: 2a040021 orr w1, w1, w4
ff3b0ad4: b9000001 str w1, [x0]
ff3b0ad8: 91080000 add x0, x0, #0x200
ff3b0adc: eb03001f cmp x0, x3
ff3b0ae0: 54ffff21 b.ne ff3b0ac4 <dmc_resume+0x3f8> // b.any
ff3b0ae4: 35ffeee6 cbnz w6, ff3b08c0 <dmc_resume+0x1f4>
ff3b0ae8: d288011b mov x27, #0x4008 // #16392
ff3b0aec: aa1303f9 mov x25, x19
ff3b0af0: f2bff51b movk x27, #0xffa8, lsl #16
ff3b0af4: 5280001a mov w26, #0x0 // #0
ff3b0af8: 52800037 mov w23, #0x1 // #1
ff3b0afc: 52800078 mov w24, #0x3 // #3
ff3b0b00: 39413660 ldrb w0, [x19, #77]
ff3b0b04: 6b1a001f cmp w0, w26
ff3b0b08: 54001028 b.hi ff3b0d0c <dmc_resume+0x640> // b.pmore
ff3b0b0c: 39400660 ldrb w0, [x19, #1]
ff3b0b10: 340002a0 cbz w0, ff3b0b64 <dmc_resume+0x498>
ff3b0b14: d2880200 mov x0, #0x4010 // #16400
ff3b0b18: b9400e61 ldr w1, [x19, #12]
ff3b0b1c: f2bff500 movk x0, #0xffa8, lsl #16
ff3b0b20: b9000001 str w1, [x0]
ff3b0b24: b9401261 ldr w1, [x19, #16]
ff3b0b28: b9000401 str w1, [x0, #4]
ff3b0b2c: b9401661 ldr w1, [x19, #20]
ff3b0b30: b9000801 str w1, [x0, #8]
ff3b0b34: b9401a61 ldr w1, [x19, #24]
ff3b0b38: b9000c01 str w1, [x0, #12]
ff3b0b3c: b9401e61 ldr w1, [x19, #28]
ff3b0b40: b9010001 str w1, [x0, #256]
ff3b0b44: 39400260 ldrb w0, [x19]
ff3b0b48: 7100041f cmp w0, #0x1
ff3b0b4c: 540000c1 b.ne ff3b0b64 <dmc_resume+0x498> // b.any
ff3b0b50: d2808a01 mov x1, #0x450 // #1104
ff3b0b54: f2bff501 movk x1, #0xffa8, lsl #16
ff3b0b58: b9400020 ldr w0, [x1]
ff3b0b5c: 320f0000 orr w0, w0, #0x20000
ff3b0b60: b9000020 str w0, [x1]
ff3b0b64: 39409660 ldrb w0, [x19, #37]
ff3b0b68: 340002a0 cbz w0, ff3b0bbc <dmc_resume+0x4f0>
ff3b0b6c: d2980200 mov x0, #0xc010 // #49168
ff3b0b70: b9403261 ldr w1, [x19, #48]
ff3b0b74: f2bff500 movk x0, #0xffa8, lsl #16
ff3b0b78: b9000001 str w1, [x0]
ff3b0b7c: b9403661 ldr w1, [x19, #52]
ff3b0b80: b9000401 str w1, [x0, #4]
ff3b0b84: b9403a61 ldr w1, [x19, #56]
ff3b0b88: b9000801 str w1, [x0, #8]
ff3b0b8c: b9403e61 ldr w1, [x19, #60]
ff3b0b90: b9000c01 str w1, [x0, #12]
ff3b0b94: b9404261 ldr w1, [x19, #64]
ff3b0b98: b9010001 str w1, [x0, #256]
ff3b0b9c: 39409260 ldrb w0, [x19, #36]
ff3b0ba0: 7100041f cmp w0, #0x1
ff3b0ba4: 540000c1 b.ne ff3b0bbc <dmc_resume+0x4f0> // b.any
ff3b0ba8: d2908a01 mov x1, #0x8450 // #33872
ff3b0bac: f2bff501 movk x1, #0xffa8, lsl #16
ff3b0bb0: b9400020 ldr w0, [x1]
ff3b0bb4: 320f0000 orr w0, w0, #0x20000
ff3b0bb8: b9000020 str w0, [x1]
ff3b0bbc: 39413a60 ldrb w0, [x19, #78]
ff3b0bc0: d29c0201 mov x1, #0xe010 // #57360
ff3b0bc4: f2bfe661 movk x1, #0xff33, lsl #16
ff3b0bc8: 53165400 lsl w0, w0, #10
ff3b0bcc: 32061000 orr w0, w0, #0x7c000000
ff3b0bd0: b9000020 str w0, [x1]
ff3b0bd4: d2802480 mov x0, #0x124 // #292
ff3b0bd8: 52803001 mov w1, #0x180 // #384
ff3b0bdc: f2bfeea0 movk x0, #0xff75, lsl #16
ff3b0be0: 72a03801 movk w1, #0x1c0, lsl #16
ff3b0be4: b9000001 str w1, [x0]
ff3b0be8: d280a201 mov x1, #0x510 // #1296
ff3b0bec: f2bfeec1 movk x1, #0xff76, lsl #16
ff3b0bf0: b9400020 ldr w0, [x1]
ff3b0bf4: 32000400 orr w0, w0, #0x3
ff3b0bf8: b9000020 str w0, [x1]
ff3b0bfc: d2803780 mov x0, #0x1bc // #444
ff3b0c00: 528000a1 mov w1, #0x5 // #5
ff3b0c04: f2bff500 movk x0, #0xffa8, lsl #16
ff3b0c08: 72a006a1 movk w1, #0x35, lsl #16
ff3b0c0c: b9400000 ldr w0, [x0]
ff3b0c10: 53107c00 lsr w0, w0, #16
ff3b0c14: 11000400 add w0, w0, #0x1
ff3b0c18: 12000014 and w20, w0, #0x1
ff3b0c1c: 531c0000 ubfiz w0, w0, #4, #1
ff3b0c20: 2a010000 orr w0, w0, w1
ff3b0c24: d2bfec41 mov x1, #0xff620000 // #4284612608
ff3b0c28: b9000020 str w0, [x1]
ff3b0c2c: d2800200 mov x0, #0x10 // #16
ff3b0c30: f2bfec40 movk x0, #0xff62, lsl #16
ff3b0c34: aa0003e1 mov x1, x0
ff3b0c38: b9400002 ldr w2, [x0]
ff3b0c3c: 3617ffe2 tbz w2, #2, ff3b0c38 <dmc_resume+0x56c>
ff3b0c40: d2bfec40 mov x0, #0xff620000 // #4284612608
ff3b0c44: 320f83e2 mov w2, #0x20002 // #131074
ff3b0c48: b9000002 str w2, [x0]
ff3b0c4c: b9400020 ldr w0, [x1]
ff3b0c50: 3607ffe0 tbz w0, #0, ff3b0c4c <dmc_resume+0x580>
ff3b0c54: 5285c016 mov w22, #0x2e00 // #11776
ff3b0c58: 53185e94 lsl w20, w20, #8
ff3b0c5c: 39413675 ldrb w21, [x19, #77]
ff3b0c60: 72bff516 movk w22, #0xffa8, lsl #16
ff3b0c64: 52800013 mov w19, #0x0 // #0
ff3b0c68: 12806037 mov w23, #0xfffffcfe // #-770
ff3b0c6c: 6b1302bf cmp w21, w19
ff3b0c70: 54000a48 b.hi ff3b0db8 <dmc_resume+0x6ec> // b.pmore
ff3b0c74: a94153f3 ldp x19, x20, [sp, #16]
ff3b0c78: a9425bf5 ldp x21, x22, [sp, #32]
ff3b0c7c: a94363f7 ldp x23, x24, [sp, #48]
ff3b0c80: a9446bf9 ldp x25, x26, [sp, #64]
ff3b0c84: f9402bfb ldr x27, [sp, #80]
ff3b0c88: a8c67bfd ldp x29, x30, [sp], #96
ff3b0c8c: d65f03c0 ret
ff3b0c90: 710004a5 subs w5, w5, #0x1
ff3b0c94: 54ffdc20 b.eq ff3b0818 <dmc_resume+0x14c> // b.none
ff3b0c98: 52800c80 mov w0, #0x64 // #100
ff3b0c9c: 97fffd1b bl ff3b0108 <sram_udelay>
ff3b0ca0: 17ffff7e b ff3b0a98 <dmc_resume+0x3cc>
ff3b0ca4: 710004a5 subs w5, w5, #0x1
ff3b0ca8: 54ffdb80 b.eq ff3b0818 <dmc_resume+0x14c> // b.none
ff3b0cac: 52800c80 mov w0, #0x64 // #100
ff3b0cb0: 97fffd16 bl ff3b0108 <sram_udelay>
ff3b0cb4: b94000c0 ldr w0, [x6]
ff3b0cb8: 361fff60 tbz w0, #3, ff3b0ca4 <dmc_resume+0x5d8>
ff3b0cbc: d2902201 mov x1, #0x8110 // #33040
ff3b0cc0: b0000002 adrp x2, ff3b1000 <rk3399m0pmu_bin>
ff3b0cc4: f2bff501 movk x1, #0xffa8, lsl #16
ff3b0cc8: d2951c83 mov x3, #0xa8e4 // #43236
ff3b0ccc: 913ca042 add x2, x2, #0xf28
ff3b0cd0: f2bff503 movk x3, #0xffa8, lsl #16
ff3b0cd4: b9400020 ldr w0, [x1]
ff3b0cd8: 120f7800 and w0, w0, #0xfffeffff
ff3b0cdc: b9000020 str w0, [x1]
ff3b0ce0: d2941c80 mov x0, #0xa0e4 // #41188
ff3b0ce4: f2bff500 movk x0, #0xffa8, lsl #16
ff3b0ce8: b9400001 ldr w1, [x0]
ff3b0cec: b8404444 ldr w4, [x2], #4
ff3b0cf0: 12044c21 and w1, w1, #0xf000ffff
ff3b0cf4: 2a040021 orr w1, w1, w4
ff3b0cf8: b9000001 str w1, [x0]
ff3b0cfc: 91080000 add x0, x0, #0x200
ff3b0d00: eb03001f cmp x0, x3
ff3b0d04: 54ffff21 b.ne ff3b0ce8 <dmc_resume+0x61c> // b.any
ff3b0d08: 17ffff78 b ff3b0ae8 <dmc_resume+0x41c>
ff3b0d0c: 39413260 ldrb w0, [x19, #76]
ff3b0d10: 7100181f cmp w0, #0x6
ff3b0d14: 54000061 b.ne ff3b0d20 <dmc_resume+0x654> // b.any
ff3b0d18: 52800140 mov w0, #0xa // #10
ff3b0d1c: 97fffcfb bl ff3b0108 <sram_udelay>
ff3b0d20: 2a1a03e0 mov w0, w26
ff3b0d24: 97fffd2c bl ff3b01d4 <data_training.constprop.0>
ff3b0d28: 35ffd780 cbnz w0, ff3b0818 <dmc_resume+0x14c>
ff3b0d2c: 39401b20 ldrb w0, [x25, #6]
ff3b0d30: 39400721 ldrb w1, [x25, #1]
ff3b0d34: 39400b22 ldrb w2, [x25, #2]
ff3b0d38: 0b000021 add w1, w1, w0
ff3b0d3c: 39400324 ldrb w4, [x25]
ff3b0d40: 0b020021 add w1, w1, w2
ff3b0d44: 39400f22 ldrb w2, [x25, #3]
ff3b0d48: b9400b23 ldr w3, [x25, #8]
ff3b0d4c: 7100049f cmp w4, #0x1
ff3b0d50: 0b020021 add w1, w1, w2
ff3b0d54: 51005021 sub w1, w1, #0x14
ff3b0d58: 1ac122e2 lsl w2, w23, w1
ff3b0d5c: 540002a9 b.ls ff3b0db0 <dmc_resume+0x6e4> // b.plast
ff3b0d60: 39401f24 ldrb w4, [x25, #7]
ff3b0d64: 4b040000 sub w0, w0, w4
ff3b0d68: 1ac02440 lsr w0, w2, w0
ff3b0d6c: 39401724 ldrb w4, [x25, #5]
ff3b0d70: 340000a4 cbz w4, ff3b0d84 <dmc_resume+0x6b8>
ff3b0d74: 0b000400 add w0, w0, w0, lsl #1
ff3b0d78: 1ac12301 lsl w1, w24, w1
ff3b0d7c: 53027c22 lsr w2, w1, #2
ff3b0d80: 53027c00 lsr w0, w0, #2
ff3b0d84: 53057c00 lsr w0, w0, #5
ff3b0d88: 2a031863 orr w3, w3, w3, lsl #6
ff3b0d8c: d3453041 ubfx x1, x2, #5, #8
ff3b0d90: b9000363 str w3, [x27]
ff3b0d94: 53181c00 ubfiz w0, w0, #8, #8
ff3b0d98: 1100075a add w26, w26, #0x1
ff3b0d9c: 2a010000 orr w0, w0, w1
ff3b0da0: 91009339 add x25, x25, #0x24
ff3b0da4: b9000760 str w0, [x27, #4]
ff3b0da8: 9140237b add x27, x27, #0x8, lsl #12
ff3b0dac: 17ffff55 b ff3b0b00 <dmc_resume+0x434>
ff3b0db0: 52800000 mov w0, #0x0 // #0
ff3b0db4: 17ffffee b ff3b0d6c <dmc_resume+0x6a0>
ff3b0db8: 0b133ec1 add w1, w22, w19, lsl #15
ff3b0dbc: b9400020 ldr w0, [x1]
ff3b0dc0: 0a170000 and w0, w0, w23
ff3b0dc4: 2a140000 orr w0, w0, w20
ff3b0dc8: b9000020 str w0, [x1]
ff3b0dcc: 2a1303e0 mov w0, w19
ff3b0dd0: 97fffd01 bl ff3b01d4 <data_training.constprop.0>
ff3b0dd4: 35fff500 cbnz w0, ff3b0c74 <dmc_resume+0x5a8>
ff3b0dd8: 11000673 add w19, w19, #0x1
ff3b0ddc: 17ffffa4 b ff3b0c6c <dmc_resume+0x5a0>
00000000ff3b0de0 <__bl31_pmusram_text_end>:
...
00000000ff3b1000 <rk3399m0pmu_bin>:
ff3b1000: 00000240 00000135 00000131 00000131 @...5...1...1...
...
ff3b102c: 00000131 00000000 00000000 00000131 1...........1...
ff3b103c: 00000131 00000000 00000000 00000000 1...............
...
ff3b10e8: 681a4b0e d0fc2a00 4a0d2101 438b6813 .K.h.*...!.J.h.C
ff3b10f8: 4b0a6013 2a10681a 2102d9fc 68134a09 .`.K.h.*...!.J.h
ff3b1108: 6013430b 681a4b05 d9fc2a19 4a052102 .C.`.K.h.*...!.J
ff3b1118: 438b6813 bf306013 46c0e7fd 47310078 .h.C.`0....Fx.1G
ff3b1128: 47310020 47310024 46c0e7fe f7ffb510 .1G$.1G...F....
ff3b1138: bd10ffd7 00000000 00000000 00000000 ................
...
00000000ff3b1240 <pmu_slp_data>:
...
00000000ff3b1248 <sdram_config>:
...
00000000ff3b1f38 <cru_clksel_con6>:
ff3b1f38: 00000000 ....
00000000ff3b1f3c <dpll_data>:
...
Disassembly of section ro:
0000000000040000 <bl31_entrypoint>:
40000: aa0003f4 mov x20, x0
40004: aa0103f5 mov x21, x1
40008: aa0203f6 mov x22, x2
4000c: aa0303f7 mov x23, x3
40010: 1012bf80 adr x0, 65800 <sync_exception_sp_el0>
40014: d51ec000 msr vbar_el3, x0
40018: d5033fdf isb
4001c: 94008101 bl 60420 <reset_handler>
40020: d2820141 mov x1, #0x100a // #4106
40024: d53e1000 mrs x0, sctlr_el3
40028: aa010000 orr x0, x0, x1
4002c: d51e1000 msr sctlr_el3, x0
40030: d5033fdf isb
40034: 940080f0 bl 603f4 <init_cpu_data_ptr>
40038: d2804700 mov x0, #0x238 // #568
4003c: d51e1100 msr scr_el3, x0
40040: d2900000 mov x0, #0x8000 // #32768
40044: f2a01020 movk x0, #0x81, lsl #16
40048: d51e1320 msr mdcr_el3, x0
4004c: d2801c00 mov x0, #0xe0 // #224
40050: d51b9c00 msr pmcr_el0, x0
40054: d50344ff msr daifclr, #0x4
40058: d2800000 mov x0, #0x0 // #0
4005c: d51e1140 msr cptr_el3, x0
40060: d5380400 mrs x0, id_aa64pfr0_el1
40064: d370cc00 ubfx x0, x0, #48, #4
40068: f100041f cmp x0, #0x1
4006c: 54000061 b.ne 40078 <bl31_entrypoint+0x78> // b.any
40070: d2a02000 mov x0, #0x1000000 // #16777216
40074: d51b42a0 msr dit, x0
40078: f0000120 adrp x0, 67000 <__RO_END__>
4007c: 91000000 add x0, x0, #0x0
40080: f00002a1 adrp x1, 97000 <__BL31_END__>
40084: 91000021 add x1, x1, #0x0
40088: cb000021 sub x1, x1, x0
4008c: 94008245 bl 609a0 <inv_dcache_range>
40090: d0000140 adrp x0, 6a000 <__STACKS_START__+0x2f80>
40094: 91020000 add x0, x0, #0x80
40098: b0000201 adrp x1, 81000 <store_sram+0x2377>
4009c: 91345421 add x1, x1, #0xd15
400a0: cb000021 sub x1, x1, x0
400a4: 9400828c bl 60ad4 <zeromem>
400a8: d00002a0 adrp x0, 96000 <rockchip_pd_lock>
400ac: 91000000 add x0, x0, #0x0
400b0: d00002a1 adrp x1, 96000 <rockchip_pd_lock>
400b4: 91048021 add x1, x1, #0x120
400b8: cb000021 sub x1, x1, x0
400bc: 94008286 bl 60ad4 <zeromem>
400c0: d50040bf msr spsel, #0x0
400c4: 940080c8 bl 603e4 <plat_set_my_stack>
400c8: aa1403e0 mov x0, x20
400cc: aa1503e1 mov x1, x21
400d0: aa1603e2 mov x2, x22
400d4: aa1703e3 mov x3, x23
400d8: 94006f0d bl 5bd0c <bl31_setup>
400dc: 94006f47 bl 5bdf8 <bl31_main>
400e0: f0000120 adrp x0, 67000 <__RO_END__>
400e4: 91000000 add x0, x0, #0x0
400e8: f0000121 adrp x1, 67000 <__RO_END__>
400ec: 9101c821 add x1, x1, #0x72
400f0: cb000021 sub x1, x1, x0
400f4: 9400821d bl 60968 <clean_dcache_range>
400f8: d0000140 adrp x0, 6a000 <__STACKS_START__+0x2f80>
400fc: 91020000 add x0, x0, #0x80
40100: b0000201 adrp x1, 81000 <store_sram+0x2377>
40104: 91345421 add x1, x1, #0xd15
40108: cb000021 sub x1, x1, x0
4010c: 94008217 bl 60968 <clean_dcache_range>
40110: 140081b8 b 607f0 <el3_exit>
40114: 00000000 .inst 0x00000000 ; undefined
40118: 14000008 b 40138 <bl31_warm_entrypoint>
4011c: d503201f nop
0000000000040120 <__sram_func_set_ddrctl_pll_veneer>:
40120: b07fc410 adrp x16, ff8c1000 <__sram_incbin_end>
40124: 91000210 add x16, x16, #0x0
40128: d61f0200 br x16
...
0000000000040138 <bl31_warm_entrypoint>:
40138: 1012b640 adr x0, 65800 <sync_exception_sp_el0>
4013c: d51ec000 msr vbar_el3, x0
40140: d5033fdf isb
40144: 940080b7 bl 60420 <reset_handler>
40148: d2820141 mov x1, #0x100a // #4106
4014c: d53e1000 mrs x0, sctlr_el3
40150: aa010000 orr x0, x0, x1
40154: d51e1000 msr sctlr_el3, x0
40158: d5033fdf isb
4015c: 940080a6 bl 603f4 <init_cpu_data_ptr>
40160: d2804700 mov x0, #0x238 // #568
40164: d51e1100 msr scr_el3, x0
40168: d2900000 mov x0, #0x8000 // #32768
4016c: f2a01020 movk x0, #0x81, lsl #16
40170: d51e1320 msr mdcr_el3, x0
40174: d2801c00 mov x0, #0xe0 // #224
40178: d51b9c00 msr pmcr_el0, x0
4017c: d50344ff msr daifclr, #0x4
40180: d2800000 mov x0, #0x0 // #0
40184: d51e1140 msr cptr_el3, x0
40188: d5380400 mrs x0, id_aa64pfr0_el1
4018c: d370cc00 ubfx x0, x0, #48, #4
40190: f100041f cmp x0, #0x1
40194: 54000061 b.ne 401a0 <bl31_warm_entrypoint+0x68> // b.any
40198: d2a02000 mov x0, #0x1000000 // #16777216
4019c: d51b42a0 msr dit, x0
401a0: d50040bf msr spsel, #0x0
401a4: 94008090 bl 603e4 <plat_set_my_stack>
401a8: d2800020 mov x0, #0x1 // #1
401ac: 94008292 bl 60bf4 <bl31_plat_enable_mmu>
401b0: 9400753e bl 5d6a8 <psci_warmboot_entrypoint>
401b4: 1400818f b 607f0 <el3_exit>
...
0000000000050000 <platform_cpu_warmboot>:
50000: d53800a0 mrs x0, mpidr_el1
50004: 92401c13 and x19, x0, #0xff
50008: 92781c14 and x20, x0, #0xff00
5000c: aa1403e0 mov x0, x20
50010: 10230844 adr x4, 96118 <clst_warmboot_data>
50014: d346fc05 lsr x5, x0, #6
50018: b8656883 ldr w3, [x4, x5]
5001c: b825689f str wzr, [x4, x5]
50020: 7102947f cmp w3, #0xa5
50024: 540000a1 b.ne 50038 <clst_warmboot_end> // b.any
50028: 18000246 ldr w6, 50070 <boot_entry+0x10>
5002c: 58000267 ldr x7, 50078 <boot_entry+0x18>
50030: d343fc02 lsr x2, x0, #3
50034: b82268e6 str w6, [x7, x2]
0000000000050038 <clst_warmboot_end>:
50038: 8b541a75 add x21, x19, x20, lsr #6
5003c: 10230624 adr x4, 96100 <cpuson_flags>
50040: 8b150884 add x4, x4, x21, lsl #2
50044: b9400081 ldr w1, [x4]
50048: 7103c03f cmp w1, #0xf0
5004c: 540000a0 b.eq 50060 <boot_entry> // b.none
50050: 713c003f cmp w1, #0xf00
50054: 54000060 b.eq 50060 <boot_entry> // b.none
0000000000050058 <wfe_loop>:
50058: d503205f wfe
5005c: 17ffffff b 50058 <wfe_loop>
0000000000050060 <boot_entry>:
50060: b900009f str wzr, [x4]
50064: 10230365 adr x5, 960d0 <cpuson_entry_point>
50068: f87578a2 ldr x2, [x5, x21, lsl #3]
5006c: d61f0040 br x2
50070: 03000100 .word 0x03000100
50074: 00000000 .inst 0x00000000 ; undefined
50078: ff76000c .word 0xff76000c
5007c: 00000000 .word 0x00000000
0000000000050080 <gicd_read_igroupr>:
50080: 53057c21 lsr w1, w1, #5
50084: 91020000 add x0, x0, #0x80
50088: d37e6821 ubfiz x1, x1, #2, #27
5008c: b8606820 ldr w0, [x1, x0]
50090: d65f03c0 ret
0000000000050094 <gicd_read_isenabler>:
50094: 53057c21 lsr w1, w1, #5
50098: 91040000 add x0, x0, #0x100
5009c: d37e6821 ubfiz x1, x1, #2, #27
500a0: b8606820 ldr w0, [x1, x0]
500a4: d65f03c0 ret
00000000000500a8 <gicd_read_ispendr>:
500a8: 53057c21 lsr w1, w1, #5
500ac: 91080000 add x0, x0, #0x200
500b0: d37e6821 ubfiz x1, x1, #2, #27
500b4: b8606820 ldr w0, [x1, x0]
500b8: d65f03c0 ret
00000000000500bc <gicd_read_isactiver>:
500bc: 53057c21 lsr w1, w1, #5
500c0: 910c0000 add x0, x0, #0x300
500c4: d37e6821 ubfiz x1, x1, #2, #27
500c8: b8606820 ldr w0, [x1, x0]
500cc: d65f03c0 ret
00000000000500d0 <gicd_read_ipriorityr>:
500d0: 927e7421 and x1, x1, #0xfffffffc
500d4: 91100000 add x0, x0, #0x400
500d8: b8606820 ldr w0, [x1, x0]
500dc: d65f03c0 ret
00000000000500e0 <gicd_read_icfgr>:
500e0: 53047c21 lsr w1, w1, #4
500e4: 91300000 add x0, x0, #0xc00
500e8: d37e6c21 ubfiz x1, x1, #2, #28
500ec: b8606820 ldr w0, [x1, x0]
500f0: d65f03c0 ret
00000000000500f4 <gicd_read_nsacr>:
500f4: 53047c21 lsr w1, w1, #4
500f8: 91380000 add x0, x0, #0xe00
500fc: d37e6c21 ubfiz x1, x1, #2, #28
50100: b8606820 ldr w0, [x1, x0]
50104: d65f03c0 ret
0000000000050108 <gicd_write_igroupr>:
50108: 53057c21 lsr w1, w1, #5
5010c: 91020000 add x0, x0, #0x80
50110: d37e6821 ubfiz x1, x1, #2, #27
50114: b8206822 str w2, [x1, x0]
50118: d65f03c0 ret
000000000005011c <gicd_write_isenabler>:
5011c: 53057c21 lsr w1, w1, #5
50120: 91040000 add x0, x0, #0x100
50124: d37e6821 ubfiz x1, x1, #2, #27
50128: b8206822 str w2, [x1, x0]
5012c: d65f03c0 ret
0000000000050130 <gicd_write_ispendr>:
50130: 53057c21 lsr w1, w1, #5
50134: 91080000 add x0, x0, #0x200
50138: d37e6821 ubfiz x1, x1, #2, #27
5013c: b8206822 str w2, [x1, x0]
50140: d65f03c0 ret
0000000000050144 <gicd_write_isactiver>:
50144: 53057c21 lsr w1, w1, #5
50148: 910c0000 add x0, x0, #0x300
5014c: d37e6821 ubfiz x1, x1, #2, #27
50150: b8206822 str w2, [x1, x0]
50154: d65f03c0 ret
0000000000050158 <gicd_write_ipriorityr>:
50158: 927e7421 and x1, x1, #0xfffffffc
5015c: 91100000 add x0, x0, #0x400
50160: b8206822 str w2, [x1, x0]
50164: d65f03c0 ret
0000000000050168 <gicd_write_icfgr>:
50168: 53047c21 lsr w1, w1, #4
5016c: 91300000 add x0, x0, #0xc00
50170: d37e6c21 ubfiz x1, x1, #2, #28
50174: b8206822 str w2, [x1, x0]
50178: d65f03c0 ret
000000000005017c <gicd_write_nsacr>:
5017c: 53047c21 lsr w1, w1, #4
50180: 91380000 add x0, x0, #0xe00
50184: d37e6c21 ubfiz x1, x1, #2, #28
50188: b8206822 str w2, [x1, x0]
5018c: d65f03c0 ret
0000000000050190 <gicd_clr_igroupr>:
50190: 2a0103e3 mov w3, w1
50194: aa0003e4 mov x4, x0
50198: a9bf7bfd stp x29, x30, [sp, #-16]!
5019c: 910003fd mov x29, sp
501a0: 97ffffb8 bl 50080 <gicd_read_igroupr>
501a4: a8c17bfd ldp x29, x30, [sp], #16
501a8: 52800021 mov w1, #0x1 // #1
501ac: 1ac32021 lsl w1, w1, w3
501b0: 0a210002 bic w2, w0, w1
501b4: 2a0303e1 mov w1, w3
501b8: aa0403e0 mov x0, x4
501bc: 17ffffd3 b 50108 <gicd_write_igroupr>
00000000000501c0 <gicd_set_isenabler>:
501c0: 52800022 mov w2, #0x1 // #1
501c4: 1ac12042 lsl w2, w2, w1
501c8: 17ffffd5 b 5011c <gicd_write_isenabler>
00000000000501cc <gicd_set_ipriorityr>:
501cc: 91100000 add x0, x0, #0x400
501d0: 2a0103e1 mov w1, w1
501d4: 12001c42 and w2, w2, #0xff
501d8: 38216802 strb w2, [x0, x1]
501dc: d65f03c0 ret
00000000000501e0 <gicd_set_icfgr>:
501e0: 531f0c26 ubfiz w6, w1, #1, #4
501e4: aa0003e5 mov x5, x0
501e8: 2a0103e4 mov w4, w1
501ec: a9bf7bfd stp x29, x30, [sp, #-16]!
501f0: 910003fd mov x29, sp
501f4: 97ffffbb bl 500e0 <gicd_read_icfgr>
501f8: 12000442 and w2, w2, #0x3
501fc: a8c17bfd ldp x29, x30, [sp], #16
50200: 52800063 mov w3, #0x3 // #3
50204: 1ac62063 lsl w3, w3, w6
50208: 0a230003 bic w3, w0, w3
5020c: 1ac62042 lsl w2, w2, w6
50210: 2a0403e1 mov w1, w4
50214: 2a030042 orr w2, w2, w3
50218: aa0503e0 mov x0, x5
5021c: 17ffffd3 b 50168 <gicd_write_icfgr>
0000000000050220 <arm_gicv3_distif_pre_save>:
50220: a9bf7bfd stp x29, x30, [sp, #-16]!
50224: f00000c1 adrp x1, 6b000 <psci_ns_context+0xc60>
50228: 910003fd mov x29, sp
5022c: f9403021 ldr x1, [x1, #96]
50230: b50000e1 cbnz x1, 5024c <arm_gicv3_distif_pre_save+0x2c>
50234: d0000082 adrp x2, 62000 <vprintf+0x400>
50238: 911a8042 add x2, x2, #0x6a0
5023c: 52800401 mov w1, #0x20 // #32
50240: d0000080 adrp x0, 62000 <vprintf+0x400>
50244: 911ac800 add x0, x0, #0x6b2
50248: 940045f9 bl 61a2c <__assert>
5024c: f9401022 ldr x2, [x1, #32]
50250: b40001c2 cbz x2, 50288 <arm_gicv3_distif_pre_save+0x68>
50254: b9401c24 ldr w4, [x1, #28]
50258: d2800001 mov x1, #0x0 // #0
5025c: 6b01009f cmp w4, w1
50260: 540001c8 b.hi 50298 <arm_gicv3_distif_pre_save+0x78> // b.pmore
50264: f8605840 ldr x0, [x2, w0, uxtw #3]
50268: 91005002 add x2, x0, #0x14
5026c: b9401401 ldr w1, [x0, #20]
50270: 32000021 orr w1, w1, #0x1
50274: b9001401 str w1, [x0, #20]
50278: b9400040 ldr w0, [x2]
5027c: 36ffffe0 tbz w0, #31, 50278 <arm_gicv3_distif_pre_save+0x58>
50280: a8c17bfd ldp x29, x30, [sp], #16
50284: d65f03c0 ret
50288: d0000082 adrp x2, 62000 <vprintf+0x400>
5028c: 52800421 mov w1, #0x21 // #33
50290: 911b6042 add x2, x2, #0x6d8
50294: 17ffffeb b 50240 <arm_gicv3_distif_pre_save+0x20>
50298: f8617843 ldr x3, [x2, x1, lsl #3]
5029c: b50000a3 cbnz x3, 502b0 <arm_gicv3_distif_pre_save+0x90>
502a0: d0000082 adrp x2, 62000 <vprintf+0x400>
502a4: 52800541 mov w1, #0x2a // #42
502a8: 911bf842 add x2, x2, #0x6fe
502ac: 17ffffe5 b 50240 <arm_gicv3_distif_pre_save+0x20>
502b0: b9401465 ldr w5, [x3, #20]
502b4: 371000a5 tbnz w5, #2, 502c8 <arm_gicv3_distif_pre_save+0xa8>
502b8: d0000082 adrp x2, 62000 <vprintf+0x400>
502bc: 52800561 mov w1, #0x2b // #43
502c0: 911c2042 add x2, x2, #0x708
502c4: 17ffffdf b 50240 <arm_gicv3_distif_pre_save+0x20>
502c8: b9401463 ldr w3, [x3, #20]
502cc: 91000421 add x1, x1, #0x1
502d0: 370ffc63 tbnz w3, #1, 5025c <arm_gicv3_distif_pre_save+0x3c>
502d4: d0000082 adrp x2, 62000 <vprintf+0x400>
502d8: 52800581 mov w1, #0x2c // #44
502dc: 911cc842 add x2, x2, #0x732
502e0: 17ffffd8 b 50240 <arm_gicv3_distif_pre_save+0x20>
00000000000502e4 <arm_gicv3_distif_post_restore>:
502e4: a9bf7bfd stp x29, x30, [sp, #-16]!
502e8: f00000c1 adrp x1, 6b000 <psci_ns_context+0xc60>
502ec: 910003fd mov x29, sp
502f0: f9403021 ldr x1, [x1, #96]
502f4: b50000e1 cbnz x1, 50310 <arm_gicv3_distif_post_restore+0x2c>
502f8: d0000082 adrp x2, 62000 <vprintf+0x400>
502fc: 911a8042 add x2, x2, #0x6a0
50300: 52800981 mov w1, #0x4c // #76
50304: d0000080 adrp x0, 62000 <vprintf+0x400>
50308: 911ac800 add x0, x0, #0x6b2
5030c: 940045c8 bl 61a2c <__assert>
50310: f9401021 ldr x1, [x1, #32]
50314: b50000a1 cbnz x1, 50328 <arm_gicv3_distif_post_restore+0x44>
50318: d0000082 adrp x2, 62000 <vprintf+0x400>
5031c: 528009a1 mov w1, #0x4d // #77
50320: 911b6042 add x2, x2, #0x6d8
50324: 17fffff8 b 50304 <arm_gicv3_distif_post_restore+0x20>
50328: f8605820 ldr x0, [x1, w0, uxtw #3]
5032c: b50000a0 cbnz x0, 50340 <arm_gicv3_distif_post_restore+0x5c>
50330: d0000082 adrp x2, 62000 <vprintf+0x400>
50334: 52800aa1 mov w1, #0x55 // #85
50338: 911bf842 add x2, x2, #0x6fe
5033c: 17fffff2 b 50304 <arm_gicv3_distif_post_restore+0x20>
50340: b9401401 ldr w1, [x0, #20]
50344: 91005002 add x2, x0, #0x14
50348: 36000181 tbz w1, #0, 50378 <arm_gicv3_distif_post_restore+0x94>
5034c: b9401401 ldr w1, [x0, #20]
50350: 37f800a1 tbnz w1, #31, 50364 <arm_gicv3_distif_post_restore+0x80>
50354: d0000082 adrp x2, 62000 <vprintf+0x400>
50358: 52800cc1 mov w1, #0x66 // #102
5035c: 911d7042 add x2, x2, #0x75c
50360: 17ffffe9 b 50304 <arm_gicv3_distif_post_restore+0x20>
50364: b9401401 ldr w1, [x0, #20]
50368: 121f7821 and w1, w1, #0xfffffffe
5036c: b9001401 str w1, [x0, #20]
50370: b9400040 ldr w0, [x2]
50374: 37ffffe0 tbnz w0, #31, 50370 <arm_gicv3_distif_post_restore+0x8c>
50378: a8c17bfd ldp x29, x30, [sp], #16
5037c: d65f03c0 ret
0000000000050380 <gicv3_distif_pre_save>:
50380: 17ffffa8 b 50220 <arm_gicv3_distif_pre_save>
0000000000050384 <gicv3_distif_post_restore>:
50384: 17ffffd8 b 502e4 <arm_gicv3_distif_post_restore>
0000000000050388 <gicr_wait_for_pending_write>:
50388: b9400001 ldr w1, [x0]
5038c: 371fffe1 tbnz w1, #3, 50388 <gicr_wait_for_pending_write>
50390: d65f03c0 ret
0000000000050394 <gicv3_driver_init>:
50394: a9bd7bfd stp x29, x30, [sp, #-48]!
50398: 910003fd mov x29, sp
5039c: a90153f3 stp x19, x20, [sp, #16]
503a0: f90013f5 str x21, [sp, #32]
503a4: b50000e0 cbnz x0, 503c0 <gicv3_driver_init+0x2c>
503a8: d0000082 adrp x2, 62000 <vprintf+0x400>
503ac: 911e2c42 add x2, x2, #0x78b
503b0: 52800801 mov w1, #0x40 // #64
503b4: d0000080 adrp x0, 62000 <vprintf+0x400>
503b8: 911e9000 add x0, x0, #0x7a4
503bc: 9400459c bl 61a2c <__assert>
503c0: f9400002 ldr x2, [x0]
503c4: aa0003f3 mov x19, x0
503c8: b50000a2 cbnz x2, 503dc <gicv3_driver_init+0x48>
503cc: d0000082 adrp x2, 62000 <vprintf+0x400>
503d0: 52800821 mov w1, #0x41 // #65
503d4: 911f1042 add x2, x2, #0x7c4
503d8: 17fffff7 b 503b4 <gicv3_driver_init+0x20>
503dc: b9401c01 ldr w1, [x0, #28]
503e0: 350000a1 cbnz w1, 503f4 <gicv3_driver_init+0x60>
503e4: d0000082 adrp x2, 62000 <vprintf+0x400>
503e8: 52800841 mov w1, #0x42 // #66
503ec: 911f9842 add x2, x2, #0x7e6
503f0: 17fffff1 b 503b4 <gicv3_driver_init+0x20>
503f4: f9401000 ldr x0, [x0, #32]
503f8: b50000a0 cbnz x0, 5040c <gicv3_driver_init+0x78>
503fc: d0000082 adrp x2, 62000 <vprintf+0x400>
50400: 52800861 mov w1, #0x43 // #67
50404: 91202842 add x2, x2, #0x80a
50408: 17ffffeb b 503b4 <gicv3_driver_init+0x20>
5040c: d5384243 mrs x3, currentel
50410: d3420c63 ubfx x3, x3, #2, #2
50414: f1000c7f cmp x3, #0x3
50418: 540000a0 b.eq 5042c <gicv3_driver_init+0x98> // b.none
5041c: d0000082 adrp x2, 62000 <vprintf+0x400>
50420: 528008a1 mov w1, #0x45 // #69
50424: 9120dc42 add x2, x2, #0x837
50428: 17ffffe3 b 503b4 <gicv3_driver_init+0x20>
5042c: b9401a63 ldr w3, [x19, #24]
50430: 340000e3 cbz w3, 5044c <gicv3_driver_init+0xb8>
50434: f9400a63 ldr x3, [x19, #16]
50438: b50000a3 cbnz x3, 5044c <gicv3_driver_init+0xb8>
5043c: d0000082 adrp x2, 62000 <vprintf+0x400>
50440: 528008e1 mov w1, #0x47 // #71
50444: 91210c42 add x2, x2, #0x843
50448: 17ffffdb b 503b4 <gicv3_driver_init+0x20>
5044c: d5380403 mrs x3, id_aa64pfr0_el1
50450: f2680c7f tst x3, #0xf000000
50454: 540000a1 b.ne 50468 <gicv3_driver_init+0xd4> // b.any
50458: d0000082 adrp x2, 62000 <vprintf+0x400>
5045c: 528009e1 mov w1, #0x4f // #79
50460: 91228c42 add x2, x2, #0x8a3
50464: 17ffffd4 b 503b4 <gicv3_driver_init+0x20>
50468: d29ffd03 mov x3, #0xffe8 // #65512
5046c: b8636843 ldr w3, [x2, x3]
50470: d3441c63 ubfx x3, x3, #4, #4
50474: 71000c7f cmp w3, #0x3
50478: 540000a0 b.eq 5048c <gicv3_driver_init+0xf8> // b.none
5047c: d0000082 adrp x2, 62000 <vprintf+0x400>
50480: 52800ae1 mov w1, #0x57 // #87
50484: 9123d042 add x2, x2, #0x8f4
50488: 17ffffcb b 503b4 <gicv3_driver_init+0x20>
5048c: b9400054 ldr w20, [x2]
50490: f9400662 ldr x2, [x19, #8]
50494: d3441294 ubfx x20, x20, #4, #1
50498: b40000e2 cbz x2, 504b4 <gicv3_driver_init+0x120>
5049c: f9401663 ldr x3, [x19, #40]
504a0: 9400038f bl 512dc <gicv3_rdistif_base_addrs_probe>
504a4: f9401260 ldr x0, [x19, #32]
504a8: b9401e61 ldr w1, [x19, #28]
504ac: d37df021 lsl x1, x1, #3
504b0: 94004120 bl 60930 <flush_dcache_range>
504b4: f00000d5 adrp x21, 6b000 <psci_ns_context+0xc60>
504b8: d2800101 mov x1, #0x8 // #8
504bc: 910182a0 add x0, x21, #0x60
504c0: f90032b3 str x19, [x21, #96]
504c4: 9400411b bl 60930 <flush_dcache_range>
504c8: f94032a0 ldr x0, [x21, #96]
504cc: d2800601 mov x1, #0x30 // #48
504d0: 94004118 bl 60930 <flush_dcache_range>
504d4: 7100029f cmp w20, #0x0
504d8: d0000080 adrp x0, 62000 <vprintf+0x400>
504dc: a94153f3 ldp x19, x20, [sp, #16]
504e0: 911e1c00 add x0, x0, #0x787
504e4: f94013f5 ldr x21, [sp, #32]
504e8: f0000081 adrp x1, 63000 <CSWTCH.22+0x37e>
504ec: a8c37bfd ldp x29, x30, [sp], #48
504f0: 911f7821 add x1, x1, #0x7de
504f4: 9a800021 csel x1, x1, x0, eq // eq = none
504f8: d0000080 adrp x0, 62000 <vprintf+0x400>
504fc: 91244800 add x0, x0, #0x912
50500: 140038e1 b 5e884 <tf_log>
0000000000050504 <gicv3_distif_init>:
50504: a9be7bfd stp x29, x30, [sp, #-32]!
50508: 910003fd mov x29, sp
5050c: f9000bf3 str x19, [sp, #16]
50510: f00000d3 adrp x19, 6b000 <psci_ns_context+0xc60>
50514: f9403260 ldr x0, [x19, #96]
50518: b50000e0 cbnz x0, 50534 <gicv3_distif_init+0x30>
5051c: d0000082 adrp x2, 62000 <vprintf+0x400>
50520: 91257842 add x2, x2, #0x95e
50524: 52801261 mov w1, #0x93 // #147
50528: d0000080 adrp x0, 62000 <vprintf+0x400>
5052c: 911e9000 add x0, x0, #0x7a4
50530: 9400453f bl 61a2c <__assert>
50534: f9400000 ldr x0, [x0]
50538: b50000a0 cbnz x0, 5054c <gicv3_distif_init+0x48>
5053c: d0000082 adrp x2, 62000 <vprintf+0x400>
50540: 52801281 mov w1, #0x94 // #148
50544: 9125e042 add x2, x2, #0x978
50548: 17fffff8 b 50528 <gicv3_distif_init+0x24>
5054c: d5384241 mrs x1, currentel
50550: d3420c21 ubfx x1, x1, #2, #2
50554: f1000c3f cmp x1, #0x3
50558: 540000a0 b.eq 5056c <gicv3_distif_init+0x68> // b.none
5055c: d0000082 adrp x2, 62000 <vprintf+0x400>
50560: 528012c1 mov w1, #0x96 // #150
50564: 9120dc42 add x2, x2, #0x837
50568: 17fffff0 b 50528 <gicv3_distif_init+0x24>
5056c: b9400001 ldr w1, [x0]
50570: 121d7021 and w1, w1, #0xfffffff8
50574: b9000001 str w1, [x0]
50578: b9400001 ldr w1, [x0]
5057c: 37ffffe1 tbnz w1, #31, 50578 <gicv3_distif_init+0x74>
50580: b9400001 ldr w1, [x0]
50584: 321c0421 orr w1, w1, #0x30
50588: b9000001 str w1, [x0]
5058c: b9400001 ldr w1, [x0]
50590: 37ffffe1 tbnz w1, #31, 5058c <gicv3_distif_init+0x88>
50594: 94000374 bl 51364 <gicv3_spis_config_defaults>
50598: f9403260 ldr x0, [x19, #96]
5059c: b9401802 ldr w2, [x0, #24]
505a0: f9400801 ldr x1, [x0, #16]
505a4: f9400000 ldr x0, [x0]
505a8: 94000396 bl 51400 <gicv3_secure_spis_config_props>
505ac: f9403261 ldr x1, [x19, #96]
505b0: f9400021 ldr x1, [x1]
505b4: b9400022 ldr w2, [x1]
505b8: 2a020000 orr w0, w0, w2
505bc: b9000020 str w0, [x1]
505c0: b9400020 ldr w0, [x1]
505c4: 37ffffe0 tbnz w0, #31, 505c0 <gicv3_distif_init+0xbc>
505c8: f9400bf3 ldr x19, [sp, #16]
505cc: a8c27bfd ldp x29, x30, [sp], #32
505d0: d65f03c0 ret
00000000000505d4 <gicv3_rdistif_on>:
505d4: d65f03c0 ret
00000000000505d8 <gicv3_rdistif_init>:
505d8: a9bd7bfd stp x29, x30, [sp, #-48]!
505dc: 910003fd mov x29, sp
505e0: a90153f3 stp x19, x20, [sp, #16]
505e4: f00000d3 adrp x19, 6b000 <psci_ns_context+0xc60>
505e8: f9403261 ldr x1, [x19, #96]
505ec: f90013f5 str x21, [sp, #32]
505f0: b50000e1 cbnz x1, 5060c <gicv3_rdistif_init+0x34>
505f4: d0000082 adrp x2, 62000 <vprintf+0x400>
505f8: 91257842 add x2, x2, #0x95e
505fc: 528017c1 mov w1, #0xbe // #190
50600: d0000080 adrp x0, 62000 <vprintf+0x400>
50604: 911e9000 add x0, x0, #0x7a4
50608: 94004509 bl 61a2c <__assert>
5060c: b9401c22 ldr w2, [x1, #28]
50610: 2a0003f4 mov w20, w0
50614: 6b00005f cmp w2, w0
50618: 540000a8 b.hi 5062c <gicv3_rdistif_init+0x54> // b.pmore
5061c: d0000082 adrp x2, 62000 <vprintf+0x400>
50620: 528017e1 mov w1, #0xbf // #191
50624: 91266c42 add x2, x2, #0x99b
50628: 17fffff6 b 50600 <gicv3_rdistif_init+0x28>
5062c: f9401022 ldr x2, [x1, #32]
50630: b50000a2 cbnz x2, 50644 <gicv3_rdistif_init+0x6c>
50634: d0000082 adrp x2, 62000 <vprintf+0x400>
50638: 52801801 mov w1, #0xc0 // #192
5063c: 91271442 add x2, x2, #0x9c5
50640: 17fffff0 b 50600 <gicv3_rdistif_init+0x28>
50644: f9400021 ldr x1, [x1]
50648: b50000a1 cbnz x1, 5065c <gicv3_rdistif_init+0x84>
5064c: d0000082 adrp x2, 62000 <vprintf+0x400>
50650: 52801821 mov w1, #0xc1 // #193
50654: 9125e042 add x2, x2, #0x978
50658: 17ffffea b 50600 <gicv3_rdistif_init+0x28>
5065c: b9400035 ldr w21, [x1]
50660: 372000b5 tbnz w21, #4, 50674 <gicv3_rdistif_init+0x9c>
50664: d0000082 adrp x2, 62000 <vprintf+0x400>
50668: 52801881 mov w1, #0xc4 // #196
5066c: 9127cc42 add x2, x2, #0x9f3
50670: 17ffffe4 b 50600 <gicv3_rdistif_init+0x28>
50674: d5384241 mrs x1, currentel
50678: d3420c21 ubfx x1, x1, #2, #2
5067c: f1000c3f cmp x1, #0x3
50680: 540000a0 b.eq 50694 <gicv3_rdistif_init+0xbc> // b.none
50684: d0000082 adrp x2, 62000 <vprintf+0x400>
50688: 528018c1 mov w1, #0xc6 // #198
5068c: 9120dc42 add x2, x2, #0x837
50690: 17ffffdc b 50600 <gicv3_rdistif_init+0x28>
50694: 97ffffd0 bl 505d4 <gicv3_rdistif_on>
50698: f9403260 ldr x0, [x19, #96]
5069c: f9401000 ldr x0, [x0, #32]
506a0: f8745814 ldr x20, [x0, w20, uxtw #3]
506a4: b50000b4 cbnz x20, 506b8 <gicv3_rdistif_init+0xe0>
506a8: d0000082 adrp x2, 62000 <vprintf+0x400>
506ac: 52801981 mov w1, #0xcc // #204
506b0: 91284442 add x2, x2, #0xa11
506b4: 17ffffd3 b 50600 <gicv3_rdistif_init+0x28>
506b8: aa1403e0 mov x0, x20
506bc: 940003a0 bl 5153c <gicv3_ppi_sgi_config_defaults>
506c0: f9403260 ldr x0, [x19, #96]
506c4: b9401802 ldr w2, [x0, #24]
506c8: f9400801 ldr x1, [x0, #16]
506cc: aa1403e0 mov x0, x20
506d0: 940003b1 bl 51594 <gicv3_secure_ppi_sgi_config_props>
506d4: 6a35001f bics wzr, w0, w21
506d8: 54000100 b.eq 506f8 <gicv3_rdistif_init+0x120> // b.none
506dc: f9403261 ldr x1, [x19, #96]
506e0: f9400021 ldr x1, [x1]
506e4: b9400022 ldr w2, [x1]
506e8: 2a020000 orr w0, w0, w2
506ec: b9000020 str w0, [x1]
506f0: b9400020 ldr w0, [x1]
506f4: 37ffffe0 tbnz w0, #31, 506f0 <gicv3_rdistif_init+0x118>
506f8: a94153f3 ldp x19, x20, [sp, #16]
506fc: f94013f5 ldr x21, [sp, #32]
50700: a8c37bfd ldp x29, x30, [sp], #48
50704: d65f03c0 ret
0000000000050708 <gicv3_cpuif_enable>:
50708: a9bf7bfd stp x29, x30, [sp, #-16]!
5070c: f00000c1 adrp x1, 6b000 <psci_ns_context+0xc60>
50710: 910003fd mov x29, sp
50714: f9403021 ldr x1, [x1, #96]
50718: b50000e1 cbnz x1, 50734 <gicv3_cpuif_enable+0x2c>
5071c: d0000082 adrp x2, 62000 <vprintf+0x400>
50720: 91257842 add x2, x2, #0x95e
50724: 52801e21 mov w1, #0xf1 // #241
50728: d0000080 adrp x0, 62000 <vprintf+0x400>
5072c: 911e9000 add x0, x0, #0x7a4
50730: 940044bf bl 61a2c <__assert>
50734: b9401c22 ldr w2, [x1, #28]
50738: 6b00005f cmp w2, w0
5073c: 540000a8 b.hi 50750 <gicv3_cpuif_enable+0x48> // b.pmore
50740: d0000082 adrp x2, 62000 <vprintf+0x400>
50744: 52801e41 mov w1, #0xf2 // #242
50748: 91266c42 add x2, x2, #0x99b
5074c: 17fffff7 b 50728 <gicv3_cpuif_enable+0x20>
50750: f9401022 ldr x2, [x1, #32]
50754: b50000a2 cbnz x2, 50768 <gicv3_cpuif_enable+0x60>
50758: d0000082 adrp x2, 62000 <vprintf+0x400>
5075c: 52801e61 mov w1, #0xf3 // #243
50760: 91271442 add x2, x2, #0x9c5
50764: 17fffff1 b 50728 <gicv3_cpuif_enable+0x20>
50768: d5384241 mrs x1, currentel
5076c: d3420c21 ubfx x1, x1, #2, #2
50770: f1000c3f cmp x1, #0x3
50774: 540000a0 b.eq 50788 <gicv3_cpuif_enable+0x80> // b.none
50778: d0000082 adrp x2, 62000 <vprintf+0x400>
5077c: 52801e81 mov w1, #0xf4 // #244
50780: 9120dc42 add x2, x2, #0x837
50784: 17ffffe9 b 50728 <gicv3_cpuif_enable+0x20>
50788: f8605840 ldr x0, [x2, w0, uxtw #3]
5078c: 940002bc bl 5127c <gicv3_rdistif_mark_core_awake>
50790: d53ecca0 mrs x0, s3_6_c12_c12_5
50794: b2400c00 orr x0, x0, #0xf
50798: d51ecca0 msr s3_6_c12_c12_5, x0
5079c: d53e1100 mrs x0, scr_el3
507a0: b2400001 orr x1, x0, #0x1
507a4: d51e1101 msr scr_el3, x1
507a8: d5033fdf isb
507ac: d53cc9a1 mrs x1, s3_4_c12_c9_5
507b0: b2400c21 orr x1, x1, #0xf
507b4: d51cc9a1 msr s3_4_c12_c9_5, x1
507b8: d2800021 mov x1, #0x1 // #1
507bc: d518cca1 msr s3_0_c12_c12_5, x1
507c0: d5033fdf isb
507c4: 927f7800 and x0, x0, #0xfffffffe
507c8: d51e1100 msr scr_el3, x0
507cc: d5033fdf isb
507d0: d518cca1 msr s3_0_c12_c12_5, x1
507d4: d5033fdf isb
507d8: d2801fe0 mov x0, #0xff // #255
507dc: d5184600 msr s3_0_c4_c6_0, x0
507e0: d518ccc1 msr s3_0_c12_c12_6, x1
507e4: d53ecce0 mrs x0, s3_6_c12_c12_7
507e8: b27f0000 orr x0, x0, #0x2
507ec: d51ecce0 msr s3_6_c12_c12_7, x0
507f0: d5033fdf isb
507f4: a8c17bfd ldp x29, x30, [sp], #16
507f8: d65f03c0 ret
00000000000507fc <gicv3_cpuif_disable>:
507fc: a9bf7bfd stp x29, x30, [sp, #-16]!
50800: f00000c2 adrp x2, 6b000 <psci_ns_context+0xc60>
50804: 910003fd mov x29, sp
50808: f9403041 ldr x1, [x2, #96]
5080c: b50000e1 cbnz x1, 50828 <gicv3_cpuif_disable+0x2c>
50810: d0000082 adrp x2, 62000 <vprintf+0x400>
50814: 91257842 add x2, x2, #0x95e
50818: 528025c1 mov w1, #0x12e // #302
5081c: d0000080 adrp x0, 62000 <vprintf+0x400>
50820: 911e9000 add x0, x0, #0x7a4
50824: 94004482 bl 61a2c <__assert>
50828: b9401c23 ldr w3, [x1, #28]
5082c: 6b00007f cmp w3, w0
50830: 540000a8 b.hi 50844 <gicv3_cpuif_disable+0x48> // b.pmore
50834: d0000082 adrp x2, 62000 <vprintf+0x400>
50838: 528025e1 mov w1, #0x12f // #303
5083c: 91266c42 add x2, x2, #0x99b
50840: 17fffff7 b 5081c <gicv3_cpuif_disable+0x20>
50844: f9401021 ldr x1, [x1, #32]
50848: b50000a1 cbnz x1, 5085c <gicv3_cpuif_disable+0x60>
5084c: d0000082 adrp x2, 62000 <vprintf+0x400>
50850: 52802601 mov w1, #0x130 // #304
50854: 91271442 add x2, x2, #0x9c5
50858: 17fffff1 b 5081c <gicv3_cpuif_disable+0x20>
5085c: d5384241 mrs x1, currentel
50860: d3420c21 ubfx x1, x1, #2, #2
50864: f1000c3f cmp x1, #0x3
50868: 540000a0 b.eq 5087c <gicv3_cpuif_disable+0x80> // b.none
5086c: d0000082 adrp x2, 62000 <vprintf+0x400>
50870: 52802641 mov w1, #0x132 // #306
50874: 9120dc42 add x2, x2, #0x837
50878: 17ffffe9 b 5081c <gicv3_cpuif_disable+0x20>
5087c: d53ecca1 mrs x1, s3_6_c12_c12_5
50880: b27f0421 orr x1, x1, #0x6
50884: d51ecca1 msr s3_6_c12_c12_5, x1
50888: d538ccc1 mrs x1, s3_0_c12_c12_6
5088c: 927f7821 and x1, x1, #0xfffffffe
50890: d518ccc1 msr s3_0_c12_c12_6, x1
50894: d53ecce1 mrs x1, s3_6_c12_c12_7
50898: 927e7421 and x1, x1, #0xfffffffc
5089c: d51ecce1 msr s3_6_c12_c12_7, x1
508a0: d5033fdf isb
508a4: f9403041 ldr x1, [x2, #96]
508a8: f9401021 ldr x1, [x1, #32]
508ac: f8605820 ldr x0, [x1, w0, uxtw #3]
508b0: b50000a0 cbnz x0, 508c4 <gicv3_cpuif_disable+0xc8>
508b4: d0000082 adrp x2, 62000 <vprintf+0x400>
508b8: 528028c1 mov w1, #0x146 // #326
508bc: 91284442 add x2, x2, #0xa11
508c0: 17ffffd7 b 5081c <gicv3_cpuif_disable+0x20>
508c4: a8c17bfd ldp x29, x30, [sp], #16
508c8: 1400027e b 512c0 <gicv3_rdistif_mark_core_asleep>
00000000000508cc <gicv3_get_pending_interrupt_type>:
508cc: d5384240 mrs x0, currentel
508d0: d3420c00 ubfx x0, x0, #2, #2
508d4: f1000c1f cmp x0, #0x3
508d8: 54000120 b.eq 508fc <gicv3_get_pending_interrupt_type+0x30> // b.none
508dc: a9bf7bfd stp x29, x30, [sp, #-16]!
508e0: d0000082 adrp x2, 62000 <vprintf+0x400>
508e4: d0000080 adrp x0, 62000 <vprintf+0x400>
508e8: 910003fd mov x29, sp
508ec: 9120dc42 add x2, x2, #0x837
508f0: 911e9000 add x0, x0, #0x7a4
508f4: 52802d41 mov w1, #0x16a // #362
508f8: 9400444d bl 61a2c <__assert>
508fc: d538c840 mrs x0, s3_0_c12_c8_2
50900: 12005c00 and w0, w0, #0xffffff
50904: d65f03c0 ret
0000000000050908 <gicv3_rdistif_save>:
50908: a9bd7bfd stp x29, x30, [sp, #-48]!
5090c: 910003fd mov x29, sp
50910: a9025bf5 stp x21, x22, [sp, #32]
50914: 2a0003f5 mov w21, w0
50918: f00000c0 adrp x0, 6b000 <psci_ns_context+0xc60>
5091c: a90153f3 stp x19, x20, [sp, #16]
50920: f9403000 ldr x0, [x0, #96]
50924: b50000e0 cbnz x0, 50940 <gicv3_rdistif_save+0x38>
50928: d0000082 adrp x2, 62000 <vprintf+0x400>
5092c: 91257842 add x2, x2, #0x95e
50930: 52803e01 mov w1, #0x1f0 // #496
50934: d0000080 adrp x0, 62000 <vprintf+0x400>
50938: 911e9000 add x0, x0, #0x7a4
5093c: 9400443c bl 61a2c <__assert>
50940: aa0103f3 mov x19, x1
50944: b9401c01 ldr w1, [x0, #28]
50948: 6b15003f cmp w1, w21
5094c: 540000a8 b.hi 50960 <gicv3_rdistif_save+0x58> // b.pmore
50950: d0000082 adrp x2, 62000 <vprintf+0x400>
50954: 52803e21 mov w1, #0x1f1 // #497
50958: 91266c42 add x2, x2, #0x99b
5095c: 17fffff6 b 50934 <gicv3_rdistif_save+0x2c>
50960: f9401001 ldr x1, [x0, #32]
50964: b50000a1 cbnz x1, 50978 <gicv3_rdistif_save+0x70>
50968: d0000082 adrp x2, 62000 <vprintf+0x400>
5096c: 52803e41 mov w1, #0x1f2 // #498
50970: 91271442 add x2, x2, #0x9c5
50974: 17fffff0 b 50934 <gicv3_rdistif_save+0x2c>
50978: d5384240 mrs x0, currentel
5097c: d3420c00 ubfx x0, x0, #2, #2
50980: f1000c1f cmp x0, #0x3
50984: 540000a0 b.eq 50998 <gicv3_rdistif_save+0x90> // b.none
50988: d0000082 adrp x2, 62000 <vprintf+0x400>
5098c: 52803e61 mov w1, #0x1f3 // #499
50990: 9120dc42 add x2, x2, #0x837
50994: 17ffffe8 b 50934 <gicv3_rdistif_save+0x2c>
50998: b50000b3 cbnz x19, 509ac <gicv3_rdistif_save+0xa4>
5099c: d0000082 adrp x2, 62000 <vprintf+0x400>
509a0: 52803e81 mov w1, #0x1f4 // #500
509a4: 91288442 add x2, x2, #0xa21
509a8: 17ffffe3 b 50934 <gicv3_rdistif_save+0x2c>
509ac: f8755834 ldr x20, [x1, w21, uxtw #3]
509b0: 52800016 mov w22, #0x0 // #0
509b4: aa1403e0 mov x0, x20
509b8: 97fffe74 bl 50388 <gicr_wait_for_pending_write>
509bc: b9400280 ldr w0, [x20]
509c0: b9001260 str w0, [x19, #16]
509c4: f9403a80 ldr x0, [x20, #112]
509c8: f9000260 str x0, [x19]
509cc: f9403e80 ldr x0, [x20, #120]
509d0: f9000660 str x0, [x19, #8]
509d4: d2801000 mov x0, #0x80 // #128
509d8: f2a00020 movk x0, #0x1, lsl #16
509dc: b8606a80 ldr w0, [x20, x0]
509e0: b9001660 str w0, [x19, #20]
509e4: d2802000 mov x0, #0x100 // #256
509e8: f2a00020 movk x0, #0x1, lsl #16
509ec: b8606a80 ldr w0, [x20, x0]
509f0: b9001a60 str w0, [x19, #24]
509f4: d2804000 mov x0, #0x200 // #512
509f8: f2a00020 movk x0, #0x1, lsl #16
509fc: b8606a80 ldr w0, [x20, x0]
50a00: b9001e60 str w0, [x19, #28]
50a04: d2806000 mov x0, #0x300 // #768
50a08: f2a00020 movk x0, #0x1, lsl #16
50a0c: b8606a80 ldr w0, [x20, x0]
50a10: b9002260 str w0, [x19, #32]
50a14: d2818000 mov x0, #0xc00 // #3072
50a18: f2a00020 movk x0, #0x1, lsl #16
50a1c: b8606a80 ldr w0, [x20, x0]
50a20: b9004660 str w0, [x19, #68]
50a24: d2818080 mov x0, #0xc04 // #3076
50a28: f2a00020 movk x0, #0x1, lsl #16
50a2c: b8606a80 ldr w0, [x20, x0]
50a30: b9004a60 str w0, [x19, #72]
50a34: d281a000 mov x0, #0xd00 // #3328
50a38: f2a00020 movk x0, #0x1, lsl #16
50a3c: b8606a80 ldr w0, [x20, x0]
50a40: b9004e60 str w0, [x19, #76]
50a44: d281c000 mov x0, #0xe00 // #3584
50a48: f2a00020 movk x0, #0x1, lsl #16
50a4c: b8606a80 ldr w0, [x20, x0]
50a50: b9005260 str w0, [x19, #80]
50a54: 2a1603e1 mov w1, w22
50a58: aa1403e0 mov x0, x20
50a5c: 940001d4 bl 511ac <gicr_read_ipriorityr>
50a60: 927e76c1 and x1, x22, #0xfffffffc
50a64: 110012d6 add w22, w22, #0x4
50a68: 8b010261 add x1, x19, x1
50a6c: 710082df cmp w22, #0x20
50a70: b9002420 str w0, [x1, #36]
50a74: 54ffff01 b.ne 50a54 <gicv3_rdistif_save+0x14c> // b.any
50a78: 2a1503e0 mov w0, w21
50a7c: a94153f3 ldp x19, x20, [sp, #16]
50a80: a9425bf5 ldp x21, x22, [sp, #32]
50a84: a8c37bfd ldp x29, x30, [sp], #48
50a88: 17fffe3e b 50380 <gicv3_distif_pre_save>
0000000000050a8c <gicv3_rdistif_init_restore>:
50a8c: a9bd7bfd stp x29, x30, [sp, #-48]!
50a90: 910003fd mov x29, sp
50a94: a90153f3 stp x19, x20, [sp, #16]
50a98: aa0103f4 mov x20, x1
50a9c: f00000c1 adrp x1, 6b000 <psci_ns_context+0xc60>
50aa0: f90013f5 str x21, [sp, #32]
50aa4: f9403021 ldr x1, [x1, #96]
50aa8: b50000e1 cbnz x1, 50ac4 <gicv3_rdistif_init_restore+0x38>
50aac: d0000082 adrp x2, 62000 <vprintf+0x400>
50ab0: 91257842 add x2, x2, #0x95e
50ab4: 528044e1 mov w1, #0x227 // #551
50ab8: d0000080 adrp x0, 62000 <vprintf+0x400>
50abc: 911e9000 add x0, x0, #0x7a4
50ac0: 940043db bl 61a2c <__assert>
50ac4: b9401c22 ldr w2, [x1, #28]
50ac8: 2a0003f5 mov w21, w0
50acc: 6b00005f cmp w2, w0
50ad0: 540000a8 b.hi 50ae4 <gicv3_rdistif_init_restore+0x58> // b.pmore
50ad4: d0000082 adrp x2, 62000 <vprintf+0x400>
50ad8: 52804501 mov w1, #0x228 // #552
50adc: 91266c42 add x2, x2, #0x99b
50ae0: 17fffff6 b 50ab8 <gicv3_rdistif_init_restore+0x2c>
50ae4: f9401022 ldr x2, [x1, #32]
50ae8: b50000a2 cbnz x2, 50afc <gicv3_rdistif_init_restore+0x70>
50aec: d0000082 adrp x2, 62000 <vprintf+0x400>
50af0: 52804521 mov w1, #0x229 // #553
50af4: 91271442 add x2, x2, #0x9c5
50af8: 17fffff0 b 50ab8 <gicv3_rdistif_init_restore+0x2c>
50afc: d5384241 mrs x1, currentel
50b00: d3420c21 ubfx x1, x1, #2, #2
50b04: f1000c3f cmp x1, #0x3
50b08: 540000a0 b.eq 50b1c <gicv3_rdistif_init_restore+0x90> // b.none
50b0c: d0000082 adrp x2, 62000 <vprintf+0x400>
50b10: 52804541 mov w1, #0x22a // #554
50b14: 9120dc42 add x2, x2, #0x837
50b18: 17ffffe8 b 50ab8 <gicv3_rdistif_init_restore+0x2c>
50b1c: b50000b4 cbnz x20, 50b30 <gicv3_rdistif_init_restore+0xa4>
50b20: d0000082 adrp x2, 62000 <vprintf+0x400>
50b24: 52804561 mov w1, #0x22b // #555
50b28: 91288442 add x2, x2, #0xa21
50b2c: 17ffffe3 b 50ab8 <gicv3_rdistif_init_restore+0x2c>
50b30: f8755853 ldr x19, [x2, w21, uxtw #3]
50b34: 97fffea8 bl 505d4 <gicv3_rdistif_on>
50b38: 2a1503e0 mov w0, w21
50b3c: 97fffe12 bl 50384 <gicv3_distif_post_restore>
50b40: d2803000 mov x0, #0x180 // #384
50b44: 12800001 mov w1, #0xffffffff // #-1
50b48: f2a00020 movk x0, #0x1, lsl #16
50b4c: 52800015 mov w21, #0x0 // #0
50b50: b8206a61 str w1, [x19, x0]
50b54: aa1303e0 mov x0, x19
50b58: 97fffe0c bl 50388 <gicr_wait_for_pending_write>
50b5c: b9401280 ldr w0, [x20, #16]
50b60: 121f7800 and w0, w0, #0xfffffffe
50b64: b9000260 str w0, [x19]
50b68: f9400280 ldr x0, [x20]
50b6c: b9401681 ldr w1, [x20, #20]
50b70: f9003a60 str x0, [x19, #112]
50b74: f9400680 ldr x0, [x20, #8]
50b78: f9003e60 str x0, [x19, #120]
50b7c: d2801000 mov x0, #0x80 // #128
50b80: f2a00020 movk x0, #0x1, lsl #16
50b84: b8206a61 str w1, [x19, x0]
50b88: 927e76a0 and x0, x21, #0xfffffffc
50b8c: 2a1503e1 mov w1, w21
50b90: 8b000280 add x0, x20, x0
50b94: 110012b5 add w21, w21, #0x4
50b98: b9402402 ldr w2, [x0, #36]
50b9c: aa1303e0 mov x0, x19
50ba0: 94000188 bl 511c0 <gicr_write_ipriorityr>
50ba4: 710082bf cmp w21, #0x20
50ba8: 54ffff01 b.ne 50b88 <gicv3_rdistif_init_restore+0xfc> // b.any
50bac: d2818000 mov x0, #0xc00 // #3072
50bb0: b9404681 ldr w1, [x20, #68]
50bb4: f2a00020 movk x0, #0x1, lsl #16
50bb8: b8206a61 str w1, [x19, x0]
50bbc: 91001000 add x0, x0, #0x4
50bc0: b9404a81 ldr w1, [x20, #72]
50bc4: b8206a61 str w1, [x19, x0]
50bc8: 9103f000 add x0, x0, #0xfc
50bcc: b9404e81 ldr w1, [x20, #76]
50bd0: b8206a61 str w1, [x19, x0]
50bd4: 91040000 add x0, x0, #0x100
50bd8: b9405281 ldr w1, [x20, #80]
50bdc: b8206a61 str w1, [x19, x0]
50be0: d2804000 mov x0, #0x200 // #512
50be4: f2a00020 movk x0, #0x1, lsl #16
50be8: b9401e81 ldr w1, [x20, #28]
50bec: b8206a61 str w1, [x19, x0]
50bf0: 91040000 add x0, x0, #0x100
50bf4: b9402281 ldr w1, [x20, #32]
50bf8: b8206a61 str w1, [x19, x0]
50bfc: b9400260 ldr w0, [x19]
50c00: 37ffffe0 tbnz w0, #31, 50bfc <gicv3_rdistif_init_restore+0x170>
50c04: d2802000 mov x0, #0x100 // #256
50c08: b9401a81 ldr w1, [x20, #24]
50c0c: f2a00020 movk x0, #0x1, lsl #16
50c10: f94013f5 ldr x21, [sp, #32]
50c14: b8206a61 str w1, [x19, x0]
50c18: b9401280 ldr w0, [x20, #16]
50c1c: b9000260 str w0, [x19]
50c20: aa1303e0 mov x0, x19
50c24: a94153f3 ldp x19, x20, [sp, #16]
50c28: a8c37bfd ldp x29, x30, [sp], #48
50c2c: 17fffdd7 b 50388 <gicr_wait_for_pending_write>
0000000000050c30 <gicv3_distif_save>:
50c30: a9bd7bfd stp x29, x30, [sp, #-48]!
50c34: 910003fd mov x29, sp
50c38: a9025bf5 stp x21, x22, [sp, #32]
50c3c: aa0003f5 mov x21, x0
50c40: f00000c0 adrp x0, 6b000 <psci_ns_context+0xc60>
50c44: a90153f3 stp x19, x20, [sp, #16]
50c48: f9403000 ldr x0, [x0, #96]
50c4c: b50000e0 cbnz x0, 50c68 <gicv3_distif_save+0x38>
50c50: d0000082 adrp x2, 62000 <vprintf+0x400>
50c54: 91257842 add x2, x2, #0x95e
50c58: 52804f01 mov w1, #0x278 // #632
50c5c: d0000080 adrp x0, 62000 <vprintf+0x400>
50c60: 911e9000 add x0, x0, #0x7a4
50c64: 94004372 bl 61a2c <__assert>
50c68: f9400014 ldr x20, [x0]
50c6c: b50000b4 cbnz x20, 50c80 <gicv3_distif_save+0x50>
50c70: d0000082 adrp x2, 62000 <vprintf+0x400>
50c74: 52804f21 mov w1, #0x279 // #633
50c78: 9125e042 add x2, x2, #0x978
50c7c: 17fffff8 b 50c5c <gicv3_distif_save+0x2c>
50c80: d5384240 mrs x0, currentel
50c84: d3420c00 ubfx x0, x0, #2, #2
50c88: f1000c1f cmp x0, #0x3
50c8c: 540000a0 b.eq 50ca0 <gicv3_distif_save+0x70> // b.none
50c90: d0000082 adrp x2, 62000 <vprintf+0x400>
50c94: 52804f41 mov w1, #0x27a // #634
50c98: 9120dc42 add x2, x2, #0x837
50c9c: 17fffff0 b 50c5c <gicv3_distif_save+0x2c>
50ca0: b50000b5 cbnz x21, 50cb4 <gicv3_distif_save+0x84>
50ca4: d0000082 adrp x2, 62000 <vprintf+0x400>
50ca8: 52804f61 mov w1, #0x27b // #635
50cac: 91288842 add x2, x2, #0xa22
50cb0: 17ffffeb b 50c5c <gicv3_distif_save+0x2c>
50cb4: b9400693 ldr w19, [x20, #4]
50cb8: 52807f80 mov w0, #0x3fc // #1020
50cbc: 531b1273 ubfiz w19, w19, #5, #5
50cc0: 11008273 add w19, w19, #0x20
50cc4: 710ff27f cmp w19, #0x3fc
50cc8: 1a809273 csel w19, w19, w0, ls // ls = plast
50ccc: b9400280 ldr w0, [x20]
50cd0: 37ffffe0 tbnz w0, #31, 50ccc <gicv3_distif_save+0x9c>
50cd4: b9400280 ldr w0, [x20]
50cd8: 52800416 mov w22, #0x20 // #32
50cdc: b91ee2a0 str w0, [x21, #7904]
50ce0: 6b16027f cmp w19, w22
50ce4: 54000428 b.hi 50d68 <gicv3_distif_save+0x138> // b.pmore
50ce8: 52800416 mov w22, #0x20 // #32
50cec: 6b16027f cmp w19, w22
50cf0: 540004e8 b.hi 50d8c <gicv3_distif_save+0x15c> // b.pmore
50cf4: 52800416 mov w22, #0x20 // #32
50cf8: 6b16027f cmp w19, w22
50cfc: 540005a8 b.hi 50db0 <gicv3_distif_save+0x180> // b.pmore
50d00: 52800416 mov w22, #0x20 // #32
50d04: 6b16027f cmp w19, w22
50d08: 54000668 b.hi 50dd4 <gicv3_distif_save+0x1a4> // b.pmore
50d0c: 52800416 mov w22, #0x20 // #32
50d10: 6b16027f cmp w19, w22
50d14: 54000728 b.hi 50df8 <gicv3_distif_save+0x1c8> // b.pmore
50d18: 52800416 mov w22, #0x20 // #32
50d1c: 6b16027f cmp w19, w22
50d20: 540007e8 b.hi 50e1c <gicv3_distif_save+0x1ec> // b.pmore
50d24: 52800416 mov w22, #0x20 // #32
50d28: 6b16027f cmp w19, w22
50d2c: 540008a8 b.hi 50e40 <gicv3_distif_save+0x210> // b.pmore
50d30: 52800416 mov w22, #0x20 // #32
50d34: 6b16027f cmp w19, w22
50d38: 54000968 b.hi 50e64 <gicv3_distif_save+0x234> // b.pmore
50d3c: 92801fe0 mov x0, #0xffffffffffffff00 // #-256
50d40: d28c2001 mov x1, #0x6100 // #24832
50d44: 8b010294 add x20, x20, x1
50d48: 8b334c13 add x19, x0, w19, uxtw #3
50d4c: d2800000 mov x0, #0x0 // #0
50d50: eb00027f cmp x19, x0
50d54: 540009a1 b.ne 50e88 <gicv3_distif_save+0x258> // b.any
50d58: a94153f3 ldp x19, x20, [sp, #16]
50d5c: a9425bf5 ldp x21, x22, [sp, #32]
50d60: a8c37bfd ldp x29, x30, [sp], #48
50d64: d65f03c0 ret
50d68: 2a1603e1 mov w1, w22
50d6c: aa1403e0 mov x0, x20
50d70: 97fffcc4 bl 50080 <gicd_read_igroupr>
50d74: 510082c1 sub w1, w22, #0x20
50d78: 110082d6 add w22, w22, #0x20
50d7c: 53057c21 lsr w1, w1, #5
50d80: 8b010aa1 add x1, x21, x1, lsl #2
50d84: b91ee420 str w0, [x1, #7908]
50d88: 17ffffd6 b 50ce0 <gicv3_distif_save+0xb0>
50d8c: 2a1603e1 mov w1, w22
50d90: aa1403e0 mov x0, x20
50d94: 97fffcc0 bl 50094 <gicd_read_isenabler>
50d98: 510082c1 sub w1, w22, #0x20
50d9c: 110082d6 add w22, w22, #0x20
50da0: 53057c21 lsr w1, w1, #5
50da4: 911f6021 add x1, x1, #0x7d8
50da8: b8217aa0 str w0, [x21, x1, lsl #2]
50dac: 17ffffd0 b 50cec <gicv3_distif_save+0xbc>
50db0: 2a1603e1 mov w1, w22
50db4: aa1403e0 mov x0, x20
50db8: 97fffcbc bl 500a8 <gicd_read_ispendr>
50dbc: 510082c1 sub w1, w22, #0x20
50dc0: 110082d6 add w22, w22, #0x20
50dc4: 53057c21 lsr w1, w1, #5
50dc8: 8b010aa1 add x1, x21, x1, lsl #2
50dcc: b91fdc20 str w0, [x1, #8156]
50dd0: 17ffffca b 50cf8 <gicv3_distif_save+0xc8>
50dd4: 2a1603e1 mov w1, w22
50dd8: aa1403e0 mov x0, x20
50ddc: 97fffcb8 bl 500bc <gicd_read_isactiver>
50de0: 510082c1 sub w1, w22, #0x20
50de4: 110082d6 add w22, w22, #0x20
50de8: 53057c21 lsr w1, w1, #5
50dec: 8b010aa1 add x1, x21, x1, lsl #2
50df0: b9205820 str w0, [x1, #8280]
50df4: 17ffffc4 b 50d04 <gicv3_distif_save+0xd4>
50df8: 2a1603e1 mov w1, w22
50dfc: aa1403e0 mov x0, x20
50e00: 97fffcb4 bl 500d0 <gicd_read_ipriorityr>
50e04: 510082c1 sub w1, w22, #0x20
50e08: 110012d6 add w22, w22, #0x4
50e0c: 927e7421 and x1, x1, #0xfffffffc
50e10: 8b0102a1 add x1, x21, x1
50e14: b920d420 str w0, [x1, #8404]
50e18: 17ffffbe b 50d10 <gicv3_distif_save+0xe0>
50e1c: 2a1603e1 mov w1, w22
50e20: aa1403e0 mov x0, x20
50e24: 97fffcaf bl 500e0 <gicd_read_icfgr>
50e28: 510082c1 sub w1, w22, #0x20
50e2c: 110042d6 add w22, w22, #0x10
50e30: 53047c21 lsr w1, w1, #4
50e34: 9124b021 add x1, x1, #0x92c
50e38: b8217aa0 str w0, [x21, x1, lsl #2]
50e3c: 17ffffb8 b 50d1c <gicv3_distif_save+0xec>
50e40: 2a1603e1 mov w1, w22
50e44: aa1403e0 mov x0, x20
50e48: 940000b7 bl 51124 <gicd_read_igrpmodr>
50e4c: 510082c1 sub w1, w22, #0x20
50e50: 110082d6 add w22, w22, #0x20
50e54: 53057c21 lsr w1, w1, #5
50e58: 8b010aa1 add x1, x21, x1, lsl #2
50e5c: b925a820 str w0, [x1, #9640]
50e60: 17ffffb2 b 50d28 <gicv3_distif_save+0xf8>
50e64: 2a1603e1 mov w1, w22
50e68: aa1403e0 mov x0, x20
50e6c: 97fffca2 bl 500f4 <gicd_read_nsacr>
50e70: 510082c1 sub w1, w22, #0x20
50e74: 110042d6 add w22, w22, #0x10
50e78: 53047c21 lsr w1, w1, #4
50e7c: 8b010aa1 add x1, x21, x1, lsl #2
50e80: b9262420 str w0, [x1, #9764]
50e84: 17ffffac b 50d34 <gicv3_distif_save+0x104>
50e88: f8606a81 ldr x1, [x20, x0]
50e8c: f8206aa1 str x1, [x21, x0]
50e90: 91002000 add x0, x0, #0x8
50e94: 17ffffaf b 50d50 <gicv3_distif_save+0x120>
0000000000050e98 <gicv3_distif_init_restore>:
50e98: a9bd7bfd stp x29, x30, [sp, #-48]!
50e9c: 910003fd mov x29, sp
50ea0: a9025bf5 stp x21, x22, [sp, #32]
50ea4: aa0003f5 mov x21, x0
50ea8: f00000c0 adrp x0, 6b000 <psci_ns_context+0xc60>
50eac: a90153f3 stp x19, x20, [sp, #16]
50eb0: f9403000 ldr x0, [x0, #96]
50eb4: b50000e0 cbnz x0, 50ed0 <gicv3_distif_init_restore+0x38>
50eb8: d0000082 adrp x2, 62000 <vprintf+0x400>
50ebc: 91257842 add x2, x2, #0x95e
50ec0: 52805741 mov w1, #0x2ba // #698
50ec4: d0000080 adrp x0, 62000 <vprintf+0x400>
50ec8: 911e9000 add x0, x0, #0x7a4
50ecc: 940042d8 bl 61a2c <__assert>
50ed0: f9400013 ldr x19, [x0]
50ed4: b50000b3 cbnz x19, 50ee8 <gicv3_distif_init_restore+0x50>
50ed8: d0000082 adrp x2, 62000 <vprintf+0x400>
50edc: 52805761 mov w1, #0x2bb // #699
50ee0: 9125e042 add x2, x2, #0x978
50ee4: 17fffff8 b 50ec4 <gicv3_distif_init_restore+0x2c>
50ee8: d5384240 mrs x0, currentel
50eec: d3420c00 ubfx x0, x0, #2, #2
50ef0: f1000c1f cmp x0, #0x3
50ef4: 540000a0 b.eq 50f08 <gicv3_distif_init_restore+0x70> // b.none
50ef8: d0000082 adrp x2, 62000 <vprintf+0x400>
50efc: 52805781 mov w1, #0x2bc // #700
50f00: 9120dc42 add x2, x2, #0x837
50f04: 17fffff0 b 50ec4 <gicv3_distif_init_restore+0x2c>
50f08: b50000b5 cbnz x21, 50f1c <gicv3_distif_init_restore+0x84>
50f0c: d0000082 adrp x2, 62000 <vprintf+0x400>
50f10: 528057a1 mov w1, #0x2bd // #701
50f14: 91288842 add x2, x2, #0xa22
50f18: 17ffffeb b 50ec4 <gicv3_distif_init_restore+0x2c>
50f1c: b9400260 ldr w0, [x19]
50f20: 121d7000 and w0, w0, #0xfffffff8
50f24: b9000260 str w0, [x19]
50f28: b9400260 ldr w0, [x19]
50f2c: 37ffffe0 tbnz w0, #31, 50f28 <gicv3_distif_init_restore+0x90>
50f30: b9400260 ldr w0, [x19]
50f34: 321c0400 orr w0, w0, #0x30
50f38: b9000260 str w0, [x19]
50f3c: b9400260 ldr w0, [x19]
50f40: 37ffffe0 tbnz w0, #31, 50f3c <gicv3_distif_init_restore+0xa4>
50f44: b9400674 ldr w20, [x19, #4]
50f48: 52807f80 mov w0, #0x3fc // #1020
50f4c: 52800416 mov w22, #0x20 // #32
50f50: 531b1294 ubfiz w20, w20, #5, #5
50f54: 11008294 add w20, w20, #0x20
50f58: 710ff29f cmp w20, #0x3fc
50f5c: 1a809294 csel w20, w20, w0, ls // ls = plast
50f60: 6b16029f cmp w20, w22
50f64: 54000488 b.hi 50ff4 <gicv3_distif_init_restore+0x15c> // b.pmore
50f68: 52800416 mov w22, #0x20 // #32
50f6c: 6b16029f cmp w20, w22
50f70: 54000548 b.hi 51018 <gicv3_distif_init_restore+0x180> // b.pmore
50f74: 52800416 mov w22, #0x20 // #32
50f78: 6b16029f cmp w20, w22
50f7c: 54000608 b.hi 5103c <gicv3_distif_init_restore+0x1a4> // b.pmore
50f80: 52800416 mov w22, #0x20 // #32
50f84: 6b16029f cmp w20, w22
50f88: 540006c8 b.hi 51060 <gicv3_distif_init_restore+0x1c8> // b.pmore
50f8c: 52800416 mov w22, #0x20 // #32
50f90: 6b16029f cmp w20, w22
50f94: 54000788 b.hi 51084 <gicv3_distif_init_restore+0x1ec> // b.pmore
50f98: d28c2000 mov x0, #0x6100 // #24832
50f9c: 8b000261 add x1, x19, x0
50fa0: d2800000 mov x0, #0x0 // #0
50fa4: 11008002 add w2, w0, #0x20
50fa8: 6b02029f cmp w20, w2
50fac: 540007e8 b.hi 510a8 <gicv3_distif_init_restore+0x210> // b.pmore
50fb0: 52800416 mov w22, #0x20 // #32
50fb4: 6b16029f cmp w20, w22
50fb8: 54000808 b.hi 510b8 <gicv3_distif_init_restore+0x220> // b.pmore
50fbc: 52800416 mov w22, #0x20 // #32
50fc0: 6b16029f cmp w20, w22
50fc4: 540008c8 b.hi 510dc <gicv3_distif_init_restore+0x244> // b.pmore
50fc8: 52800416 mov w22, #0x20 // #32
50fcc: 6b16029f cmp w20, w22
50fd0: 54000988 b.hi 51100 <gicv3_distif_init_restore+0x268> // b.pmore
50fd4: b95ee2a0 ldr w0, [x21, #7904]
50fd8: b9000260 str w0, [x19]
50fdc: b9400260 ldr w0, [x19]
50fe0: 37ffffe0 tbnz w0, #31, 50fdc <gicv3_distif_init_restore+0x144>
50fe4: a94153f3 ldp x19, x20, [sp, #16]
50fe8: a9425bf5 ldp x21, x22, [sp, #32]
50fec: a8c37bfd ldp x29, x30, [sp], #48
50ff0: d65f03c0 ret
50ff4: 510082c0 sub w0, w22, #0x20
50ff8: 2a1603e1 mov w1, w22
50ffc: 110082d6 add w22, w22, #0x20
51000: 53057c00 lsr w0, w0, #5
51004: 8b000aa0 add x0, x21, x0, lsl #2
51008: b95ee402 ldr w2, [x0, #7908]
5100c: aa1303e0 mov x0, x19
51010: 97fffc3e bl 50108 <gicd_write_igroupr>
51014: 17ffffd3 b 50f60 <gicv3_distif_init_restore+0xc8>
51018: 510082c0 sub w0, w22, #0x20
5101c: 2a1603e1 mov w1, w22
51020: 927e7400 and x0, x0, #0xfffffffc
51024: 110012d6 add w22, w22, #0x4
51028: 8b0002a0 add x0, x21, x0
5102c: b960d402 ldr w2, [x0, #8404]
51030: aa1303e0 mov x0, x19
51034: 97fffc49 bl 50158 <gicd_write_ipriorityr>
51038: 17ffffcd b 50f6c <gicv3_distif_init_restore+0xd4>
5103c: 510082c0 sub w0, w22, #0x20
51040: 2a1603e1 mov w1, w22
51044: 110042d6 add w22, w22, #0x10
51048: 53047c00 lsr w0, w0, #4
5104c: 9124b000 add x0, x0, #0x92c
51050: b8607aa2 ldr w2, [x21, x0, lsl #2]
51054: aa1303e0 mov x0, x19
51058: 97fffc44 bl 50168 <gicd_write_icfgr>
5105c: 17ffffc7 b 50f78 <gicv3_distif_init_restore+0xe0>
51060: 510082c0 sub w0, w22, #0x20
51064: 2a1603e1 mov w1, w22
51068: 110082d6 add w22, w22, #0x20
5106c: 53057c00 lsr w0, w0, #5
51070: 8b000aa0 add x0, x21, x0, lsl #2
51074: b965a802 ldr w2, [x0, #9640]
51078: aa1303e0 mov x0, x19
5107c: 9400002f bl 51138 <gicd_write_igrpmodr>
51080: 17ffffc1 b 50f84 <gicv3_distif_init_restore+0xec>
51084: 510082c0 sub w0, w22, #0x20
51088: 2a1603e1 mov w1, w22
5108c: 110042d6 add w22, w22, #0x10
51090: 53047c00 lsr w0, w0, #4
51094: 8b000aa0 add x0, x21, x0, lsl #2
51098: b9662402 ldr w2, [x0, #9764]
5109c: aa1303e0 mov x0, x19
510a0: 97fffc37 bl 5017c <gicd_write_nsacr>
510a4: 17ffffbb b 50f90 <gicv3_distif_init_restore+0xf8>
510a8: f8607aa2 ldr x2, [x21, x0, lsl #3]
510ac: 91000400 add x0, x0, #0x1
510b0: f8008422 str x2, [x1], #8
510b4: 17ffffbc b 50fa4 <gicv3_distif_init_restore+0x10c>
510b8: 510082c0 sub w0, w22, #0x20
510bc: 2a1603e1 mov w1, w22
510c0: 110082d6 add w22, w22, #0x20
510c4: 53057c00 lsr w0, w0, #5
510c8: 911f6000 add x0, x0, #0x7d8
510cc: b8607aa2 ldr w2, [x21, x0, lsl #2]
510d0: aa1303e0 mov x0, x19
510d4: 97fffc12 bl 5011c <gicd_write_isenabler>
510d8: 17ffffb7 b 50fb4 <gicv3_distif_init_restore+0x11c>
510dc: 510082c0 sub w0, w22, #0x20
510e0: 2a1603e1 mov w1, w22
510e4: 110082d6 add w22, w22, #0x20
510e8: 53057c00 lsr w0, w0, #5
510ec: 8b000aa0 add x0, x21, x0, lsl #2
510f0: b95fdc02 ldr w2, [x0, #8156]
510f4: aa1303e0 mov x0, x19
510f8: 97fffc0e bl 50130 <gicd_write_ispendr>
510fc: 17ffffb1 b 50fc0 <gicv3_distif_init_restore+0x128>
51100: 510082c0 sub w0, w22, #0x20
51104: 2a1603e1 mov w1, w22
51108: 110082d6 add w22, w22, #0x20
5110c: 53057c00 lsr w0, w0, #5
51110: 8b000aa0 add x0, x21, x0, lsl #2
51114: b9605802 ldr w2, [x0, #8280]
51118: aa1303e0 mov x0, x19
5111c: 97fffc0a bl 50144 <gicd_write_isactiver>
51120: 17ffffab b 50fcc <gicv3_distif_init_restore+0x134>
0000000000051124 <gicd_read_igrpmodr>:
51124: 53057c21 lsr w1, w1, #5
51128: 91340000 add x0, x0, #0xd00
5112c: d37e6821 ubfiz x1, x1, #2, #27
51130: b8606820 ldr w0, [x1, x0]
51134: d65f03c0 ret
0000000000051138 <gicd_write_igrpmodr>:
51138: 53057c21 lsr w1, w1, #5
5113c: 91340000 add x0, x0, #0xd00
51140: d37e6821 ubfiz x1, x1, #2, #27
51144: b8206822 str w2, [x1, x0]
51148: d65f03c0 ret
000000000005114c <gicd_set_igrpmodr>:
5114c: 2a0103e3 mov w3, w1
51150: aa0003e4 mov x4, x0
51154: a9bf7bfd stp x29, x30, [sp, #-16]!
51158: 910003fd mov x29, sp
5115c: 97fffff2 bl 51124 <gicd_read_igrpmodr>
51160: a8c17bfd ldp x29, x30, [sp], #16
51164: 52800021 mov w1, #0x1 // #1
51168: 1ac32021 lsl w1, w1, w3
5116c: 2a000022 orr w2, w1, w0
51170: 2a0303e1 mov w1, w3
51174: aa0403e0 mov x0, x4
51178: 17fffff0 b 51138 <gicd_write_igrpmodr>
000000000005117c <gicd_clr_igrpmodr>:
5117c: 2a0103e3 mov w3, w1
51180: aa0003e4 mov x4, x0
51184: a9bf7bfd stp x29, x30, [sp, #-16]!
51188: 910003fd mov x29, sp
5118c: 97ffffe6 bl 51124 <gicd_read_igrpmodr>
51190: a8c17bfd ldp x29, x30, [sp], #16
51194: 52800021 mov w1, #0x1 // #1
51198: 1ac32021 lsl w1, w1, w3
5119c: 0a210002 bic w2, w0, w1
511a0: 2a0303e1 mov w1, w3
511a4: aa0403e0 mov x0, x4
511a8: 17ffffe4 b 51138 <gicd_write_igrpmodr>
00000000000511ac <gicr_read_ipriorityr>:
511ac: 91404000 add x0, x0, #0x10, lsl #12
511b0: 927e7421 and x1, x1, #0xfffffffc
511b4: 91100000 add x0, x0, #0x400
511b8: b8606820 ldr w0, [x1, x0]
511bc: d65f03c0 ret
00000000000511c0 <gicr_write_ipriorityr>:
511c0: 91404000 add x0, x0, #0x10, lsl #12
511c4: 927e7421 and x1, x1, #0xfffffffc
511c8: 91100000 add x0, x0, #0x400
511cc: b8206822 str w2, [x1, x0]
511d0: d65f03c0 ret
00000000000511d4 <gicr_clr_igroupr0>:
511d4: d2801003 mov x3, #0x80 // #128
511d8: 52800022 mov w2, #0x1 // #1
511dc: f2a00023 movk x3, #0x1, lsl #16
511e0: 1ac12042 lsl w2, w2, w1
511e4: b8636804 ldr w4, [x0, x3]
511e8: 0a220082 bic w2, w4, w2
511ec: b8236802 str w2, [x0, x3]
511f0: d65f03c0 ret
00000000000511f4 <gicr_set_igrpmodr0>:
511f4: d281a003 mov x3, #0xd00 // #3328
511f8: 52800022 mov w2, #0x1 // #1
511fc: f2a00023 movk x3, #0x1, lsl #16
51200: 1ac12042 lsl w2, w2, w1
51204: b8636804 ldr w4, [x0, x3]
51208: 2a040042 orr w2, w2, w4
5120c: b8236802 str w2, [x0, x3]
51210: d65f03c0 ret
0000000000051214 <gicr_clr_igrpmodr0>:
51214: d281a003 mov x3, #0xd00 // #3328
51218: 52800022 mov w2, #0x1 // #1
5121c: f2a00023 movk x3, #0x1, lsl #16
51220: 1ac12042 lsl w2, w2, w1
51224: b8636804 ldr w4, [x0, x3]
51228: 0a220082 bic w2, w4, w2
5122c: b8236802 str w2, [x0, x3]
51230: d65f03c0 ret
0000000000051234 <gicr_set_isenabler0>:
51234: 52800022 mov w2, #0x1 // #1
51238: 1ac12042 lsl w2, w2, w1
5123c: d2802001 mov x1, #0x100 // #256
51240: f2a00021 movk x1, #0x1, lsl #16
51244: b8216802 str w2, [x0, x1]
51248: d65f03c0 ret
000000000005124c <gicr_set_icfgr1>:
5124c: d2818084 mov x4, #0xc04 // #3076
51250: 531f0c21 ubfiz w1, w1, #1, #4
51254: f2a00024 movk x4, #0x1, lsl #16
51258: 12000442 and w2, w2, #0x3
5125c: 52800063 mov w3, #0x3 // #3
51260: b8646805 ldr w5, [x0, x4]
51264: 1ac12063 lsl w3, w3, w1
51268: 1ac12042 lsl w2, w2, w1
5126c: 0a2300a3 bic w3, w5, w3
51270: 2a030042 orr w2, w2, w3
51274: b8246802 str w2, [x0, x4]
51278: d65f03c0 ret
000000000005127c <gicv3_rdistif_mark_core_awake>:
5127c: b9401401 ldr w1, [x0, #20]
51280: 37100121 tbnz w1, #2, 512a4 <gicv3_rdistif_mark_core_awake+0x28>
51284: a9bf7bfd stp x29, x30, [sp, #-16]!
51288: b0000082 adrp x2, 62000 <vprintf+0x400>
5128c: b0000080 adrp x0, 62000 <vprintf+0x400>
51290: 910003fd mov x29, sp
51294: 9128cc42 add x2, x2, #0xa33
51298: 91299400 add x0, x0, #0xa65
5129c: 528023a1 mov w1, #0x11d // #285
512a0: 940041e3 bl 61a2c <__assert>
512a4: b9401401 ldr w1, [x0, #20]
512a8: 91005002 add x2, x0, #0x14
512ac: 121e7821 and w1, w1, #0xfffffffd
512b0: b9001401 str w1, [x0, #20]
512b4: b9400040 ldr w0, [x2]
512b8: 3717ffe0 tbnz w0, #2, 512b4 <gicv3_rdistif_mark_core_awake+0x38>
512bc: d65f03c0 ret
00000000000512c0 <gicv3_rdistif_mark_core_asleep>:
512c0: b9401401 ldr w1, [x0, #20]
512c4: 91005002 add x2, x0, #0x14
512c8: 321f0021 orr w1, w1, #0x2
512cc: b9001401 str w1, [x0, #20]
512d0: b9400040 ldr w0, [x2]
512d4: 3617ffe0 tbz w0, #2, 512d0 <gicv3_rdistif_mark_core_asleep+0x10>
512d8: d65f03c0 ret
00000000000512dc <gicv3_rdistif_base_addrs_probe>:
512dc: a9bc7bfd stp x29, x30, [sp, #-64]!
512e0: 910003fd mov x29, sp
512e4: a90153f3 stp x19, x20, [sp, #16]
512e8: a9025bf5 stp x21, x22, [sp, #32]
512ec: f9001bf7 str x23, [sp, #48]
512f0: b50000e0 cbnz x0, 5130c <gicv3_rdistif_base_addrs_probe+0x30>
512f4: b0000082 adrp x2, 62000 <vprintf+0x400>
512f8: b0000080 adrp x0, 62000 <vprintf+0x400>
512fc: 91276042 add x2, x2, #0x9d8
51300: 91299400 add x0, x0, #0xa65
51304: 528028c1 mov w1, #0x146 // #326
51308: 940041c9 bl 61a2c <__assert>
5130c: aa0003f5 mov x21, x0
51310: 2a0103f7 mov w23, w1
51314: aa0203f3 mov x19, x2
51318: aa0303f6 mov x22, x3
5131c: f9400674 ldr x20, [x19, #8]
51320: b40001f6 cbz x22, 5135c <gicv3_rdistif_base_addrs_probe+0x80>
51324: d360de81 ubfx x1, x20, #32, #24
51328: d378fe80 lsr x0, x20, #56
5132c: aa008020 orr x0, x1, x0, lsl #32
51330: d63f02c0 blr x22
51334: 6b17001f cmp w0, w23
51338: 54000042 b.cs 51340 <gicv3_rdistif_base_addrs_probe+0x64> // b.hs, b.nlast
5133c: f8205ab3 str x19, [x21, w0, uxtw #3]
51340: 91408273 add x19, x19, #0x20, lsl #12
51344: 3627fed4 tbz w20, #4, 5131c <gicv3_rdistif_base_addrs_probe+0x40>
51348: a94153f3 ldp x19, x20, [sp, #16]
5134c: a9425bf5 ldp x21, x22, [sp, #32]
51350: f9401bf7 ldr x23, [sp, #48]
51354: a8c47bfd ldp x29, x30, [sp], #64
51358: d65f03c0 ret
5135c: 53085e80 ubfx w0, w20, #8, #16
51360: 17fffff5 b 51334 <gicv3_rdistif_base_addrs_probe+0x58>
0000000000051364 <gicv3_spis_config_defaults>:
51364: a9bd7bfd stp x29, x30, [sp, #-48]!
51368: 910003fd mov x29, sp
5136c: a90153f3 stp x19, x20, [sp, #16]
51370: aa0003f4 mov x20, x0
51374: b9400413 ldr w19, [x0, #4]
51378: f90013f5 str x21, [sp, #32]
5137c: 52800415 mov w21, #0x20 // #32
51380: 531b1273 ubfiz w19, w19, #5, #5
51384: 11008273 add w19, w19, #0x20
51388: 6b1302bf cmp w21, w19
5138c: 54000163 b.cc 513b8 <gicv3_spis_config_defaults+0x54> // b.lo, b.ul, b.last
51390: 52800415 mov w21, #0x20 // #32
51394: 6b1302bf cmp w21, w19
51398: 540001c3 b.cc 513d0 <gicv3_spis_config_defaults+0x6c> // b.lo, b.ul, b.last
5139c: 52800415 mov w21, #0x20 // #32
513a0: 6b1302bf cmp w21, w19
513a4: 54000223 b.cc 513e8 <gicv3_spis_config_defaults+0x84> // b.lo, b.ul, b.last
513a8: a94153f3 ldp x19, x20, [sp, #16]
513ac: f94013f5 ldr x21, [sp, #32]
513b0: a8c37bfd ldp x29, x30, [sp], #48
513b4: d65f03c0 ret
513b8: 2a1503e1 mov w1, w21
513bc: aa1403e0 mov x0, x20
513c0: 12800002 mov w2, #0xffffffff // #-1
513c4: 110082b5 add w21, w21, #0x20
513c8: 97fffb50 bl 50108 <gicd_write_igroupr>
513cc: 17ffffef b 51388 <gicv3_spis_config_defaults+0x24>
513d0: 2a1503e1 mov w1, w21
513d4: aa1403e0 mov x0, x20
513d8: 3201c3e2 mov w2, #0x80808080 // #-2139062144
513dc: 110012b5 add w21, w21, #0x4
513e0: 97fffb5e bl 50158 <gicd_write_ipriorityr>
513e4: 17ffffec b 51394 <gicv3_spis_config_defaults+0x30>
513e8: 2a1503e1 mov w1, w21
513ec: aa1403e0 mov x0, x20
513f0: 52800002 mov w2, #0x0 // #0
513f4: 110042b5 add w21, w21, #0x10
513f8: 97fffb5c bl 50168 <gicd_write_icfgr>
513fc: 17ffffe9 b 513a0 <gicv3_spis_config_defaults+0x3c>
0000000000051400 <gicv3_secure_spis_config_props>:
51400: a9bc7bfd stp x29, x30, [sp, #-64]!
51404: 910003fd mov x29, sp
51408: a90153f3 stp x19, x20, [sp, #16]
5140c: 2a0203f4 mov w20, w2
51410: a9025bf5 stp x21, x22, [sp, #32]
51414: f9001bf7 str x23, [sp, #48]
51418: 34000122 cbz w2, 5143c <gicv3_secure_spis_config_props+0x3c>
5141c: aa0103f3 mov x19, x1
51420: b40001a1 cbz x1, 51454 <gicv3_secure_spis_config_props+0x54>
51424: aa0003f5 mov x21, x0
51428: 8b224836 add x22, x1, w2, uxtw #2
5142c: 91401817 add x23, x0, #0x6, lsl #12
51430: 52800014 mov w20, #0x0 // #0
51434: eb1302df cmp x22, x19
51438: 540001a1 b.ne 5146c <gicv3_secure_spis_config_props+0x6c> // b.any
5143c: 2a1403e0 mov w0, w20
51440: a94153f3 ldp x19, x20, [sp, #16]
51444: a9425bf5 ldp x21, x22, [sp, #32]
51448: f9401bf7 ldr x23, [sp, #48]
5144c: a8c47bfd ldp x29, x30, [sp], #64
51450: d65f03c0 ret
51454: b0000082 adrp x2, 62000 <vprintf+0x400>
51458: 912a2042 add x2, x2, #0xa88
5145c: 528031c1 mov w1, #0x18e // #398
51460: b0000080 adrp x0, 62000 <vprintf+0x400>
51464: 91299400 add x0, x0, #0xa65
51468: 94004171 bl 61a2c <__assert>
5146c: 79400261 ldrh w1, [x19]
51470: 12002421 and w1, w1, #0x3ff
51474: 71007c3f cmp w1, #0x1f
51478: 540005e9 b.ls 51534 <gicv3_secure_spis_config_props+0x134> // b.plast
5147c: aa1503e0 mov x0, x21
51480: 97fffb44 bl 50190 <gicd_clr_igroupr>
51484: 39400a60 ldrb w0, [x19, #2]
51488: 121e0402 and w2, w0, #0xc
5148c: 361800a0 tbz w0, #3, 514a0 <gicv3_secure_spis_config_props+0xa0>
51490: b0000082 adrp x2, 62000 <vprintf+0x400>
51494: 52803341 mov w1, #0x19a // #410
51498: 912a8042 add x2, x2, #0xaa0
5149c: 17fffff1 b 51460 <gicv3_secure_spis_config_props+0x60>
514a0: 79400261 ldrh w1, [x19]
514a4: aa1503e0 mov x0, x21
514a8: 12002421 and w1, w1, #0x3ff
514ac: 35000362 cbnz w2, 51518 <gicv3_secure_spis_config_props+0x118>
514b0: 321e0294 orr w20, w20, #0x4
514b4: 97ffff26 bl 5114c <gicd_set_igrpmodr>
514b8: 39400a62 ldrb w2, [x19, #2]
514bc: aa1503e0 mov x0, x21
514c0: 79400261 ldrh w1, [x19]
514c4: d3441442 ubfx x2, x2, #4, #2
514c8: 12002421 and w1, w1, #0x3ff
514cc: 97fffb45 bl 501e0 <gicd_set_icfgr>
514d0: b9400262 ldr w2, [x19]
514d4: aa1503e0 mov x0, x21
514d8: 79400261 ldrh w1, [x19]
514dc: d34a4442 ubfx x2, x2, #10, #8
514e0: 12002421 and w1, w1, #0x3ff
514e4: 97fffb3a bl 501cc <gicd_set_ipriorityr>
514e8: d53800a0 mrs x0, mpidr_el1
514ec: 79400261 ldrh w1, [x19]
514f0: 92405c00 and x0, x0, #0xffffff
514f4: 12002421 and w1, w1, #0x3ff
514f8: 71007c3f cmp w1, #0x1f
514fc: 54000148 b.hi 51524 <gicv3_secure_spis_config_props+0x124> // b.pmore
51500: b0000082 adrp x2, 62000 <vprintf+0x400>
51504: b0000080 adrp x0, 62000 <vprintf+0x400>
51508: 912bd042 add x2, x2, #0xaf4
5150c: 912c1400 add x0, x0, #0xb05
51510: 528011e1 mov w1, #0x8f // #143
51514: 17ffffd5 b 51468 <gicv3_secure_spis_config_props+0x68>
51518: 32000294 orr w20, w20, #0x1
5151c: 97ffff18 bl 5117c <gicd_clr_igrpmodr>
51520: 17ffffe6 b 514b8 <gicv3_secure_spis_config_props+0xb8>
51524: d37d2422 ubfiz x2, x1, #3, #10
51528: f8376840 str x0, [x2, x23]
5152c: aa1503e0 mov x0, x21
51530: 97fffb24 bl 501c0 <gicd_set_isenabler>
51534: 91001273 add x19, x19, #0x4
51538: 17ffffbf b 51434 <gicv3_secure_spis_config_props+0x34>
000000000005153c <gicv3_ppi_sgi_config_defaults>:
5153c: d2803001 mov x1, #0x180 // #384
51540: 12800002 mov w2, #0xffffffff // #-1
51544: f2a00021 movk x1, #0x1, lsl #16
51548: b8216802 str w2, [x0, x1]
5154c: b9400001 ldr w1, [x0]
51550: 371fffe1 tbnz w1, #3, 5154c <gicv3_ppi_sgi_config_defaults+0x10>
51554: d2801001 mov x1, #0x80 // #128
51558: 12800002 mov w2, #0xffffffff // #-1
5155c: f2a00021 movk x1, #0x1, lsl #16
51560: 3201c3e3 mov w3, #0x80808080 // #-2139062144
51564: b8216802 str w2, [x0, x1]
51568: 91404001 add x1, x0, #0x10, lsl #12
5156c: 91404002 add x2, x0, #0x10, lsl #12
51570: 91100021 add x1, x1, #0x400
51574: 91108042 add x2, x2, #0x420
51578: b8004423 str w3, [x1], #4
5157c: eb02003f cmp x1, x2
51580: 54ffffc1 b.ne 51578 <gicv3_ppi_sgi_config_defaults+0x3c> // b.any
51584: d2818081 mov x1, #0xc04 // #3076
51588: f2a00021 movk x1, #0x1, lsl #16
5158c: b821681f str wzr, [x0, x1]
51590: d65f03c0 ret
0000000000051594 <gicv3_secure_ppi_sgi_config_props>:
51594: 340007a2 cbz w2, 51688 <gicv3_secure_ppi_sgi_config_props+0xf4>
51598: a9bf7bfd stp x29, x30, [sp, #-16]!
5159c: aa0103e6 mov x6, x1
515a0: 910003fd mov x29, sp
515a4: b4000141 cbz x1, 515cc <gicv3_secure_ppi_sgi_config_props+0x38>
515a8: 91404009 add x9, x0, #0x10, lsl #12
515ac: 8b224828 add x8, x1, w2, uxtw #2
515b0: 91100129 add x9, x9, #0x400
515b4: 52800007 mov w7, #0x0 // #0
515b8: eb06011f cmp x8, x6
515bc: 54000141 b.ne 515e4 <gicv3_secure_ppi_sgi_config_props+0x50> // b.any
515c0: 2a0703e0 mov w0, w7
515c4: a8c17bfd ldp x29, x30, [sp], #16
515c8: d65f03c0 ret
515cc: b0000082 adrp x2, 62000 <vprintf+0x400>
515d0: b0000080 adrp x0, 62000 <vprintf+0x400>
515d4: 912a2042 add x2, x2, #0xa88
515d8: 91299400 add x0, x0, #0xa65
515dc: 52803c41 mov w1, #0x1e2 // #482
515e0: 94004113 bl 61a2c <__assert>
515e4: 794000c1 ldrh w1, [x6]
515e8: 12002421 and w1, w1, #0x3ff
515ec: 71007c3f cmp w1, #0x1f
515f0: 54000428 b.hi 51674 <gicv3_secure_ppi_sgi_config_props+0xe0> // b.pmore
515f4: 97fffef8 bl 511d4 <gicr_clr_igroupr0>
515f8: 394008c1 ldrb w1, [x6, #2]
515fc: 121e0422 and w2, w1, #0xc
51600: 361800e1 tbz w1, #3, 5161c <gicv3_secure_ppi_sgi_config_props+0x88>
51604: b0000082 adrp x2, 62000 <vprintf+0x400>
51608: b0000080 adrp x0, 62000 <vprintf+0x400>
5160c: 912a8042 add x2, x2, #0xaa0
51610: 91299400 add x0, x0, #0xa65
51614: 52803dc1 mov w1, #0x1ee // #494
51618: 94004105 bl 61a2c <__assert>
5161c: 794000c1 ldrh w1, [x6]
51620: 12002421 and w1, w1, #0x3ff
51624: 350002c2 cbnz w2, 5167c <gicv3_secure_ppi_sgi_config_props+0xe8>
51628: 97fffef3 bl 511f4 <gicr_set_igrpmodr0>
5162c: 321e00e7 orr w7, w7, #0x4
51630: 794000c1 ldrh w1, [x6]
51634: b94000c2 ldr w2, [x6]
51638: 92402421 and x1, x1, #0x3ff
5163c: d34a4442 ubfx x2, x2, #10, #8
51640: 38296822 strb w2, [x1, x9]
51644: 794000c1 ldrh w1, [x6]
51648: 12002421 and w1, w1, #0x3ff
5164c: 110fc022 add w2, w1, #0x3f0
51650: 12002442 and w2, w2, #0x3ff
51654: 71003c5f cmp w2, #0xf
51658: 54000088 b.hi 51668 <gicv3_secure_ppi_sgi_config_props+0xd4> // b.pmore
5165c: 394008c2 ldrb w2, [x6, #2]
51660: d3441442 ubfx x2, x2, #4, #2
51664: 97fffefa bl 5124c <gicr_set_icfgr1>
51668: 794000c1 ldrh w1, [x6]
5166c: 12002421 and w1, w1, #0x3ff
51670: 97fffef1 bl 51234 <gicr_set_isenabler0>
51674: 910010c6 add x6, x6, #0x4
51678: 17ffffd0 b 515b8 <gicv3_secure_ppi_sgi_config_props+0x24>
5167c: 97fffee6 bl 51214 <gicr_clr_igrpmodr0>
51680: 320000e7 orr w7, w7, #0x1
51684: 17ffffeb b 51630 <gicv3_secure_ppi_sgi_config_props+0x9c>
51688: 2a0203e0 mov w0, w2
5168c: d65f03c0 ret
0000000000051690 <plat_ic_get_pending_interrupt_type>:
51690: a9bf7bfd stp x29, x30, [sp, #-16]!
51694: 910003fd mov x29, sp
51698: d5384240 mrs x0, currentel
5169c: d3420c00 ubfx x0, x0, #2, #2
516a0: f1000c1f cmp x0, #0x3
516a4: 540000e0 b.eq 516c0 <plat_ic_get_pending_interrupt_type+0x30> // b.none
516a8: b0000082 adrp x2, 62000 <vprintf+0x400>
516ac: b0000080 adrp x0, 62000 <vprintf+0x400>
516b0: 9120dc42 add x2, x2, #0x837
516b4: 912ca000 add x0, x0, #0xb28
516b8: 52800a21 mov w1, #0x51 // #81
516bc: 940040dc bl 61a2c <__assert>
516c0: 97fffc83 bl 508cc <gicv3_get_pending_interrupt_type>
516c4: 510ff000 sub w0, w0, #0x3fc
516c8: 71000c1f cmp w0, #0x3
516cc: 540000c8 b.hi 516e4 <plat_ic_get_pending_interrupt_type+0x54> // b.pmore
516d0: b0000081 adrp x1, 62000 <vprintf+0x400>