init.s

.set SCTRL_M,		(1 << 0)	/* MMU enable */
.set SCTRL_A,		(1 << 1)	/* Strict alignment enable */
.set SCTRL_C,		(1 << 2)	/* Data cache enable */
.set SCTRL_Z,		(1 << 11)	/* Program flow prediction enable */
.set SCTRL_I,		(1 << 12)	/* Instruction cache enable */
.set SCTRL_V,		(1 << 13)	/* Vectors bit */

.section ".text.vectors", "x"
.globl _vectors
_vectors:
	b	reset 		/* Reset */
	b	.		/* Undefined instruction */
	b	.		/* SWI */
	b	.		/* Prefetch abort */
	b	.		/* Data abort */
	b	.		/* Reserved */
	b	.		/* IRQ */
	b	.		/* FIQ */

.section ".text.init", "x"
.align 5
.globl reset
reset:
	/* When called by the A10 bootrom the following registers are
	 * defined (A10 HPS TRM A--44):
	 *
	 * r0: Contains the pointer to the shared memory block,
	       which is used to pass information from the boot ROM code to
	       the second-stage boot loader. The shared memory block is
	       located in the top 4 KB of on-chip RAM.
	 * r1: Contains the length of the shared memory.
	 * r2: Unused and set to 0x0.
	 * r3: Points to the version block.
	 */

	mov	r0, #0
	/* Clear CP15 ACTRL (A9 TRM 4.2.12) */
	mcr	p15, 0, r0, c1, c0, 1
	/* Clear CP15 CPACR (A9 TRM 4.3.13 ) */
	mcr	p15, 0, r0, c1, c0, 2

	mrs	r0, cpsr
	/* Select Mode bits */
	and	r1, r0, #0x1f
	/* Test if in hypervisor (HYP) mode */
	teq	r1, #0x1a
	/* If not hypervisor, switch to supervisor (SVC) mode */
	bicne	r0, r0, #0x1f
	orrne	r0, r0, #0x13

	/* Disable FIQ/IRQ */
	orr	r0, r0, #0xc0
	msr	cpsr, r0

	mov	r0, #0
	/* Invalidate all TLBs (TLBIALL, A9 TRM 4.2.21) */
	mcr	p15, 0, r0, c8, c7, 0
	/* Invalidate icache to the point of unification
	 * (ICIALLU, A9 TRM 4.2.20) */
	mcr	p15, 0, r0, c7, c5, 0
	/* Invalidate Branch Prediction (BPIALL, A9 TRM 4.2.20) */
	mcr	p15, 0, r0, c7, c5, 6

	/* Data sync barrier. A9 TRM says that this is "optional and deprecated"
	 * since we have equivalents in the instruction set. That being
	 * said U-Boot still uses these CP15 instructions so I'm going
	 * to err on the side of caution and do the same thing. */
	mcr	p15, 0, r0, c7, c10, 4
	/* Instruction sync barrier. Same remark as above. */
	mcr	p15, 0, r0, c7, c5, 4

	/* Load SCTRL (A9 TRM 4.2.11) */
	mrc	p15, 0, r0, c1, c0, 0

	/* Clear V to set reset vectors at VBAR. */
	bic	r0, r0, #(SCTRL_V)
	/* Clear C to disable data caching.
	 * Clear M to disable MMU */
	bic 	r0, r0, #(SCTRL_C | SCTRL_M)
	/* Enable strict alignment checks */
	orr	r0, r0, #(SCTRL_A)
	/* Enable program flow prediction */
	orr	r0, r0, #(SCTRL_Z)
	/* Enable Icache */
	orr	r0, r0, #(SCTRL_I)

	/* Store SCTRL */
	mcr	p15, 0, r0, c1, c0, 0

	/* Set vector base address to redirect vector base address to our
	 * code (VBAR, A9 TRM 4.2.26) */
	ldr	r0, =_vectors
	mcr	p15, 0, r0, c12, c0, 0

	/* Clear BSS (assume that it's word-aligned) */
	ldr	r1, =_bss_start
	ldr	r2, =_bss_end
	mov	r0, #0
1:
	cmp	r1, r2
	strlo	r0, [r1]
	addlo	r1, r1, #4
	blo	1b

	/* Stack setup */
	ldr	sp, =_stack_base
	/* ARM ABI constraint: stack must be 8-byte aligned */
	bic	sp, sp, #7

	/* We can run C now. */
	bl	main

	/* Shouldn't be reached */
	b	reset