Created
May 18, 2016 23:49
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** Timing model | |
Those are all very approximate timings, they can vary by a significant | |
amount between calls. | |
| Step | Duration (CPU cycles) | | |
|------------------------------------------+-----------------------| | |
| Command register write -> param transfer | [9400; 1540][fn:1] | | |
| Param transfer (if any) | 1800 * n | | |
| Command execution | 2000 | | |
| RX FIFO clear | 2000 | | |
| Push response | 1500 * n[fn:2] | | |
| Delay until the busy flag goes low | 3300 | | |
| Delay until the IRQ triggers | 2000 | | |
[fn:1] The delay between the command register write and execution is | |
extremely variable (even more so when a disc is spinning in the | |
drive), it can be much shorter or much, much slower | |
[fn:2]The ~RX_EMPTY flag is set at the end of the first "push response". |
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