uart_rx_32.v

`timescale 1ns / 1ps

module uart_rx_32(clock, reset, RxD, RxData);
    input clock, reset;
    input RxD;
    //output [7:0] RxData;
   output [31:0] RxData;
	 
	 //reg [10:0]RxRegister;
	 reg [34:0]RxRegister;
	 
	 //reg [3:0]bitCounter, sampleCounter;
	 reg [5:0] bitCounter, sampleCounter;
	 reg [1:0] state, nextState;
	 reg shift, clear_bC, inc_bC, clear_sC, inc_sC;
	 reg [12:0] counter;
	 parameter IDLE = 0;
	 parameter STARTING = 1;
	 parameter RECEIVING = 2;
	 
	 //assign RxData = RxRegister[8:1];
	 assign RxData = RxRegister[32:1];
	 
	 //Sequential Logic
	 always @ (posedge clock)
	 begin
		if (reset) begin
			state <= IDLE;
			bitCounter<=0;
			sampleCounter<=0;
			end
		else begin
		//counter <= counter +1;
		//if (counter >= 5208/4) begin
			state<=nextState;
			//if (shift) RxRegister <= {RxD,RxRegister[10:1]};
			if (shift) RxRegister <= {RxD,RxRegister[32:1]};
			if (clear_sC) sampleCounter <= 0;
			else if (inc_sC) sampleCounter <= sampleCounter +1;
			if (clear_bC) bitCounter <= 0;
			else if (inc_bC) bitCounter <= bitCounter +1;
			counter <=0;
		//end
			
			end
	end

	//Combinational Logic
	always @ (state or RxD or bitCounter or sampleCounter) 
	begin
		shift = 0; clear_sC = 0; inc_sC = 0; clear_bC = 0; inc_bC =0;
		
		case(state)
			IDLE: begin
					if(RxD == 0)nextState = STARTING;
					else nextState = IDLE;
					end
			
			STARTING: begin
						 if (RxD) nextState = IDLE;
						 else begin
							if (sampleCounter != 0) begin
								nextState = STARTING;
								clear_sC = 1;
								end
							else begin
								nextState = RECEIVING;
								inc_sC = 1;
								end
							end
						end
			RECEIVING:	begin
							if (sampleCounter < 3) begin
								inc_sC = 1; 
								nextState = RECEIVING;
								end
							//else if (bitCounter < 10) begin
							else if (bitCounter < 34) begin
								clear_sC = 1;
								inc_bC = 1;
								shift = 1;
								nextState = RECEIVING;
								end
							else begin
								nextState = IDLE;
								clear_sC = 1;
								clear_bC = 1;
								end
							end
			default:		nextState = IDLE;
		endcase
	end
endmodule