uart_tx_32.v

uart_tx_32.v

`timescale 1ns / 1ps

module uart_tx_32(clock, reset, TxData, transmit, TxD, state, nextState);
parameter IDLE = 0;
parameter TRANSMITTING=1;
   input clock;
    input reset;
    //input [7:0] TxData;
    input [31:0] TxData;
    input transmit;
    output TxD; reg TxD;
    output state; reg state;
    output nextState; reg nextState;
	 reg load, shift, clear;
	 //reg [3:0]bitCounter;
	 reg [5:0] bitCounter;
	 reg [13:0]counter;
	 //reg [10:0]rightShiftRegister;
	 reg [34:0]rightShiftRegister; //1 bit start, 1bit xor parity, 32bit data, 1bit stop
	 
	 //Sequential Logic
	 always @ (posedge clock) begin
		if (reset) begin
			state <= IDLE;
			counter <= 0;
		end
		else begin
//			counter <= counter +1;
//			if (counter >=5207) begin 
				counter <= 0;
				state <= nextState;
				if (load) rightShiftRegister <= {1'b1,^TxData,TxData,1'b0};
				else if (shift) rightShiftRegister <= rightShiftRegister>>1;
				if (clear) bitCounter <=0;	
				else if (shift) bitCounter <= bitCounter+1;
//				end
		end
	end
	 //Combinational Logic
	 always @ (transmit or state or bitCounter) begin
	 load =0; shift =0; clear =0;
		case (state)
			IDLE: begin
					TxD = 1;
					if (transmit)begin
						clear = 1;
						nextState = TRANSMITTING;
						load = 1;
						end
					else
						nextState = IDLE;
			
					end
			TRANSMITTING: begin
						
								TxD = rightShiftRegister[0];
								if (bitCounter >= 34) begin
									nextState = IDLE;
									clear = 1;	
								end
								else begin
									nextState = TRANSMITTING;
									shift = 1;

								end
							end
		endcase
	end
									
endmodule