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Ryzen 3900X coreinfo
Raw
01_basic.md

Machine Info

Ryzen 9 3900X, C8H

qemu --version

QEMU emulator version 4.2.0
Copyright (c) 2003-2019 Fabrice Bellard and the QEMU Project developers

/etc/os-release

NAME="void"
ID="void"
DISTRIB_ID="void"
PRETTY_NAME="void"

lscpu -e

CPU NODE SOCKET CORE L1d:L1i:L2:L3 ONLINE    MAXMHZ    MINMHZ
  0    0      0    0 0:0:0:0          yes 3800.0000 2200.0000
  1    0      0    1 1:1:1:0          yes 3800.0000 2200.0000
  2    0      0    2 2:2:2:0          yes 3800.0000 2200.0000
  3    0      0    3 3:3:3:1          yes 3800.0000 2200.0000
  4    0      0    4 4:4:4:1          yes 3800.0000 2200.0000
  5    0      0    5 5:5:5:1          yes 3800.0000 2200.0000
  6    0      0    6 6:6:6:2          yes 3800.0000 2200.0000
  7    0      0    7 7:7:7:2          yes 3800.0000 2200.0000
  8    0      0    8 8:8:8:2          yes 3800.0000 2200.0000
  9    0      0    9 9:9:9:3          yes 3800.0000 2200.0000
 10    0      0   10 10:10:10:3       yes 3800.0000 2200.0000
 11    0      0   11 11:11:11:3       yes 3800.0000 2200.0000
 12    0      0    0 0:0:0:0          yes 3800.0000 2200.0000
 13    0      0    1 1:1:1:0          yes 3800.0000 2200.0000
 14    0      0    2 2:2:2:0          yes 3800.0000 2200.0000
 15    0      0    3 3:3:3:1          yes 3800.0000 2200.0000
 16    0      0    4 4:4:4:1          yes 3800.0000 2200.0000
 17    0      0    5 5:5:5:1          yes 3800.0000 2200.0000
 18    0      0    6 6:6:6:2          yes 3800.0000 2200.0000
 19    0      0    7 7:7:7:2          yes 3800.0000 2200.0000
 20    0      0    8 8:8:8:2          yes 3800.0000 2200.0000
 21    0      0    9 9:9:9:3          yes 3800.0000 2200.0000
 22    0      0   10 10:10:10:3       yes 3800.0000 2200.0000
 23    0      0   11 11:11:11:3       yes 3800.0000 2200.0000
Raw
02_epyc-ibpb.md

EPYC

libvirt

  <cputune>
    <vcpupin vcpu="0" cpuset="3"/>
    <vcpupin vcpu="1" cpuset="15"/>
    <vcpupin vcpu="2" cpuset="4"/>
    <vcpupin vcpu="3" cpuset="16"/>
    <vcpupin vcpu="4" cpuset="5"/>
    <vcpupin vcpu="5" cpuset="17"/>
    <!-- ... -->
  </cputune>
  <cpu mode="custom" match="exact" check="partial">
    <model fallback="forbid">EPYC-IBPB</model>
    <topology sockets="1" cores="6" threads="1"/>
  </cpu>

coreinfo

Logical to Physical Processor Map:
*-----  Physical Processor 0
-*----  Physical Processor 1
--*---  Physical Processor 2
---*--  Physical Processor 3
----*-  Physical Processor 4
-----*  Physical Processor 5

Logical Processor to Socket Map:
******  Socket 0

Logical Processor to NUMA Node Map:
******  NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
*-----  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
*-----  Instruction Cache   0, Level 1,   64 KB, Assoc   4, LineSize  64
*-----  Unified Cache       0, Level 2,  512 KB, Assoc   8, LineSize  64
****--  Unified Cache       1, Level 3,    8 MB, Assoc  16, LineSize  64
-*----  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
-*----  Instruction Cache   1, Level 1,   64 KB, Assoc   4, LineSize  64
-*----  Unified Cache       2, Level 2,  512 KB, Assoc   8, LineSize  64
--*---  Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
--*---  Instruction Cache   2, Level 1,   64 KB, Assoc   4, LineSize  64
--*---  Unified Cache       3, Level 2,  512 KB, Assoc   8, LineSize  64
---*--  Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
---*--  Instruction Cache   3, Level 1,   64 KB, Assoc   4, LineSize  64
---*--  Unified Cache       4, Level 2,  512 KB, Assoc   8, LineSize  64
----*-  Data Cache          4, Level 1,   32 KB, Assoc   8, LineSize  64
----*-  Instruction Cache   4, Level 1,   64 KB, Assoc   4, LineSize  64
----*-  Unified Cache       5, Level 2,  512 KB, Assoc   8, LineSize  64
----**  Unified Cache       6, Level 3,    8 MB, Assoc  16, LineSize  64
-----*  Data Cache          5, Level 1,   32 KB, Assoc   8, LineSize  64
-----*  Instruction Cache   5, Level 1,   64 KB, Assoc   4, LineSize  64
-----*  Unified Cache       7, Level 2,  512 KB, Assoc   8, LineSize  64

Logical Processor to Group Map:
******  Group 0
Raw
02_host-passthrough.md

host-passthrough

libvirt

  <cputune>
    <vcpupin vcpu="0" cpuset="3"/>
    <vcpupin vcpu="1" cpuset="15"/>
    <vcpupin vcpu="2" cpuset="4"/>
    <vcpupin vcpu="3" cpuset="16"/>
    <vcpupin vcpu="4" cpuset="5"/>
    <vcpupin vcpu="5" cpuset="17"/>
    <!-- ... -->
  </cputune>
  <cpu mode="host-passthrough" check="none">
    <topology sockets="1" cores="3" threads="2"/>
    <cache mode="passthrough"/>
    <feature policy="require" name="topoext"/>
  </cpu>

coreinfo

Logical to Physical Processor Map:
*-----  Physical Processor 0
-*----  Physical Processor 1
--*---  Physical Processor 2
---*--  Physical Processor 3
----*-  Physical Processor 4
-----*  Physical Processor 5

Logical Processor to Socket Map:
******  Socket 0

Logical Processor to NUMA Node Map:
******  NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
*-----  Data Cache          0, Level 1,   64 KB, Assoc   2, LineSize  64
*-----  Instruction Cache   0, Level 1,   64 KB, Assoc   2, LineSize  64
*-----  Unified Cache       0, Level 2,  512 KB, Assoc  16, LineSize  64
*-----  Unified Cache       1, Level 3,   16 MB, Assoc  16, LineSize  64
-*----  Data Cache          1, Level 1,   64 KB, Assoc   2, LineSize  64
-*----  Instruction Cache   1, Level 1,   64 KB, Assoc   2, LineSize  64
-*----  Unified Cache       2, Level 2,  512 KB, Assoc  16, LineSize  64
-*----  Unified Cache       3, Level 3,   16 MB, Assoc  16, LineSize  64
--*---  Data Cache          2, Level 1,   64 KB, Assoc   2, LineSize  64
--*---  Instruction Cache   2, Level 1,   64 KB, Assoc   2, LineSize  64
--*---  Unified Cache       4, Level 2,  512 KB, Assoc  16, LineSize  64
--*---  Unified Cache       5, Level 3,   16 MB, Assoc  16, LineSize  64
---*--  Data Cache          3, Level 1,   64 KB, Assoc   2, LineSize  64
---*--  Instruction Cache   3, Level 1,   64 KB, Assoc   2, LineSize  64
---*--  Unified Cache       6, Level 2,  512 KB, Assoc  16, LineSize  64
---*--  Unified Cache       7, Level 3,   16 MB, Assoc  16, LineSize  64
----*-  Data Cache          4, Level 1,   64 KB, Assoc   2, LineSize  64
----*-  Instruction Cache   4, Level 1,   64 KB, Assoc   2, LineSize  64
----*-  Unified Cache       8, Level 2,  512 KB, Assoc  16, LineSize  64
----*-  Unified Cache       9, Level 3,   16 MB, Assoc  16, LineSize  64
-----*  Data Cache          5, Level 1,   64 KB, Assoc   2, LineSize  64
-----*  Instruction Cache   5, Level 1,   64 KB, Assoc   2, LineSize  64
-----*  Unified Cache      10, Level 2,  512 KB, Assoc  16, LineSize  64
-----*  Unified Cache      11, Level 3,   16 MB, Assoc  16, LineSize  64

Logical Processor to Group Map:
******  Group 0
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