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sirop/RerunAll_Xilinx_MESA

Created October 11, 2015 10:27
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RerunAll_Xilinx_MESA5i25 Output
Raw
RerunAll_Xilinx_MESA
Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "C:/Users/Boris/Desktop/CameraMotion/MESA/5i25/configs/hostmot2/source/hostmot2/TopPCIHostMot2.xst" -ofn "C:/Users/Boris/Desktop/CameraMotion/MESA/5i25/configs/hostmot2/source/hostmot2/TopPCIHostMot2.syr"
Reading design: TopPCIHostMot2.prj
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\log2.vhd" into library work
Parsing package <log2>.
Parsing package body <log2>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\dpram.vhd" into library work
Parsing entity <dpram>.
Parsing architecture <syn> of entity <dpram>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\adpram.vhd" into library work
Parsing entity <adpram>.
Parsing architecture <syn> of entity <adpram>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\waveram.vhd" into library work
Parsing entity <waveram>.
Parsing architecture <syn> of entity <waveram>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\uartx8.vhd" into library work
Parsing entity <uartx8>.
Parsing architecture <Behavioral> of entity <uartx8>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\uartr8.vhd" into library work
Parsing entity <uartr8>.
Parsing architecture <Behavioral> of entity <uartr8>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\twidrom.vhd" into library work
Parsing entity <twidrom>.
Parsing architecture <syn> of entity <twidrom>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\syncwavegen.vhd" into library work
Parsing entity <syncwavegen>.
Parsing architecture <behavioral> of entity <syncwavegen>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\sslbprom43.vhd" into library work
Parsing entity <sslbp>.
Parsing architecture <syn> of entity <sslbp>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\sslbpram.vhd" into library work
Parsing entity <sslbpram>.
Parsing architecture <syn> of entity <sslbpram>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\sine16.vhd" into library work
Parsing entity <sine16>.
Parsing architecture <syn> of entity <sine16>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\resrom.vhd" into library work
Parsing entity <resrom>.
Parsing architecture <syn> of entity <resrom>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\resolverdaq2.vhd" into library work
Parsing entity <resolverdaq2>.
Parsing architecture <behavioral> of entity <resolverdaq2>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\OutputInteg.vhd" into library work
Parsing entity <OutputInteg>.
Parsing architecture <Behavioral> of entity <outputinteg>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\oneofndecode.vhd" into library work
Parsing package <oneofndecode>.
Parsing package body <oneofndecode>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\IDROMConst.vhd" into library work
Parsing package <IDROMConst>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\decodedstrobe.vhd" into library work
Parsing package <decodedstrobe>.
Parsing package body <decodedstrobe>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\d8o8sqws.vhd" into library work
Parsing entity <DumbAss8sqws>.
Parsing architecture <Behavioral> of entity <dumbass8sqws>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\b32qcondmac2ws.vhd" into library work
Parsing entity <Big32v2>.
Parsing architecture <Behavioral> of entity <big32v2>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\wordrb.vhd" into library work
Parsing entity <wordrb>.
Parsing architecture <behavioral> of entity <wordrb>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\wordpr.vhd" into library work
Parsing entity <wordpr>.
Parsing architecture <behavioral> of entity <wordpr>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\wavegen.vhd" into library work
Parsing entity <wavegen>.
Parsing architecture <behavioral> of entity <wavegen>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\watchdog.vhd" into library work
Parsing entity <watchdog>.
Parsing architecture <Behavioral> of entity <watchdog>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\ubrategend.vhd" into library work
Parsing entity <rategend>.
Parsing architecture <Behavioral> of entity <rategend>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\ubrategen.vhd" into library work
Parsing entity <rategen>.
Parsing architecture <Behavioral> of entity <rategen>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\uartx.vhd" into library work
Parsing entity <uartx>.
Parsing architecture <Behavioral> of entity <uartx>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\uartr.vhd" into library work
Parsing entity <uartr>.
Parsing architecture <Behavioral> of entity <uartr>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\twiddle.vhd" into library work
Parsing entity <twiddle>.
Parsing architecture <Behavioral> of entity <twiddle>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\timestamp.vhd" into library work
Parsing entity <timestamp>.
Parsing architecture <Behavioral> of entity <timestamp>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\threephasepwm.vhd" into library work
Parsing entity <threephasepwm>.
Parsing architecture <behavioral> of entity <threephasepwm>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\sserialwa.vhd" into library work
Parsing entity <sserialwa>.
Parsing architecture <Behavioral> of entity <sserialwa>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\srl16delay.vhd" into library work
Parsing entity <srl16delay>.
Parsing architecture <Behavioral> of entity <srl16delay>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\simplessi.vhd" into library work
Parsing entity <SimpleSSI>.
Parsing architecture <Behavioral> of entity <simplessi>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\simplespix.vhd" into library work
Parsing entity <simplespi>.
Parsing architecture <behavioral> of entity <simplespi>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\scalertimer.vhd" into library work
Parsing entity <scalertimer>.
Parsing architecture <Behavioral> of entity <scalertimer>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\scalercounter.vhd" into library work
Parsing entity <scalercounter>.
Parsing architecture <Behavioral> of entity <scalercounter>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\resolver.vhd" into library work
Parsing entity <resolver>.
Parsing architecture <dataflow> of entity <resolver>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\qcountersfpd.vhd" into library work
Parsing entity <qcounterpd>.
Parsing architecture <behavioral> of entity <qcounterpd>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\qcountersfp.vhd" into library work
Parsing entity <qcounterp>.
Parsing architecture <behavioral> of entity <qcounterp>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\qcountersfd.vhd" into library work
Parsing entity <qcounterd>.
Parsing architecture <behavioral> of entity <qcounterd>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\qcountersf.vhd" into library work
Parsing entity <qcounter>.
Parsing architecture <behavioral> of entity <qcounter>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\qcounterateskd.vhd" into library work
Parsing entity <qcounterateskd>.
Parsing architecture <Behavioral> of entity <qcounterateskd>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\qcounteratesk.vhd" into library work
Parsing entity <qcounteratesk>.
Parsing architecture <Behavioral> of entity <qcounteratesk>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\qcounterated.vhd" into library work
Parsing entity <qcounterated>.
Parsing architecture <Behavioral> of entity <qcounterated>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\qcounterate.vhd" into library work
Parsing entity <qcounterate>.
Parsing architecture <Behavioral> of entity <qcounterate>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\pwmrefh.vhd" into library work
Parsing entity <pwmrefh>.
Parsing architecture <behavioral> of entity <pwmrefh>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\pwmpdmgenh.vhd" into library work
Parsing entity <pwmpdmgenh>.
Parsing architecture <behavioral> of entity <pwmpdmgenh>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\pktuartx.vhd" into library work
Parsing entity <pktuartx>.
Parsing architecture <Behavioral> of entity <pktuartx>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\pktuartr.vhd" into library work
Parsing entity <pktuartr>.
Parsing architecture <Behavioral> of entity <pktuartr>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\PinExists.vhd" into library work
Parsing package <PinExists>.
Parsing package body <PinExists>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\NumberOfModules.vhd" into library work
Parsing package <NumberOfModules>.
Parsing package body <NumberOfModules>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\ModuleExists.vhd" into library work
Parsing package <ModuleExists>.
Parsing package body <ModuleExists>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\MaxPinsPerModule.vhd" into library work
Parsing package <MaxPinsPerModule>.
Parsing package body <MaxPinsPerModule>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\MaxOutputPinsPerModule.vhd" into library work
Parsing package <MaxOutputPinsPerModule>.
Parsing package body <MaxOutputPinsPerModule>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\MaxIOPinsPerModule.vhd" into library work
Parsing package <MaxIOPinsPerModule>.
Parsing package body <MaxIOPinsPerModule>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\MaxInputPinsPerModule.vhd" into library work
Parsing package <MaxInputPinsPerModule>.
Parsing package body <MaxInputPinsPerModule>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\kubstepgenzid.vhd" into library work
Parsing entity <stepgenid>.
Parsing architecture <Behavioral> of entity <stepgenid>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\kubstepgenzi.vhd" into library work
Parsing entity <stepgeni>.
Parsing architecture <Behavioral> of entity <stepgeni>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\kubstepgenzd.vhd" into library work
Parsing entity <stepgend>.
Parsing architecture <Behavioral> of entity <stepgend>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\kubstepgenz.vhd" into library work
Parsing entity <stepgen>.
Parsing architecture <Behavioral> of entity <stepgen>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\irqlogics.vhd" into library work
Parsing entity <irqlogics>.
Parsing architecture <Behavioral> of entity <irqlogics>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\InputPinsPerModule.vhd" into library work
Parsing package <InputPinsPerModule>.
Parsing package body <InputPinsPerModule>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\idrom.vhd" into library work
Parsing entity <IDROM>.
Parsing architecture <syn> of entity <idrom>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\hostmotid.vhd" into library work
Parsing entity <hostmotid>.
Parsing architecture <Behavioral> of entity <hostmotid>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\hmtimers.vhd" into library work
Parsing entity <hm2dpll>.
Parsing architecture <behavioral> of entity <hm2dpll>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\fanucabs.vhd" into library work
Parsing entity <FanucAbs>.
Parsing architecture <Behavioral> of entity <fanucabs>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\drqlogic.vhd" into library work
Parsing entity <dmdrqlogic>.
Parsing architecture <Behavioral> of entity <dmdrqlogic>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\daqfifo16.vhd" into library work
Parsing entity <DAQFIFO16>.
Parsing architecture <Behavioral> of entity <daqfifo16>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\CountPinsInRange.vhd" into library work
Parsing package <CountPinsInRange>.
Parsing package body <CountPinsInRange>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\bufferedspi.vhd" into library work
Parsing entity <bufferedspi>.
Parsing architecture <behavioral> of entity <bufferedspi>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\boutreg.vhd" into library work
Parsing entity <boutreg>.
Parsing architecture <Behavioral> of entity <boutreg>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\biss.vhd" into library work
Parsing entity <biss>.
Parsing architecture <Behavioral> of entity <biss>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\binosc.vhd" into library work
Parsing entity <binosc>.
Parsing architecture <Behavioral> of entity <binosc>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\simplespi8x.vhd" into library work
Parsing entity <simplespi8>.
Parsing architecture <behavioral> of entity <simplespi8>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\PIN_cps5i25_34.vhd" into library work
Parsing package <PIN_cps5i25_34>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\parity.vhd" into library work
Parsing package <parity>.
Parsing package body <parity>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\i25_x9card.vhd" into library work
Parsing package <i25_x9card>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\hostmot2.vhd" into library work
Parsing entity <HostMot2>.
Parsing architecture <dataflow> of entity <hostmot2>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\fixicap.vhd" into library work
Parsing package <FixICap>.
Parsing package body <fixicap>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\decodedstrobe2.vhd" into library work
Parsing package <decodedstrobe2>.
Parsing package body <decodedstrobe2>.
Parsing VHDL file "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\TopPCIHostMot2.vhd" into library work
Parsing entity <TopPCIHostMot2>.
Parsing architecture <Behavioral> of entity <toppcihostmot2>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating entity <TopPCIHostMot2> (architecture <Behavioral>) with generics from library <work>.
Elaborating entity <HostMot2> (architecture <dataflow>) with generics from library <work>.
WARNING:HDLCompiler:746 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 248: Range is empty (null range)
Elaborating entity <hostmotid> (architecture <Behavioral>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\hostmotid.vhd" Line 98. Case statement is complete. others clause is never selected
Elaborating entity <wordpr> (architecture <behavioral>) with generics from library <work>.
Elaborating entity <wordrb> (architecture <behavioral>) with generics from library <work>.
Elaborating entity <watchdog> (architecture <Behavioral>) with generics from library <work>.
Elaborating entity <irqlogics> (architecture <Behavioral>) with generics from library <work>.
Elaborating entity <rategen> (architecture <Behavioral>) from library <work>.
Elaborating entity <stepgen> (architecture <Behavioral>) with generics from library <work>.
WARNING:HDLCompiler:89 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\kubstepgenz.vhd" Line 147: <srl16e> remains a black-box since it has no binding entity.
INFO:HDLCompiler:679 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\kubstepgenz.vhd" Line 351. Case statement is complete. others clause is never selected
Elaborating entity <timestamp> (architecture <Behavioral>) from library <work>.
Elaborating entity <qcounterate> (architecture <Behavioral>) with generics from library <work>.
Note: "Encoder rate divisor: 0.0"
Elaborating entity <qcounter> (architecture <behavioral>) with generics from library <work>.
Elaborating entity <pwmrefh> (architecture <behavioral>) with generics from library <work>.
Elaborating entity <pwmpdmgenh> (architecture <behavioral>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\pwmpdmgenh.vhd" Line 159. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\pwmpdmgenh.vhd" Line 188. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\pwmpdmgenh.vhd" Line 229. Case statement is complete. others clause is never selected
Elaborating entity <boutreg> (architecture <Behavioral>) with generics from library <work>.
WARNING:HDLCompiler:746 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\boutreg.vhd" Line 107: Range is empty (null range)
WARNING:HDLCompiler:220 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\boutreg.vhd" Line 107: Assignment ignored
Elaborating entity <boutreg> (architecture <Behavioral>) with generics from library <work>.
Elaborating entity <IDROM> (architecture <syn>) with generics from library <work>.
WARNING:HDLCompiler:634 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 215: Net <AltData[33]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 259: Net <RateSources[4]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\hostmot2.vhd" Line 911: Net <makeqcounters.IndexMask[1]> does not have a driver.
WARNING:HDLCompiler:1127 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\TopPCIHostMot2.vhd" Line 527: Assignment to configreadstb ignored, since the identifier is never used
WARNING:HDLCompiler:92 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\TopPCIHostMot2.vhd" Line 791: readstb should be on the sensitivity list of the process
WARNING:HDLCompiler:92 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\TopPCIHostMot2.vhd" Line 807: readicapcookie should be on the sensitivity list of the process
Elaborating entity <simplespi8> (architecture <behavioral>) with generics from library <work>.
WARNING:HDLCompiler:634 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\TopPCIHostMot2.vhd" Line 348: Net <BAR0Reg[15]> does not have a driver.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <TopPCIHostMot2>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\TopPCIHostMot2.vhd".
ThePinDesc =
010110000010","0000001
1000001110000010110000001","00000011000000000000000000000000","00000011000000010000010000000001","00000011000000010000010000000010","00000011000000010000010000000011","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","000000000000000000
00000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000
000","0000000000000000
("00000011000000000000011010000001","00000011000000000000010000000010","00000011000000000000010110000010","00000011000000000000010000000001","00000011000000000000010110000001","00000011000000000000010000000011","00000011000000010000010110000010","00000011000000000000000000000000","00000011000000010000010110000001","00000011000000100000010110000010","00000011000000100000010110000001","00000011000000110000010110000010","00000011000000110000010110000001","00000011000000000000000000000000","000000110
00000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000010000011010000001","00000011000000000000000000000000","00000011000001000000010110000010","00000011000000000000000000000000","00000011000001000000010110000001","00000011000000000000000000000000","00000011000001010000010110000010","00000011000000000000000000000000","00000011000001010000010110000001","00000011000001100000010110000010","00000011000001100000010110000001","00000011000001110000
"0000000000000000000000000
0000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","0
0000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","000000000000
00000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","0000000000
0000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000")
0000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","000000000000000000000000000
00000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000",
TheModuleID =
(("00000010","00000000","00000001","00000001","0000110000000000","00000011","00000000","00000000000000000000000000000000"),("00000011","00000000","00000001","00000010","0001000000000000","00000101","00000000","00000000000000000000000000011111"),("00000100","00000010","00000001","00000010","0011000000000000","00000101","00000000","00000000000000000000000000000011"),("00000101","00000010","00000001","00001000","0010000000000000","00001010","00000000","00000000000000000000000111111111"),("00000110",
"00000000","00000010","00000010","0100000100000000","00000101","00000000","00000000000000000000000000000011"),("10000000","00000000","00000001","00000001","0000001000000000","00000001","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","0
0000000","00000000","0
000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","00000000000000
00","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000
","00000000","00000000
000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","000000000000000000000
00000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000")
,("00000000","00000000
","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000",
"00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"))
PWMRefWidth = 13
IDROMType = 3
UseIRQLogic = true
UseWatchDog = true
OffsetToModules = 64
OffsetToPinDesc = 448
BusWidth = 32
AddrWidth = 16
InstStride0 = 4
InstStride1 = 64
RegStride0 = 256
RegStride1 = 256
FallBack = false
WARNING:Xst:647 - Input <NLOCK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\TopPCIHostMot2.vhd" line 474: Output port <rates> of the instance <ahostmot2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\TopPCIHostMot2.vhd" line 474: Output port <dreq> of the instance <ahostmot2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\TopPCIHostMot2.vhd" line 474: Output port <demandmode> of the instance <ahostmot2> is unconnected or connected to loadless signal.
WARNING:Xst:2935 - Signal 'BAR0Reg<15:0>', unconnected in block 'TopPCIHostMot2', is tied to its initial value (0000000000000000).
Found 4-bit register for signal <BusCmd>.
Found 1-bit register for signal <PCIFrame>.
Found 1-bit register for signal <SerrStb>.
Found 1-bit register for signal <LIDSel>.
Found 1-bit register for signal <IDevSel>.
Found 1-bit register for signal <ITRDY>.
Found 1-bit register for signal <IDevSel2>.
Found 1-bit register for signal <IDevSel1>.
Found 1-bit register for signal <BusWrite2>.
Found 1-bit register for signal <BusWrite1>.
Found 1-bit register for signal <PerrStb2>.
Found 1-bit register for signal <PerrStb1>.
Found 1-bit register for signal <SerrStb1>.
Found 1-bit register for signal <NFrame1>.
Found 1-bit register for signal <PAR1>.
Found 1-bit register for signal <IPar>.
Found 1-bit register for signal <CPar>.
Found 1-bit register for signal <ParDrive>.
Found 32-bit register for signal <StatComReg>.
Found 1-bit register for signal <BAR0Reg<31>>.
Found 1-bit register for signal <BAR0Reg<30>>.
Found 1-bit register for signal <BAR0Reg<29>>.
Found 1-bit register for signal <BAR0Reg<28>>.
Found 1-bit register for signal <BAR0Reg<27>>.
Found 1-bit register for signal <BAR0Reg<26>>.
Found 1-bit register for signal <BAR0Reg<25>>.
Found 1-bit register for signal <BAR0Reg<24>>.
Found 1-bit register for signal <BAR0Reg<23>>.
Found 1-bit register for signal <BAR0Reg<22>>.
Found 1-bit register for signal <BAR0Reg<21>>.
Found 1-bit register for signal <BAR0Reg<20>>.
Found 1-bit register for signal <BAR0Reg<19>>.
Found 1-bit register for signal <BAR0Reg<18>>.
Found 1-bit register for signal <BAR0Reg<17>>.
Found 1-bit register for signal <BAR0Reg<16>>.
Found 32-bit register for signal <IntReg>.
Found 16-bit register for signal <ICapI>.
Found 4-bit register for signal <ICapTimer>.
Found 1-bit register for signal <ICapClock>.
Found 32-bit register for signal <A>.
Found 32-bit adder for signal <A[31]_GND_12_o_add_4_OUT> created at line 566.
Found 4-bit subtractor for signal <GND_12_o_GND_12_o_sub_88_OUT<3:0>> created at line 802.
Found 1-bit tristate buffer for signal <AD<31>> created at line 518
Found 1-bit tristate buffer for signal <AD<30>> created at line 518
Found 1-bit tristate buffer for signal <AD<29>> created at line 518
Found 1-bit tristate buffer for signal <AD<28>> created at line 518
Found 1-bit tristate buffer for signal <AD<27>> created at line 518
Found 1-bit tristate buffer for signal <AD<26>> created at line 518
Found 1-bit tristate buffer for signal <AD<25>> created at line 518
Found 1-bit tristate buffer for signal <AD<24>> created at line 518
Found 1-bit tristate buffer for signal <AD<23>> created at line 518
Found 1-bit tristate buffer for signal <AD<22>> created at line 518
Found 1-bit tristate buffer for signal <AD<21>> created at line 518
Found 1-bit tristate buffer for signal <AD<20>> created at line 518
Found 1-bit tristate buffer for signal <AD<19>> created at line 518
Found 1-bit tristate buffer for signal <AD<18>> created at line 518
Found 1-bit tristate buffer for signal <AD<17>> created at line 518
Found 1-bit tristate buffer for signal <AD<16>> created at line 518
Found 1-bit tristate buffer for signal <AD<15>> created at line 518
Found 1-bit tristate buffer for signal <AD<14>> created at line 518
Found 1-bit tristate buffer for signal <AD<13>> created at line 518
Found 1-bit tristate buffer for signal <AD<12>> created at line 518
Found 1-bit tristate buffer for signal <AD<11>> created at line 518
Found 1-bit tristate buffer for signal <AD<10>> created at line 518
Found 1-bit tristate buffer for signal <AD<9>> created at line 518
Found 1-bit tristate buffer for signal <AD<8>> created at line 518
Found 1-bit tristate buffer for signal <AD<7>> created at line 518
Found 1-bit tristate buffer for signal <AD<6>> created at line 518
Found 1-bit tristate buffer for signal <AD<5>> created at line 518
Found 1-bit tristate buffer for signal <AD<4>> created at line 518
Found 1-bit tristate buffer for signal <AD<3>> created at line 518
Found 1-bit tristate buffer for signal <AD<2>> created at line 518
Found 1-bit tristate buffer for signal <AD<1>> created at line 518
Found 1-bit tristate buffer for signal <AD<0>> created at line 518
Found 1-bit tristate buffer for signal <NDEVSEL> created at line 527
Found 1-bit tristate buffer for signal <NTRDY> created at line 527
Found 1-bit tristate buffer for signal <NSTOP> created at line 527
Found 1-bit tristate buffer for signal <PAR> created at line 527
Found 1-bit tristate buffer for signal <NPERR> created at line 527
Found 1-bit tristate buffer for signal <NSERR> created at line 527
Found 1-bit tristate buffer for signal <NINTA> created at line 527
Found 1-bit tristate buffer for signal <D<31>> created at line 712
Found 1-bit tristate buffer for signal <D<30>> created at line 712
Found 1-bit tristate buffer for signal <D<29>> created at line 712
Found 1-bit tristate buffer for signal <D<28>> created at line 712
Found 1-bit tristate buffer for signal <D<27>> created at line 712
Found 1-bit tristate buffer for signal <D<26>> created at line 712
Found 1-bit tristate buffer for signal <D<25>> created at line 712
Found 1-bit tristate buffer for signal <D<24>> created at line 712
Found 1-bit tristate buffer for signal <D<23>> created at line 712
Found 1-bit tristate buffer for signal <D<22>> created at line 712
Found 1-bit tristate buffer for signal <D<21>> created at line 712
Found 1-bit tristate buffer for signal <D<20>> created at line 712
Found 1-bit tristate buffer for signal <D<19>> created at line 712
Found 1-bit tristate buffer for signal <D<18>> created at line 712
Found 1-bit tristate buffer for signal <D<17>> created at line 712
Found 1-bit tristate buffer for signal <D<16>> created at line 712
Found 1-bit tristate buffer for signal <D<15>> created at line 712
Found 1-bit tristate buffer for signal <D<14>> created at line 712
Found 1-bit tristate buffer for signal <D<13>> created at line 712
Found 1-bit tristate buffer for signal <D<12>> created at line 712
Found 1-bit tristate buffer for signal <D<11>> created at line 712
Found 1-bit tristate buffer for signal <D<10>> created at line 712
Found 1-bit tristate buffer for signal <D<9>> created at line 712
Found 1-bit tristate buffer for signal <D<8>> created at line 712
Found 1-bit tristate buffer for signal <D<7>> created at line 712
Found 1-bit tristate buffer for signal <D<6>> created at line 712
Found 1-bit tristate buffer for signal <D<5>> created at line 712
Found 1-bit tristate buffer for signal <D<4>> created at line 712
Found 1-bit tristate buffer for signal <D<3>> created at line 712
Found 1-bit tristate buffer for signal <D<2>> created at line 712
Found 1-bit tristate buffer for signal <D<1>> created at line 712
Found 1-bit tristate buffer for signal <D<0>> created at line 712
Found 1-bit tristate buffer for signal <D<31>> created at line 794
Found 1-bit tristate buffer for signal <D<30>> created at line 794
Found 1-bit tristate buffer for signal <D<29>> created at line 794
Found 1-bit tristate buffer for signal <D<28>> created at line 794
Found 1-bit tristate buffer for signal <D<27>> created at line 794
Found 1-bit tristate buffer for signal <D<26>> created at line 794
Found 1-bit tristate buffer for signal <D<25>> created at line 794
Found 1-bit tristate buffer for signal <D<24>> created at line 794
Found 1-bit tristate buffer for signal <D<23>> created at line 794
Found 1-bit tristate buffer for signal <D<22>> created at line 794
Found 1-bit tristate buffer for signal <D<21>> created at line 794
Found 1-bit tristate buffer for signal <D<20>> created at line 794
Found 1-bit tristate buffer for signal <D<19>> created at line 794
Found 1-bit tristate buffer for signal <D<18>> created at line 794
Found 1-bit tristate buffer for signal <D<17>> created at line 794
Found 1-bit tristate buffer for signal <D<16>> created at line 794
Found 1-bit tristate buffer for signal <D<15>> created at line 794
Found 1-bit tristate buffer for signal <D<14>> created at line 794
Found 1-bit tristate buffer for signal <D<13>> created at line 794
Found 1-bit tristate buffer for signal <D<12>> created at line 794
Found 1-bit tristate buffer for signal <D<11>> created at line 794
Found 1-bit tristate buffer for signal <D<10>> created at line 794
Found 1-bit tristate buffer for signal <D<9>> created at line 794
Found 1-bit tristate buffer for signal <D<8>> created at line 794
Found 1-bit tristate buffer for signal <D<7>> created at line 794
Found 1-bit tristate buffer for signal <D<6>> created at line 794
Found 1-bit tristate buffer for signal <D<5>> created at line 794
Found 1-bit tristate buffer for signal <D<4>> created at line 794
Found 1-bit tristate buffer for signal <D<3>> created at line 794
Found 1-bit tristate buffer for signal <D<2>> created at line 794
Found 1-bit tristate buffer for signal <D<1>> created at line 794
Found 1-bit tristate buffer for signal <D<0>> created at line 794
Found 1-bit tristate buffer for signal <NINIT> created at line 851
Found 16-bit comparator equal for signal <BAR0Reg[31]_A[31]_equal_19_o> created at line 685
WARNING:Xst:2404 - FFs/Latches <IStop<0:0>> (without init value) have a constant value of 0 in block <TopPCIHostMot2>.
Summary:
inferred 2 Adder/Subtractor(s).
inferred 154 D-type flip-flop(s).
inferred 1 Comparator(s).
inferred 50 Multiplexer(s).
inferred 104 Tristate(s).
Unit <TopPCIHostMot2> synthesized.
Synthesizing Unit <HostMot2>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\hostmot2.vhd".
ThePinDesc =
("00000011000000000000011010000001","00000011000000000000010000000010","00000011000000000000010110000010","00000011000000000000010000000001","00000011000000000000010110000001","00000011000000000000010000000011","00000011000000010000010110000010","00000011000000000000000000000000","00000011000000010000010110000001","00000011000000100000010110000010","00000011000000100000010110000001","00000011000000110000010110000010","00000011000000110000010110000001","00000011000000000000000000000000","000000110
00000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000010000011010000001","00000011000000000000000000000000","00000011000001000000010110000010","00000011000000000000000000000000","00000011000001000000010110000001","00000011000000000000000000000000","00000011000001010000010110000010","00000011000000000000000000000000","00000011000001010000010110000001","00000011000001100000010110000010","00000011000001100000010110000001","00000011000001110000
010110000010","0000001
1000001110000010110000001","00000011000000000000000000000000","00000011000000010000010000000001","00000011000000010000010000000010","00000011000000010000010000000011","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","000000000000000000
00000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000
000","0000000000000000
"0000000000000000000000000
0000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","0
0000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","000000000000
00000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","0000000000
0000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000")
TheModuleID =
(("00000010","00000000","00000001","00000001","0000110000000000","00000011","00000000","00000000000000000000000000000000"),("00000011","00000000","00000001","00000010","0001000000000000","00000101","00000000","00000000000000000000000000011111"),("00000100","00000010","00000001","00000010","0011000000000000","00000101","00000000","00000000000000000000000000000011"),("00000101","00000010","00000001","00001000","0010000000000000","00001010","00000000","00000000000000000000000111111111"),("00000110",
"00000000","00000010","00000010","0100000100000000","00000101","00000000","00000000000000000000000000000011"),("10000000","00000000","00000001","00000001","0000001000000000","00000001","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","0
0000000","00000000","0
000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","00000000000000
00","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000
","00000000","00000000
000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","000000000000000000000
00000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000")
,("00000000","00000000
","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000",
"00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"))
IDROMType = 3
SepClocks = true
OneWS = true
UseIRQLogic = true
PWMRefWidth = 13
0000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","000000000000000000000000000
00000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000",
UseWatchDog = true
OffsetToModules = 64
OffsetToPinDesc = 448
ClockHigh = 200000000
ClockMed = 100000000
ClockLow = 33333333
BoardNameLow = "01000001010100110100010101001101"
BoardNameHigh = "00110101001100100100100100110101"
FPGASize = 9
FPGAPins = 144
IOPorts = 2
IOWidth = 34
LIOWidth = 6
PortWidth = 17
BusWidth = 32
AddrWidth = 16
InstStride0 = 4
InstStride1 = 64
RegStride0 = 256
RegStride1 = 256
LEDCount = 2
WARNING:Xst:647 - Input <clkmed> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\hostmot2.vhd" line 323: Output port <wdlatchedbite> of the instance <makewatchdog.wdogabittus> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\hostmot2.vhd" line 1599: Output port <pwmoutb> of the instance <makepwms.makepwmgens[0].pwmgenx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\hostmot2.vhd" line 1599: Output port <pwmoutb> of the instance <makepwms.makepwmgens[1].pwmgenx> is unconnected or connected to loadless signal.
WARNING:Xst:2563 - Inout <liobits> is never assigned. Tied to value Z.
WARNING:Xst:653 - Signal <rates> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:2935 - Signal 'AltData<33:30>', unconnected in block 'HostMot2', is tied to its initial value (0000).
WARNING:Xst:2935 - Signal 'AltData<24>', unconnected in block 'HostMot2', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'AltData<22>', unconnected in block 'HostMot2', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'AltData<20>', unconnected in block 'HostMot2', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'AltData<18>', unconnected in block 'HostMot2', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'AltData<16:13>', unconnected in block 'HostMot2', is tied to its initial value (0000).
WARNING:Xst:2935 - Signal 'AltData<7>', unconnected in block 'HostMot2', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'AltData<5>', unconnected in block 'HostMot2', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'AltData<3>', unconnected in block 'HostMot2', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'AltData<1>', unconnected in block 'HostMot2', is tied to its initial value (0).
WARNING:Xst:653 - Signal <RateSources> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <makeqcounters.IndexMask> is used but never assigned. This sourceless signal will be automatically connected to value GND.
Found 14-bit register for signal <A>.
Found 6-bit tristate buffer for signal <liobits> created at line 135
Summary:
inferred 14 D-type flip-flop(s).
inferred 31 Multiplexer(s).
inferred 1 Tristate(s).
Unit <HostMot2> synthesized.
Synthesizing Unit <hostmotid>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\hostmotid.vhd".
buswidth = 32
cookie = "01010101101010101100101011111110"
namelow = "01010100010100110100111101001000"
namehigh = "00110010010101000100111101001101"
idromoffset = "00000000000000000000010000000000"
Found 1-bit tristate buffer for signal <obus<31>> created at line 89
Found 1-bit tristate buffer for signal <obus<30>> created at line 89
Found 1-bit tristate buffer for signal <obus<29>> created at line 89
Found 1-bit tristate buffer for signal <obus<28>> created at line 89
Found 1-bit tristate buffer for signal <obus<27>> created at line 89
Found 1-bit tristate buffer for signal <obus<26>> created at line 89
Found 1-bit tristate buffer for signal <obus<25>> created at line 89
Found 1-bit tristate buffer for signal <obus<24>> created at line 89
Found 1-bit tristate buffer for signal <obus<23>> created at line 89
Found 1-bit tristate buffer for signal <obus<22>> created at line 89
Found 1-bit tristate buffer for signal <obus<21>> created at line 89
Found 1-bit tristate buffer for signal <obus<20>> created at line 89
Found 1-bit tristate buffer for signal <obus<19>> created at line 89
Found 1-bit tristate buffer for signal <obus<18>> created at line 89
Found 1-bit tristate buffer for signal <obus<17>> created at line 89
Found 1-bit tristate buffer for signal <obus<16>> created at line 89
Found 1-bit tristate buffer for signal <obus<15>> created at line 89
Found 1-bit tristate buffer for signal <obus<14>> created at line 89
Found 1-bit tristate buffer for signal <obus<13>> created at line 89
Found 1-bit tristate buffer for signal <obus<12>> created at line 89
Found 1-bit tristate buffer for signal <obus<11>> created at line 89
Found 1-bit tristate buffer for signal <obus<10>> created at line 89
Found 1-bit tristate buffer for signal <obus<9>> created at line 89
Found 1-bit tristate buffer for signal <obus<8>> created at line 89
Found 1-bit tristate buffer for signal <obus<7>> created at line 89
Found 1-bit tristate buffer for signal <obus<6>> created at line 89
Found 1-bit tristate buffer for signal <obus<5>> created at line 89
Found 1-bit tristate buffer for signal <obus<4>> created at line 89
Found 1-bit tristate buffer for signal <obus<3>> created at line 89
Found 1-bit tristate buffer for signal <obus<2>> created at line 89
Found 1-bit tristate buffer for signal <obus<1>> created at line 89
Found 1-bit tristate buffer for signal <obus<0>> created at line 89
Summary:
inferred 32 Tristate(s).
Unit <hostmotid> synthesized.
Synthesizing Unit <wordpr>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\wordpr.vhd".
size = 17
buswidth = 32
WARNING:Xst:647 - Input <ibus<31:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 17-bit register for signal <ddrreg>.
Found 17-bit register for signal <altdatasel>.
Found 17-bit register for signal <opendrainsel>.
Found 17-bit register for signal <invertsel>.
Found 17-bit register for signal <outreg>.
Found 1-bit tristate buffer for signal <tsoutreg<16>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<15>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<14>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<13>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<12>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<11>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<10>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<9>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<8>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<7>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<6>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<5>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<4>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<3>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<2>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<1>> created at line 103
Found 1-bit tristate buffer for signal <tsoutreg<0>> created at line 103
Found 1-bit tristate buffer for signal <obus<31>> created at line 103
Found 1-bit tristate buffer for signal <obus<30>> created at line 103
Found 1-bit tristate buffer for signal <obus<29>> created at line 103
Found 1-bit tristate buffer for signal <obus<28>> created at line 103
Found 1-bit tristate buffer for signal <obus<27>> created at line 103
Found 1-bit tristate buffer for signal <obus<26>> created at line 103
Found 1-bit tristate buffer for signal <obus<25>> created at line 103
Found 1-bit tristate buffer for signal <obus<24>> created at line 103
Found 1-bit tristate buffer for signal <obus<23>> created at line 103
Found 1-bit tristate buffer for signal <obus<22>> created at line 103
Found 1-bit tristate buffer for signal <obus<21>> created at line 103
Found 1-bit tristate buffer for signal <obus<20>> created at line 103
Found 1-bit tristate buffer for signal <obus<19>> created at line 103
Found 1-bit tristate buffer for signal <obus<18>> created at line 103
Found 1-bit tristate buffer for signal <obus<17>> created at line 103
Found 1-bit tristate buffer for signal <obus<16>> created at line 103
Found 1-bit tristate buffer for signal <obus<15>> created at line 103
Found 1-bit tristate buffer for signal <obus<14>> created at line 103
Found 1-bit tristate buffer for signal <obus<13>> created at line 103
Found 1-bit tristate buffer for signal <obus<12>> created at line 103
Found 1-bit tristate buffer for signal <obus<11>> created at line 103
Found 1-bit tristate buffer for signal <obus<10>> created at line 103
Found 1-bit tristate buffer for signal <obus<9>> created at line 103
Found 1-bit tristate buffer for signal <obus<8>> created at line 103
Found 1-bit tristate buffer for signal <obus<7>> created at line 103
Found 1-bit tristate buffer for signal <obus<6>> created at line 103
Found 1-bit tristate buffer for signal <obus<5>> created at line 103
Found 1-bit tristate buffer for signal <obus<4>> created at line 103
Found 1-bit tristate buffer for signal <obus<3>> created at line 103
Found 1-bit tristate buffer for signal <obus<2>> created at line 103
Found 1-bit tristate buffer for signal <obus<1>> created at line 103
Found 1-bit tristate buffer for signal <obus<0>> created at line 103
Summary:
inferred 85 D-type flip-flop(s).
inferred 85 Multiplexer(s).
inferred 49 Tristate(s).
Unit <wordpr> synthesized.
Synthesizing Unit <wordrb>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\wordrb.vhd".
size = 17
buswidth = 32
Found 1-bit tristate buffer for signal <obus<31>> created at line 82
Found 1-bit tristate buffer for signal <obus<30>> created at line 82
Found 1-bit tristate buffer for signal <obus<29>> created at line 82
Found 1-bit tristate buffer for signal <obus<28>> created at line 82
Found 1-bit tristate buffer for signal <obus<27>> created at line 82
Found 1-bit tristate buffer for signal <obus<26>> created at line 82
Found 1-bit tristate buffer for signal <obus<25>> created at line 82
Found 1-bit tristate buffer for signal <obus<24>> created at line 82
Found 1-bit tristate buffer for signal <obus<23>> created at line 82
Found 1-bit tristate buffer for signal <obus<22>> created at line 82
Found 1-bit tristate buffer for signal <obus<21>> created at line 82
Found 1-bit tristate buffer for signal <obus<20>> created at line 82
Found 1-bit tristate buffer for signal <obus<19>> created at line 82
Found 1-bit tristate buffer for signal <obus<18>> created at line 82
Found 1-bit tristate buffer for signal <obus<17>> created at line 82
Found 1-bit tristate buffer for signal <obus<16>> created at line 82
Found 1-bit tristate buffer for signal <obus<15>> created at line 82
Found 1-bit tristate buffer for signal <obus<14>> created at line 82
Found 1-bit tristate buffer for signal <obus<13>> created at line 82
Found 1-bit tristate buffer for signal <obus<12>> created at line 82
Found 1-bit tristate buffer for signal <obus<11>> created at line 82
Found 1-bit tristate buffer for signal <obus<10>> created at line 82
Found 1-bit tristate buffer for signal <obus<9>> created at line 82
Found 1-bit tristate buffer for signal <obus<8>> created at line 82
Found 1-bit tristate buffer for signal <obus<7>> created at line 82
Found 1-bit tristate buffer for signal <obus<6>> created at line 82
Found 1-bit tristate buffer for signal <obus<5>> created at line 82
Found 1-bit tristate buffer for signal <obus<4>> created at line 82
Found 1-bit tristate buffer for signal <obus<3>> created at line 82
Found 1-bit tristate buffer for signal <obus<2>> created at line 82
Found 1-bit tristate buffer for signal <obus<1>> created at line 82
Found 1-bit tristate buffer for signal <obus<0>> created at line 82
Summary:
inferred 32 Tristate(s).
Unit <wordrb> synthesized.
Synthesizing Unit <watchdog>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\watchdog.vhd".
buswidth = 32
Found 32-bit register for signal <wdtimer>.
Found 32-bit register for signal <wdtime>.
Found 1-bit register for signal <wdstatus>.
Found 1-bit register for signal <wdbite>.
Found 1-bit register for signal <oldwdtimermsb>.
Found 32-bit subtractor for signal <GND_154_o_GND_154_o_sub_1_OUT<31:0>> created at line 106.
Found 1-bit tristate buffer for signal <obus<31>> created at line 97
Found 1-bit tristate buffer for signal <obus<30>> created at line 97
Found 1-bit tristate buffer for signal <obus<29>> created at line 97
Found 1-bit tristate buffer for signal <obus<28>> created at line 97
Found 1-bit tristate buffer for signal <obus<27>> created at line 97
Found 1-bit tristate buffer for signal <obus<26>> created at line 97
Found 1-bit tristate buffer for signal <obus<25>> created at line 97
Found 1-bit tristate buffer for signal <obus<24>> created at line 97
Found 1-bit tristate buffer for signal <obus<23>> created at line 97
Found 1-bit tristate buffer for signal <obus<22>> created at line 97
Found 1-bit tristate buffer for signal <obus<21>> created at line 97
Found 1-bit tristate buffer for signal <obus<20>> created at line 97
Found 1-bit tristate buffer for signal <obus<19>> created at line 97
Found 1-bit tristate buffer for signal <obus<18>> created at line 97
Found 1-bit tristate buffer for signal <obus<17>> created at line 97
Found 1-bit tristate buffer for signal <obus<16>> created at line 97
Found 1-bit tristate buffer for signal <obus<15>> created at line 97
Found 1-bit tristate buffer for signal <obus<14>> created at line 97
Found 1-bit tristate buffer for signal <obus<13>> created at line 97
Found 1-bit tristate buffer for signal <obus<12>> created at line 97
Found 1-bit tristate buffer for signal <obus<11>> created at line 97
Found 1-bit tristate buffer for signal <obus<10>> created at line 97
Found 1-bit tristate buffer for signal <obus<9>> created at line 97
Found 1-bit tristate buffer for signal <obus<8>> created at line 97
Found 1-bit tristate buffer for signal <obus<7>> created at line 97
Found 1-bit tristate buffer for signal <obus<6>> created at line 97
Found 1-bit tristate buffer for signal <obus<5>> created at line 97
Found 1-bit tristate buffer for signal <obus<4>> created at line 97
Found 1-bit tristate buffer for signal <obus<3>> created at line 97
Found 1-bit tristate buffer for signal <obus<2>> created at line 97
Found 1-bit tristate buffer for signal <obus<1>> created at line 97
Found 1-bit tristate buffer for signal <obus<0>> created at line 97
Summary:
inferred 1 Adder/Subtractor(s).
inferred 67 D-type flip-flop(s).
inferred 36 Multiplexer(s).
inferred 32 Tristate(s).
Unit <watchdog> synthesized.
Synthesizing Unit <irqlogics>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\irqlogics.vhd".
buswidth = 32
WARNING:Xst:647 - Input <ibus<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 5-bit register for signal <statusreg>.
Found 2-bit register for signal <rated>.
Found 1-bit tristate buffer for signal <obus<31>> created at line 96
Found 1-bit tristate buffer for signal <obus<30>> created at line 96
Found 1-bit tristate buffer for signal <obus<29>> created at line 96
Found 1-bit tristate buffer for signal <obus<28>> created at line 96
Found 1-bit tristate buffer for signal <obus<27>> created at line 96
Found 1-bit tristate buffer for signal <obus<26>> created at line 96
Found 1-bit tristate buffer for signal <obus<25>> created at line 96
Found 1-bit tristate buffer for signal <obus<24>> created at line 96
Found 1-bit tristate buffer for signal <obus<23>> created at line 96
Found 1-bit tristate buffer for signal <obus<22>> created at line 96
Found 1-bit tristate buffer for signal <obus<21>> created at line 96
Found 1-bit tristate buffer for signal <obus<20>> created at line 96
Found 1-bit tristate buffer for signal <obus<19>> created at line 96
Found 1-bit tristate buffer for signal <obus<18>> created at line 96
Found 1-bit tristate buffer for signal <obus<17>> created at line 96
Found 1-bit tristate buffer for signal <obus<16>> created at line 96
Found 1-bit tristate buffer for signal <obus<15>> created at line 96
Found 1-bit tristate buffer for signal <obus<14>> created at line 96
Found 1-bit tristate buffer for signal <obus<13>> created at line 96
Found 1-bit tristate buffer for signal <obus<12>> created at line 96
Found 1-bit tristate buffer for signal <obus<11>> created at line 96
Found 1-bit tristate buffer for signal <obus<10>> created at line 96
Found 1-bit tristate buffer for signal <obus<9>> created at line 96
Found 1-bit tristate buffer for signal <obus<8>> created at line 96
Found 1-bit tristate buffer for signal <obus<7>> created at line 96
Found 1-bit tristate buffer for signal <obus<6>> created at line 96
Found 1-bit tristate buffer for signal <obus<5>> created at line 96
Found 1-bit tristate buffer for signal <obus<4>> created at line 96
Found 1-bit tristate buffer for signal <obus<3>> created at line 96
Found 1-bit tristate buffer for signal <obus<2>> created at line 96
Found 1-bit tristate buffer for signal <obus<1>> created at line 96
Found 1-bit tristate buffer for signal <obus<0>> created at line 96
Summary:
inferred 7 D-type flip-flop(s).
inferred 3 Multiplexer(s).
inferred 32 Tristate(s).
Unit <irqlogics> synthesized.
Synthesizing Unit <rategen>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\ubrategen.vhd".
Found 1-bit register for signal <rateout>.
Found 1-bit register for signal <oldratemsb>.
Found 32-bit register for signal <ratelatch>.
Found 33-bit register for signal <rateaccum>.
Found 33-bit adder for signal <rateaccum[32]_rateaccum[32]_mux_1_OUT> created at line 94.
Found 1-bit tristate buffer for signal <obus<31>> created at line 90
Found 1-bit tristate buffer for signal <obus<30>> created at line 90
Found 1-bit tristate buffer for signal <obus<29>> created at line 90
Found 1-bit tristate buffer for signal <obus<28>> created at line 90
Found 1-bit tristate buffer for signal <obus<27>> created at line 90
Found 1-bit tristate buffer for signal <obus<26>> created at line 90
Found 1-bit tristate buffer for signal <obus<25>> created at line 90
Found 1-bit tristate buffer for signal <obus<24>> created at line 90
Found 1-bit tristate buffer for signal <obus<23>> created at line 90
Found 1-bit tristate buffer for signal <obus<22>> created at line 90
Found 1-bit tristate buffer for signal <obus<21>> created at line 90
Found 1-bit tristate buffer for signal <obus<20>> created at line 90
Found 1-bit tristate buffer for signal <obus<19>> created at line 90
Found 1-bit tristate buffer for signal <obus<18>> created at line 90
Found 1-bit tristate buffer for signal <obus<17>> created at line 90
Found 1-bit tristate buffer for signal <obus<16>> created at line 90
Found 1-bit tristate buffer for signal <obus<15>> created at line 90
Found 1-bit tristate buffer for signal <obus<14>> created at line 90
Found 1-bit tristate buffer for signal <obus<13>> created at line 90
Found 1-bit tristate buffer for signal <obus<12>> created at line 90
Found 1-bit tristate buffer for signal <obus<11>> created at line 90
Found 1-bit tristate buffer for signal <obus<10>> created at line 90
Found 1-bit tristate buffer for signal <obus<9>> created at line 90
Found 1-bit tristate buffer for signal <obus<8>> created at line 90
Found 1-bit tristate buffer for signal <obus<7>> created at line 90
Found 1-bit tristate buffer for signal <obus<6>> created at line 90
Found 1-bit tristate buffer for signal <obus<5>> created at line 90
Found 1-bit tristate buffer for signal <obus<4>> created at line 90
Found 1-bit tristate buffer for signal <obus<3>> created at line 90
Found 1-bit tristate buffer for signal <obus<2>> created at line 90
Found 1-bit tristate buffer for signal <obus<1>> created at line 90
Found 1-bit tristate buffer for signal <obus<0>> created at line 90
Summary:
inferred 1 Adder/Subtractor(s).
inferred 67 D-type flip-flop(s).
inferred 32 Tristate(s).
Unit <rategen> synthesized.
Synthesizing Unit <stepgen>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\kubstepgenz.vhd".
buswidth = 32
timersize = 14
tablewidth = 2
asize = 48
rsize = 32
WARNING:Xst:647 - Input <readsteprate> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <readstepmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <readdirsetuptime> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <readdirholdtime> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <readpulseactivetime> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <readpulseidletime> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <readtable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <readtablemax> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit register for signal <dstepdir>.
Found 14-bit register for signal <pulsewidthcount>.
Found 1-bit register for signal <steppulse>.
Found 14-bit register for signal <dirshcount>.
Found 1-bit register for signal <dirhold>.
Found 1-bit register for signal <stepdirout>.
Found 4-bit register for signal <tableptr>.
Found 2-bit register for signal <stepmode>.
Found 32-bit register for signal <steprate>.
Found 1-bit register for signal <dstepmsb>.
Found 14-bit register for signal <dirsetuptime>.
Found 14-bit register for signal <dirholdtime>.
Found 14-bit register for signal <pulseactivetime>.
Found 14-bit register for signal <pulseidletime>.
Found 4-bit register for signal <tablemax>.
Found 1-bit register for signal <dpulsewait>.
Found 48-bit register for signal <stepaccum>.
Found 4-bit adder for signal <tableptr[3]_GND_254_o_add_11_OUT> created at line 225.
Found 48-bit adder for signal <nextaccum> created at line 280.
Found 14-bit subtractor for signal <GND_254_o_GND_254_o_sub_2_OUT<13:0>> created at line 192.
Found 14-bit subtractor for signal <GND_254_o_GND_254_o_sub_5_OUT<13:0>> created at line 201.
Found 4-bit subtractor for signal <GND_254_o_GND_254_o_sub_16_OUT<3:0>> created at line 232.
Found 4x2-bit Read Only RAM for signal <stepaccum[31]_PWR_33_o_wide_mux_41_OUT>
Found 2-bit 4-to-1 multiplexer for signal <localout> created at line 338.
Found 1-bit tristate buffer for signal <obus<31>> created at line 179
Found 1-bit tristate buffer for signal <obus<30>> created at line 179
Found 1-bit tristate buffer for signal <obus<29>> created at line 179
Found 1-bit tristate buffer for signal <obus<28>> created at line 179
Found 1-bit tristate buffer for signal <obus<27>> created at line 179
Found 1-bit tristate buffer for signal <obus<26>> created at line 179
Found 1-bit tristate buffer for signal <obus<25>> created at line 179
Found 1-bit tristate buffer for signal <obus<24>> created at line 179
Found 1-bit tristate buffer for signal <obus<23>> created at line 179
Found 1-bit tristate buffer for signal <obus<22>> created at line 179
Found 1-bit tristate buffer for signal <obus<21>> created at line 179
Found 1-bit tristate buffer for signal <obus<20>> created at line 179
Found 1-bit tristate buffer for signal <obus<19>> created at line 179
Found 1-bit tristate buffer for signal <obus<18>> created at line 179
Found 1-bit tristate buffer for signal <obus<17>> created at line 179
Found 1-bit tristate buffer for signal <obus<16>> created at line 179
Found 1-bit tristate buffer for signal <obus<15>> created at line 179
Found 1-bit tristate buffer for signal <obus<14>> created at line 179
Found 1-bit tristate buffer for signal <obus<13>> created at line 179
Found 1-bit tristate buffer for signal <obus<12>> created at line 179
Found 1-bit tristate buffer for signal <obus<11>> created at line 179
Found 1-bit tristate buffer for signal <obus<10>> created at line 179
Found 1-bit tristate buffer for signal <obus<9>> created at line 179
Found 1-bit tristate buffer for signal <obus<8>> created at line 179
Found 1-bit tristate buffer for signal <obus<7>> created at line 179
Found 1-bit tristate buffer for signal <obus<6>> created at line 179
Found 1-bit tristate buffer for signal <obus<5>> created at line 179
Found 1-bit tristate buffer for signal <obus<4>> created at line 179
Found 1-bit tristate buffer for signal <obus<3>> created at line 179
Found 1-bit tristate buffer for signal <obus<2>> created at line 179
Found 1-bit tristate buffer for signal <obus<1>> created at line 179
Found 1-bit tristate buffer for signal <obus<0>> created at line 179
Found 4-bit comparator equal for signal <tableptr[3]_tablemax[3]_equal_11_o> created at line 222
Summary:
inferred 1 RAM(s).
inferred 4 Adder/Subtractor(s).
inferred 180 D-type flip-flop(s).
inferred 1 Comparator(s).
inferred 43 Multiplexer(s).
inferred 32 Tristate(s).
Unit <stepgen> synthesized.
Synthesizing Unit <timestamp>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\timestamp.vhd".
Found 16-bit register for signal <counter>.
Found 16-bit register for signal <divlatch>.
Found 16-bit register for signal <div>.
Found 16-bit adder for signal <counter[15]_GND_295_o_add_1_OUT> created at line 97.
Found 16-bit subtractor for signal <GND_295_o_GND_295_o_sub_1_OUT<15:0>> created at line 94.
Found 1-bit tristate buffer for signal <obus<15>> created at line 91
Found 1-bit tristate buffer for signal <obus<14>> created at line 91
Found 1-bit tristate buffer for signal <obus<13>> created at line 91
Found 1-bit tristate buffer for signal <obus<12>> created at line 91
Found 1-bit tristate buffer for signal <obus<11>> created at line 91
Found 1-bit tristate buffer for signal <obus<10>> created at line 91
Found 1-bit tristate buffer for signal <obus<9>> created at line 91
Found 1-bit tristate buffer for signal <obus<8>> created at line 91
Found 1-bit tristate buffer for signal <obus<7>> created at line 91
Found 1-bit tristate buffer for signal <obus<6>> created at line 91
Found 1-bit tristate buffer for signal <obus<5>> created at line 91
Found 1-bit tristate buffer for signal <obus<4>> created at line 91
Found 1-bit tristate buffer for signal <obus<3>> created at line 91
Found 1-bit tristate buffer for signal <obus<2>> created at line 91
Found 1-bit tristate buffer for signal <obus<1>> created at line 91
Found 1-bit tristate buffer for signal <obus<0>> created at line 91
Summary:
inferred 2 Adder/Subtractor(s).
inferred 48 D-type flip-flop(s).
inferred 17 Multiplexer(s).
inferred 16 Tristate(s).
Unit <timestamp> synthesized.
Synthesizing Unit <qcounterate>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\qcounterate.vhd".
clock = 33333333
Found 12-bit register for signal <rate>.
Found 12-bit register for signal <count>.
Found 12-bit subtractor for signal <GND_314_o_GND_314_o_sub_1_OUT<11:0>> created at line 92.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 24 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <qcounterate> synthesized.
Synthesizing Unit <qcounter>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\qcountersf.vhd".
buswidth = 32
WARNING:Xst:647 - Input <ibus<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ibus<13:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ibus<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit register for signal <quada1>.
Found 1-bit register for signal <quada2>.
Found 1-bit register for signal <quadbdel>.
Found 1-bit register for signal <quadb1>.
Found 1-bit register for signal <quadb2>.
Found 1-bit register for signal <indexdel>.
Found 1-bit register for signal <index1>.
Found 1-bit register for signal <index2>.
Found 4-bit register for signal <quadacnt>.
Found 1-bit register for signal <quadafilt>.
Found 4-bit register for signal <quadbcnt>.
Found 1-bit register for signal <quadbfilt>.
Found 4-bit register for signal <indexcnt>.
Found 1-bit register for signal <indexfilt>.
Found 1-bit register for signal <doclear>.
Found 1-bit register for signal <clearonindex>.
Found 16-bit register for signal <countlatch>.
Found 1-bit register for signal <latchonindex>.
Found 1-bit register for signal <quaderror>.
Found 16-bit register for signal <timestamplatch>.
Found 16-bit register for signal <count>.
Found 1-bit register for signal <abmaskpol>.
Found 1-bit register for signal <quadfilter>.
Found 1-bit register for signal <countermode>.
Found 1-bit register for signal <useindexmask>.
Found 1-bit register for signal <indexmaskpol>.
Found 1-bit register for signal <abgateindex>.
Found 1-bit register for signal <justonce>.
Found 1-bit register for signal <indexpol>.
Found 1-bit register for signal <quadadel>.
Found 4-bit adder for signal <quadacnt[3]_GND_315_o_add_2_OUT> created at line 235.
Found 4-bit adder for signal <quadbcnt[3]_GND_315_o_add_10_OUT> created at line 249.
Found 4-bit adder for signal <indexcnt[3]_GND_315_o_add_18_OUT> created at line 263.
Found 16-bit adder for signal <count[15]_GND_315_o_add_29_OUT> created at line 305.
Found 4-bit subtractor for signal <GND_315_o_GND_315_o_sub_6_OUT<3:0>> created at line 238.
Found 4-bit subtractor for signal <GND_315_o_GND_315_o_sub_14_OUT<3:0>> created at line 252.
Found 4-bit subtractor for signal <GND_315_o_GND_315_o_sub_22_OUT<3:0>> created at line 266.
Found 16-bit subtractor for signal <GND_315_o_GND_315_o_sub_31_OUT<15:0>> created at line 307.
Found 1-bit tristate buffer for signal <obus<31>> created at line 136
Found 1-bit tristate buffer for signal <obus<30>> created at line 136
Found 1-bit tristate buffer for signal <obus<29>> created at line 136
Found 1-bit tristate buffer for signal <obus<28>> created at line 136
Found 1-bit tristate buffer for signal <obus<27>> created at line 136
Found 1-bit tristate buffer for signal <obus<26>> created at line 136
Found 1-bit tristate buffer for signal <obus<25>> created at line 136
Found 1-bit tristate buffer for signal <obus<24>> created at line 136
Found 1-bit tristate buffer for signal <obus<23>> created at line 136
Found 1-bit tristate buffer for signal <obus<22>> created at line 136
Found 1-bit tristate buffer for signal <obus<21>> created at line 136
Found 1-bit tristate buffer for signal <obus<20>> created at line 136
Found 1-bit tristate buffer for signal <obus<19>> created at line 136
Found 1-bit tristate buffer for signal <obus<18>> created at line 136
Found 1-bit tristate buffer for signal <obus<17>> created at line 136
Found 1-bit tristate buffer for signal <obus<16>> created at line 136
Found 1-bit tristate buffer for signal <obus<15>> created at line 136
Found 1-bit tristate buffer for signal <obus<14>> created at line 136
Found 1-bit tristate buffer for signal <obus<13>> created at line 136
Found 1-bit tristate buffer for signal <obus<12>> created at line 136
Found 1-bit tristate buffer for signal <obus<11>> created at line 136
Found 1-bit tristate buffer for signal <obus<10>> created at line 136
Found 1-bit tristate buffer for signal <obus<9>> created at line 136
Found 1-bit tristate buffer for signal <obus<8>> created at line 136
Found 1-bit tristate buffer for signal <obus<7>> created at line 136
Found 1-bit tristate buffer for signal <obus<6>> created at line 136
Found 1-bit tristate buffer for signal <obus<5>> created at line 136
Found 1-bit tristate buffer for signal <obus<4>> created at line 136
Found 1-bit tristate buffer for signal <obus<3>> created at line 136
Found 1-bit tristate buffer for signal <obus<2>> created at line 136
Found 1-bit tristate buffer for signal <obus<1>> created at line 136
Found 1-bit tristate buffer for signal <obus<0>> created at line 136
Found 4-bit comparator greater for signal <quadacnt[3]_flimit[3]_LessThan_2_o> created at line 234
Found 4-bit comparator greater for signal <quadbcnt[3]_flimit[3]_LessThan_10_o> created at line 248
Found 4-bit comparator greater for signal <indexcnt[3]_flimit[3]_LessThan_18_o> created at line 262
Summary:
inferred 4 Adder/Subtractor(s).
inferred 84 D-type flip-flop(s).
inferred 3 Comparator(s).
inferred 38 Multiplexer(s).
inferred 32 Tristate(s).
Unit <qcounter> synthesized.
Synthesizing Unit <pwmrefh>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\pwmrefh.vhd".
buswidth = 16
refwidth = 13
Found 1-bit register for signal <pdmratelatchloadreq>.
Found 1-bit register for signal <pwmratelatchloadreq>.
Found 1-bit register for signal <oldpwmratelatchloadreq>.
Found 1-bit register for signal <olderpwmratelatchloadreq>.
Found 17-bit register for signal <pwmrateacc>.
Found 1-bit register for signal <oldpwmratemsb>.
Found 13-bit register for signal <count>.
Found 16-bit register for signal <pdmratelatch>.
Found 1-bit register for signal <oldpdmratelatchloadreq>.
Found 1-bit register for signal <olderpdmratelatchloadreq>.
Found 17-bit register for signal <pdmrateacc>.
Found 1-bit register for signal <oldpdmratemsb>.
Found 1-bit register for signal <prate>.
Found 16-bit register for signal <prepwmratelatch>.
Found 16-bit register for signal <prepdmratelatch>.
Found 16-bit register for signal <pwmratelatch>.
Found 17-bit adder for signal <pwmrateacc[16]_GND_348_o_add_1_OUT> created at line 124.
Found 13-bit adder for signal <count[12]_GND_348_o_add_2_OUT> created at line 127.
Found 17-bit adder for signal <pdmrateacc[16]_GND_348_o_add_5_OUT> created at line 136.
Summary:
inferred 3 Adder/Subtractor(s).
inferred 120 D-type flip-flop(s).
Unit <pwmrefh> synthesized.
Synthesizing Unit <pwmpdmgenh>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\pwmpdmgenh.vhd".
buswidth = 32
refwidth = 13
WARNING:Xst:647 - Input <ibus<15:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ibus<30:28>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit register for signal <loadpcrreq>.
Found 1-bit register for signal <loadpwmreq>.
Found 12-bit register for signal <pwmval>.
Found 1-bit register for signal <dir>.
Found 1-bit register for signal <oldloadpwmreq>.
Found 6-bit register for signal <modereg>.
Found 1-bit register for signal <olderloadpwmreq>.
Found 1-bit register for signal <olderloadpcrreq>.
Found 1-bit register for signal <oldloadpcrreq>.
Found 1-bit register for signal <pwm>.
Found 12-bit register for signal <fixedrefcount>.
Found 1-bit register for signal <oldtoggle>.
Found 12-bit register for signal <prepwmval>.
Found 1-bit register for signal <predir>.
Found 6-bit register for signal <premodereg>.
Found 13-bit register for signal <pdmaccum>.
Found 13-bit adder for signal <GND_349_o_GND_349_o_add_0_OUT> created at line 126.
Found 4x12-bit Read Only RAM for signal <mask>
Found 1-bit 4-to-1 multiplexer for signal <toggle> created at line 172.
Found 1-bit 4-to-1 multiplexer for signal <pwmouta> created at line 211.
Found 1-bit 4-to-1 multiplexer for signal <pwmoutb> created at line 211.
Found 12-bit comparator greater for signal <maskedrefcount[11]_pwmval[11]_LessThan_5_o> created at line 146
Summary:
inferred 1 RAM(s).
inferred 1 Adder/Subtractor(s).
inferred 71 D-type flip-flop(s).
inferred 1 Comparator(s).
inferred 8 Multiplexer(s).
Unit <pwmpdmgenh> synthesized.
Synthesizing Unit <boutreg_1>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\boutreg.vhd".
size = 2
buswidth = 2
invert = true
Found 2-bit register for signal <oreg>.
Found 1-bit tristate buffer for signal <obus<1>> created at line 93
Found 1-bit tristate buffer for signal <obus<0>> created at line 93
Summary:
inferred 2 D-type flip-flop(s).
inferred 2 Tristate(s).
Unit <boutreg_1> synthesized.
Synthesizing Unit <boutreg_2>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\boutreg.vhd".
size = 1
buswidth = 32
invert = false
WARNING:Xst:647 - Input <ibus<31:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit register for signal <oreg>.
Found 1-bit tristate buffer for signal <obus<31>> created at line 93
Found 1-bit tristate buffer for signal <obus<30>> created at line 93
Found 1-bit tristate buffer for signal <obus<29>> created at line 93
Found 1-bit tristate buffer for signal <obus<28>> created at line 93
Found 1-bit tristate buffer for signal <obus<27>> created at line 93
Found 1-bit tristate buffer for signal <obus<26>> created at line 93
Found 1-bit tristate buffer for signal <obus<25>> created at line 93
Found 1-bit tristate buffer for signal <obus<24>> created at line 93
Found 1-bit tristate buffer for signal <obus<23>> created at line 93
Found 1-bit tristate buffer for signal <obus<22>> created at line 93
Found 1-bit tristate buffer for signal <obus<21>> created at line 93
Found 1-bit tristate buffer for signal <obus<20>> created at line 93
Found 1-bit tristate buffer for signal <obus<19>> created at line 93
Found 1-bit tristate buffer for signal <obus<18>> created at line 93
Found 1-bit tristate buffer for signal <obus<17>> created at line 93
Found 1-bit tristate buffer for signal <obus<16>> created at line 93
Found 1-bit tristate buffer for signal <obus<15>> created at line 93
Found 1-bit tristate buffer for signal <obus<14>> created at line 93
Found 1-bit tristate buffer for signal <obus<13>> created at line 93
Found 1-bit tristate buffer for signal <obus<12>> created at line 93
Found 1-bit tristate buffer for signal <obus<11>> created at line 93
Found 1-bit tristate buffer for signal <obus<10>> created at line 93
Found 1-bit tristate buffer for signal <obus<9>> created at line 93
Found 1-bit tristate buffer for signal <obus<8>> created at line 93
Found 1-bit tristate buffer for signal <obus<7>> created at line 93
Found 1-bit tristate buffer for signal <obus<6>> created at line 93
Found 1-bit tristate buffer for signal <obus<5>> created at line 93
Found 1-bit tristate buffer for signal <obus<4>> created at line 93
Found 1-bit tristate buffer for signal <obus<3>> created at line 93
Found 1-bit tristate buffer for signal <obus<2>> created at line 93
Found 1-bit tristate buffer for signal <obus<1>> created at line 93
Found 1-bit tristate buffer for signal <obus<0>> created at line 93
Summary:
inferred 1 D-type flip-flop(s).
inferred 32 Tristate(s).
Unit <boutreg_2> synthesized.
Synthesizing Unit <IDROM>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\idrom.vhd".
idromtype = 3
offsettomodules = 64
offsettopindesc = 448
boardnamelow = "01000001010100110100010101001101"
boardnamehigh = "00110101001100100100100100110101"
fpgasize = 9
fpgapins = 144
ioports = 2
iowidth = 34
portwidth = 17
clocklow = 33333333
clockhigh = 200000000
inststride0 = 4
inststride1 = 64
regstride0 = 256
regstride1 = 256
pindesc =
("00000011000000000000011010000001","00000011000000000000010000000010","00000011000000000000010110000010","00000011000000000000010000000001","00000011000000000000010110000001","00000011000000000000010000000011","00000011000000010000010110000010","00000011000000000000000000000000","00000011000000010000010110000001","00000011000000100000010110000010","00000011000000100000010110000001","00000011000000110000010110000010","00000011000000110000010110000001","00000011000000000000000000000000","000000110
00000000000000000000000","00000011000000000000000000000000","00000011000000000000000000000000","00000011000000010000011010000001","00000011000000000000000000000000","00000011000001000000010110000010","00000011000000000000000000000000","00000011000001000000010110000001","00000011000000000000000000000000","00000011000001010000010110000010","00000011000000000000000000000000","00000011000001010000010110000001","00000011000001100000010110000010","00000011000001100000010110000001","00000011000001110000
010110000010","0000001
1000001110000010110000001","00000011000000000000000000000000","00000011000000010000010000000001","00000011000000010000010000000010","00000011000000010000010000000011","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","000000000000000000
00000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000
000","0000000000000000
0000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","000000000000000000000000000
00000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","000
0000000000000000000000
0000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","0
0000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","000000000000
00000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","0000000000
0000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000","00000000000000000000000000000000")
moduleid =
(("00000010","00000000","00000001","00000001","0000110000000000","00000011","00000000","00000000000000000000000000000000"),("00000011","00000000","00000001","00000010","0001000000000000","00000101","00000000","00000000000000000000000000011111"),("00000100","00000010","00000001","00000010","0011000000000000","00000101","00000000","00000000000000000000000000000011"),("00000101","00000010","00000001","00001000","0010000000000000","00001010","00000000","00000000000000000000000111111111"),("00000110",
"00000000","00000010","00000010","0100000100000000","00000101","00000000","00000000000000000000000000000011"),("10000000","00000000","00000001","00000001","0000001000000000","00000001","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","0
0000000","00000000","0
000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","00000000000000
00","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000
","00000000","00000000
"),("00000000","00000000
","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000",
"00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"))
Found 256x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.
Found 8-bit register for signal <dradd>.
000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","000000000000000000000
00000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000"),("00000000","00000000","00000000","00000000","0000000000000000","00000000","00000000","00000000000000000000000000000000>
created at line 285
Found 1-bit tristate buffer for signal <dout<30>> created at line 285
Found 1-bit tristate buffer for signal <dout<29>> created at line 285
Found 1-bit tristate buffer for signal <dout<28>> created at line 285
Found 1-bit tristate buffer for signal <dout<27>> created at line 285
Found 1-bit tristate buffer for signal <dout<26>> created at line 285
Found 1-bit tristate buffer for signal <dout<25>> created at line 285
Found 1-bit tristate buffer for signal <dout<24>> created at line 285
Found 1-bit tristate buffer for signal <dout<23>> created at line 285
Found 1-bit tristate buffer for signal <dout<22>> created at line 285
Found 1-bit tristate buffer for signal <dout<21>> created at line 285
Found 1-bit tristate buffer for signal <dout<20>> created at line 285
Found 1-bit tristate buffer for signal <dout<19>> created at line 285
Found 1-bit tristate buffer for signal <dout<18>> created at line 285
Found 1-bit tristate buffer for signal <dout<17>> created at line 285
Found 1-bit tristate buffer for signal <dout<16>> created at line 285
Found 1-bit tristate buffer for signal <dout<15>> created at line 285
Found 1-bit tristate buffer for signal <dout<14>> created at line 285
Found 1-bit tristate buffer for signal <dout<13>> created at line 285
Found 1-bit tristate buffer for signal <dout<12>> created at line 285
Found 1-bit tristate buffer for signal <dout<11>> created at line 285
Found 1-bit tristate buffer for signal <dout<10>> created at line 285
Found 1-bit tristate buffer for signal <dout<9>> created at line 285
Found 1-bit tristate buffer for signal <dout<8>> created at line 285
Found 1-bit tristate buffer for signal <dout<7>> created at line 285
Found 1-bit tristate buffer for signal <dout<6>> created at line 285
Found 1-bit tristate buffer for signal <dout<5>> created at line 285
Found 1-bit tristate buffer for signal <dout<4>> created at line 285
Found 1-bit tristate buffer for signal <dout<3>> created at line 285
Found 1-bit tristate buffer for signal <dout<2>> created at line 285
Found 1-bit tristate buffer for signal <dout<1>> created at line 285
Found 1-bit tristate buffer for signal <dout<0>> created at line 285
Summary:
inferred 1 RAM(s).
inferred 8 D-type flip-flop(s).
inferred 32 Tristate(s).
Unit <IDROM> synthesized.
Synthesizing Unit <simplespi8>.
Related source file is "C:\Users\Boris\Desktop\CameraMotion\MESA\5i25\configs\hostmot2\source\hostmot2\simplespi8x.vhd".
buswidth = 8
div = 2
bits = 8
Found 4-bit register for signal <BitCount>.
Found 1-bit register for signal <Go>.
Found 1-bit register for signal <Dav>.
Found 1-bit register for signal <ClockFF>.
Found 3-bit register for signal <RateDiv>.
Found 1-bit register for signal <CS>.
Found 8-bit register for signal <SPISregI>.
Found 8-bit register for signal <SPISregO>.
Found 4-bit subtractor for signal <GND_525_o_GND_525_o_sub_5_OUT<3:0>> created at line 134.
Found 3-bit subtractor for signal <GND_525_o_GND_525_o_sub_10_OUT<2:0>> created at line 141.
Found 1-bit tristate buffer for signal <obus<7>> created at line 108
Found 1-bit tristate buffer for signal <obus<6>> created at line 108
Found 1-bit tristate buffer for signal <obus<5>> created at line 108
Found 1-bit tristate buffer for signal <obus<4>> created at line 108
Found 1-bit tristate buffer for signal <obus<3>> created at line 108
Found 1-bit tristate buffer for signal <obus<2>> created at line 108
Found 1-bit tristate buffer for signal <obus<1>> created at line 108
Found 1-bit tristate buffer for signal <obus<0>> created at line 108
Summary:
inferred 2 Adder/Subtractor(s).
inferred 27 D-type flip-flop(s).
inferred 11 Multiplexer(s).
inferred 8 Tristate(s).
Unit <simplespi8> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# RAMs : 11
256x32-bit dual-port RAM : 1
4x12-bit single-port Read Only RAM : 2
4x2-bit single-port Read Only RAM : 8
# Adders/Subtractors : 54
12-bit subtractor : 1
13-bit adder : 3
14-bit subtractor : 16
16-bit adder : 1
16-bit addsub : 2
16-bit subtractor : 1
17-bit adder : 2
3-bit subtractor : 1
32-bit adder : 1
32-bit subtractor : 1
33-bit adder : 1
4-bit addsub : 14
4-bit subtractor : 2
48-bit adder : 8
# Registers : 321
1-bit register : 167
12-bit register : 8
13-bit register : 3
14-bit register : 49
16-bit register : 14
17-bit register : 12
2-bit register : 11
3-bit register : 1
32-bit register : 14
33-bit register : 1
4-bit register : 25
48-bit register : 8
5-bit register : 1
6-bit register : 4
8-bit register : 3
# Comparators : 17
12-bit comparator greater : 2
16-bit comparator equal : 1
4-bit comparator equal : 8
4-bit comparator greater : 6
# Multiplexers : 755
1-bit 2-to-1 multiplexer : 612
1-bit 4-to-1 multiplexer : 6
12-bit 2-to-1 multiplexer : 5
14-bit 2-to-1 multiplexer : 40
16-bit 2-to-1 multiplexer : 1
2-bit 2-to-1 multiplexer : 13
2-bit 4-to-1 multiplexer : 8
32-bit 2-to-1 multiplexer : 5
4-bit 2-to-1 multiplexer : 35
48-bit 2-to-1 multiplexer : 8
5-bit 2-to-1 multiplexer : 1
8-bit 2-to-1 multiplexer : 21
# Tristates : 805
1-bit tristate buffer : 804
6-bit tristate buffer : 1
# Xors : 17
1-bit xor2 : 16
1-bit xor36 : 1
=========================================================================
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <rated_0> (without init value) has a constant value of 0 in block <makeirqlogic.somoldirqlogic>. This FF/Latch will be trimmed during the optimization process.
Found 1-bit tristate buffer for signal <dout<31>WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_0> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_2> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_3> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_4> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_5> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_7> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_9> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_11> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_12> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_13> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_14> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_15> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_16> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_17> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_18> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_20> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_21> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_22> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_23> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_24> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_25> has a constant value of 1 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_26> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_28> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_29> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rated_1> (without init value) has a constant value of 0 in block <makeirqlogic.somoldirqlogic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_8> has a constant value of 1 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_9> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_10> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_11> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_12> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_13> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_14> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_15> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_16> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_17> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_18> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_19> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_20> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_21> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_22> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_23> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_24> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_25> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_26> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_27> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_28> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_29> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_30> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_31> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
Synthesizing (advanced) Unit <HostMot2>.
INFO:Xst:3226 - The RAM <IDROM/Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <IDROM/dradd>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 256-word x 32-bit | |
| mode | read-first | |
| clkA | connected to signal <clklow> | rise |
| weA | connected to signal <LoadIDROM> | high |
| addrA | connected to signal <A<9:2>> | |
| diA | connected to signal <ibus> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
|
| aspect ratio | 256-word x 32-bit | |
| mode | read-first | |
| clkB | connected to signal <clklow> | rise |
| addrB | connected to signal <addr<9:2>> | |
| doB | connected to internal node | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
Unit <HostMot2> synthesized (advanced).
Synthesizing (advanced) Unit <TopPCIHostMot2>.
The following registers are absorbed into counter <ICapTimer>: 1 register on signal <ICapTimer>.
Unit <TopPCIHostMot2> synthesized (advanced).
Synthesizing (advanced) Unit <pwmpdmgenh>.
INFO:Xst:3231 - The small RAM <Mram_mask> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4-word x 12-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <modereg<1:0>> | |
| diA | connected to signal <GND> | |
| doA | connected to signal <mask> | |
-----------------------------------------------------------------------
Unit <pwmpdmgenh> synthesized (advanced).
Synthesizing (advanced) Unit <pwmrefh>.
The following registers are absorbed into accumulator <pdmrateacc>: 1 register on signal <pdmrateacc>.
The following registers are absorbed into accumulator <pwmrateacc>: 1 register on signal <pwmrateacc>.
The following registers are absorbed into counter <count>: 1 register on signal <count>.
Unit <pwmrefh> synthesized (advanced).
Synthesizing (advanced) Unit <qcounter>.
The following registers are absorbed into counter <quadacnt>: 1 register on signal <quadacnt>.
The following registers are absorbed into counter <quadbcnt>: 1 register on signal <quadbcnt>.
The following registers are absorbed into counter <indexcnt>: 1 register on signal <indexcnt>.
The following registers are absorbed into counter <count>: 1 register on signal <count>.
Unit <qcounter> synthesized (advanced).
Synthesizing (advanced) Unit <qcounterate>.
The following registers are absorbed into counter <count>: 1 register on signal <count>.
Unit <qcounterate> synthesized (advanced).
Synthesizing (advanced) Unit <rategen>.
The following registers are absorbed into accumulator <rateaccum>: 1 register on signal <rateaccum>.
Unit <rategen> synthesized (advanced).
Synthesizing (advanced) Unit <simplespi8>.
The following registers are absorbed into counter <RateDiv>: 1 register on signal <RateDiv>.
Unit <simplespi8> synthesized (advanced).
Synthesizing (advanced) Unit <stepgen>.
INFO:Xst:3231 - The small RAM <Mram_stepaccum[31]_PWR_33_o_wide_mux_41_OUT> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
| Port B -----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4-word x 2-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <stepaccum<31:30>> | |
| diA | connected to signal <GND> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
Unit <stepgen> synthesized (advanced).
Synthesizing (advanced) Unit <timestamp>.
The following registers are absorbed into counter <div>: 1 register on signal <div>.
The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
Unit <timestamp> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 11
256x32-bit dual-port block RAM : 1
4x12-bit single-port distributed Read Only RAM : 2
4x2-bit single-port distributed Read Only RAM : 8
# Adders/Subtractors : 37
13-bit adder : 2
14-bit subtractor : 16
32-bit adder : 1
32-bit subtractor : 1
4-bit addsub : 8
4-bit subtractor : 1
48-bit adder : 8
# Counters : 14
12-bit down counter : 1
13-bit up counter : 1
16-bit down counter : 1
16-bit up counter : 1
16-bit updown counter : 2
3-bit down counter : 1
4-bit down counter : 1
4-bit updown counter : 6
# Accumulators : 3
17-bit up accumulator : 2
33-bit up accumulator : 1
# Registers : 2264
Flip-Flops : 2264
# Comparators : 17
12-bit comparator greater : 2
16-bit comparator equal : 1
4-bit comparator equal : 8
4-bit comparator greater : 6
# Multiplexers : 1155
1-bit 2-to-1 multiplexer : 1031
1-bit 4-to-1 multiplexer : 6
12-bit 2-to-1 multiplexer : 4
14-bit 2-to-1 multiplexer : 40
2-bit 2-to-1 multiplexer : 13
2-bit 4-to-1 multiplexer : 8
32-bit 2-to-1 multiplexer : 5
4-bit 2-to-1 multiplexer : 27
8-bit 2-to-1 multiplexer : 21
# Xors : 17
1-bit xor2 : 16
1-bit xor36 : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <rated_0> (without init value) has a constant value of 0 in block <irqlogics>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rated_1> (without init value) has a constant value of 0 in block <irqlogics>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <StatComReg_0> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_2> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_3> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_4> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_5> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_7> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_9> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_11> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_12> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_13> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_14> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_15> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_16> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_17> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_18> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_20> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_21> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_22> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_23> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_24> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_25> has a constant value of 1 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_26> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_28> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <StatComReg_29> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_8> has a constant value of 1 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_9> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_10> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_11> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_12> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_13> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_14> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_15> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_16> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_17> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_18> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_19> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_20> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_21> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_22> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_23> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_24> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_25> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_26> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_27> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_28> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_29> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_30> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <IntReg_31> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:1901 - Instance ClockMult1 in unit TopPCIHostMot2 of type DCM has been replaced by DCM_SP
INFO:Xst:1901 - Instance ClockMult0 in unit TopPCIHostMot2 of type DCM has been replaced by DCM_SP
WARNING:Xst:2040 - Unit TopPCIHostMot2: 32 multi-source signals are replaced by logic (pull-up yes): D<10>, D<11>, D<12>, D<13>, D<14>, D<15>, D<16>, D<17>, D<18>, D<19>, D<20>, D<21>, D<22>, D<23>, D<24>, D<25>, D<26>, D<27>, D<28>, D<29>, D<30>, D<31>, D<8>, D<9>, n0417<0>, n0417<1>, n0417<2>, n0417<3>, n0417<4>, n0417<5>, n0417<6>, n0417<7>.
, obus<5>, obus<6>, obus<7>.
WARNING:Xst:2042 - Unit hostmotid: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>.
WARNING:Xst:2042 - Unit wordrb: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>.
WARNING:Xst:2042 - Unit timestamp: 16 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<1>, obus<2>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>.
WARNING:Xst:2042 - Unit boutreg_2: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>.
WARNING:Xst:2042 - Unit stepgen: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>.
WARNING:Xst:2042 - Unit rategen: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>.
WARNING:Xst:2042 - Unit irqlogics: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>.
WARNING:Xst:2042 - Unit watchdog: 32 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<10>, obus<11>, obus<12>, obus<13>, obus<14>, obus<15>, obus<16>, obus<17>, obus<18>, obus<19>, obus<1>, obus<20>, obus<21>, obus<22>, obus<23>, obus<24>, obus<25>, obus<26>, obus<27>, obus<28>, obus<29>, obus<2>, obus<30>, obus<31>, obus<3>, obus<4>, obus<5>, obus<6>, obus<7>, obus<8>, obus<9>.
Optimizing unit <qcounterate> ...
Optimizing unit <TopPCIHostMot2> ...
WARNING:Xst:1293 - FF/Latch <StatComReg_27> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
Optimizing unit <pwmrefh> ...
WARNING:Xst:1293 - FF/Latch <asimplspi/RateDiv_2> has a constant value of 0 in block <TopPCIHostMot2>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <ahostmot2/makepwms.pwmref/count_0> in Unit <TopPCIHostMot2> is equivalent to the following FF/Latch, which will be removed : <ahostmot2/makepwms.pwmref/oldpwmratemsb>
INFO:Xst:3203 - The FF/Latch <asimplspi/Dav> in Unit <TopPCIHostMot2> is the opposite to the following FF/Latch, which will be removed : <asimplspi/Go>
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block TopPCIHostMot2, actual ratio is 84.
FlipFlop IPar has been replicated 1 time(s) to handle iob=true attribute.
WARNING:Xst:2042 - Unit simplespi8: 8 internal tristates are replaced by logic (pull-up yes): obus<0>, obus<1>, obus<2>, obus<3>, obus<4>
Final Macro Processing ...
Processing Unit <TopPCIHostMot2> :
Found 2-bit shift register for signal <SerrStb1>.
Unit <TopPCIHostMot2> processed.
=========================================================================
Final Register Report
Macro Statistics
# Registers : 2396
Flip-Flops : 2396
# Shift Registers : 1
2-bit shift register : 1
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Clock Information:
------------------
-----------------------------------+--------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+--------------------------+-------+
PCLK | BUFGP | 2230 |
XCLK | DCM_SP:CLKFX+DCM_SP:CLKFX| 185 |
-----------------------------------+--------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -2
Minimum period: 13.866ns (Maximum Frequency: 72.119MHz)
Minimum input arrival time before clock: 11.918ns
Maximum output required time after clock: 14.757ns
Maximum combinational path delay: 15.667ns
=========================================================================
Process "Synthesize - XST" completed successfully
Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -aut -nt timestamp -uc 5i25.ucf -p xc6slx9-tqg144-2 TopPCIHostMot2.ngc TopPCIHostMot2.ngd
Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -aut -nt timestamp -uc 5i25.ucf -p xc6slx9-tqg144-2
TopPCIHostMot2.ngc TopPCIHostMot2.ngd
Reading NGO file
"C:/Users/Boris/Desktop/CameraMotion/MESA/5i25/configs/hostmot2/source/hostmot2/
TopPCIHostMot2.ngc" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "5i25.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem - TNM : async_med was distributed to a DCM but new TNM
constraints were not derived. This TNM is used in the following user groups
or specifications:
<TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;>
[5i25.ucf(120)]
<TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;>
[5i25.ucf(121)]
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 1
Writing NGD file "TopPCIHostMot2.ngd" ...
Total REAL time to NGDBUILD completion: 5 sec
Total CPU time to NGDBUILD completion: 5 sec
Writing NGDBUILD log file "TopPCIHostMot2.bld"...
NGDBUILD done.
Process "Translate" completed successfully
Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr b -lc off -power off -o TopPCIHostMot2_map.ncd TopPCIHostMot2.ngd TopPCIHostMot2.pcf
Using target part "6slx9tqg144-2".
Mapping design into LUTs...
WARNING:MapLib:701 - Signal NINIT connected to top level port NINIT has been
removed.
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
WARNING:Timing:3223 - Timing constraint PATH "TSLowToMed_path" TIG ignored during timing analysis.
WARNING:Timing:3223 - Timing constraint PATH "TSMedtoLow_path" TIG ignored during timing analysis.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 9 secs
Total CPU time at the beginning of Placer: 9 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:88d680ca) REAL time: 10 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:88d680ca) REAL time: 11 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:88d680ca) REAL time: 11 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
REAL time: 14 secs
(Checksum:be42f7aa) Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:be42f7aa) REAL time: 14 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:be42f7aa) REAL time: 14 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:1d0f672f) REAL time: 14 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:1d0f672f) REAL time: 15 secs
Phase 9.8 Global Placement
..............
........................................
.....................................................................................................................................................
.....................................................................................................................................
.............
REAL time: 31 secs
Phase 9.8 Global Placement (Checksum:8cf95a7e) Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:8cf95a7e) REAL time: 31 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:1dbe6008) REAL time: 35 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:1dbe6008) REAL time: 35 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:217f44ba) REAL time: 35 secs
Total REAL time to Placer completion: 35 secs
Total CPU time to Placer completion: 35 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 4
Slice Logic Utilization:
Number of Slice Registers: 2,349 out of 11,440 20%
Number used as Flip Flops: 2,349
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 2,510 out of 5,720 43%
Number used as logic: 2,452 out of 5,720 42%
Number using O6 output only: 1,627
Number using O5 output only: 70
Number using O5 and O6: 755
Number used as ROM: 0
Number used as Memory: 17 out of 1,440 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 17
Number using O6 output only: 17
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 41
Number with same-slice register load: 35
Number with same-slice carry load: 6
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,009 out of 1,430 70%
Number of MUXCYs used: 1,312 out of 2,860 45%
Number of LUT Flip Flop pairs used: 3,335
Number with an unused Flip Flop: 1,122 out of 3,335 33%
Number with an unused LUT: 825 out of 3,335 24%
Number of fully used LUT-FF pairs: 1,388 out of 3,335 41%
Number of unique control sets: 147
Number of slice register sites lost
to control set restrictions: 466 out of 11,440 4%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 91 out of 102 89%
Number of LOCed IOBs: 91 out of 91 100%
IOB Flip Flops: 48
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 1 out of 64 1%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 5 out of 16 31%
Number used as BUFGs: 5
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 2 out of 4 50%
Number used as DCMs: 2
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 46 out of 200 23%
Number used as ILOGIC2s: 46
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 2 out of 200 1%
Number used as OLOGIC2s: 2
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 16 0%
Number of ICAPs: 1 out of 1 100%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.35
Peak Memory Usage: 423 MB
Total REAL time to MAP completion: 38 secs
Total CPU time to MAP completion: 38 secs
Mapping completed.
See MAP report file "TopPCIHostMot2_map.mrp" for details.
Process "Map" completed successfully
Started : "Place & Route".
Running par...
Command Line: par -w -intstyle ise -ol high -mt off TopPCIHostMot2_map.ncd TopPCIHostMot2.ncd TopPCIHostMot2.pcf
Constraints file: TopPCIHostMot2.pcf.
Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
"TopPCIHostMot2" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 2,349 out of 11,440 20%
Number used as Flip Flops: 2,349
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 2,510 out of 5,720 43%
Number used as logic: 2,452 out of 5,720 42%
Number using O6 output only: 1,627
Number using O5 output only: 70
Number using O5 and O6: 755
Number used as ROM: 0
Number used as Memory: 17 out of 1,440 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 17
Number using O6 output only: 17
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 41
Number with same-slice register load: 35
Number with same-slice carry load: 6
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,009 out of 1,430 70%
Number of MUXCYs used: 1,312 out of 2,860 45%
Number of LUT Flip Flop pairs used: 3,335
Number with an unused Flip Flop: 1,122 out of 3,335 33%
Number with an unused LUT: 825 out of 3,335 24%
Number of fully used LUT-FF pairs: 1,388 out of 3,335 41%
Number of slice register sites lost
to control set restrictions: 0 out of 11,440 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 91 out of 102 89%
Number of LOCed IOBs: 91 out of 91 100%
IOB Flip Flops: 48
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 1 out of 64 1%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 5 out of 16 31%
Number used as BUFGs: 5
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 2 out of 4 50%
Number used as DCMs: 2
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 46 out of 200 23%
Number used as ILOGIC2s: 46
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 2 out of 200 1%
Number used as OLOGIC2s: 2
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 16 0%
Number of ICAPs: 1 out of 1 100%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
WARNING:Timing:3223 - Timing constraint PATH "TSLowToMed_path" TIG; ignored during timing analysis.
WARNING:Timing:3223 - Timing constraint PATH "TSMedtoLow_path" TIG; ignored during timing analysis.
Starting initial Timing Analysis. REAL time: 5 secs
REAL time: 6 secs
Finished initial Timing Analysis. WARNING:Par:288 - The signal NLOCK_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
REAL time: 6 secs
Phase 1 : 14185 unrouted;
REAL time: 7 secs
Phase 2 : 12269 unrouted;
Phase 3 : 5060 unrouted; REAL time: 13 secs
(Setup:0, Hold:0, Component Switching Limit:0) REAL time: 14 secs
Phase 4 : 5060 unrouted;
Updating file: TopPCIHostMot2.ncd with current fully routed design.
(Setup:0, Hold:0, Component Switching Limit:0) REAL time: 21 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 21 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 21 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 21 secs
Phase 5 : 0 unrouted;
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 21 secs
(Setup:0, Hold:0, Component Switching Limit:0) REAL time: 21 secs
Phase 10 : 0 unrouted; Total REAL time to Router completion: 21 secs
Total CPU time to Router completion: 22 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| PCLK_BUFGP | BUFGMUX_X2Y9| No 694 | 0.698 | 2.089 |
+---------------------+--------------+------+------+------------+-------------+
| BUFGMUX_X2Y2| No | 57 | 0.077 | 1.471 |
+---------------------+--------------+------+------+------------+-------------+
| ICapClock | Local| | 1 | 0.000 | 2.119 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 4
|| fclk
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_clkfx0 = PERIOD TIMEGRP "clkfx0" TS_cl | SETUP | 1.308ns| 3.692ns| 0| 0
kfx1 / 2 HIGH 50% | HOLD | 0.401ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_clkfx1 = PERIOD TIMEGRP "clkfx1" TS_XC | MINLOWPULSE | 4.660ns| 5.340ns| 0| 0
LK / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_XCLK = PERIOD TIMEGRP "XCLK" 20 ns HIG | MINLOWPULSE | 12.000ns| 8.000ns| 0| 0
H 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_PCLK = PERIOD TIMEGRP "PCLK" 30 ns HIG | SETUP | 17.692ns| 12.308ns| 0| 0
H 50% | HOLD | 0.394ns| | 0| 0
----------------------------------------------------------------------------------------------------------
PATH "TSLowToMed_path" TIG | N/A | N/A| N/A| N/A| N/A
----------------------------------------------------------------------------------------------------------
PATH "TSMedtoLow_path" TIG | N/A | N/A| N/A| N/A| N/A
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_XCLK
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_XCLK | 20.000ns| 8.000ns| 14.768ns| 0| 0| 0| 2036|
| TS_clkfx1 | 10.000ns| 5.340ns| 7.384ns| 0| 0| 0| 2036|
| TS_clkfx0 | 5.000ns| 3.692ns| N/A| 0| 0| 2036| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 23 secs
Total CPU time to PAR completion: 23 secs
Peak Memory Usage: 368 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 5
Number of info messages: 0
Writing design to file TopPCIHostMot2.ncd
PAR done!
Process "Place & Route" completed successfully
Started : "Generate Post-Place & Route Static Timing".
Running trce...
Command Line: trce -intstyle ise -v 10 -s 2 -n 3 -fastpaths -xml TopPCIHostMot2.twx TopPCIHostMot2.ncd -o TopPCIHostMot2.twr TopPCIHostMot2.pcf -ucf 5i25.ucf
Loading device for application Rf_Device from file '6slx9.nph' in environment
C:\Xilinx\14.7\ISE_DS\ISE\.
"TopPCIHostMot2" is an NCD, version 3.2, device xc6slx9, package tqg144,
speed -2
WARNING:Timing:3223 - Timing constraint PATH "TSLowToMed_path" TIG; ignored
during timing analysis.
WARNING:Timing:3223 - Timing constraint PATH "TSMedtoLow_path" TIG; ignored
during timing analysis.
Analysis completed Sun Oct 11 12:22:31 2015
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 2
Total time: 7 secs
Process "Generate Post-Place & Route Static Timing" completed successfully
Started : "Generate Programming File".
Running bitgen...
Command Line: bitgen -intstyle ise -f TopPCIHostMot2.ut TopPCIHostMot2.ncd
WARNING:Bitgen:284 - Setting next_config_register_write to Disable will cause
the next_config_addr, next_config_new_mode, and next_config_boot_mode options
to be ignored and their respective register writes to be excluded from the
bitstream.
INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER).
9K Block RAM initialization data, both user defined and default, requires a
special bit stream format. For more information, please reference Xilinx
Answer Record 39999.
INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
with the CLKFX and CLKFX180 outputs of the DCM comp ClockMult0, consult the
device Data Sheet.
INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
with the CLKFX and CLKFX180 outputs of the DCM comp ClockMult1, consult the
device Data Sheet.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
INFO:WebTalk:4 -
C:/Users/Boris/Desktop/CameraMotion/MESA/5i25/configs/hostmot2/source/hostmot2/u
sage_statistics_webtalk.html WebTalk report has been successfully sent to
Xilinx. For additional details about this file, please refer to the WebTalk log
file at
C:/Users/Boris/Desktop/CameraMotion/MESA/5i25/configs/hostmot2/source/hostmot2/w
ebtalk.log
WebTalk is complete.
Process "Generate Programming File" completed successfully
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