|
/dts-v1/; |
|
|
|
/ { |
|
compatible = "pine64,pinebook-pro\0rockchip,rk3399"; |
|
interrupt-parent = <0x01>; |
|
#address-cells = <0x02>; |
|
#size-cells = <0x02>; |
|
model = "Pine64 Pinebook Pro"; |
|
chassis-type = "laptop"; |
|
|
|
aliases { |
|
ethernet0 = "/ethernet@fe300000"; |
|
i2c0 = "/i2c@ff3c0000"; |
|
i2c1 = "/i2c@ff110000"; |
|
i2c2 = "/i2c@ff120000"; |
|
i2c3 = "/i2c@ff130000"; |
|
i2c4 = "/i2c@ff3d0000"; |
|
i2c5 = "/i2c@ff140000"; |
|
i2c6 = "/i2c@ff150000"; |
|
i2c7 = "/i2c@ff160000"; |
|
i2c8 = "/i2c@ff3e0000"; |
|
serial0 = "/serial@ff180000"; |
|
serial1 = "/serial@ff190000"; |
|
serial2 = "/serial@ff1a0000"; |
|
serial3 = "/serial@ff1b0000"; |
|
serial4 = "/serial@ff370000"; |
|
mmc0 = "/mmc@fe310000"; |
|
mmc1 = "/mmc@fe320000"; |
|
mmc2 = "/mmc@fe330000"; |
|
}; |
|
|
|
cpus { |
|
#address-cells = <0x02>; |
|
#size-cells = <0x00>; |
|
|
|
cpu-map { |
|
|
|
cluster0 { |
|
|
|
core0 { |
|
cpu = <0x02>; |
|
}; |
|
|
|
core1 { |
|
cpu = <0x03>; |
|
}; |
|
|
|
core2 { |
|
cpu = <0x04>; |
|
}; |
|
|
|
core3 { |
|
cpu = <0x05>; |
|
}; |
|
}; |
|
|
|
cluster1 { |
|
|
|
core0 { |
|
cpu = <0x06>; |
|
}; |
|
|
|
core1 { |
|
cpu = <0x07>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu@0 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a53"; |
|
reg = <0x00 0x00>; |
|
enable-method = "psci"; |
|
capacity-dmips-mhz = <0x1e5>; |
|
clocks = <0x08 0x08>; |
|
#cooling-cells = <0x02>; |
|
dynamic-power-coefficient = <0x64>; |
|
cpu-idle-states = <0x09 0x0a>; |
|
operating-points-v2 = <0x0b>; |
|
cpu-supply = <0x0c>; |
|
phandle = <0x02>; |
|
}; |
|
|
|
cpu@1 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a53"; |
|
reg = <0x00 0x01>; |
|
enable-method = "psci"; |
|
capacity-dmips-mhz = <0x1e5>; |
|
clocks = <0x08 0x08>; |
|
#cooling-cells = <0x02>; |
|
dynamic-power-coefficient = <0x64>; |
|
cpu-idle-states = <0x09 0x0a>; |
|
operating-points-v2 = <0x0b>; |
|
cpu-supply = <0x0c>; |
|
phandle = <0x03>; |
|
}; |
|
|
|
cpu@2 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a53"; |
|
reg = <0x00 0x02>; |
|
enable-method = "psci"; |
|
capacity-dmips-mhz = <0x1e5>; |
|
clocks = <0x08 0x08>; |
|
#cooling-cells = <0x02>; |
|
dynamic-power-coefficient = <0x64>; |
|
cpu-idle-states = <0x09 0x0a>; |
|
operating-points-v2 = <0x0b>; |
|
cpu-supply = <0x0c>; |
|
phandle = <0x04>; |
|
}; |
|
|
|
cpu@3 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a53"; |
|
reg = <0x00 0x03>; |
|
enable-method = "psci"; |
|
capacity-dmips-mhz = <0x1e5>; |
|
clocks = <0x08 0x08>; |
|
#cooling-cells = <0x02>; |
|
dynamic-power-coefficient = <0x64>; |
|
cpu-idle-states = <0x09 0x0a>; |
|
operating-points-v2 = <0x0b>; |
|
cpu-supply = <0x0c>; |
|
phandle = <0x05>; |
|
}; |
|
|
|
cpu@100 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a72"; |
|
reg = <0x00 0x100>; |
|
enable-method = "psci"; |
|
capacity-dmips-mhz = <0x400>; |
|
clocks = <0x08 0x09>; |
|
#cooling-cells = <0x02>; |
|
dynamic-power-coefficient = <0x1b4>; |
|
cpu-idle-states = <0x09 0x0a>; |
|
operating-points-v2 = <0x0d>; |
|
cpu-supply = <0x0e>; |
|
phandle = <0x06>; |
|
|
|
thermal-idle { |
|
#cooling-cells = <0x02>; |
|
duration-us = <0x2710>; |
|
exit-latency-us = <0x1f4>; |
|
}; |
|
}; |
|
|
|
cpu@101 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a72"; |
|
reg = <0x00 0x101>; |
|
enable-method = "psci"; |
|
capacity-dmips-mhz = <0x400>; |
|
clocks = <0x08 0x09>; |
|
#cooling-cells = <0x02>; |
|
dynamic-power-coefficient = <0x1b4>; |
|
cpu-idle-states = <0x09 0x0a>; |
|
operating-points-v2 = <0x0d>; |
|
cpu-supply = <0x0e>; |
|
phandle = <0x07>; |
|
|
|
thermal-idle { |
|
#cooling-cells = <0x02>; |
|
duration-us = <0x2710>; |
|
exit-latency-us = <0x1f4>; |
|
}; |
|
}; |
|
|
|
idle-states { |
|
entry-method = "psci"; |
|
|
|
cpu-sleep { |
|
compatible = "arm,idle-state"; |
|
local-timer-stop; |
|
arm,psci-suspend-param = <0x10000>; |
|
entry-latency-us = <0x78>; |
|
exit-latency-us = <0xfa>; |
|
min-residency-us = <0x384>; |
|
phandle = <0x09>; |
|
}; |
|
|
|
cluster-sleep { |
|
compatible = "arm,idle-state"; |
|
local-timer-stop; |
|
arm,psci-suspend-param = <0x1010000>; |
|
entry-latency-us = <0x190>; |
|
exit-latency-us = <0x1f4>; |
|
min-residency-us = <0x7d0>; |
|
phandle = <0x0a>; |
|
}; |
|
}; |
|
}; |
|
|
|
display-subsystem { |
|
compatible = "rockchip,display-subsystem"; |
|
ports = <0x0f 0x10>; |
|
}; |
|
|
|
memory-controller { |
|
compatible = "rockchip,rk3399-dmc"; |
|
rockchip,pmu = <0x11>; |
|
devfreq-events = <0x12>; |
|
clocks = <0x08 0xa8>; |
|
clock-names = "dmc_clk"; |
|
status = "disabled"; |
|
phandle = <0xdd>; |
|
}; |
|
|
|
pmu_a53 { |
|
compatible = "arm,cortex-a53-pmu"; |
|
interrupts = <0x01 0x07 0x08 0x13>; |
|
}; |
|
|
|
pmu_a72 { |
|
compatible = "arm,cortex-a72-pmu"; |
|
interrupts = <0x01 0x07 0x08 0x14>; |
|
}; |
|
|
|
psci { |
|
compatible = "arm,psci-1.0"; |
|
method = "smc"; |
|
}; |
|
|
|
timer { |
|
compatible = "arm,armv8-timer"; |
|
interrupts = <0x01 0x0d 0x08 0x00 0x01 0x0e 0x08 0x00 0x01 0x0b 0x08 0x00 0x01 0x0a 0x08 0x00>; |
|
arm,no-tick-in-suspend; |
|
}; |
|
|
|
xin24m { |
|
compatible = "fixed-clock"; |
|
clock-frequency = <0x16e3600>; |
|
clock-output-names = "xin24m"; |
|
#clock-cells = <0x00>; |
|
phandle = <0x98>; |
|
}; |
|
|
|
pcie@f8000000 { |
|
compatible = "rockchip,rk3399-pcie"; |
|
reg = <0x00 0xf8000000 0x00 0x2000000 0x00 0xfd000000 0x00 0x1000000>; |
|
reg-names = "axi-base\0apb-base"; |
|
device_type = "pci"; |
|
#address-cells = <0x03>; |
|
#size-cells = <0x02>; |
|
#interrupt-cells = <0x01>; |
|
aspm-no-l0s; |
|
bus-range = <0x00 0x1f>; |
|
clocks = <0x08 0xc5 0x08 0xc4 0x08 0x147 0x08 0xa0>; |
|
clock-names = "aclk\0aclk-perf\0hclk\0pm"; |
|
interrupts = <0x00 0x31 0x04 0x00 0x00 0x32 0x04 0x00 0x00 0x33 0x04 0x00>; |
|
interrupt-names = "sys\0legacy\0client"; |
|
interrupt-map-mask = <0x00 0x00 0x00 0x07>; |
|
interrupt-map = <0x00 0x00 0x00 0x01 0x15 0x00 0x00 0x00 0x00 0x02 0x15 0x01 0x00 0x00 0x00 0x03 0x15 0x02 0x00 0x00 0x00 0x04 0x15 0x03>; |
|
max-link-speed = <0x01>; |
|
msi-map = <0x00 0x16 0x00 0x1000>; |
|
phys = <0x17 0x00 0x17 0x01 0x17 0x02 0x17 0x03>; |
|
phy-names = "pcie-phy-0\0pcie-phy-1\0pcie-phy-2\0pcie-phy-3"; |
|
ranges = <0x82000000 0x00 0xfa000000 0x00 0xfa000000 0x00 0x1e00000 0x81000000 0x00 0xfbe00000 0x00 0xfbe00000 0x00 0x100000>; |
|
resets = <0x08 0x82 0x08 0x83 0x08 0x84 0x08 0x85 0x08 0x86 0x08 0x81 0x08 0x80>; |
|
reset-names = "core\0mgmt\0mgmt-sticky\0pipe\0pm\0pclk\0aclk"; |
|
status = "okay"; |
|
bus-scan-delay-ms = <0x3e8>; |
|
ep-gpios = <0x18 0x1c 0x00>; |
|
num-lanes = <0x04>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x19>; |
|
vpcie0v9-supply = <0x1a>; |
|
vpcie1v8-supply = <0x1b>; |
|
vpcie3v3-supply = <0x1c>; |
|
phandle = <0xde>; |
|
|
|
interrupt-controller { |
|
interrupt-controller; |
|
#address-cells = <0x00>; |
|
#interrupt-cells = <0x01>; |
|
phandle = <0x15>; |
|
}; |
|
}; |
|
|
|
ethernet@fe300000 { |
|
compatible = "rockchip,rk3399-gmac"; |
|
reg = <0x00 0xfe300000 0x00 0x10000>; |
|
interrupts = <0x00 0x0c 0x04 0x00>; |
|
interrupt-names = "macirq"; |
|
clocks = <0x08 0x69 0x08 0x67 0x08 0x68 0x08 0x66 0x08 0x6a 0x08 0xd5 0x08 0x166>; |
|
clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_ref\0clk_mac_refout\0aclk_mac\0pclk_mac"; |
|
power-domains = <0x1d 0x16>; |
|
resets = <0x08 0x89>; |
|
reset-names = "stmmaceth"; |
|
rockchip,grf = <0x1e>; |
|
snps,txpbl = <0x04>; |
|
status = "disabled"; |
|
phandle = <0xdf>; |
|
}; |
|
|
|
mmc@fe310000 { |
|
compatible = "rockchip,rk3399-dw-mshc\0rockchip,rk3288-dw-mshc"; |
|
reg = <0x00 0xfe310000 0x00 0x4000>; |
|
interrupts = <0x00 0x40 0x04 0x00>; |
|
max-frequency = <0x8f0d180>; |
|
clocks = <0x08 0x1ee 0x08 0x4d 0x08 0x9c 0x08 0x9d>; |
|
clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; |
|
fifo-depth = <0x100>; |
|
power-domains = <0x1d 0x1c>; |
|
resets = <0x08 0x79>; |
|
reset-names = "reset"; |
|
status = "okay"; |
|
bus-width = <0x04>; |
|
cap-sd-highspeed; |
|
cap-sdio-irq; |
|
keep-power-in-suspend; |
|
mmc-pwrseq = <0x1f>; |
|
non-removable; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x20 0x21 0x22>; |
|
sd-uhs-sdr104; |
|
phandle = <0xe0>; |
|
}; |
|
|
|
mmc@fe320000 { |
|
compatible = "rockchip,rk3399-dw-mshc\0rockchip,rk3288-dw-mshc"; |
|
reg = <0x00 0xfe320000 0x00 0x4000>; |
|
interrupts = <0x00 0x41 0x04 0x00>; |
|
max-frequency = <0x8f0d180>; |
|
assigned-clocks = <0x08 0x1cd>; |
|
assigned-clock-rates = <0xbebc200>; |
|
clocks = <0x08 0x1ce 0x08 0x4c 0x08 0x9a 0x08 0x9b>; |
|
clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; |
|
fifo-depth = <0x100>; |
|
power-domains = <0x1d 0x1b>; |
|
resets = <0x08 0x7a>; |
|
reset-names = "reset"; |
|
status = "okay"; |
|
bus-width = <0x04>; |
|
cap-mmc-highspeed; |
|
cap-sd-highspeed; |
|
cd-gpios = <0x23 0x07 0x01>; |
|
disable-wp; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x24 0x25 0x26>; |
|
sd-uhs-sdr50; |
|
vmmc-supply = <0x27>; |
|
vqmmc-supply = <0x28>; |
|
phandle = <0xe1>; |
|
}; |
|
|
|
mmc@fe330000 { |
|
compatible = "rockchip,rk3399-sdhci-5.1\0arasan,sdhci-5.1"; |
|
reg = <0x00 0xfe330000 0x00 0x10000>; |
|
interrupts = <0x00 0x0b 0x04 0x00>; |
|
arasan,soc-ctl-syscon = <0x1e>; |
|
assigned-clocks = <0x08 0x4e>; |
|
assigned-clock-rates = <0xbebc200>; |
|
clocks = <0x08 0x4e 0x08 0xf0>; |
|
clock-names = "clk_xin\0clk_ahb"; |
|
clock-output-names = "emmc_cardclock"; |
|
#clock-cells = <0x00>; |
|
phys = <0x29>; |
|
phy-names = "phy_arasan"; |
|
power-domains = <0x1d 0x17>; |
|
disable-cqe-dcmd; |
|
status = "okay"; |
|
bus-width = <0x08>; |
|
mmc-hs200-1_8v; |
|
non-removable; |
|
phandle = <0x9b>; |
|
}; |
|
|
|
usb@fe380000 { |
|
compatible = "generic-ehci"; |
|
reg = <0x00 0xfe380000 0x00 0x20000>; |
|
interrupts = <0x00 0x1a 0x04 0x00>; |
|
clocks = <0x08 0x1c8 0x08 0x1c9 0x2a>; |
|
phys = <0x2b>; |
|
phy-names = "usb"; |
|
status = "okay"; |
|
phandle = <0xe2>; |
|
}; |
|
|
|
usb@fe3a0000 { |
|
compatible = "generic-ohci"; |
|
reg = <0x00 0xfe3a0000 0x00 0x20000>; |
|
interrupts = <0x00 0x1c 0x04 0x00>; |
|
clocks = <0x08 0x1c8 0x08 0x1c9 0x2a>; |
|
phys = <0x2b>; |
|
phy-names = "usb"; |
|
status = "okay"; |
|
phandle = <0xe3>; |
|
}; |
|
|
|
usb@fe3c0000 { |
|
compatible = "generic-ehci"; |
|
reg = <0x00 0xfe3c0000 0x00 0x20000>; |
|
interrupts = <0x00 0x1e 0x04 0x00>; |
|
clocks = <0x08 0x1ca 0x08 0x1cb 0x2c>; |
|
phys = <0x2d>; |
|
phy-names = "usb"; |
|
status = "okay"; |
|
phandle = <0xe4>; |
|
}; |
|
|
|
usb@fe3e0000 { |
|
compatible = "generic-ohci"; |
|
reg = <0x00 0xfe3e0000 0x00 0x20000>; |
|
interrupts = <0x00 0x20 0x04 0x00>; |
|
clocks = <0x08 0x1ca 0x08 0x1cb 0x2c>; |
|
phys = <0x2d>; |
|
phy-names = "usb"; |
|
status = "okay"; |
|
phandle = <0xe5>; |
|
}; |
|
|
|
debug@fe430000 { |
|
compatible = "arm,coresight-cpu-debug\0arm,primecell"; |
|
reg = <0x00 0xfe430000 0x00 0x1000>; |
|
clocks = <0x08 0x14d>; |
|
clock-names = "apb_pclk"; |
|
cpu = <0x02>; |
|
}; |
|
|
|
debug@fe432000 { |
|
compatible = "arm,coresight-cpu-debug\0arm,primecell"; |
|
reg = <0x00 0xfe432000 0x00 0x1000>; |
|
clocks = <0x08 0x14d>; |
|
clock-names = "apb_pclk"; |
|
cpu = <0x03>; |
|
}; |
|
|
|
debug@fe434000 { |
|
compatible = "arm,coresight-cpu-debug\0arm,primecell"; |
|
reg = <0x00 0xfe434000 0x00 0x1000>; |
|
clocks = <0x08 0x14d>; |
|
clock-names = "apb_pclk"; |
|
cpu = <0x04>; |
|
}; |
|
|
|
debug@fe436000 { |
|
compatible = "arm,coresight-cpu-debug\0arm,primecell"; |
|
reg = <0x00 0xfe436000 0x00 0x1000>; |
|
clocks = <0x08 0x14d>; |
|
clock-names = "apb_pclk"; |
|
cpu = <0x05>; |
|
}; |
|
|
|
debug@fe610000 { |
|
compatible = "arm,coresight-cpu-debug\0arm,primecell"; |
|
reg = <0x00 0xfe610000 0x00 0x1000>; |
|
clocks = <0x08 0x14c>; |
|
clock-names = "apb_pclk"; |
|
cpu = <0x06>; |
|
}; |
|
|
|
debug@fe710000 { |
|
compatible = "arm,coresight-cpu-debug\0arm,primecell"; |
|
reg = <0x00 0xfe710000 0x00 0x1000>; |
|
clocks = <0x08 0x14c>; |
|
clock-names = "apb_pclk"; |
|
cpu = <0x07>; |
|
}; |
|
|
|
usb@fe800000 { |
|
compatible = "rockchip,rk3399-dwc3"; |
|
#address-cells = <0x02>; |
|
#size-cells = <0x02>; |
|
ranges; |
|
clocks = <0x08 0x81 0x08 0x83 0x08 0xf6 0x08 0xf8 0x08 0xf4 0x08 0xf9>; |
|
clock-names = "ref_clk\0suspend_clk\0bus_clk\0aclk_usb3_rksoc_axi_perf\0aclk_usb3\0grf_clk"; |
|
resets = <0x08 0x125>; |
|
reset-names = "usb3-otg"; |
|
status = "okay"; |
|
phandle = <0xe6>; |
|
|
|
usb@fe800000 { |
|
compatible = "snps,dwc3"; |
|
reg = <0x00 0xfe800000 0x00 0x100000>; |
|
interrupts = <0x00 0x69 0x04 0x00>; |
|
clocks = <0x08 0x81 0x08 0xf6 0x08 0x83>; |
|
clock-names = "ref\0bus_early\0suspend"; |
|
dr_mode = "host"; |
|
phys = <0x2e 0x2f>; |
|
phy-names = "usb2-phy\0usb3-phy"; |
|
phy_type = "utmi_wide"; |
|
snps,dis_enblslpm_quirk; |
|
snps,dis-u2-freeclk-exists-quirk; |
|
snps,dis_u2_susphy_quirk; |
|
snps,dis-del-phy-power-chg-quirk; |
|
snps,dis-tx-ipgap-linecheck-quirk; |
|
power-domains = <0x1d 0x18>; |
|
status = "okay"; |
|
phandle = <0xe7>; |
|
}; |
|
}; |
|
|
|
usb@fe900000 { |
|
compatible = "rockchip,rk3399-dwc3"; |
|
#address-cells = <0x02>; |
|
#size-cells = <0x02>; |
|
ranges; |
|
clocks = <0x08 0x82 0x08 0x84 0x08 0xf7 0x08 0xf8 0x08 0xf4 0x08 0xf9>; |
|
clock-names = "ref_clk\0suspend_clk\0bus_clk\0aclk_usb3_rksoc_axi_perf\0aclk_usb3\0grf_clk"; |
|
resets = <0x08 0x126>; |
|
reset-names = "usb3-otg"; |
|
status = "okay"; |
|
phandle = <0xe8>; |
|
|
|
usb@fe900000 { |
|
compatible = "snps,dwc3"; |
|
reg = <0x00 0xfe900000 0x00 0x100000>; |
|
interrupts = <0x00 0x6e 0x04 0x00>; |
|
clocks = <0x08 0x82 0x08 0xf7 0x08 0x84>; |
|
clock-names = "ref\0bus_early\0suspend"; |
|
dr_mode = "host"; |
|
phys = <0x30 0x31>; |
|
phy-names = "usb2-phy\0usb3-phy"; |
|
phy_type = "utmi_wide"; |
|
snps,dis_enblslpm_quirk; |
|
snps,dis-u2-freeclk-exists-quirk; |
|
snps,dis_u2_susphy_quirk; |
|
snps,dis-del-phy-power-chg-quirk; |
|
snps,dis-tx-ipgap-linecheck-quirk; |
|
power-domains = <0x1d 0x18>; |
|
status = "okay"; |
|
phandle = <0xe9>; |
|
}; |
|
}; |
|
|
|
dp@fec00000 { |
|
compatible = "rockchip,rk3399-cdn-dp"; |
|
reg = <0x00 0xfec00000 0x00 0x100000>; |
|
interrupts = <0x00 0x09 0x04 0x00>; |
|
assigned-clocks = <0x08 0x72 0x08 0xa1>; |
|
assigned-clock-rates = <0x5f5e100 0xbebc200>; |
|
clocks = <0x08 0x72 0x08 0x175 0x08 0xa1 0x08 0x16f>; |
|
clock-names = "core-clk\0pclk\0spdif\0grf"; |
|
phys = <0x32 0x33>; |
|
power-domains = <0x1d 0x15>; |
|
resets = <0x08 0x103 0x08 0x148 0x08 0x14a 0x08 0xfd>; |
|
reset-names = "spdif\0dptx\0apb\0core"; |
|
rockchip,grf = <0x1e>; |
|
#sound-dai-cells = <0x01>; |
|
status = "disabled"; |
|
phandle = <0xea>; |
|
|
|
ports { |
|
|
|
port { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
phandle = <0xeb>; |
|
|
|
endpoint@0 { |
|
reg = <0x00>; |
|
remote-endpoint = <0x34>; |
|
phandle = <0xad>; |
|
}; |
|
|
|
endpoint@1 { |
|
reg = <0x01>; |
|
remote-endpoint = <0x35>; |
|
phandle = <0xa7>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
interrupt-controller@fee00000 { |
|
compatible = "arm,gic-v3"; |
|
#interrupt-cells = <0x04>; |
|
#address-cells = <0x02>; |
|
#size-cells = <0x02>; |
|
ranges; |
|
interrupt-controller; |
|
reg = <0x00 0xfee00000 0x00 0x10000 0x00 0xfef00000 0x00 0xc0000 0x00 0xfff00000 0x00 0x10000 0x00 0xfff10000 0x00 0x10000 0x00 0xfff20000 0x00 0x10000>; |
|
interrupts = <0x01 0x09 0x04 0x00>; |
|
phandle = <0x01>; |
|
|
|
interrupt-controller@fee20000 { |
|
compatible = "arm,gic-v3-its"; |
|
msi-controller; |
|
#msi-cells = <0x01>; |
|
reg = <0x00 0xfee20000 0x00 0x20000>; |
|
phandle = <0x16>; |
|
}; |
|
|
|
ppi-partitions { |
|
|
|
interrupt-partition-0 { |
|
affinity = <0x02 0x03 0x04 0x05>; |
|
phandle = <0x13>; |
|
}; |
|
|
|
interrupt-partition-1 { |
|
affinity = <0x06 0x07>; |
|
phandle = <0x14>; |
|
}; |
|
}; |
|
}; |
|
|
|
saradc@ff100000 { |
|
compatible = "rockchip,rk3399-saradc"; |
|
reg = <0x00 0xff100000 0x00 0x100>; |
|
interrupts = <0x00 0x3e 0x04 0x00>; |
|
#io-channel-cells = <0x01>; |
|
clocks = <0x08 0x50 0x08 0x165>; |
|
clock-names = "saradc\0apb_pclk"; |
|
resets = <0x08 0xd4>; |
|
reset-names = "saradc-apb"; |
|
status = "okay"; |
|
vref-supply = <0x1b>; |
|
phandle = <0xec>; |
|
}; |
|
|
|
i2c@ff110000 { |
|
compatible = "rockchip,rk3399-i2c"; |
|
reg = <0x00 0xff110000 0x00 0x1000>; |
|
assigned-clocks = <0x08 0x41>; |
|
assigned-clock-rates = <0xbebc200>; |
|
clocks = <0x08 0x41 0x08 0x155>; |
|
clock-names = "i2c\0pclk"; |
|
interrupts = <0x00 0x3b 0x04 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x36>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "okay"; |
|
clock-frequency = <0x186a0>; |
|
i2c-scl-falling-time-ns = <0x04>; |
|
i2c-scl-rising-time-ns = <0xa8>; |
|
phandle = <0xed>; |
|
|
|
es8316@11 { |
|
compatible = "everest,es8316"; |
|
reg = <0x11>; |
|
clocks = <0x08 0x59>; |
|
clock-names = "mclk"; |
|
#sound-dai-cells = <0x00>; |
|
phandle = <0xd3>; |
|
}; |
|
}; |
|
|
|
i2c@ff120000 { |
|
compatible = "rockchip,rk3399-i2c"; |
|
reg = <0x00 0xff120000 0x00 0x1000>; |
|
assigned-clocks = <0x08 0x42>; |
|
assigned-clock-rates = <0xbebc200>; |
|
clocks = <0x08 0x42 0x08 0x156>; |
|
clock-names = "i2c\0pclk"; |
|
interrupts = <0x00 0x23 0x04 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x37>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0xee>; |
|
}; |
|
|
|
i2c@ff130000 { |
|
compatible = "rockchip,rk3399-i2c"; |
|
reg = <0x00 0xff130000 0x00 0x1000>; |
|
assigned-clocks = <0x08 0x43>; |
|
assigned-clock-rates = <0xbebc200>; |
|
clocks = <0x08 0x43 0x08 0x157>; |
|
clock-names = "i2c\0pclk"; |
|
interrupts = <0x00 0x22 0x04 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x38>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "okay"; |
|
i2c-scl-falling-time-ns = <0x0f>; |
|
i2c-scl-rising-time-ns = <0x1c2>; |
|
phandle = <0xef>; |
|
}; |
|
|
|
i2c@ff140000 { |
|
compatible = "rockchip,rk3399-i2c"; |
|
reg = <0x00 0xff140000 0x00 0x1000>; |
|
assigned-clocks = <0x08 0x44>; |
|
assigned-clock-rates = <0xbebc200>; |
|
clocks = <0x08 0x44 0x08 0x158>; |
|
clock-names = "i2c\0pclk"; |
|
interrupts = <0x00 0x26 0x04 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x39>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0xf0>; |
|
}; |
|
|
|
i2c@ff150000 { |
|
compatible = "rockchip,rk3399-i2c"; |
|
reg = <0x00 0xff150000 0x00 0x1000>; |
|
assigned-clocks = <0x08 0x45>; |
|
assigned-clock-rates = <0xbebc200>; |
|
clocks = <0x08 0x45 0x08 0x159>; |
|
clock-names = "i2c\0pclk"; |
|
interrupts = <0x00 0x25 0x04 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x3a>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0xf1>; |
|
}; |
|
|
|
i2c@ff160000 { |
|
compatible = "rockchip,rk3399-i2c"; |
|
reg = <0x00 0xff160000 0x00 0x1000>; |
|
assigned-clocks = <0x08 0x46>; |
|
assigned-clock-rates = <0xbebc200>; |
|
clocks = <0x08 0x46 0x08 0x15a>; |
|
clock-names = "i2c\0pclk"; |
|
interrupts = <0x00 0x24 0x04 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x3b>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0xf2>; |
|
}; |
|
|
|
serial@ff180000 { |
|
compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart"; |
|
reg = <0x00 0xff180000 0x00 0x100>; |
|
clocks = <0x08 0x51 0x08 0x160>; |
|
clock-names = "baudclk\0apb_pclk"; |
|
interrupts = <0x00 0x63 0x04 0x00>; |
|
reg-shift = <0x02>; |
|
reg-io-width = <0x04>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x3c 0x3d 0x3e>; |
|
status = "okay"; |
|
uart-has-rtscts; |
|
phandle = <0xf3>; |
|
|
|
bluetooth { |
|
compatible = "brcm,bcm4345c5"; |
|
clocks = <0x3f 0x01>; |
|
clock-names = "lpo"; |
|
device-wakeup-gpios = <0x18 0x1b 0x00>; |
|
host-wakeup-gpios = <0x23 0x04 0x00>; |
|
max-speed = <0x16e360>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x40 0x41 0x42>; |
|
shutdown-gpios = <0x23 0x09 0x00>; |
|
vbat-supply = <0x43>; |
|
vddio-supply = <0x44>; |
|
}; |
|
}; |
|
|
|
serial@ff190000 { |
|
compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart"; |
|
reg = <0x00 0xff190000 0x00 0x100>; |
|
clocks = <0x08 0x52 0x08 0x161>; |
|
clock-names = "baudclk\0apb_pclk"; |
|
interrupts = <0x00 0x62 0x04 0x00>; |
|
reg-shift = <0x02>; |
|
reg-io-width = <0x04>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x45>; |
|
status = "disabled"; |
|
phandle = <0xf4>; |
|
}; |
|
|
|
serial@ff1a0000 { |
|
compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart"; |
|
reg = <0x00 0xff1a0000 0x00 0x100>; |
|
clocks = <0x08 0x53 0x08 0x162>; |
|
clock-names = "baudclk\0apb_pclk"; |
|
interrupts = <0x00 0x64 0x04 0x00>; |
|
reg-shift = <0x02>; |
|
reg-io-width = <0x04>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x46>; |
|
status = "okay"; |
|
phandle = <0xf5>; |
|
}; |
|
|
|
serial@ff1b0000 { |
|
compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart"; |
|
reg = <0x00 0xff1b0000 0x00 0x100>; |
|
clocks = <0x08 0x54 0x08 0x163>; |
|
clock-names = "baudclk\0apb_pclk"; |
|
interrupts = <0x00 0x65 0x04 0x00>; |
|
reg-shift = <0x02>; |
|
reg-io-width = <0x04>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x47>; |
|
status = "disabled"; |
|
phandle = <0xf6>; |
|
}; |
|
|
|
spi@ff1c0000 { |
|
compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi"; |
|
reg = <0x00 0xff1c0000 0x00 0x1000>; |
|
clocks = <0x08 0x47 0x08 0x15b>; |
|
clock-names = "spiclk\0apb_pclk"; |
|
interrupts = <0x00 0x44 0x04 0x00>; |
|
dmas = <0x48 0x0a 0x48 0x0b>; |
|
dma-names = "tx\0rx"; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x49 0x4a 0x4b 0x4c>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0xf7>; |
|
}; |
|
|
|
spi@ff1d0000 { |
|
compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi"; |
|
reg = <0x00 0xff1d0000 0x00 0x1000>; |
|
clocks = <0x08 0x48 0x08 0x15c>; |
|
clock-names = "spiclk\0apb_pclk"; |
|
interrupts = <0x00 0x35 0x04 0x00>; |
|
dmas = <0x48 0x0c 0x48 0x0d>; |
|
dma-names = "tx\0rx"; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x4d 0x4e 0x4f 0x50>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "okay"; |
|
max-freq = <0x989680>; |
|
phandle = <0xf8>; |
|
|
|
flash@0 { |
|
compatible = "jedec,spi-nor"; |
|
reg = <0x00>; |
|
m25p,fast-read; |
|
spi-max-frequency = <0x989680>; |
|
phandle = <0xf9>; |
|
}; |
|
}; |
|
|
|
spi@ff1e0000 { |
|
compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi"; |
|
reg = <0x00 0xff1e0000 0x00 0x1000>; |
|
clocks = <0x08 0x49 0x08 0x15d>; |
|
clock-names = "spiclk\0apb_pclk"; |
|
interrupts = <0x00 0x34 0x04 0x00>; |
|
dmas = <0x48 0x0e 0x48 0x0f>; |
|
dma-names = "tx\0rx"; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x51 0x52 0x53 0x54>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0xfa>; |
|
}; |
|
|
|
spi@ff1f0000 { |
|
compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi"; |
|
reg = <0x00 0xff1f0000 0x00 0x1000>; |
|
clocks = <0x08 0x4a 0x08 0x15e>; |
|
clock-names = "spiclk\0apb_pclk"; |
|
interrupts = <0x00 0x43 0x04 0x00>; |
|
dmas = <0x48 0x12 0x48 0x13>; |
|
dma-names = "tx\0rx"; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x55 0x56 0x57 0x58>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0xfb>; |
|
}; |
|
|
|
spi@ff200000 { |
|
compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi"; |
|
reg = <0x00 0xff200000 0x00 0x1000>; |
|
clocks = <0x08 0x4b 0x08 0x15f>; |
|
clock-names = "spiclk\0apb_pclk"; |
|
interrupts = <0x00 0x84 0x04 0x00>; |
|
dmas = <0x59 0x08 0x59 0x09>; |
|
dma-names = "tx\0rx"; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x5a 0x5b 0x5c 0x5d>; |
|
power-domains = <0x1d 0x1c>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0xfc>; |
|
}; |
|
|
|
thermal-zones { |
|
phandle = <0xfd>; |
|
|
|
cpu-thermal { |
|
polling-delay-passive = <0x64>; |
|
polling-delay = <0x3e8>; |
|
thermal-sensors = <0x5e 0x00>; |
|
phandle = <0xfe>; |
|
|
|
trips { |
|
|
|
cpu_alert0 { |
|
temperature = <0x11170>; |
|
hysteresis = <0x7d0>; |
|
type = "passive"; |
|
phandle = <0x5f>; |
|
}; |
|
|
|
cpu_alert1 { |
|
temperature = <0x124f8>; |
|
hysteresis = <0x7d0>; |
|
type = "passive"; |
|
phandle = <0x60>; |
|
}; |
|
|
|
cpu_crit { |
|
temperature = <0x17318>; |
|
hysteresis = <0x7d0>; |
|
type = "critical"; |
|
phandle = <0xff>; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
|
|
map0 { |
|
trip = <0x5f>; |
|
cooling-device = <0x06 0xffffffff 0xffffffff 0x07 0xffffffff 0xffffffff>; |
|
}; |
|
|
|
map1 { |
|
trip = <0x60>; |
|
cooling-device = <0x02 0xffffffff 0xffffffff 0x03 0xffffffff 0xffffffff 0x04 0xffffffff 0xffffffff 0x05 0xffffffff 0xffffffff 0x06 0xffffffff 0xffffffff 0x07 0xffffffff 0xffffffff>; |
|
}; |
|
}; |
|
}; |
|
|
|
gpu-thermal { |
|
polling-delay-passive = <0x64>; |
|
polling-delay = <0x3e8>; |
|
thermal-sensors = <0x5e 0x01>; |
|
phandle = <0x100>; |
|
|
|
trips { |
|
|
|
gpu_alert0 { |
|
temperature = <0x124f8>; |
|
hysteresis = <0x7d0>; |
|
type = "passive"; |
|
phandle = <0x61>; |
|
}; |
|
|
|
gpu_crit { |
|
temperature = <0x17318>; |
|
hysteresis = <0x7d0>; |
|
type = "critical"; |
|
phandle = <0x101>; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
|
|
map0 { |
|
trip = <0x61>; |
|
cooling-device = <0x62 0xffffffff 0xffffffff>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
tsadc@ff260000 { |
|
compatible = "rockchip,rk3399-tsadc"; |
|
reg = <0x00 0xff260000 0x00 0x100>; |
|
interrupts = <0x00 0x61 0x04 0x00>; |
|
assigned-clocks = <0x08 0x4f>; |
|
assigned-clock-rates = <0xb71b0>; |
|
clocks = <0x08 0x4f 0x08 0x164>; |
|
clock-names = "tsadc\0apb_pclk"; |
|
resets = <0x08 0xe8>; |
|
reset-names = "tsadc-apb"; |
|
rockchip,grf = <0x1e>; |
|
rockchip,hw-tshut-temp = <0x17318>; |
|
pinctrl-names = "init\0default\0sleep"; |
|
pinctrl-0 = <0x63>; |
|
pinctrl-1 = <0x64>; |
|
pinctrl-2 = <0x63>; |
|
#thermal-sensor-cells = <0x01>; |
|
status = "okay"; |
|
rockchip,hw-tshut-mode = <0x01>; |
|
rockchip,hw-tshut-polarity = <0x01>; |
|
phandle = <0x5e>; |
|
}; |
|
|
|
qos@ffa58000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffa58000 0x00 0x20>; |
|
phandle = <0x6c>; |
|
}; |
|
|
|
qos@ffa5c000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffa5c000 0x00 0x20>; |
|
phandle = <0x6d>; |
|
}; |
|
|
|
qos@ffa60080 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffa60080 0x00 0x20>; |
|
phandle = <0x102>; |
|
}; |
|
|
|
qos@ffa60100 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffa60100 0x00 0x20>; |
|
phandle = <0x103>; |
|
}; |
|
|
|
qos@ffa60180 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffa60180 0x00 0x20>; |
|
phandle = <0x104>; |
|
}; |
|
|
|
qos@ffa70000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffa70000 0x00 0x20>; |
|
phandle = <0x70>; |
|
}; |
|
|
|
qos@ffa70080 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffa70080 0x00 0x20>; |
|
phandle = <0x71>; |
|
}; |
|
|
|
qos@ffa74000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffa74000 0x00 0x20>; |
|
phandle = <0x6e>; |
|
}; |
|
|
|
qos@ffa76000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffa76000 0x00 0x20>; |
|
phandle = <0x6f>; |
|
}; |
|
|
|
qos@ffa90000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffa90000 0x00 0x20>; |
|
phandle = <0x72>; |
|
}; |
|
|
|
qos@ffa98000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffa98000 0x00 0x20>; |
|
phandle = <0x65>; |
|
}; |
|
|
|
qos@ffaa0000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffaa0000 0x00 0x20>; |
|
phandle = <0x73>; |
|
}; |
|
|
|
qos@ffaa0080 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffaa0080 0x00 0x20>; |
|
phandle = <0x74>; |
|
}; |
|
|
|
qos@ffaa8000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffaa8000 0x00 0x20>; |
|
phandle = <0x75>; |
|
}; |
|
|
|
qos@ffaa8080 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffaa8080 0x00 0x20>; |
|
phandle = <0x76>; |
|
}; |
|
|
|
qos@ffab0000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffab0000 0x00 0x20>; |
|
phandle = <0x66>; |
|
}; |
|
|
|
qos@ffab0080 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffab0080 0x00 0x20>; |
|
phandle = <0x67>; |
|
}; |
|
|
|
qos@ffab8000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffab8000 0x00 0x20>; |
|
phandle = <0x68>; |
|
}; |
|
|
|
qos@ffac0000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffac0000 0x00 0x20>; |
|
phandle = <0x69>; |
|
}; |
|
|
|
qos@ffac0080 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffac0080 0x00 0x20>; |
|
phandle = <0x6a>; |
|
}; |
|
|
|
qos@ffac8000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffac8000 0x00 0x20>; |
|
phandle = <0x77>; |
|
}; |
|
|
|
qos@ffac8080 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffac8080 0x00 0x20>; |
|
phandle = <0x78>; |
|
}; |
|
|
|
qos@ffad0000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffad0000 0x00 0x20>; |
|
phandle = <0x79>; |
|
}; |
|
|
|
qos@ffad8080 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffad8080 0x00 0x20>; |
|
phandle = <0x105>; |
|
}; |
|
|
|
qos@ffae0000 { |
|
compatible = "rockchip,rk3399-qos\0syscon"; |
|
reg = <0x00 0xffae0000 0x00 0x20>; |
|
phandle = <0x6b>; |
|
}; |
|
|
|
power-management@ff310000 { |
|
compatible = "rockchip,rk3399-pmu\0syscon\0simple-mfd"; |
|
reg = <0x00 0xff310000 0x00 0x1000>; |
|
phandle = <0x106>; |
|
|
|
power-controller { |
|
compatible = "rockchip,rk3399-power-controller"; |
|
#power-domain-cells = <0x01>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
phandle = <0x1d>; |
|
|
|
power-domain@34 { |
|
reg = <0x22>; |
|
clocks = <0x08 0xe1 0x08 0x1dd>; |
|
pm_qos = <0x65>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@33 { |
|
reg = <0x21>; |
|
clocks = <0x08 0xdc 0x08 0x1e5>; |
|
pm_qos = <0x66 0x67>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@31 { |
|
reg = <0x1f>; |
|
clocks = <0x08 0xeb 0x08 0x1ea>; |
|
pm_qos = <0x68>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@32 { |
|
reg = <0x20>; |
|
clocks = <0x08 0xed 0x08 0x1ec>; |
|
pm_qos = <0x69 0x6a>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@35 { |
|
reg = <0x23>; |
|
clocks = <0x08 0xd0>; |
|
pm_qos = <0x6b>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@25 { |
|
reg = <0x19>; |
|
clocks = <0x08 0x16c>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@23 { |
|
reg = <0x17>; |
|
clocks = <0x08 0xf0>; |
|
pm_qos = <0x6c>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@22 { |
|
reg = <0x16>; |
|
clocks = <0x08 0xd5 0x08 0x166>; |
|
pm_qos = <0x6d>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@27 { |
|
reg = <0x1b>; |
|
clocks = <0x08 0x1ce 0x08 0x4c>; |
|
pm_qos = <0x6e>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@28 { |
|
reg = <0x1c>; |
|
clocks = <0x08 0x1ee>; |
|
pm_qos = <0x6f>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@8 { |
|
reg = <0x08>; |
|
clocks = <0x08 0x7e 0x08 0x7d>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@9 { |
|
reg = <0x09>; |
|
clocks = <0x08 0x80 0x08 0x7f>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@24 { |
|
reg = <0x18>; |
|
clocks = <0x08 0xf4>; |
|
pm_qos = <0x70 0x71>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@15 { |
|
reg = <0x0f>; |
|
#power-domain-cells = <0x01>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
|
|
power-domain@21 { |
|
reg = <0x15>; |
|
clocks = <0x08 0xde 0x08 0x1e7 0x08 0x172>; |
|
pm_qos = <0x72>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@19 { |
|
reg = <0x13>; |
|
clocks = <0x08 0xe5 0x08 0x1df>; |
|
pm_qos = <0x73 0x74>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@20 { |
|
reg = <0x14>; |
|
clocks = <0x08 0xe6 0x08 0x1e0>; |
|
pm_qos = <0x75 0x76>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@16 { |
|
reg = <0x10>; |
|
#power-domain-cells = <0x01>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
|
|
power-domain@17 { |
|
reg = <0x11>; |
|
clocks = <0x08 0xd9 0x08 0x1d9>; |
|
pm_qos = <0x77 0x78>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
|
|
power-domain@18 { |
|
reg = <0x12>; |
|
clocks = <0x08 0xdb 0x08 0x1db>; |
|
pm_qos = <0x79>; |
|
#power-domain-cells = <0x00>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
syscon@ff320000 { |
|
compatible = "rockchip,rk3399-pmugrf\0syscon\0simple-mfd"; |
|
reg = <0x00 0xff320000 0x00 0x1000>; |
|
phandle = <0x11>; |
|
|
|
io-domains { |
|
compatible = "rockchip,rk3399-pmu-io-voltage-domain"; |
|
status = "okay"; |
|
pmu1830-supply = <0x7a>; |
|
phandle = <0x107>; |
|
}; |
|
}; |
|
|
|
spi@ff350000 { |
|
compatible = "rockchip,rk3399-spi\0rockchip,rk3066-spi"; |
|
reg = <0x00 0xff350000 0x00 0x1000>; |
|
clocks = <0x7b 0x03 0x7b 0x1f>; |
|
clock-names = "spiclk\0apb_pclk"; |
|
interrupts = <0x00 0x3c 0x04 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x7c 0x7d 0x7e 0x7f>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0x108>; |
|
}; |
|
|
|
serial@ff370000 { |
|
compatible = "rockchip,rk3399-uart\0snps,dw-apb-uart"; |
|
reg = <0x00 0xff370000 0x00 0x100>; |
|
clocks = <0x7b 0x06 0x7b 0x22>; |
|
clock-names = "baudclk\0apb_pclk"; |
|
interrupts = <0x00 0x66 0x04 0x00>; |
|
reg-shift = <0x02>; |
|
reg-io-width = <0x04>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x80>; |
|
status = "disabled"; |
|
phandle = <0x109>; |
|
}; |
|
|
|
i2c@ff3c0000 { |
|
compatible = "rockchip,rk3399-i2c"; |
|
reg = <0x00 0xff3c0000 0x00 0x1000>; |
|
assigned-clocks = <0x7b 0x09>; |
|
assigned-clock-rates = <0xbebc200>; |
|
clocks = <0x7b 0x09 0x7b 0x1b>; |
|
clock-names = "i2c\0pclk"; |
|
interrupts = <0x00 0x39 0x04 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x81>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "okay"; |
|
clock-frequency = <0x61a80>; |
|
i2c-scl-falling-time-ns = <0x04>; |
|
i2c-scl-rising-time-ns = <0xa8>; |
|
phandle = <0x10a>; |
|
|
|
pmic@1b { |
|
compatible = "rockchip,rk808"; |
|
reg = <0x1b>; |
|
#clock-cells = <0x01>; |
|
clock-output-names = "xin32k\0rk808-clkout2"; |
|
interrupt-parent = <0x82>; |
|
interrupts = <0x0a 0x08>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x83>; |
|
rockchip,system-power-controller; |
|
wakeup-source; |
|
vcc1-supply = <0x84>; |
|
vcc2-supply = <0x84>; |
|
vcc3-supply = <0x84>; |
|
vcc4-supply = <0x84>; |
|
vcc6-supply = <0x84>; |
|
vcc7-supply = <0x84>; |
|
vcc8-supply = <0x43>; |
|
vcc9-supply = <0x84>; |
|
vcc10-supply = <0x84>; |
|
vcc11-supply = <0x84>; |
|
vcc12-supply = <0x43>; |
|
phandle = <0x3f>; |
|
|
|
regulators { |
|
|
|
DCDC_REG1 { |
|
regulator-name = "vdd_center"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0xb71b0>; |
|
regulator-max-microvolt = <0x149970>; |
|
regulator-ramp-delay = <0x1771>; |
|
phandle = <0x10b>; |
|
|
|
regulator-state-mem { |
|
regulator-off-in-suspend; |
|
}; |
|
}; |
|
|
|
DCDC_REG2 { |
|
regulator-name = "vdd_cpu_l"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0xb71b0>; |
|
regulator-max-microvolt = <0x149970>; |
|
regulator-ramp-delay = <0x1771>; |
|
phandle = <0x0c>; |
|
|
|
regulator-state-mem { |
|
regulator-off-in-suspend; |
|
}; |
|
}; |
|
|
|
DCDC_REG3 { |
|
regulator-name = "vcc_ddr"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
phandle = <0x10c>; |
|
|
|
regulator-state-mem { |
|
regulator-on-in-suspend; |
|
}; |
|
}; |
|
|
|
DCDC_REG4 { |
|
regulator-name = "vcc_1v8"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0x1b7740>; |
|
regulator-max-microvolt = <0x1b7740>; |
|
phandle = <0x44>; |
|
|
|
regulator-state-mem { |
|
regulator-on-in-suspend; |
|
regulator-suspend-microvolt = <0x1b7740>; |
|
}; |
|
}; |
|
|
|
LDO_REG1 { |
|
}; |
|
|
|
LDO_REG2 { |
|
}; |
|
|
|
LDO_REG3 { |
|
regulator-name = "vcc1v8_pmupll"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0x1b7740>; |
|
regulator-max-microvolt = <0x1b7740>; |
|
phandle = <0x10d>; |
|
|
|
regulator-state-mem { |
|
regulator-on-in-suspend; |
|
regulator-suspend-microvolt = <0x1b7740>; |
|
}; |
|
}; |
|
|
|
LDO_REG4 { |
|
regulator-name = "vcc_sdio"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0x1b7740>; |
|
regulator-max-microvolt = <0x2dc6c0>; |
|
phandle = <0x28>; |
|
|
|
regulator-state-mem { |
|
regulator-on-in-suspend; |
|
regulator-suspend-microvolt = <0x2dc6c0>; |
|
}; |
|
}; |
|
|
|
LDO_REG5 { |
|
regulator-name = "vcca3v0_codec"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0x2dc6c0>; |
|
regulator-max-microvolt = <0x2dc6c0>; |
|
phandle = <0x10e>; |
|
|
|
regulator-state-mem { |
|
regulator-off-in-suspend; |
|
}; |
|
}; |
|
|
|
LDO_REG6 { |
|
regulator-name = "vcc_1v5"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0x16e360>; |
|
regulator-max-microvolt = <0x16e360>; |
|
phandle = <0x10f>; |
|
|
|
regulator-state-mem { |
|
regulator-on-in-suspend; |
|
regulator-suspend-microvolt = <0x16e360>; |
|
}; |
|
}; |
|
|
|
LDO_REG7 { |
|
regulator-name = "vcca1v8_codec"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0x1b7740>; |
|
regulator-max-microvolt = <0x1b7740>; |
|
phandle = <0x110>; |
|
|
|
regulator-state-mem { |
|
regulator-off-in-suspend; |
|
}; |
|
}; |
|
|
|
LDO_REG8 { |
|
regulator-name = "vcc_3v0"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0x2dc6c0>; |
|
regulator-max-microvolt = <0x2dc6c0>; |
|
phandle = <0x7a>; |
|
|
|
regulator-state-mem { |
|
regulator-on-in-suspend; |
|
regulator-suspend-microvolt = <0x2dc6c0>; |
|
}; |
|
}; |
|
|
|
SWITCH_REG1 { |
|
regulator-name = "vcc3v3_s3"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
phandle = <0x111>; |
|
|
|
regulator-state-mem { |
|
regulator-off-in-suspend; |
|
}; |
|
}; |
|
|
|
SWITCH_REG2 { |
|
regulator-name = "vcc3v3_s0"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
phandle = <0x112>; |
|
|
|
regulator-state-mem { |
|
regulator-off-in-suspend; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
regulator@40 { |
|
compatible = "silergy,syr827"; |
|
reg = <0x40>; |
|
fcs,suspend-voltage-selector = <0x01>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x85>; |
|
regulator-name = "vdd_cpu_b"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0xadf34>; |
|
regulator-max-microvolt = <0x16e360>; |
|
regulator-ramp-delay = <0x3e8>; |
|
vin-supply = <0x44>; |
|
phandle = <0x0e>; |
|
|
|
regulator-state-mem { |
|
regulator-off-in-suspend; |
|
}; |
|
}; |
|
|
|
regulator@41 { |
|
compatible = "silergy,syr828"; |
|
reg = <0x41>; |
|
fcs,suspend-voltage-selector = <0x01>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x86>; |
|
regulator-name = "vdd_gpu"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0xadf34>; |
|
regulator-max-microvolt = <0x16e360>; |
|
regulator-ramp-delay = <0x3e8>; |
|
vin-supply = <0x44>; |
|
phandle = <0xbf>; |
|
|
|
regulator-state-mem { |
|
regulator-off-in-suspend; |
|
}; |
|
}; |
|
}; |
|
|
|
i2c@ff3d0000 { |
|
compatible = "rockchip,rk3399-i2c"; |
|
reg = <0x00 0xff3d0000 0x00 0x1000>; |
|
assigned-clocks = <0x7b 0x0a>; |
|
assigned-clock-rates = <0xbebc200>; |
|
clocks = <0x7b 0x0a 0x7b 0x1c>; |
|
clock-names = "i2c\0pclk"; |
|
interrupts = <0x00 0x38 0x04 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x87>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "okay"; |
|
i2c-scl-falling-time-ns = <0x14>; |
|
i2c-scl-rising-time-ns = <0x258>; |
|
phandle = <0x113>; |
|
|
|
fusb30x@22 { |
|
compatible = "fcs,fusb302"; |
|
reg = <0x22>; |
|
interrupt-parent = <0x88>; |
|
interrupts = <0x02 0x08>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x89>; |
|
vbus-supply = <0x8a>; |
|
phandle = <0x90>; |
|
|
|
connector { |
|
compatible = "usb-c-connector"; |
|
data-role = "dual"; |
|
label = "USB-C"; |
|
op-sink-microwatt = <0xf4240>; |
|
power-role = "dual"; |
|
sink-pdos = <0x40190fa>; |
|
source-pdos = <0x401908c>; |
|
try-power-role = "sink"; |
|
|
|
ports { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
|
|
port@0 { |
|
reg = <0x00>; |
|
|
|
endpoint { |
|
remote-endpoint = <0x8b>; |
|
phandle = <0x9a>; |
|
}; |
|
}; |
|
|
|
port@1 { |
|
reg = <0x01>; |
|
|
|
endpoint { |
|
remote-endpoint = <0x8c>; |
|
phandle = <0x9d>; |
|
}; |
|
}; |
|
|
|
port@2 { |
|
reg = <0x02>; |
|
|
|
endpoint { |
|
remote-endpoint = <0x8d>; |
|
phandle = <0x9c>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
cw2015@62 { |
|
compatible = "cellwise,cw2015"; |
|
reg = <0x62>; |
|
cellwise,battery-profile = <0x17678073 0x6e6c6b63 0x77515c58 0x504c4836 0x150c0c19 0x5b7d6f69 0x695b0c29 0x20405259 0x5756544f 0x3b1f7f17 0x61a305a 0x8593962d 0x48779cb3 0x805294cb 0x2f0064a5 0xb511f011>; |
|
cellwise,monitor-interval-ms = <0x1388>; |
|
monitored-battery = <0x8e>; |
|
power-supplies = <0x8f 0x90>; |
|
}; |
|
}; |
|
|
|
i2c@ff3e0000 { |
|
compatible = "rockchip,rk3399-i2c"; |
|
reg = <0x00 0xff3e0000 0x00 0x1000>; |
|
assigned-clocks = <0x7b 0x0b>; |
|
assigned-clock-rates = <0xbebc200>; |
|
clocks = <0x7b 0x0b 0x7b 0x1d>; |
|
clock-names = "i2c\0pclk"; |
|
interrupts = <0x00 0x3a 0x04 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x91>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0x114>; |
|
}; |
|
|
|
pwm@ff420000 { |
|
compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm"; |
|
reg = <0x00 0xff420000 0x00 0x10>; |
|
#pwm-cells = <0x03>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x92>; |
|
clocks = <0x7b 0x1e>; |
|
status = "okay"; |
|
phandle = <0xc6>; |
|
}; |
|
|
|
pwm@ff420010 { |
|
compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm"; |
|
reg = <0x00 0xff420010 0x00 0x10>; |
|
#pwm-cells = <0x03>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x93>; |
|
clocks = <0x7b 0x1e>; |
|
status = "disabled"; |
|
phandle = <0x115>; |
|
}; |
|
|
|
pwm@ff420020 { |
|
compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm"; |
|
reg = <0x00 0xff420020 0x00 0x10>; |
|
#pwm-cells = <0x03>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x94>; |
|
clocks = <0x7b 0x1e>; |
|
status = "okay"; |
|
phandle = <0xd7>; |
|
}; |
|
|
|
pwm@ff420030 { |
|
compatible = "rockchip,rk3399-pwm\0rockchip,rk3288-pwm"; |
|
reg = <0x00 0xff420030 0x00 0x10>; |
|
#pwm-cells = <0x03>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x95>; |
|
clocks = <0x7b 0x1e>; |
|
status = "disabled"; |
|
phandle = <0x116>; |
|
}; |
|
|
|
dfi@ff630000 { |
|
reg = <0x00 0xff630000 0x00 0x4000>; |
|
compatible = "rockchip,rk3399-dfi"; |
|
rockchip,pmu = <0x11>; |
|
interrupts = <0x00 0x83 0x04 0x00>; |
|
clocks = <0x08 0x179>; |
|
clock-names = "pclk_ddr_mon"; |
|
status = "disabled"; |
|
phandle = <0x12>; |
|
}; |
|
|
|
video-codec@ff650000 { |
|
compatible = "rockchip,rk3399-vpu"; |
|
reg = <0x00 0xff650000 0x00 0x800>; |
|
interrupts = <0x00 0x72 0x04 0x00 0x00 0x71 0x04 0x00>; |
|
interrupt-names = "vepu\0vdpu"; |
|
clocks = <0x08 0xeb 0x08 0x1ea>; |
|
clock-names = "aclk\0hclk"; |
|
iommus = <0x96>; |
|
power-domains = <0x1d 0x1f>; |
|
phandle = <0x117>; |
|
}; |
|
|
|
iommu@ff650800 { |
|
compatible = "rockchip,iommu"; |
|
reg = <0x00 0xff650800 0x00 0x40>; |
|
interrupts = <0x00 0x73 0x04 0x00>; |
|
clocks = <0x08 0xeb 0x08 0x1ea>; |
|
clock-names = "aclk\0iface"; |
|
#iommu-cells = <0x00>; |
|
power-domains = <0x1d 0x1f>; |
|
phandle = <0x96>; |
|
}; |
|
|
|
video-codec@ff660000 { |
|
compatible = "rockchip,rk3399-vdec"; |
|
reg = <0x00 0xff660000 0x00 0x400>; |
|
interrupts = <0x00 0x74 0x04 0x00>; |
|
clocks = <0x08 0xed 0x08 0x1ec 0x08 0x9f 0x08 0x9e>; |
|
clock-names = "axi\0ahb\0cabac\0core"; |
|
iommus = <0x97>; |
|
power-domains = <0x1d 0x20>; |
|
phandle = <0x118>; |
|
}; |
|
|
|
iommu@ff660480 { |
|
compatible = "rockchip,iommu"; |
|
reg = <0x00 0xff660480 0x00 0x40 0x00 0xff6604c0 0x00 0x40>; |
|
interrupts = <0x00 0x75 0x04 0x00>; |
|
clocks = <0x08 0xed 0x08 0x1ec>; |
|
clock-names = "aclk\0iface"; |
|
power-domains = <0x1d 0x20>; |
|
#iommu-cells = <0x00>; |
|
phandle = <0x97>; |
|
}; |
|
|
|
iommu@ff670800 { |
|
compatible = "rockchip,iommu"; |
|
reg = <0x00 0xff670800 0x00 0x40>; |
|
interrupts = <0x00 0x2a 0x04 0x00>; |
|
clocks = <0x08 0xe1 0x08 0x1dd>; |
|
clock-names = "aclk\0iface"; |
|
#iommu-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0x119>; |
|
}; |
|
|
|
rga@ff680000 { |
|
compatible = "rockchip,rk3399-rga"; |
|
reg = <0x00 0xff680000 0x00 0x10000>; |
|
interrupts = <0x00 0x37 0x04 0x00>; |
|
clocks = <0x08 0xdc 0x08 0x1e5 0x08 0x6d>; |
|
clock-names = "aclk\0hclk\0sclk"; |
|
resets = <0x08 0x6a 0x08 0x67 0x08 0x69>; |
|
reset-names = "core\0axi\0ahb"; |
|
power-domains = <0x1d 0x21>; |
|
phandle = <0x11a>; |
|
}; |
|
|
|
efuse@ff690000 { |
|
compatible = "rockchip,rk3399-efuse"; |
|
reg = <0x00 0xff690000 0x00 0x80>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x01>; |
|
clocks = <0x08 0x17d>; |
|
clock-names = "pclk_efuse"; |
|
phandle = <0x11b>; |
|
|
|
cpu-id@7 { |
|
reg = <0x07 0x10>; |
|
phandle = <0x11c>; |
|
}; |
|
|
|
cpu-leakage@17 { |
|
reg = <0x17 0x01>; |
|
phandle = <0x11d>; |
|
}; |
|
|
|
gpu-leakage@18 { |
|
reg = <0x18 0x01>; |
|
phandle = <0x11e>; |
|
}; |
|
|
|
center-leakage@19 { |
|
reg = <0x19 0x01>; |
|
phandle = <0x11f>; |
|
}; |
|
|
|
cpu-leakage@1a { |
|
reg = <0x1a 0x01>; |
|
phandle = <0x120>; |
|
}; |
|
|
|
logic-leakage@1b { |
|
reg = <0x1b 0x01>; |
|
phandle = <0x121>; |
|
}; |
|
|
|
wafer-info@1c { |
|
reg = <0x1c 0x01>; |
|
phandle = <0x122>; |
|
}; |
|
}; |
|
|
|
dma-controller@ff6d0000 { |
|
compatible = "arm,pl330\0arm,primecell"; |
|
reg = <0x00 0xff6d0000 0x00 0x4000>; |
|
interrupts = <0x00 0x05 0x04 0x00 0x00 0x06 0x04 0x00>; |
|
#dma-cells = <0x01>; |
|
arm,pl330-periph-burst; |
|
clocks = <0x08 0xd3>; |
|
clock-names = "apb_pclk"; |
|
phandle = <0x59>; |
|
}; |
|
|
|
dma-controller@ff6e0000 { |
|
compatible = "arm,pl330\0arm,primecell"; |
|
reg = <0x00 0xff6e0000 0x00 0x4000>; |
|
interrupts = <0x00 0x07 0x04 0x00 0x00 0x08 0x04 0x00>; |
|
#dma-cells = <0x01>; |
|
arm,pl330-periph-burst; |
|
clocks = <0x08 0xd4>; |
|
clock-names = "apb_pclk"; |
|
phandle = <0x48>; |
|
}; |
|
|
|
clock-controller@ff750000 { |
|
compatible = "rockchip,rk3399-pmucru"; |
|
reg = <0x00 0xff750000 0x00 0x1000>; |
|
clocks = <0x98>; |
|
clock-names = "xin24m"; |
|
rockchip,grf = <0x11>; |
|
#clock-cells = <0x01>; |
|
#reset-cells = <0x01>; |
|
assigned-clocks = <0x7b 0x01>; |
|
assigned-clock-rates = <0x284af100>; |
|
phandle = <0x7b>; |
|
}; |
|
|
|
clock-controller@ff760000 { |
|
compatible = "rockchip,rk3399-cru"; |
|
reg = <0x00 0xff760000 0x00 0x1000>; |
|
clocks = <0x98>; |
|
clock-names = "xin24m"; |
|
rockchip,grf = <0x1e>; |
|
#clock-cells = <0x01>; |
|
#reset-cells = <0x01>; |
|
assigned-clocks = <0x08 0x05 0x08 0x04 0x08 0x06 0x08 0xc0 0x08 0x1c0 0x08 0x140 0x08 0xc2 0x08 0x1c1 0x08 0x142 0x08 0xc9 0x08 0x1c2 0x08 0x143 0x08 0xe3 0x08 0xde 0x08 0x106 0x08 0x178 0x08 0xed>; |
|
assigned-clock-rates = <0x2367b880 0x2faf0800 0x3b9aca00 0x8f0d180 0x47868c0 0x23c3460 0x5f5e100 0x5f5e100 0x2faf080 0x23c34600 0x5f5e100 0x2faf080 0x17d78400 0x17d78400 0xbebc200 0xbebc200 0x17d78400>; |
|
phandle = <0x08>; |
|
}; |
|
|
|
syscon@ff770000 { |
|
compatible = "rockchip,rk3399-grf\0syscon\0simple-mfd"; |
|
reg = <0x00 0xff770000 0x00 0x10000>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x01>; |
|
phandle = <0x1e>; |
|
|
|
io-domains { |
|
compatible = "rockchip,rk3399-io-voltage-domain"; |
|
status = "okay"; |
|
audio-supply = <0x7a>; |
|
gpio1830-supply = <0x7a>; |
|
sdmmc-supply = <0x28>; |
|
phandle = <0x123>; |
|
}; |
|
|
|
mipi-dphy-rx0 { |
|
compatible = "rockchip,rk3399-mipi-dphy-rx0"; |
|
clocks = <0x08 0x77 0x08 0xa5 0x08 0x16f>; |
|
clock-names = "dphy-ref\0dphy-cfg\0grf"; |
|
power-domains = <0x1d 0x0f>; |
|
#phy-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0xaf>; |
|
}; |
|
|
|
usb2phy@e450 { |
|
compatible = "rockchip,rk3399-usb2phy"; |
|
reg = <0xe450 0x10>; |
|
clocks = <0x08 0x7b>; |
|
clock-names = "phyclk"; |
|
#clock-cells = <0x00>; |
|
clock-output-names = "clk_usbphy0_480m"; |
|
status = "okay"; |
|
phandle = <0x2a>; |
|
|
|
host-port { |
|
#phy-cells = <0x00>; |
|
interrupts = <0x00 0x1b 0x04 0x00>; |
|
interrupt-names = "linestate"; |
|
status = "okay"; |
|
phy-supply = <0x99>; |
|
phandle = <0x2b>; |
|
}; |
|
|
|
otg-port { |
|
#phy-cells = <0x00>; |
|
interrupts = <0x00 0x67 0x04 0x00 0x00 0x68 0x04 0x00 0x00 0x6a 0x04 0x00>; |
|
interrupt-names = "otg-bvalid\0otg-id\0linestate"; |
|
status = "okay"; |
|
phandle = <0x2e>; |
|
}; |
|
|
|
port { |
|
|
|
endpoint { |
|
remote-endpoint = <0x9a>; |
|
phandle = <0x8b>; |
|
}; |
|
}; |
|
}; |
|
|
|
usb2phy@e460 { |
|
compatible = "rockchip,rk3399-usb2phy"; |
|
reg = <0xe460 0x10>; |
|
clocks = <0x08 0x7c>; |
|
clock-names = "phyclk"; |
|
#clock-cells = <0x00>; |
|
clock-output-names = "clk_usbphy1_480m"; |
|
status = "okay"; |
|
phandle = <0x2c>; |
|
|
|
host-port { |
|
#phy-cells = <0x00>; |
|
interrupts = <0x00 0x1f 0x04 0x00>; |
|
interrupt-names = "linestate"; |
|
status = "okay"; |
|
phy-supply = <0x99>; |
|
phandle = <0x2d>; |
|
}; |
|
|
|
otg-port { |
|
#phy-cells = <0x00>; |
|
interrupts = <0x00 0x6c 0x04 0x00 0x00 0x6d 0x04 0x00 0x00 0x6f 0x04 0x00>; |
|
interrupt-names = "otg-bvalid\0otg-id\0linestate"; |
|
status = "okay"; |
|
phandle = <0x30>; |
|
}; |
|
}; |
|
|
|
phy@f780 { |
|
compatible = "rockchip,rk3399-emmc-phy"; |
|
reg = <0xf780 0x24>; |
|
clocks = <0x9b>; |
|
clock-names = "emmcclk"; |
|
drive-impedance-ohm = <0x32>; |
|
#phy-cells = <0x00>; |
|
status = "okay"; |
|
phandle = <0x29>; |
|
}; |
|
|
|
pcie-phy { |
|
compatible = "rockchip,rk3399-pcie-phy"; |
|
clocks = <0x08 0x8a>; |
|
clock-names = "refclk"; |
|
#phy-cells = <0x01>; |
|
resets = <0x08 0x87>; |
|
reset-names = "phy"; |
|
status = "okay"; |
|
phandle = <0x17>; |
|
}; |
|
}; |
|
|
|
phy@ff7c0000 { |
|
compatible = "rockchip,rk3399-typec-phy"; |
|
reg = <0x00 0xff7c0000 0x00 0x40000>; |
|
clocks = <0x08 0x7e 0x08 0x7d>; |
|
clock-names = "tcpdcore\0tcpdphy-ref"; |
|
assigned-clocks = <0x08 0x7e>; |
|
assigned-clock-rates = <0x2faf080>; |
|
power-domains = <0x1d 0x08>; |
|
resets = <0x08 0x95 0x08 0x94 0x08 0x14c>; |
|
reset-names = "uphy\0uphy-pipe\0uphy-tcphy"; |
|
rockchip,grf = <0x1e>; |
|
status = "okay"; |
|
phandle = <0x124>; |
|
|
|
dp-port { |
|
#phy-cells = <0x00>; |
|
phandle = <0x32>; |
|
|
|
port { |
|
|
|
endpoint { |
|
remote-endpoint = <0x9c>; |
|
phandle = <0x8d>; |
|
}; |
|
}; |
|
}; |
|
|
|
usb3-port { |
|
#phy-cells = <0x00>; |
|
phandle = <0x2f>; |
|
|
|
port { |
|
|
|
endpoint { |
|
remote-endpoint = <0x9d>; |
|
phandle = <0x8c>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
phy@ff800000 { |
|
compatible = "rockchip,rk3399-typec-phy"; |
|
reg = <0x00 0xff800000 0x00 0x40000>; |
|
clocks = <0x08 0x80 0x08 0x7f>; |
|
clock-names = "tcpdcore\0tcpdphy-ref"; |
|
assigned-clocks = <0x08 0x80>; |
|
assigned-clock-rates = <0x2faf080>; |
|
power-domains = <0x1d 0x09>; |
|
resets = <0x08 0x9d 0x08 0x9c 0x08 0x14d>; |
|
reset-names = "uphy\0uphy-pipe\0uphy-tcphy"; |
|
rockchip,grf = <0x1e>; |
|
status = "okay"; |
|
phandle = <0x125>; |
|
|
|
dp-port { |
|
#phy-cells = <0x00>; |
|
phandle = <0x33>; |
|
}; |
|
|
|
usb3-port { |
|
#phy-cells = <0x00>; |
|
phandle = <0x31>; |
|
}; |
|
}; |
|
|
|
watchdog@ff848000 { |
|
compatible = "rockchip,rk3399-wdt\0snps,dw-wdt"; |
|
reg = <0x00 0xff848000 0x00 0x100>; |
|
clocks = <0x08 0x17c>; |
|
interrupts = <0x00 0x78 0x04 0x00>; |
|
}; |
|
|
|
rktimer@ff850000 { |
|
compatible = "rockchip,rk3399-timer"; |
|
reg = <0x00 0xff850000 0x00 0x1000>; |
|
interrupts = <0x00 0x51 0x04 0x00>; |
|
clocks = <0x08 0x168 0x08 0x5a>; |
|
clock-names = "pclk\0timer"; |
|
phandle = <0x126>; |
|
}; |
|
|
|
spdif@ff870000 { |
|
compatible = "rockchip,rk3399-spdif"; |
|
reg = <0x00 0xff870000 0x00 0x1000>; |
|
interrupts = <0x00 0x42 0x04 0x00>; |
|
dmas = <0x59 0x07>; |
|
dma-names = "tx"; |
|
clock-names = "mclk\0hclk"; |
|
clocks = <0x08 0x55 0x08 0x1d7>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x9e>; |
|
power-domains = <0x1d 0x1c>; |
|
#sound-dai-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0x127>; |
|
}; |
|
|
|
i2s@ff880000 { |
|
compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s"; |
|
reg = <0x00 0xff880000 0x00 0x1000>; |
|
rockchip,grf = <0x1e>; |
|
interrupts = <0x00 0x27 0x04 0x00>; |
|
dmas = <0x59 0x00 0x59 0x01>; |
|
dma-names = "tx\0rx"; |
|
clock-names = "i2s_clk\0i2s_hclk"; |
|
clocks = <0x08 0x56 0x08 0x1d4>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0x9f>; |
|
power-domains = <0x1d 0x1c>; |
|
#sound-dai-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0x128>; |
|
}; |
|
|
|
i2s@ff890000 { |
|
compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s"; |
|
reg = <0x00 0xff890000 0x00 0x1000>; |
|
interrupts = <0x00 0x28 0x04 0x00>; |
|
dmas = <0x59 0x02 0x59 0x03>; |
|
dma-names = "tx\0rx"; |
|
clock-names = "i2s_clk\0i2s_hclk"; |
|
clocks = <0x08 0x57 0x08 0x1d5>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0xa0 0xa1>; |
|
power-domains = <0x1d 0x1c>; |
|
#sound-dai-cells = <0x00>; |
|
status = "okay"; |
|
rockchip,capture-channels = <0x08>; |
|
rockchip,playback-channels = <0x08>; |
|
phandle = <0xd2>; |
|
}; |
|
|
|
i2s@ff8a0000 { |
|
compatible = "rockchip,rk3399-i2s\0rockchip,rk3066-i2s"; |
|
reg = <0x00 0xff8a0000 0x00 0x1000>; |
|
interrupts = <0x00 0x29 0x04 0x00>; |
|
dmas = <0x59 0x04 0x59 0x05>; |
|
dma-names = "tx\0rx"; |
|
clock-names = "i2s_clk\0i2s_hclk"; |
|
clocks = <0x08 0x58 0x08 0x1d6>; |
|
power-domains = <0x1d 0x1c>; |
|
#sound-dai-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0xb2>; |
|
}; |
|
|
|
vop@ff8f0000 { |
|
compatible = "rockchip,rk3399-vop-lit"; |
|
reg = <0x00 0xff8f0000 0x00 0x2000 0x00 0xff8f2000 0x00 0x400>; |
|
interrupts = <0x00 0x77 0x04 0x00>; |
|
assigned-clocks = <0x08 0xdb 0x08 0x1db>; |
|
assigned-clock-rates = <0x17d78400 0x5f5e100>; |
|
clocks = <0x08 0xdb 0x08 0xb5 0x08 0x1db>; |
|
clock-names = "aclk_vop\0dclk_vop\0hclk_vop"; |
|
iommus = <0xa2>; |
|
power-domains = <0x1d 0x12>; |
|
resets = <0x08 0x113 0x08 0x117 0x08 0x119>; |
|
reset-names = "axi\0ahb\0dclk"; |
|
status = "okay"; |
|
phandle = <0x129>; |
|
|
|
port { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
phandle = <0x0f>; |
|
|
|
endpoint@0 { |
|
reg = <0x00>; |
|
remote-endpoint = <0xa3>; |
|
phandle = <0xb7>; |
|
}; |
|
|
|
endpoint@1 { |
|
reg = <0x01>; |
|
remote-endpoint = <0xa4>; |
|
phandle = <0xbc>; |
|
}; |
|
|
|
endpoint@2 { |
|
reg = <0x02>; |
|
remote-endpoint = <0xa5>; |
|
phandle = <0xb5>; |
|
}; |
|
|
|
endpoint@3 { |
|
reg = <0x03>; |
|
remote-endpoint = <0xa6>; |
|
phandle = <0xb9>; |
|
}; |
|
|
|
endpoint@4 { |
|
reg = <0x04>; |
|
remote-endpoint = <0xa7>; |
|
phandle = <0x35>; |
|
}; |
|
}; |
|
}; |
|
|
|
iommu@ff8f3f00 { |
|
compatible = "rockchip,iommu"; |
|
reg = <0x00 0xff8f3f00 0x00 0x100>; |
|
interrupts = <0x00 0x77 0x04 0x00>; |
|
clocks = <0x08 0xdb 0x08 0x1db>; |
|
clock-names = "aclk\0iface"; |
|
power-domains = <0x1d 0x12>; |
|
#iommu-cells = <0x00>; |
|
status = "okay"; |
|
phandle = <0xa2>; |
|
}; |
|
|
|
vop@ff900000 { |
|
compatible = "rockchip,rk3399-vop-big"; |
|
reg = <0x00 0xff900000 0x00 0x2000 0x00 0xff902000 0x00 0x1000>; |
|
interrupts = <0x00 0x76 0x04 0x00>; |
|
assigned-clocks = <0x08 0xd9 0x08 0x1d9>; |
|
assigned-clock-rates = <0x17d78400 0x5f5e100>; |
|
clocks = <0x08 0xd9 0x08 0xb4 0x08 0x1d9>; |
|
clock-names = "aclk_vop\0dclk_vop\0hclk_vop"; |
|
iommus = <0xa8>; |
|
power-domains = <0x1d 0x11>; |
|
resets = <0x08 0x112 0x08 0x116 0x08 0x118>; |
|
reset-names = "axi\0ahb\0dclk"; |
|
status = "okay"; |
|
phandle = <0x12a>; |
|
|
|
port { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
phandle = <0x10>; |
|
|
|
endpoint@0 { |
|
reg = <0x00>; |
|
remote-endpoint = <0xa9>; |
|
phandle = <0xbb>; |
|
}; |
|
|
|
endpoint@1 { |
|
reg = <0x01>; |
|
remote-endpoint = <0xaa>; |
|
phandle = <0xb6>; |
|
}; |
|
|
|
endpoint@2 { |
|
reg = <0x02>; |
|
remote-endpoint = <0xab>; |
|
phandle = <0xb4>; |
|
}; |
|
|
|
endpoint@3 { |
|
reg = <0x03>; |
|
remote-endpoint = <0xac>; |
|
phandle = <0xb8>; |
|
}; |
|
|
|
endpoint@4 { |
|
reg = <0x04>; |
|
remote-endpoint = <0xad>; |
|
phandle = <0x34>; |
|
}; |
|
}; |
|
}; |
|
|
|
iommu@ff903f00 { |
|
compatible = "rockchip,iommu"; |
|
reg = <0x00 0xff903f00 0x00 0x100>; |
|
interrupts = <0x00 0x76 0x04 0x00>; |
|
clocks = <0x08 0xd9 0x08 0x1d9>; |
|
clock-names = "aclk\0iface"; |
|
power-domains = <0x1d 0x11>; |
|
#iommu-cells = <0x00>; |
|
status = "okay"; |
|
phandle = <0xa8>; |
|
}; |
|
|
|
isp0@ff910000 { |
|
compatible = "rockchip,rk3399-cif-isp"; |
|
reg = <0x00 0xff910000 0x00 0x4000>; |
|
interrupts = <0x00 0x2b 0x04 0x00>; |
|
clocks = <0x08 0x6e 0x08 0xe9 0x08 0x1e3>; |
|
clock-names = "isp\0aclk\0hclk"; |
|
iommus = <0xae>; |
|
phys = <0xaf>; |
|
phy-names = "dphy"; |
|
power-domains = <0x1d 0x13>; |
|
status = "disabled"; |
|
phandle = <0x12b>; |
|
|
|
ports { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
|
|
port@0 { |
|
reg = <0x00>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
}; |
|
}; |
|
}; |
|
|
|
iommu@ff914000 { |
|
compatible = "rockchip,iommu"; |
|
reg = <0x00 0xff914000 0x00 0x100 0x00 0xff915000 0x00 0x100>; |
|
interrupts = <0x00 0x2b 0x04 0x00>; |
|
clocks = <0x08 0xe9 0x08 0x1e3>; |
|
clock-names = "aclk\0iface"; |
|
#iommu-cells = <0x00>; |
|
power-domains = <0x1d 0x13>; |
|
rockchip,disable-mmu-reset; |
|
phandle = <0xae>; |
|
}; |
|
|
|
isp1@ff920000 { |
|
compatible = "rockchip,rk3399-cif-isp"; |
|
reg = <0x00 0xff920000 0x00 0x4000>; |
|
interrupts = <0x00 0x2c 0x04 0x00>; |
|
clocks = <0x08 0x6f 0x08 0xea 0x08 0x1e4>; |
|
clock-names = "isp\0aclk\0hclk"; |
|
iommus = <0xb0>; |
|
phys = <0xb1>; |
|
phy-names = "dphy"; |
|
power-domains = <0x1d 0x14>; |
|
status = "disabled"; |
|
phandle = <0x12c>; |
|
|
|
ports { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
|
|
port@0 { |
|
reg = <0x00>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
}; |
|
}; |
|
}; |
|
|
|
iommu@ff924000 { |
|
compatible = "rockchip,iommu"; |
|
reg = <0x00 0xff924000 0x00 0x100 0x00 0xff925000 0x00 0x100>; |
|
interrupts = <0x00 0x2c 0x04 0x00>; |
|
clocks = <0x08 0xea 0x08 0x1e4>; |
|
clock-names = "aclk\0iface"; |
|
#iommu-cells = <0x00>; |
|
power-domains = <0x1d 0x14>; |
|
rockchip,disable-mmu-reset; |
|
phandle = <0xb0>; |
|
}; |
|
|
|
hdmi-sound { |
|
compatible = "simple-audio-card"; |
|
simple-audio-card,format = "i2s"; |
|
simple-audio-card,mclk-fs = <0x100>; |
|
simple-audio-card,name = "hdmi-sound"; |
|
status = "okay"; |
|
phandle = <0x12d>; |
|
|
|
simple-audio-card,cpu { |
|
sound-dai = <0xb2>; |
|
}; |
|
|
|
simple-audio-card,codec { |
|
sound-dai = <0xb3>; |
|
}; |
|
}; |
|
|
|
hdmi@ff940000 { |
|
compatible = "rockchip,rk3399-dw-hdmi"; |
|
reg = <0x00 0xff940000 0x00 0x20000>; |
|
interrupts = <0x00 0x17 0x04 0x00>; |
|
clocks = <0x08 0x174 0x08 0x71 0x08 0x70 0x08 0x16f 0x08 0x07>; |
|
clock-names = "iahb\0isfr\0cec\0grf\0ref"; |
|
power-domains = <0x1d 0x15>; |
|
reg-io-width = <0x04>; |
|
rockchip,grf = <0x1e>; |
|
#sound-dai-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0xb3>; |
|
|
|
ports { |
|
|
|
port { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
phandle = <0x12e>; |
|
|
|
endpoint@0 { |
|
reg = <0x00>; |
|
remote-endpoint = <0xb4>; |
|
phandle = <0xab>; |
|
}; |
|
|
|
endpoint@1 { |
|
reg = <0x01>; |
|
remote-endpoint = <0xb5>; |
|
phandle = <0xa5>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
mipi@ff960000 { |
|
compatible = "rockchip,rk3399-mipi-dsi\0snps,dw-mipi-dsi"; |
|
reg = <0x00 0xff960000 0x00 0x8000>; |
|
interrupts = <0x00 0x2d 0x04 0x00>; |
|
clocks = <0x08 0xa2 0x08 0x170 0x08 0xa3 0x08 0x16f>; |
|
clock-names = "ref\0pclk\0phy_cfg\0grf"; |
|
power-domains = <0x1d 0x0f>; |
|
resets = <0x08 0xfb>; |
|
reset-names = "apb"; |
|
rockchip,grf = <0x1e>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0x12f>; |
|
|
|
ports { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
|
|
port@0 { |
|
reg = <0x00>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
phandle = <0x130>; |
|
|
|
endpoint@0 { |
|
reg = <0x00>; |
|
remote-endpoint = <0xb6>; |
|
phandle = <0xaa>; |
|
}; |
|
|
|
endpoint@1 { |
|
reg = <0x01>; |
|
remote-endpoint = <0xb7>; |
|
phandle = <0xa3>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
mipi@ff968000 { |
|
compatible = "rockchip,rk3399-mipi-dsi\0snps,dw-mipi-dsi"; |
|
reg = <0x00 0xff968000 0x00 0x8000>; |
|
interrupts = <0x00 0x2e 0x04 0x00>; |
|
clocks = <0x08 0xa2 0x08 0x171 0x08 0xa4 0x08 0x16f>; |
|
clock-names = "ref\0pclk\0phy_cfg\0grf"; |
|
power-domains = <0x1d 0x0f>; |
|
resets = <0x08 0xfc>; |
|
reset-names = "apb"; |
|
rockchip,grf = <0x1e>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
#phy-cells = <0x00>; |
|
status = "disabled"; |
|
phandle = <0xb1>; |
|
|
|
ports { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
|
|
port@0 { |
|
reg = <0x00>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
phandle = <0x131>; |
|
|
|
endpoint@0 { |
|
reg = <0x00>; |
|
remote-endpoint = <0xb8>; |
|
phandle = <0xac>; |
|
}; |
|
|
|
endpoint@1 { |
|
reg = <0x01>; |
|
remote-endpoint = <0xb9>; |
|
phandle = <0xa6>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
edp@ff970000 { |
|
compatible = "rockchip,rk3399-edp"; |
|
reg = <0x00 0xff970000 0x00 0x8000>; |
|
interrupts = <0x00 0x0a 0x04 0x00>; |
|
clocks = <0x08 0x16a 0x08 0x16c 0x08 0x16f>; |
|
clock-names = "dp\0pclk\0grf"; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0xba>; |
|
power-domains = <0x1d 0x19>; |
|
resets = <0x08 0x11d>; |
|
reset-names = "dp"; |
|
rockchip,grf = <0x1e>; |
|
status = "okay"; |
|
force-hpd; |
|
phandle = <0x132>; |
|
|
|
ports { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
|
|
port@0 { |
|
reg = <0x00>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
phandle = <0x133>; |
|
|
|
endpoint@0 { |
|
reg = <0x00>; |
|
remote-endpoint = <0xbb>; |
|
phandle = <0xa9>; |
|
}; |
|
|
|
endpoint@1 { |
|
reg = <0x01>; |
|
remote-endpoint = <0xbc>; |
|
phandle = <0xa4>; |
|
}; |
|
}; |
|
|
|
port@1 { |
|
reg = <0x01>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
phandle = <0x134>; |
|
|
|
endpoint@0 { |
|
reg = <0x00>; |
|
remote-endpoint = <0xbd>; |
|
phandle = <0xca>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
gpu@ff9a0000 { |
|
compatible = "rockchip,rk3399-mali\0arm,mali-t860"; |
|
reg = <0x00 0xff9a0000 0x00 0x10000>; |
|
interrupts = <0x00 0x14 0x04 0x00 0x00 0x15 0x04 0x00 0x00 0x13 0x04 0x00>; |
|
interrupt-names = "job\0mmu\0gpu"; |
|
clocks = <0x08 0xd0>; |
|
#cooling-cells = <0x02>; |
|
power-domains = <0x1d 0x23>; |
|
status = "okay"; |
|
operating-points-v2 = <0xbe>; |
|
mali-supply = <0xbf>; |
|
phandle = <0x62>; |
|
}; |
|
|
|
pinctrl { |
|
compatible = "rockchip,rk3399-pinctrl"; |
|
rockchip,grf = <0x1e>; |
|
rockchip,pmu = <0x11>; |
|
#address-cells = <0x02>; |
|
#size-cells = <0x02>; |
|
ranges; |
|
phandle = <0x135>; |
|
|
|
gpio@ff720000 { |
|
compatible = "rockchip,gpio-bank"; |
|
reg = <0x00 0xff720000 0x00 0x100>; |
|
clocks = <0x7b 0x17>; |
|
interrupts = <0x00 0x0e 0x04 0x00>; |
|
gpio-controller; |
|
#gpio-cells = <0x02>; |
|
interrupt-controller; |
|
#interrupt-cells = <0x02>; |
|
phandle = <0x23>; |
|
}; |
|
|
|
gpio@ff730000 { |
|
compatible = "rockchip,gpio-bank"; |
|
reg = <0x00 0xff730000 0x00 0x100>; |
|
clocks = <0x7b 0x18>; |
|
interrupts = <0x00 0x0f 0x04 0x00>; |
|
gpio-controller; |
|
#gpio-cells = <0x02>; |
|
interrupt-controller; |
|
#interrupt-cells = <0x02>; |
|
phandle = <0x88>; |
|
}; |
|
|
|
gpio@ff780000 { |
|
compatible = "rockchip,gpio-bank"; |
|
reg = <0x00 0xff780000 0x00 0x100>; |
|
clocks = <0x08 0x150>; |
|
interrupts = <0x00 0x10 0x04 0x00>; |
|
gpio-controller; |
|
#gpio-cells = <0x02>; |
|
interrupt-controller; |
|
#interrupt-cells = <0x02>; |
|
phandle = <0x18>; |
|
}; |
|
|
|
gpio@ff788000 { |
|
compatible = "rockchip,gpio-bank"; |
|
reg = <0x00 0xff788000 0x00 0x100>; |
|
clocks = <0x08 0x151>; |
|
interrupts = <0x00 0x11 0x04 0x00>; |
|
gpio-controller; |
|
#gpio-cells = <0x02>; |
|
interrupt-controller; |
|
#interrupt-cells = <0x02>; |
|
phandle = <0x82>; |
|
}; |
|
|
|
gpio@ff790000 { |
|
compatible = "rockchip,gpio-bank"; |
|
reg = <0x00 0xff790000 0x00 0x100>; |
|
clocks = <0x08 0x152>; |
|
interrupts = <0x00 0x12 0x04 0x00>; |
|
gpio-controller; |
|
#gpio-cells = <0x02>; |
|
interrupt-controller; |
|
#interrupt-cells = <0x02>; |
|
phandle = <0xd4>; |
|
}; |
|
|
|
pcfg-pull-up { |
|
bias-pull-up; |
|
phandle = <0xc3>; |
|
}; |
|
|
|
pcfg-pull-down { |
|
bias-pull-down; |
|
phandle = <0xc4>; |
|
}; |
|
|
|
pcfg-pull-none { |
|
bias-disable; |
|
phandle = <0xc0>; |
|
}; |
|
|
|
pcfg-pull-none-12ma { |
|
bias-disable; |
|
drive-strength = <0x0c>; |
|
phandle = <0xc2>; |
|
}; |
|
|
|
pcfg-pull-none-13ma { |
|
bias-disable; |
|
drive-strength = <0x0d>; |
|
phandle = <0xc1>; |
|
}; |
|
|
|
pcfg-pull-none-18ma { |
|
bias-disable; |
|
drive-strength = <0x12>; |
|
phandle = <0x136>; |
|
}; |
|
|
|
pcfg-pull-none-20ma { |
|
bias-disable; |
|
drive-strength = <0x14>; |
|
phandle = <0x137>; |
|
}; |
|
|
|
pcfg-pull-up-2ma { |
|
bias-pull-up; |
|
drive-strength = <0x02>; |
|
phandle = <0x138>; |
|
}; |
|
|
|
pcfg-pull-up-8ma { |
|
bias-pull-up; |
|
drive-strength = <0x08>; |
|
phandle = <0x139>; |
|
}; |
|
|
|
pcfg-pull-up-18ma { |
|
bias-pull-up; |
|
drive-strength = <0x12>; |
|
phandle = <0x13a>; |
|
}; |
|
|
|
pcfg-pull-up-20ma { |
|
bias-pull-up; |
|
drive-strength = <0x14>; |
|
phandle = <0x13b>; |
|
}; |
|
|
|
pcfg-pull-down-4ma { |
|
bias-pull-down; |
|
drive-strength = <0x04>; |
|
phandle = <0x13c>; |
|
}; |
|
|
|
pcfg-pull-down-8ma { |
|
bias-pull-down; |
|
drive-strength = <0x08>; |
|
phandle = <0x13d>; |
|
}; |
|
|
|
pcfg-pull-down-12ma { |
|
bias-pull-down; |
|
drive-strength = <0x0c>; |
|
phandle = <0x13e>; |
|
}; |
|
|
|
pcfg-pull-down-18ma { |
|
bias-pull-down; |
|
drive-strength = <0x12>; |
|
phandle = <0x13f>; |
|
}; |
|
|
|
pcfg-pull-down-20ma { |
|
bias-pull-down; |
|
drive-strength = <0x14>; |
|
phandle = <0x140>; |
|
}; |
|
|
|
pcfg-output-high { |
|
output-high; |
|
phandle = <0x141>; |
|
}; |
|
|
|
pcfg-output-low { |
|
output-low; |
|
phandle = <0x142>; |
|
}; |
|
|
|
pcfg-input-enable { |
|
input-enable; |
|
phandle = <0x143>; |
|
}; |
|
|
|
pcfg-input-pull-up { |
|
input-enable; |
|
bias-pull-up; |
|
drive-strength = <0x02>; |
|
phandle = <0x144>; |
|
}; |
|
|
|
pcfg-input-pull-down { |
|
input-enable; |
|
bias-pull-down; |
|
drive-strength = <0x02>; |
|
phandle = <0x145>; |
|
}; |
|
|
|
clock { |
|
|
|
clk-32k { |
|
rockchip,pins = <0x00 0x00 0x02 0xc0>; |
|
phandle = <0x146>; |
|
}; |
|
}; |
|
|
|
cif { |
|
|
|
cif-clkin { |
|
rockchip,pins = <0x02 0x0a 0x03 0xc0>; |
|
phandle = <0x147>; |
|
}; |
|
|
|
cif-clkouta { |
|
rockchip,pins = <0x02 0x0b 0x03 0xc0>; |
|
phandle = <0x148>; |
|
}; |
|
}; |
|
|
|
edp { |
|
|
|
edp-hpd { |
|
rockchip,pins = <0x04 0x17 0x02 0xc0>; |
|
phandle = <0xba>; |
|
}; |
|
}; |
|
|
|
gmac { |
|
|
|
rgmii-pins { |
|
rockchip,pins = <0x03 0x11 0x01 0xc1 0x03 0x0e 0x01 0xc0 0x03 0x0d 0x01 0xc0 0x03 0x0c 0x01 0xc1 0x03 0x0b 0x01 0xc0 0x03 0x09 0x01 0xc0 0x03 0x08 0x01 0xc0 0x03 0x07 0x01 0xc0 0x03 0x06 0x01 0xc0 0x03 0x05 0x01 0xc1 0x03 0x04 0x01 0xc1 0x03 0x03 0x01 0xc0 0x03 0x02 0x01 0xc0 0x03 0x01 0x01 0xc1 0x03 0x00 0x01 0xc1>; |
|
phandle = <0x149>; |
|
}; |
|
|
|
rmii-pins { |
|
rockchip,pins = <0x03 0x0d 0x01 0xc0 0x03 0x0c 0x01 0xc1 0x03 0x0b 0x01 0xc0 0x03 0x0a 0x01 0xc0 0x03 0x09 0x01 0xc0 0x03 0x08 0x01 0xc0 0x03 0x07 0x01 0xc0 0x03 0x06 0x01 0xc0 0x03 0x05 0x01 0xc1 0x03 0x04 0x01 0xc1>; |
|
phandle = <0x14a>; |
|
}; |
|
}; |
|
|
|
i2c0 { |
|
|
|
i2c0-xfer { |
|
rockchip,pins = <0x01 0x0f 0x02 0xc0 0x01 0x10 0x02 0xc0>; |
|
phandle = <0x81>; |
|
}; |
|
}; |
|
|
|
i2c1 { |
|
|
|
i2c1-xfer { |
|
rockchip,pins = <0x04 0x02 0x01 0xc0 0x04 0x01 0x01 0xc0>; |
|
phandle = <0x36>; |
|
}; |
|
}; |
|
|
|
i2c2 { |
|
|
|
i2c2-xfer { |
|
rockchip,pins = <0x02 0x01 0x02 0xc2 0x02 0x00 0x02 0xc2>; |
|
phandle = <0x37>; |
|
}; |
|
}; |
|
|
|
i2c3 { |
|
|
|
i2c3-xfer { |
|
rockchip,pins = <0x04 0x11 0x01 0xc0 0x04 0x10 0x01 0xc0>; |
|
phandle = <0x38>; |
|
}; |
|
}; |
|
|
|
i2c4 { |
|
|
|
i2c4-xfer { |
|
rockchip,pins = <0x01 0x0c 0x01 0xc0 0x01 0x0b 0x01 0xc0>; |
|
phandle = <0x87>; |
|
}; |
|
}; |
|
|
|
i2c5 { |
|
|
|
i2c5-xfer { |
|
rockchip,pins = <0x03 0x0b 0x02 0xc0 0x03 0x0a 0x02 0xc0>; |
|
phandle = <0x39>; |
|
}; |
|
}; |
|
|
|
i2c6 { |
|
|
|
i2c6-xfer { |
|
rockchip,pins = <0x02 0x0a 0x02 0xc0 0x02 0x09 0x02 0xc0>; |
|
phandle = <0x3a>; |
|
}; |
|
}; |
|
|
|
i2c7 { |
|
|
|
i2c7-xfer { |
|
rockchip,pins = <0x02 0x08 0x02 0xc0 0x02 0x07 0x02 0xc0>; |
|
phandle = <0x3b>; |
|
}; |
|
}; |
|
|
|
i2c8 { |
|
|
|
i2c8-xfer { |
|
rockchip,pins = <0x01 0x15 0x01 0xc0 0x01 0x14 0x01 0xc0>; |
|
phandle = <0x91>; |
|
}; |
|
}; |
|
|
|
i2s0 { |
|
|
|
i2s0-2ch-bus { |
|
rockchip,pins = <0x03 0x18 0x01 0xc0 0x03 0x19 0x01 0xc0 0x03 0x1a 0x01 0xc0 0x03 0x1b 0x01 0xc0 0x03 0x1f 0x01 0xc0 0x04 0x00 0x01 0xc0>; |
|
phandle = <0x14b>; |
|
}; |
|
|
|
i2s0-8ch-bus { |
|
rockchip,pins = <0x03 0x18 0x01 0xc0 0x03 0x19 0x01 0xc0 0x03 0x1a 0x01 0xc0 0x03 0x1b 0x01 0xc0 0x03 0x1c 0x01 0xc0 0x03 0x1d 0x01 0xc0 0x03 0x1e 0x01 0xc0 0x03 0x1f 0x01 0xc0 0x04 0x00 0x01 0xc0>; |
|
phandle = <0x9f>; |
|
}; |
|
}; |
|
|
|
i2s1 { |
|
|
|
i2s1-2ch-bus { |
|
rockchip,pins = <0x04 0x03 0x01 0xc0 0x04 0x04 0x01 0xc0 0x04 0x05 0x01 0xc0 0x04 0x06 0x01 0xc0 0x04 0x07 0x01 0xc0>; |
|
phandle = <0xa1>; |
|
}; |
|
|
|
i2s-8ch-mclk-pin { |
|
rockchip,pins = <0x04 0x00 0x01 0xc0>; |
|
phandle = <0xa0>; |
|
}; |
|
}; |
|
|
|
sdio0 { |
|
|
|
sdio0-bus1 { |
|
rockchip,pins = <0x02 0x14 0x01 0xc3>; |
|
phandle = <0x14c>; |
|
}; |
|
|
|
sdio0-bus4 { |
|
rockchip,pins = <0x02 0x14 0x01 0xc3 0x02 0x15 0x01 0xc3 0x02 0x16 0x01 0xc3 0x02 0x17 0x01 0xc3>; |
|
phandle = <0x20>; |
|
}; |
|
|
|
sdio0-cmd { |
|
rockchip,pins = <0x02 0x18 0x01 0xc3>; |
|
phandle = <0x21>; |
|
}; |
|
|
|
sdio0-clk { |
|
rockchip,pins = <0x02 0x19 0x01 0xc0>; |
|
phandle = <0x22>; |
|
}; |
|
|
|
sdio0-cd { |
|
rockchip,pins = <0x02 0x1a 0x01 0xc3>; |
|
phandle = <0x14d>; |
|
}; |
|
|
|
sdio0-pwr { |
|
rockchip,pins = <0x02 0x1b 0x01 0xc3>; |
|
phandle = <0x14e>; |
|
}; |
|
|
|
sdio0-bkpwr { |
|
rockchip,pins = <0x02 0x1c 0x01 0xc3>; |
|
phandle = <0x14f>; |
|
}; |
|
|
|
sdio0-wp { |
|
rockchip,pins = <0x00 0x03 0x01 0xc3>; |
|
phandle = <0x150>; |
|
}; |
|
|
|
sdio0-int { |
|
rockchip,pins = <0x00 0x04 0x01 0xc3>; |
|
phandle = <0x151>; |
|
}; |
|
}; |
|
|
|
sdmmc { |
|
|
|
sdmmc-bus1 { |
|
rockchip,pins = <0x04 0x08 0x01 0xc3>; |
|
phandle = <0x152>; |
|
}; |
|
|
|
sdmmc-bus4 { |
|
rockchip,pins = <0x04 0x08 0x01 0xc3 0x04 0x09 0x01 0xc3 0x04 0x0a 0x01 0xc3 0x04 0x0b 0x01 0xc3>; |
|
phandle = <0x26>; |
|
}; |
|
|
|
sdmmc-clk { |
|
rockchip,pins = <0x04 0x0c 0x01 0xc0>; |
|
phandle = <0x24>; |
|
}; |
|
|
|
sdmmc-cmd { |
|
rockchip,pins = <0x04 0x0d 0x01 0xc3>; |
|
phandle = <0x25>; |
|
}; |
|
|
|
sdmmc-cd { |
|
rockchip,pins = <0x00 0x07 0x01 0xc3>; |
|
phandle = <0x153>; |
|
}; |
|
|
|
sdmmc-wp { |
|
rockchip,pins = <0x00 0x08 0x01 0xc3>; |
|
phandle = <0x154>; |
|
}; |
|
}; |
|
|
|
suspend { |
|
|
|
ap-pwroff { |
|
rockchip,pins = <0x01 0x05 0x01 0xc0>; |
|
phandle = <0x155>; |
|
}; |
|
|
|
ddrio-pwroff { |
|
rockchip,pins = <0x00 0x01 0x01 0xc0>; |
|
phandle = <0x156>; |
|
}; |
|
}; |
|
|
|
spdif { |
|
|
|
spdif-bus { |
|
rockchip,pins = <0x04 0x15 0x01 0xc0>; |
|
phandle = <0x9e>; |
|
}; |
|
|
|
spdif-bus-1 { |
|
rockchip,pins = <0x03 0x10 0x03 0xc0>; |
|
phandle = <0x157>; |
|
}; |
|
}; |
|
|
|
spi0 { |
|
|
|
spi0-clk { |
|
rockchip,pins = <0x03 0x06 0x02 0xc3>; |
|
phandle = <0x49>; |
|
}; |
|
|
|
spi0-cs0 { |
|
rockchip,pins = <0x03 0x07 0x02 0xc3>; |
|
phandle = <0x4c>; |
|
}; |
|
|
|
spi0-cs1 { |
|
rockchip,pins = <0x03 0x08 0x02 0xc3>; |
|
phandle = <0x158>; |
|
}; |
|
|
|
spi0-tx { |
|
rockchip,pins = <0x03 0x05 0x02 0xc3>; |
|
phandle = <0x4a>; |
|
}; |
|
|
|
spi0-rx { |
|
rockchip,pins = <0x03 0x04 0x02 0xc3>; |
|
phandle = <0x4b>; |
|
}; |
|
}; |
|
|
|
spi1 { |
|
|
|
spi1-clk { |
|
rockchip,pins = <0x01 0x09 0x02 0xc3>; |
|
phandle = <0x4d>; |
|
}; |
|
|
|
spi1-cs0 { |
|
rockchip,pins = <0x01 0x0a 0x02 0xc3>; |
|
phandle = <0x50>; |
|
}; |
|
|
|
spi1-rx { |
|
rockchip,pins = <0x01 0x07 0x02 0xc3>; |
|
phandle = <0x4f>; |
|
}; |
|
|
|
spi1-tx { |
|
rockchip,pins = <0x01 0x08 0x02 0xc3>; |
|
phandle = <0x4e>; |
|
}; |
|
}; |
|
|
|
spi2 { |
|
|
|
spi2-clk { |
|
rockchip,pins = <0x02 0x0b 0x01 0xc3>; |
|
phandle = <0x51>; |
|
}; |
|
|
|
spi2-cs0 { |
|
rockchip,pins = <0x02 0x0c 0x01 0xc3>; |
|
phandle = <0x54>; |
|
}; |
|
|
|
spi2-rx { |
|
rockchip,pins = <0x02 0x09 0x01 0xc3>; |
|
phandle = <0x53>; |
|
}; |
|
|
|
spi2-tx { |
|
rockchip,pins = <0x02 0x0a 0x01 0xc3>; |
|
phandle = <0x52>; |
|
}; |
|
}; |
|
|
|
spi3 { |
|
|
|
spi3-clk { |
|
rockchip,pins = <0x01 0x11 0x01 0xc3>; |
|
phandle = <0x7c>; |
|
}; |
|
|
|
spi3-cs0 { |
|
rockchip,pins = <0x01 0x12 0x01 0xc3>; |
|
phandle = <0x7f>; |
|
}; |
|
|
|
spi3-rx { |
|
rockchip,pins = <0x01 0x0f 0x01 0xc3>; |
|
phandle = <0x7e>; |
|
}; |
|
|
|
spi3-tx { |
|
rockchip,pins = <0x01 0x10 0x01 0xc3>; |
|
phandle = <0x7d>; |
|
}; |
|
}; |
|
|
|
spi4 { |
|
|
|
spi4-clk { |
|
rockchip,pins = <0x03 0x02 0x02 0xc3>; |
|
phandle = <0x55>; |
|
}; |
|
|
|
spi4-cs0 { |
|
rockchip,pins = <0x03 0x03 0x02 0xc3>; |
|
phandle = <0x58>; |
|
}; |
|
|
|
spi4-rx { |
|
rockchip,pins = <0x03 0x00 0x02 0xc3>; |
|
phandle = <0x57>; |
|
}; |
|
|
|
spi4-tx { |
|
rockchip,pins = <0x03 0x01 0x02 0xc3>; |
|
phandle = <0x56>; |
|
}; |
|
}; |
|
|
|
spi5 { |
|
|
|
spi5-clk { |
|
rockchip,pins = <0x02 0x16 0x02 0xc3>; |
|
phandle = <0x5a>; |
|
}; |
|
|
|
spi5-cs0 { |
|
rockchip,pins = <0x02 0x17 0x02 0xc3>; |
|
phandle = <0x5d>; |
|
}; |
|
|
|
spi5-rx { |
|
rockchip,pins = <0x02 0x14 0x02 0xc3>; |
|
phandle = <0x5c>; |
|
}; |
|
|
|
spi5-tx { |
|
rockchip,pins = <0x02 0x15 0x02 0xc3>; |
|
phandle = <0x5b>; |
|
}; |
|
}; |
|
|
|
testclk { |
|
|
|
test-clkout0 { |
|
rockchip,pins = <0x00 0x00 0x01 0xc0>; |
|
phandle = <0x159>; |
|
}; |
|
|
|
test-clkout1 { |
|
rockchip,pins = <0x02 0x19 0x02 0xc0>; |
|
phandle = <0x15a>; |
|
}; |
|
|
|
test-clkout2 { |
|
rockchip,pins = <0x00 0x08 0x03 0xc0>; |
|
phandle = <0x15b>; |
|
}; |
|
}; |
|
|
|
tsadc { |
|
|
|
otp-pin { |
|
rockchip,pins = <0x01 0x06 0x00 0xc0>; |
|
phandle = <0x63>; |
|
}; |
|
|
|
otp-out { |
|
rockchip,pins = <0x01 0x06 0x01 0xc0>; |
|
phandle = <0x64>; |
|
}; |
|
}; |
|
|
|
uart0 { |
|
|
|
uart0-xfer { |
|
rockchip,pins = <0x02 0x10 0x01 0xc3 0x02 0x11 0x01 0xc0>; |
|
phandle = <0x3c>; |
|
}; |
|
|
|
uart0-cts { |
|
rockchip,pins = <0x02 0x12 0x01 0xc0>; |
|
phandle = <0x3d>; |
|
}; |
|
|
|
uart0-rts { |
|
rockchip,pins = <0x02 0x13 0x01 0xc0>; |
|
phandle = <0x3e>; |
|
}; |
|
}; |
|
|
|
uart1 { |
|
|
|
uart1-xfer { |
|
rockchip,pins = <0x03 0x0c 0x02 0xc3 0x03 0x0d 0x02 0xc0>; |
|
phandle = <0x45>; |
|
}; |
|
}; |
|
|
|
uart2a { |
|
|
|
uart2a-xfer { |
|
rockchip,pins = <0x04 0x08 0x02 0xc3 0x04 0x09 0x02 0xc0>; |
|
phandle = <0x15c>; |
|
}; |
|
}; |
|
|
|
uart2b { |
|
|
|
uart2b-xfer { |
|
rockchip,pins = <0x04 0x10 0x02 0xc3 0x04 0x11 0x02 0xc0>; |
|
phandle = <0x15d>; |
|
}; |
|
}; |
|
|
|
uart2c { |
|
|
|
uart2c-xfer { |
|
rockchip,pins = <0x04 0x13 0x01 0xc3 0x04 0x14 0x01 0xc0>; |
|
phandle = <0x46>; |
|
}; |
|
}; |
|
|
|
uart3 { |
|
|
|
uart3-xfer { |
|
rockchip,pins = <0x03 0x0e 0x02 0xc3 0x03 0x0f 0x02 0xc0>; |
|
phandle = <0x47>; |
|
}; |
|
|
|
uart3-cts { |
|
rockchip,pins = <0x03 0x10 0x02 0xc0>; |
|
phandle = <0x15e>; |
|
}; |
|
|
|
uart3-rts { |
|
rockchip,pins = <0x03 0x11 0x02 0xc0>; |
|
phandle = <0x15f>; |
|
}; |
|
}; |
|
|
|
uart4 { |
|
|
|
uart4-xfer { |
|
rockchip,pins = <0x01 0x07 0x01 0xc3 0x01 0x08 0x01 0xc0>; |
|
phandle = <0x80>; |
|
}; |
|
}; |
|
|
|
uarthdcp { |
|
|
|
uarthdcp-xfer { |
|
rockchip,pins = <0x04 0x15 0x02 0xc3 0x04 0x16 0x02 0xc0>; |
|
phandle = <0x160>; |
|
}; |
|
}; |
|
|
|
pwm0 { |
|
|
|
pwm0-pin { |
|
rockchip,pins = <0x04 0x12 0x01 0xc0>; |
|
phandle = <0x92>; |
|
}; |
|
|
|
pwm0-pin-pull-down { |
|
rockchip,pins = <0x04 0x12 0x01 0xc4>; |
|
phandle = <0x161>; |
|
}; |
|
|
|
vop0-pwm-pin { |
|
rockchip,pins = <0x04 0x12 0x02 0xc0>; |
|
phandle = <0x162>; |
|
}; |
|
|
|
vop1-pwm-pin { |
|
rockchip,pins = <0x04 0x12 0x03 0xc0>; |
|
phandle = <0x163>; |
|
}; |
|
}; |
|
|
|
pwm1 { |
|
|
|
pwm1-pin { |
|
rockchip,pins = <0x04 0x16 0x01 0xc0>; |
|
phandle = <0x93>; |
|
}; |
|
|
|
pwm1-pin-pull-down { |
|
rockchip,pins = <0x04 0x16 0x01 0xc4>; |
|
phandle = <0x164>; |
|
}; |
|
}; |
|
|
|
pwm2 { |
|
|
|
pwm2-pin { |
|
rockchip,pins = <0x01 0x13 0x01 0xc0>; |
|
phandle = <0x94>; |
|
}; |
|
|
|
pwm2-pin-pull-down { |
|
rockchip,pins = <0x01 0x13 0x01 0xc4>; |
|
phandle = <0x165>; |
|
}; |
|
}; |
|
|
|
pwm3a { |
|
|
|
pwm3a-pin { |
|
rockchip,pins = <0x00 0x06 0x01 0xc0>; |
|
phandle = <0x95>; |
|
}; |
|
}; |
|
|
|
pwm3b { |
|
|
|
pwm3b-pin { |
|
rockchip,pins = <0x01 0x0e 0x01 0xc0>; |
|
phandle = <0x166>; |
|
}; |
|
}; |
|
|
|
hdmi { |
|
|
|
hdmi-i2c-xfer { |
|
rockchip,pins = <0x04 0x11 0x03 0xc0 0x04 0x10 0x03 0xc0>; |
|
phandle = <0x167>; |
|
}; |
|
|
|
hdmi-cec { |
|
rockchip,pins = <0x04 0x17 0x01 0xc0>; |
|
phandle = <0x168>; |
|
}; |
|
}; |
|
|
|
pcie { |
|
|
|
pci-clkreqn-cpm { |
|
rockchip,pins = <0x02 0x1a 0x00 0xc0>; |
|
phandle = <0x19>; |
|
}; |
|
|
|
pci-clkreqnb-cpm { |
|
rockchip,pins = <0x04 0x18 0x00 0xc0>; |
|
phandle = <0x169>; |
|
}; |
|
}; |
|
|
|
buttons { |
|
|
|
pwrbtn-pin { |
|
rockchip,pins = <0x00 0x05 0x00 0xc3>; |
|
phandle = <0xcc>; |
|
}; |
|
|
|
lidbtn-pin { |
|
rockchip,pins = <0x01 0x01 0x00 0xc3>; |
|
phandle = <0xcb>; |
|
}; |
|
}; |
|
|
|
dc-charger { |
|
|
|
dc-det-pin { |
|
rockchip,pins = <0x04 0x18 0x00 0xc3>; |
|
phandle = <0xdc>; |
|
}; |
|
}; |
|
|
|
es8316 { |
|
|
|
hp-det-pin { |
|
rockchip,pins = <0x00 0x08 0x00 0xc3>; |
|
phandle = <0xd0>; |
|
}; |
|
}; |
|
|
|
fusb302x { |
|
|
|
fusb0-int-pin { |
|
rockchip,pins = <0x01 0x02 0x00 0xc3>; |
|
phandle = <0x89>; |
|
}; |
|
}; |
|
|
|
lcd-panel { |
|
|
|
lcdvcc-en-pin { |
|
rockchip,pins = <0x01 0x16 0x00 0xc0>; |
|
phandle = <0xd9>; |
|
}; |
|
|
|
panel-en-pin { |
|
rockchip,pins = <0x01 0x00 0x00 0xc0>; |
|
phandle = <0xc8>; |
|
}; |
|
|
|
lcd-panel-reset-pin { |
|
rockchip,pins = <0x04 0x1e 0x00 0xc3>; |
|
phandle = <0x16a>; |
|
}; |
|
}; |
|
|
|
leds { |
|
|
|
pwr-led-pin { |
|
rockchip,pins = <0x00 0x0b 0x00 0xc0>; |
|
phandle = <0xcd>; |
|
}; |
|
|
|
slp-led-pin { |
|
rockchip,pins = <0x00 0x02 0x00 0xc0>; |
|
phandle = <0xce>; |
|
}; |
|
}; |
|
|
|
pmic { |
|
|
|
pmic-int-l-pin { |
|
rockchip,pins = <0x03 0x0a 0x00 0xc3>; |
|
phandle = <0x83>; |
|
}; |
|
|
|
vsel1-pin { |
|
rockchip,pins = <0x01 0x11 0x00 0xc4>; |
|
phandle = <0x85>; |
|
}; |
|
|
|
vsel2-pin { |
|
rockchip,pins = <0x01 0x0e 0x00 0xc4>; |
|
phandle = <0x86>; |
|
}; |
|
}; |
|
|
|
sdcard { |
|
|
|
sdmmc0-pwr-h-pin { |
|
rockchip,pins = <0x00 0x01 0x00 0xc0>; |
|
phandle = <0xd8>; |
|
}; |
|
}; |
|
|
|
sdio-pwrseq { |
|
|
|
wifi-enable-h-pin { |
|
rockchip,pins = <0x00 0x0a 0x00 0xc0>; |
|
phandle = <0xcf>; |
|
}; |
|
}; |
|
|
|
usb-typec { |
|
|
|
vcc5v0-typec0-en-pin { |
|
rockchip,pins = <0x01 0x03 0x00 0xc3>; |
|
phandle = <0xdb>; |
|
}; |
|
}; |
|
|
|
usb2 { |
|
|
|
pwr-5v-pin { |
|
rockchip,pins = <0x01 0x0d 0x00 0xc0>; |
|
phandle = <0xd6>; |
|
}; |
|
|
|
vcc5v0-host-en-pin { |
|
rockchip,pins = <0x04 0x1a 0x00 0xc0>; |
|
phandle = <0xda>; |
|
}; |
|
}; |
|
|
|
wireless-bluetooth { |
|
|
|
bt-wake-pin { |
|
rockchip,pins = <0x02 0x1b 0x00 0xc0>; |
|
phandle = <0x41>; |
|
}; |
|
|
|
bt-host-wake-pin { |
|
rockchip,pins = <0x00 0x04 0x00 0xc0>; |
|
phandle = <0x40>; |
|
}; |
|
|
|
bt-reset-pin { |
|
rockchip,pins = <0x00 0x09 0x00 0xc0>; |
|
phandle = <0x42>; |
|
}; |
|
}; |
|
}; |
|
|
|
opp-table-0 { |
|
compatible = "operating-points-v2"; |
|
opp-shared; |
|
phandle = <0x0b>; |
|
|
|
opp00 { |
|
opp-hz = /bits/ 64 <408000000>; |
|
opp-microvolt = <800000 800000 1200000>; |
|
clock-latency-ns = <40000>; |
|
}; |
|
opp01 { |
|
opp-hz = /bits/ 64 <600000000>; |
|
opp-microvolt = <825000 825000 1200000>; |
|
}; |
|
opp02 { |
|
opp-hz = /bits/ 64 <816000000>; |
|
opp-microvolt = <850000 850000 1200000>; |
|
}; |
|
opp03 { |
|
opp-hz = /bits/ 64 <1008000000>; |
|
opp-microvolt = <900000 900000 1200000>; |
|
}; |
|
opp04 { |
|
opp-hz = /bits/ 64 <1200000000>; |
|
opp-microvolt = <975000 975000 1200000>; |
|
}; |
|
opp05 { |
|
opp-hz = /bits/ 64 <1416000000>; |
|
opp-microvolt = <1100000 1100000 1200000>; |
|
}; |
|
opp06 { |
|
opp-hz = /bits/ 64 <1608000000>; |
|
opp-microvolt = <1200000 1200000 1200000>; |
|
}; |
|
opp07 { |
|
opp-hz = /bits/ 64 <1704000000>; |
|
opp-microvolt = <1200000 1200000 1200000>; |
|
}; |
|
}; |
|
|
|
opp-table-1 { |
|
compatible = "operating-points-v2"; |
|
opp-shared; |
|
phandle = <0x0d>; |
|
|
|
opp00 { |
|
opp-hz = /bits/ 64 <408000000>; |
|
opp-microvolt = <800000 800000 1250000>; |
|
clock-latency-ns = <40000>; |
|
}; |
|
opp01 { |
|
opp-hz = /bits/ 64 <600000000>; |
|
opp-microvolt = <800000 800000 1250000>; |
|
}; |
|
opp02 { |
|
opp-hz = /bits/ 64 <816000000>; |
|
opp-microvolt = <825000 825000 1250000>; |
|
}; |
|
opp03 { |
|
opp-hz = /bits/ 64 <1008000000>; |
|
opp-microvolt = <850000 850000 1250000>; |
|
}; |
|
opp04 { |
|
opp-hz = /bits/ 64 <1200000000>; |
|
opp-microvolt = <900000 900000 1250000>; |
|
}; |
|
opp05 { |
|
opp-hz = /bits/ 64 <1416000000>; |
|
opp-microvolt = <975000 975000 1250000>; |
|
}; |
|
opp06 { |
|
opp-hz = /bits/ 64 <1608000000>; |
|
opp-microvolt = <1050000 1050000 1250000>; |
|
}; |
|
opp07 { |
|
opp-hz = /bits/ 64 <1800000000>; |
|
opp-microvolt = <1150000 1150000 1250000>; |
|
}; |
|
opp08 { |
|
opp-hz = /bits/ 64 <2088000000>; |
|
opp-microvolt = <1250000 1250000 1250000>; |
|
}; |
|
}; |
|
|
|
opp-table-2 { |
|
compatible = "operating-points-v2"; |
|
phandle = <0xbe>; |
|
|
|
opp00 { |
|
opp-hz = <0x00 0xbebc200>; |
|
opp-microvolt = <0xc96a8 0xc96a8 0x118c30>; |
|
}; |
|
|
|
opp01 { |
|
opp-hz = <0x00 0x11b3dc40>; |
|
opp-microvolt = <0xc96a8 0xc96a8 0x118c30>; |
|
}; |
|
|
|
opp02 { |
|
opp-hz = <0x00 0x17d78400>; |
|
opp-microvolt = <0xc96a8 0xc96a8 0x118c30>; |
|
}; |
|
|
|
opp03 { |
|
opp-hz = <0x00 0x1dcd6500>; |
|
opp-microvolt = <0xd59f8 0xd59f8 0x118c30>; |
|
}; |
|
|
|
opp04 { |
|
opp-hz = <0x00 0x23c34600>; |
|
opp-microvolt = <0xe1d48 0xe1d48 0x118c30>; |
|
}; |
|
|
|
opp05 { |
|
opp-hz = <0x00 0x2faf0800>; |
|
opp-microvolt = <0x10c8e0 0x10c8e0 0x118c30>; |
|
}; |
|
}; |
|
|
|
chosen { |
|
stdout-path = "serial2:1500000n8"; |
|
}; |
|
|
|
edp-backlight { |
|
compatible = "pwm-backlight"; |
|
power-supply = <0xc5>; |
|
pwms = <0xc6 0x00 0x186A0 0x00>; |
|
phandle = <0xc7>; |
|
}; |
|
|
|
battery { |
|
compatible = "simple-battery"; |
|
charge-full-design-microamp-hours = <0x958940>; |
|
voltage-max-design-microvolt = <0x426030>; |
|
voltage-min-design-microvolt = <0x2dc6c0>; |
|
phandle = <0x8e>; |
|
}; |
|
|
|
edp-panel { |
|
compatible = "boe,nv140fhmn49"; |
|
backlight = <0xc7>; |
|
enable-gpios = <0x88 0x00 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0xc8>; |
|
power-supply = <0xc9>; |
|
phandle = <0x16b>; |
|
|
|
ports { |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
|
|
port@0 { |
|
reg = <0x00>; |
|
#address-cells = <0x01>; |
|
#size-cells = <0x00>; |
|
|
|
endpoint@0 { |
|
reg = <0x00>; |
|
remote-endpoint = <0xca>; |
|
phandle = <0xbd>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
gpio-key-lid { |
|
compatible = "gpio-keys"; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0xcb>; |
|
|
|
switch-lid { |
|
debounce-interval = <0x14>; |
|
gpios = <0x88 0x01 0x01>; |
|
label = "Lid"; |
|
linux,code = <0x00>; |
|
linux,input-type = <0x05>; |
|
wakeup-event-action = <0x02>; |
|
wakeup-source; |
|
}; |
|
}; |
|
|
|
gpio-key-power { |
|
compatible = "gpio-keys"; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0xcc>; |
|
|
|
key-power { |
|
debounce-interval = <0x14>; |
|
gpios = <0x23 0x05 0x01>; |
|
label = "Delete"; |
|
linux,code = <0x6f>; |
|
wakeup-source; |
|
}; |
|
}; |
|
|
|
leds { |
|
compatible = "gpio-leds"; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0xcd 0xce>; |
|
|
|
led-0 { |
|
color = <0x02>; |
|
default-state = "on"; |
|
function = "power"; |
|
gpios = <0x23 0x0b 0x00>; |
|
label = "green:power"; |
|
phandle = <0x16c>; |
|
}; |
|
|
|
led-1 { |
|
color = <0x01>; |
|
default-state = "off"; |
|
function = "standby"; |
|
gpios = <0x23 0x02 0x00>; |
|
label = "red:standby"; |
|
panic-indicator; |
|
retain-state-suspended; |
|
phandle = <0x16d>; |
|
}; |
|
}; |
|
|
|
sdio-pwrseq { |
|
compatible = "mmc-pwrseq-simple"; |
|
clocks = <0x3f 0x01>; |
|
clock-names = "ext_clock"; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0xcf>; |
|
post-power-on-delay-ms = <0x64>; |
|
power-off-delay-us = <0x7a120>; |
|
reset-gpios = <0x23 0x0a 0x01>; |
|
phandle = <0x1f>; |
|
}; |
|
|
|
es8316-sound { |
|
compatible = "simple-audio-card"; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0xd0>; |
|
simple-audio-card,name = "rockchip,es8316-codec"; |
|
simple-audio-card,format = "i2s"; |
|
simple-audio-card,mclk-fs = <0x100>; |
|
simple-audio-card,widgets = "Microphone\0Mic Jack\0Headphone\0Headphones\0Speaker\0Speaker"; |
|
simple-audio-card,routing = "MIC1\0Mic Jack\0Headphones\0HPOL\0Headphones\0HPOR\0Speaker Amplifier INL\0HPOL\0Speaker Amplifier INR\0HPOR\0Speaker\0Speaker Amplifier OUTL\0Speaker\0Speaker Amplifier OUTR"; |
|
simple-audio-card,hp-det-gpio = <0x23 0x08 0x00>; |
|
simple-audio-card,aux-devs = <0xd1>; |
|
simple-audio-card,pin-switches = "Speaker"; |
|
|
|
simple-audio-card,cpu { |
|
sound-dai = <0xd2>; |
|
}; |
|
|
|
simple-audio-card,codec { |
|
sound-dai = <0xd3>; |
|
}; |
|
}; |
|
|
|
speaker-amplifier { |
|
compatible = "simple-audio-amplifier"; |
|
enable-gpios = <0xd4 0x1b 0x00>; |
|
sound-name-prefix = "Speaker Amplifier"; |
|
VCC-supply = <0xd5>; |
|
phandle = <0xd1>; |
|
}; |
|
|
|
vcc-sysin { |
|
compatible = "regulator-fixed"; |
|
regulator-name = "vcc_sysin"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
phandle = <0x84>; |
|
}; |
|
|
|
vcc-12v { |
|
compatible = "regulator-fixed"; |
|
regulator-name = "vcc_12v"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0xb71b00>; |
|
regulator-max-microvolt = <0xb71b00>; |
|
vin-supply = <0x84>; |
|
phandle = <0xc5>; |
|
|
|
regulator-state-mem { |
|
regulator-off-in-suspend; |
|
}; |
|
}; |
|
|
|
vcc3v3-sys { |
|
compatible = "regulator-fixed"; |
|
regulator-name = "vcc3v3_sys"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0x325aa0>; |
|
regulator-max-microvolt = <0x325aa0>; |
|
vin-supply = <0x84>; |
|
phandle = <0x43>; |
|
|
|
regulator-state-mem { |
|
regulator-on-in-suspend; |
|
}; |
|
}; |
|
|
|
vcc5v0-usb-regulator { |
|
compatible = "regulator-fixed"; |
|
enable-active-high; |
|
gpio = <0x88 0x0d 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0xd6>; |
|
regulator-name = "vcc5v0_usb"; |
|
regulator-always-on; |
|
regulator-min-microvolt = <0x4c4b40>; |
|
regulator-max-microvolt = <0x4c4b40>; |
|
vin-supply = <0x84>; |
|
phandle = <0xd5>; |
|
|
|
regulator-state-mem { |
|
regulator-off-in-suspend; |
|
}; |
|
}; |
|
|
|
vdd-log { |
|
compatible = "pwm-regulator"; |
|
pwms = <0xd7 0x00 0x61a8 0x01>; |
|
pwm-supply = <0x84>; |
|
regulator-name = "vdd_log"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = "\0\f5"; |
|
regulator-max-microvolt = <0x155cc0>; |
|
phandle = <0x16e>; |
|
|
|
regulator-state-mem { |
|
regulator-on-in-suspend; |
|
}; |
|
}; |
|
|
|
vcc-0v9 { |
|
compatible = "regulator-fixed"; |
|
regulator-name = "vcc_0v9"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0xdbba0>; |
|
regulator-max-microvolt = <0xdbba0>; |
|
vin-supply = <0x43>; |
|
phandle = <0x16f>; |
|
}; |
|
|
|
vcc1v8-s3 { |
|
compatible = "regulator-fixed"; |
|
regulator-name = "vcca1v8_s3"; |
|
regulator-always-on; |
|
regulator-boot-on; |
|
regulator-min-microvolt = <0x1b7740>; |
|
regulator-max-microvolt = <0x1b7740>; |
|
vin-supply = <0x43>; |
|
phandle = <0x1b>; |
|
}; |
|
|
|
vcc3v0-sd { |
|
compatible = "regulator-fixed"; |
|
enable-active-high; |
|
gpio = <0x23 0x01 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0xd8>; |
|
regulator-name = "vcc3v0_sd"; |
|
regulator-always-on; |
|
regulator-min-microvolt = <0x2dc6c0>; |
|
regulator-max-microvolt = <0x2dc6c0>; |
|
vin-supply = <0x43>; |
|
phandle = <0x27>; |
|
|
|
regulator-state-mem { |
|
regulator-off-in-suspend; |
|
}; |
|
}; |
|
|
|
vcc3v3-panel { |
|
compatible = "regulator-fixed"; |
|
enable-active-high; |
|
gpio = <0x88 0x16 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0xd9>; |
|
regulator-name = "vcc3v3_panel"; |
|
regulator-always-on; |
|
regulator-min-microvolt = <0x325aa0>; |
|
regulator-max-microvolt = <0x325aa0>; |
|
regulator-enable-ramp-delay = <0x186a0>; |
|
vin-supply = <0x43>; |
|
phandle = <0xc9>; |
|
|
|
regulator-state-mem { |
|
regulator-off-in-suspend; |
|
}; |
|
}; |
|
|
|
vcc3v3-ssd { |
|
compatible = "regulator-fixed"; |
|
regulator-name = "vcc3v3_ssd"; |
|
regulator-min-microvolt = <0x325aa0>; |
|
regulator-max-microvolt = <0x325aa0>; |
|
vin-supply = <0x43>; |
|
phandle = <0x1c>; |
|
}; |
|
|
|
vcc5v0-otg { |
|
compatible = "regulator-fixed"; |
|
enable-active-high; |
|
gpio = <0xd4 0x1a 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0xda>; |
|
regulator-name = "vcc5v0_otg"; |
|
regulator-always-on; |
|
regulator-min-microvolt = <0x4c4b40>; |
|
regulator-max-microvolt = <0x4c4b40>; |
|
vin-supply = <0xd5>; |
|
phandle = <0x99>; |
|
|
|
regulator-state-mem { |
|
regulator-off-in-suspend; |
|
}; |
|
}; |
|
|
|
vbus-5vout { |
|
compatible = "regulator-fixed"; |
|
enable-active-high; |
|
gpio = <0x88 0x03 0x00>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0xdb>; |
|
regulator-name = "vbus_5vout"; |
|
regulator-min-microvolt = <0x4c4b40>; |
|
regulator-max-microvolt = <0x4c4b40>; |
|
vin-supply = <0xd5>; |
|
phandle = <0x8a>; |
|
|
|
regulator-state-mem { |
|
regulator-off-in-suspend; |
|
}; |
|
}; |
|
|
|
vcca0v9-s3 { |
|
compatible = "regulator-fixed"; |
|
regulator-name = "vcc0v9_s3"; |
|
regulator-min-microvolt = <0x4c4b40>; |
|
regulator-max-microvolt = <0x4c4b40>; |
|
vin-supply = <0x44>; |
|
phandle = <0x1a>; |
|
|
|
regulator-state-mem { |
|
regulator-on-in-suspend; |
|
}; |
|
}; |
|
|
|
dc-charger { |
|
compatible = "gpio-charger"; |
|
charger-type = "mains"; |
|
gpios = <0xd4 0x18 0x01>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <0xdc>; |
|
phandle = <0x8f>; |
|
}; |
|
|
|
__symbols__ { |
|
cpu_l0 = "/cpus/cpu@0"; |
|
cpu_l1 = "/cpus/cpu@1"; |
|
cpu_l2 = "/cpus/cpu@2"; |
|
cpu_l3 = "/cpus/cpu@3"; |
|
cpu_b0 = "/cpus/cpu@100"; |
|
cpu_b1 = "/cpus/cpu@101"; |
|
CPU_SLEEP = "/cpus/idle-states/cpu-sleep"; |
|
CLUSTER_SLEEP = "/cpus/idle-states/cluster-sleep"; |
|
dmc = "/memory-controller"; |
|
xin24m = "/xin24m"; |
|
pcie0 = "/pcie@f8000000"; |
|
pcie0_intc = "/pcie@f8000000/interrupt-controller"; |
|
gmac = "/ethernet@fe300000"; |
|
sdio0 = "/mmc@fe310000"; |
|
sdmmc = "/mmc@fe320000"; |
|
sdhci = "/mmc@fe330000"; |
|
usb_host0_ehci = "/usb@fe380000"; |
|
usb_host0_ohci = "/usb@fe3a0000"; |
|
usb_host1_ehci = "/usb@fe3c0000"; |
|
usb_host1_ohci = "/usb@fe3e0000"; |
|
usbdrd3_0 = "/usb@fe800000"; |
|
usbdrd_dwc3_0 = "/usb@fe800000/usb@fe800000"; |
|
usbdrd3_1 = "/usb@fe900000"; |
|
usbdrd_dwc3_1 = "/usb@fe900000/usb@fe900000"; |
|
cdn_dp = "/dp@fec00000"; |
|
dp_in = "/dp@fec00000/ports/port"; |
|
dp_in_vopb = "/dp@fec00000/ports/port/endpoint@0"; |
|
dp_in_vopl = "/dp@fec00000/ports/port/endpoint@1"; |
|
gic = "/interrupt-controller@fee00000"; |
|
its = "/interrupt-controller@fee00000/interrupt-controller@fee20000"; |
|
ppi_cluster0 = "/interrupt-controller@fee00000/ppi-partitions/interrupt-partition-0"; |
|
ppi_cluster1 = "/interrupt-controller@fee00000/ppi-partitions/interrupt-partition-1"; |
|
saradc = "/saradc@ff100000"; |
|
i2c1 = "/i2c@ff110000"; |
|
es8316 = "/i2c@ff110000/es8316@11"; |
|
i2c2 = "/i2c@ff120000"; |
|
i2c3 = "/i2c@ff130000"; |
|
i2c5 = "/i2c@ff140000"; |
|
i2c6 = "/i2c@ff150000"; |
|
i2c7 = "/i2c@ff160000"; |
|
uart0 = "/serial@ff180000"; |
|
uart1 = "/serial@ff190000"; |
|
uart2 = "/serial@ff1a0000"; |
|
uart3 = "/serial@ff1b0000"; |
|
spi0 = "/spi@ff1c0000"; |
|
spi1 = "/spi@ff1d0000"; |
|
spiflash = "/spi@ff1d0000/flash@0"; |
|
spi2 = "/spi@ff1e0000"; |
|
spi4 = "/spi@ff1f0000"; |
|
spi5 = "/spi@ff200000"; |
|
thermal_zones = "/thermal-zones"; |
|
cpu_thermal = "/thermal-zones/cpu-thermal"; |
|
cpu_alert0 = "/thermal-zones/cpu-thermal/trips/cpu_alert0"; |
|
cpu_alert1 = "/thermal-zones/cpu-thermal/trips/cpu_alert1"; |
|
cpu_crit = "/thermal-zones/cpu-thermal/trips/cpu_crit"; |
|
gpu_thermal = "/thermal-zones/gpu-thermal"; |
|
gpu_alert0 = "/thermal-zones/gpu-thermal/trips/gpu_alert0"; |
|
gpu_crit = "/thermal-zones/gpu-thermal/trips/gpu_crit"; |
|
tsadc = "/tsadc@ff260000"; |
|
qos_emmc = "/qos@ffa58000"; |
|
qos_gmac = "/qos@ffa5c000"; |
|
qos_pcie = "/qos@ffa60080"; |
|
qos_usb_host0 = "/qos@ffa60100"; |
|
qos_usb_host1 = "/qos@ffa60180"; |
|
qos_usb_otg0 = "/qos@ffa70000"; |
|
qos_usb_otg1 = "/qos@ffa70080"; |
|
qos_sd = "/qos@ffa74000"; |
|
qos_sdioaudio = "/qos@ffa76000"; |
|
qos_hdcp = "/qos@ffa90000"; |
|
qos_iep = "/qos@ffa98000"; |
|
qos_isp0_m0 = "/qos@ffaa0000"; |
|
qos_isp0_m1 = "/qos@ffaa0080"; |
|
qos_isp1_m0 = "/qos@ffaa8000"; |
|
qos_isp1_m1 = "/qos@ffaa8080"; |
|
qos_rga_r = "/qos@ffab0000"; |
|
qos_rga_w = "/qos@ffab0080"; |
|
qos_video_m0 = "/qos@ffab8000"; |
|
qos_video_m1_r = "/qos@ffac0000"; |
|
qos_video_m1_w = "/qos@ffac0080"; |
|
qos_vop_big_r = "/qos@ffac8000"; |
|
qos_vop_big_w = "/qos@ffac8080"; |
|
qos_vop_little = "/qos@ffad0000"; |
|
qos_perihp = "/qos@ffad8080"; |
|
qos_gpu = "/qos@ffae0000"; |
|
pmu = "/power-management@ff310000"; |
|
power = "/power-management@ff310000/power-controller"; |
|
pmugrf = "/syscon@ff320000"; |
|
pmu_io_domains = "/syscon@ff320000/io-domains"; |
|
spi3 = "/spi@ff350000"; |
|
uart4 = "/serial@ff370000"; |
|
i2c0 = "/i2c@ff3c0000"; |
|
rk808 = "/i2c@ff3c0000/pmic@1b"; |
|
vdd_center = "/i2c@ff3c0000/pmic@1b/regulators/DCDC_REG1"; |
|
vdd_cpu_l = "/i2c@ff3c0000/pmic@1b/regulators/DCDC_REG2"; |
|
vcc_ddr = "/i2c@ff3c0000/pmic@1b/regulators/DCDC_REG3"; |
|
vcc_1v8 = "/i2c@ff3c0000/pmic@1b/regulators/DCDC_REG4"; |
|
vcc_wl = "/i2c@ff3c0000/pmic@1b/regulators/DCDC_REG4"; |
|
vcc1v8_pmupll = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG3"; |
|
vcc_sdio = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG4"; |
|
vcca3v0_codec = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG5"; |
|
vcc_1v5 = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG6"; |
|
vcca1v8_codec = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG7"; |
|
vcc_3v0 = "/i2c@ff3c0000/pmic@1b/regulators/LDO_REG8"; |
|
vcc3v3_s3 = "/i2c@ff3c0000/pmic@1b/regulators/SWITCH_REG1"; |
|
vcc3v3_s0 = "/i2c@ff3c0000/pmic@1b/regulators/SWITCH_REG2"; |
|
vdd_cpu_b = "/i2c@ff3c0000/regulator@40"; |
|
vdd_gpu = "/i2c@ff3c0000/regulator@41"; |
|
i2c4 = "/i2c@ff3d0000"; |
|
fusb0 = "/i2c@ff3d0000/fusb30x@22"; |
|
usbc_hs = "/i2c@ff3d0000/fusb30x@22/connector/ports/port@0/endpoint"; |
|
usbc_ss = "/i2c@ff3d0000/fusb30x@22/connector/ports/port@1/endpoint"; |
|
usbc_dp = "/i2c@ff3d0000/fusb30x@22/connector/ports/port@2/endpoint"; |
|
i2c8 = "/i2c@ff3e0000"; |
|
pwm0 = "/pwm@ff420000"; |
|
pwm1 = "/pwm@ff420010"; |
|
pwm2 = "/pwm@ff420020"; |
|
pwm3 = "/pwm@ff420030"; |
|
dfi = "/dfi@ff630000"; |
|
vpu = "/video-codec@ff650000"; |
|
vpu_mmu = "/iommu@ff650800"; |
|
vdec = "/video-codec@ff660000"; |
|
vdec_mmu = "/iommu@ff660480"; |
|
iep_mmu = "/iommu@ff670800"; |
|
rga = "/rga@ff680000"; |
|
efuse0 = "/efuse@ff690000"; |
|
cpu_id = "/efuse@ff690000/cpu-id@7"; |
|
cpub_leakage = "/efuse@ff690000/cpu-leakage@17"; |
|
gpu_leakage = "/efuse@ff690000/gpu-leakage@18"; |
|
center_leakage = "/efuse@ff690000/center-leakage@19"; |
|
cpul_leakage = "/efuse@ff690000/cpu-leakage@1a"; |
|
logic_leakage = "/efuse@ff690000/logic-leakage@1b"; |
|
wafer_info = "/efuse@ff690000/wafer-info@1c"; |
|
dmac_bus = "/dma-controller@ff6d0000"; |
|
dmac_peri = "/dma-controller@ff6e0000"; |
|
pmucru = "/clock-controller@ff750000"; |
|
cru = "/clock-controller@ff760000"; |
|
grf = "/syscon@ff770000"; |
|
io_domains = "/syscon@ff770000/io-domains"; |
|
mipi_dphy_rx0 = "/syscon@ff770000/mipi-dphy-rx0"; |
|
u2phy0 = "/syscon@ff770000/usb2phy@e450"; |
|
u2phy0_host = "/syscon@ff770000/usb2phy@e450/host-port"; |
|
u2phy0_otg = "/syscon@ff770000/usb2phy@e450/otg-port"; |
|
u2phy0_typec_hs = "/syscon@ff770000/usb2phy@e450/port/endpoint"; |
|
u2phy1 = "/syscon@ff770000/usb2phy@e460"; |
|
u2phy1_host = "/syscon@ff770000/usb2phy@e460/host-port"; |
|
u2phy1_otg = "/syscon@ff770000/usb2phy@e460/otg-port"; |
|
emmc_phy = "/syscon@ff770000/phy@f780"; |
|
pcie_phy = "/syscon@ff770000/pcie-phy"; |
|
tcphy0 = "/phy@ff7c0000"; |
|
tcphy0_dp = "/phy@ff7c0000/dp-port"; |
|
tcphy0_typec_dp = "/phy@ff7c0000/dp-port/port/endpoint"; |
|
tcphy0_usb3 = "/phy@ff7c0000/usb3-port"; |
|
tcphy0_typec_ss = "/phy@ff7c0000/usb3-port/port/endpoint"; |
|
tcphy1 = "/phy@ff800000"; |
|
tcphy1_dp = "/phy@ff800000/dp-port"; |
|
tcphy1_usb3 = "/phy@ff800000/usb3-port"; |
|
rktimer = "/rktimer@ff850000"; |
|
spdif = "/spdif@ff870000"; |
|
i2s0 = "/i2s@ff880000"; |
|
i2s1 = "/i2s@ff890000"; |
|
i2s2 = "/i2s@ff8a0000"; |
|
vopl = "/vop@ff8f0000"; |
|
vopl_out = "/vop@ff8f0000/port"; |
|
vopl_out_mipi = "/vop@ff8f0000/port/endpoint@0"; |
|
vopl_out_edp = "/vop@ff8f0000/port/endpoint@1"; |
|
vopl_out_hdmi = "/vop@ff8f0000/port/endpoint@2"; |
|
vopl_out_mipi1 = "/vop@ff8f0000/port/endpoint@3"; |
|
vopl_out_dp = "/vop@ff8f0000/port/endpoint@4"; |
|
vopl_mmu = "/iommu@ff8f3f00"; |
|
vopb = "/vop@ff900000"; |
|
vopb_out = "/vop@ff900000/port"; |
|
vopb_out_edp = "/vop@ff900000/port/endpoint@0"; |
|
vopb_out_mipi = "/vop@ff900000/port/endpoint@1"; |
|
vopb_out_hdmi = "/vop@ff900000/port/endpoint@2"; |
|
vopb_out_mipi1 = "/vop@ff900000/port/endpoint@3"; |
|
vopb_out_dp = "/vop@ff900000/port/endpoint@4"; |
|
vopb_mmu = "/iommu@ff903f00"; |
|
isp0 = "/isp0@ff910000"; |
|
isp0_mmu = "/iommu@ff914000"; |
|
isp1 = "/isp1@ff920000"; |
|
isp1_mmu = "/iommu@ff924000"; |
|
hdmi_sound = "/hdmi-sound"; |
|
hdmi = "/hdmi@ff940000"; |
|
hdmi_in = "/hdmi@ff940000/ports/port"; |
|
hdmi_in_vopb = "/hdmi@ff940000/ports/port/endpoint@0"; |
|
hdmi_in_vopl = "/hdmi@ff940000/ports/port/endpoint@1"; |
|
mipi_dsi = "/mipi@ff960000"; |
|
mipi_in = "/mipi@ff960000/ports/port@0"; |
|
mipi_in_vopb = "/mipi@ff960000/ports/port@0/endpoint@0"; |
|
mipi_in_vopl = "/mipi@ff960000/ports/port@0/endpoint@1"; |
|
mipi_dsi1 = "/mipi@ff968000"; |
|
mipi1_in = "/mipi@ff968000/ports/port@0"; |
|
mipi1_in_vopb = "/mipi@ff968000/ports/port@0/endpoint@0"; |
|
mipi1_in_vopl = "/mipi@ff968000/ports/port@0/endpoint@1"; |
|
edp = "/edp@ff970000"; |
|
edp_in = "/edp@ff970000/ports/port@0"; |
|
edp_in_vopb = "/edp@ff970000/ports/port@0/endpoint@0"; |
|
edp_in_vopl = "/edp@ff970000/ports/port@0/endpoint@1"; |
|
edp_out = "/edp@ff970000/ports/port@1"; |
|
edp_out_panel = "/edp@ff970000/ports/port@1/endpoint@0"; |
|
gpu = "/gpu@ff9a0000"; |
|
pinctrl = "/pinctrl"; |
|
gpio0 = "/pinctrl/gpio@ff720000"; |
|
gpio1 = "/pinctrl/gpio@ff730000"; |
|
gpio2 = "/pinctrl/gpio@ff780000"; |
|
gpio3 = "/pinctrl/gpio@ff788000"; |
|
gpio4 = "/pinctrl/gpio@ff790000"; |
|
pcfg_pull_up = "/pinctrl/pcfg-pull-up"; |
|
pcfg_pull_down = "/pinctrl/pcfg-pull-down"; |
|
pcfg_pull_none = "/pinctrl/pcfg-pull-none"; |
|
pcfg_pull_none_12ma = "/pinctrl/pcfg-pull-none-12ma"; |
|
pcfg_pull_none_13ma = "/pinctrl/pcfg-pull-none-13ma"; |
|
pcfg_pull_none_18ma = "/pinctrl/pcfg-pull-none-18ma"; |
|
pcfg_pull_none_20ma = "/pinctrl/pcfg-pull-none-20ma"; |
|
pcfg_pull_up_2ma = "/pinctrl/pcfg-pull-up-2ma"; |
|
pcfg_pull_up_8ma = "/pinctrl/pcfg-pull-up-8ma"; |
|
pcfg_pull_up_18ma = "/pinctrl/pcfg-pull-up-18ma"; |
|
pcfg_pull_up_20ma = "/pinctrl/pcfg-pull-up-20ma"; |
|
pcfg_pull_down_4ma = "/pinctrl/pcfg-pull-down-4ma"; |
|
pcfg_pull_down_8ma = "/pinctrl/pcfg-pull-down-8ma"; |
|
pcfg_pull_down_12ma = "/pinctrl/pcfg-pull-down-12ma"; |
|
pcfg_pull_down_18ma = "/pinctrl/pcfg-pull-down-18ma"; |
|
pcfg_pull_down_20ma = "/pinctrl/pcfg-pull-down-20ma"; |
|
pcfg_output_high = "/pinctrl/pcfg-output-high"; |
|
pcfg_output_low = "/pinctrl/pcfg-output-low"; |
|
pcfg_input_enable = "/pinctrl/pcfg-input-enable"; |
|
pcfg_input_pull_up = "/pinctrl/pcfg-input-pull-up"; |
|
pcfg_input_pull_down = "/pinctrl/pcfg-input-pull-down"; |
|
clk_32k = "/pinctrl/clock/clk-32k"; |
|
cif_clkin = "/pinctrl/cif/cif-clkin"; |
|
cif_clkouta = "/pinctrl/cif/cif-clkouta"; |
|
edp_hpd = "/pinctrl/edp/edp-hpd"; |
|
rgmii_pins = "/pinctrl/gmac/rgmii-pins"; |
|
rmii_pins = "/pinctrl/gmac/rmii-pins"; |
|
i2c0_xfer = "/pinctrl/i2c0/i2c0-xfer"; |
|
i2c1_xfer = "/pinctrl/i2c1/i2c1-xfer"; |
|
i2c2_xfer = "/pinctrl/i2c2/i2c2-xfer"; |
|
i2c3_xfer = "/pinctrl/i2c3/i2c3-xfer"; |
|
i2c4_xfer = "/pinctrl/i2c4/i2c4-xfer"; |
|
i2c5_xfer = "/pinctrl/i2c5/i2c5-xfer"; |
|
i2c6_xfer = "/pinctrl/i2c6/i2c6-xfer"; |
|
i2c7_xfer = "/pinctrl/i2c7/i2c7-xfer"; |
|
i2c8_xfer = "/pinctrl/i2c8/i2c8-xfer"; |
|
i2s0_2ch_bus = "/pinctrl/i2s0/i2s0-2ch-bus"; |
|
i2s0_8ch_bus = "/pinctrl/i2s0/i2s0-8ch-bus"; |
|
i2s1_2ch_bus = "/pinctrl/i2s1/i2s1-2ch-bus"; |
|
i2s_8ch_mclk_pin = "/pinctrl/i2s1/i2s-8ch-mclk-pin"; |
|
sdio0_bus1 = "/pinctrl/sdio0/sdio0-bus1"; |
|
sdio0_bus4 = "/pinctrl/sdio0/sdio0-bus4"; |
|
sdio0_cmd = "/pinctrl/sdio0/sdio0-cmd"; |
|
sdio0_clk = "/pinctrl/sdio0/sdio0-clk"; |
|
sdio0_cd = "/pinctrl/sdio0/sdio0-cd"; |
|
sdio0_pwr = "/pinctrl/sdio0/sdio0-pwr"; |
|
sdio0_bkpwr = "/pinctrl/sdio0/sdio0-bkpwr"; |
|
sdio0_wp = "/pinctrl/sdio0/sdio0-wp"; |
|
sdio0_int = "/pinctrl/sdio0/sdio0-int"; |
|
sdmmc_bus1 = "/pinctrl/sdmmc/sdmmc-bus1"; |
|
sdmmc_bus4 = "/pinctrl/sdmmc/sdmmc-bus4"; |
|
sdmmc_clk = "/pinctrl/sdmmc/sdmmc-clk"; |
|
sdmmc_cmd = "/pinctrl/sdmmc/sdmmc-cmd"; |
|
sdmmc_cd = "/pinctrl/sdmmc/sdmmc-cd"; |
|
sdmmc_wp = "/pinctrl/sdmmc/sdmmc-wp"; |
|
ap_pwroff = "/pinctrl/suspend/ap-pwroff"; |
|
ddrio_pwroff = "/pinctrl/suspend/ddrio-pwroff"; |
|
spdif_bus = "/pinctrl/spdif/spdif-bus"; |
|
spdif_bus_1 = "/pinctrl/spdif/spdif-bus-1"; |
|
spi0_clk = "/pinctrl/spi0/spi0-clk"; |
|
spi0_cs0 = "/pinctrl/spi0/spi0-cs0"; |
|
spi0_cs1 = "/pinctrl/spi0/spi0-cs1"; |
|
spi0_tx = "/pinctrl/spi0/spi0-tx"; |
|
spi0_rx = "/pinctrl/spi0/spi0-rx"; |
|
spi1_clk = "/pinctrl/spi1/spi1-clk"; |
|
spi1_cs0 = "/pinctrl/spi1/spi1-cs0"; |
|
spi1_rx = "/pinctrl/spi1/spi1-rx"; |
|
spi1_tx = "/pinctrl/spi1/spi1-tx"; |
|
spi2_clk = "/pinctrl/spi2/spi2-clk"; |
|
spi2_cs0 = "/pinctrl/spi2/spi2-cs0"; |
|
spi2_rx = "/pinctrl/spi2/spi2-rx"; |
|
spi2_tx = "/pinctrl/spi2/spi2-tx"; |
|
spi3_clk = "/pinctrl/spi3/spi3-clk"; |
|
spi3_cs0 = "/pinctrl/spi3/spi3-cs0"; |
|
spi3_rx = "/pinctrl/spi3/spi3-rx"; |
|
spi3_tx = "/pinctrl/spi3/spi3-tx"; |
|
spi4_clk = "/pinctrl/spi4/spi4-clk"; |
|
spi4_cs0 = "/pinctrl/spi4/spi4-cs0"; |
|
spi4_rx = "/pinctrl/spi4/spi4-rx"; |
|
spi4_tx = "/pinctrl/spi4/spi4-tx"; |
|
spi5_clk = "/pinctrl/spi5/spi5-clk"; |
|
spi5_cs0 = "/pinctrl/spi5/spi5-cs0"; |
|
spi5_rx = "/pinctrl/spi5/spi5-rx"; |
|
spi5_tx = "/pinctrl/spi5/spi5-tx"; |
|
test_clkout0 = "/pinctrl/testclk/test-clkout0"; |
|
test_clkout1 = "/pinctrl/testclk/test-clkout1"; |
|
test_clkout2 = "/pinctrl/testclk/test-clkout2"; |
|
otp_pin = "/pinctrl/tsadc/otp-pin"; |
|
otp_out = "/pinctrl/tsadc/otp-out"; |
|
uart0_xfer = "/pinctrl/uart0/uart0-xfer"; |
|
uart0_cts = "/pinctrl/uart0/uart0-cts"; |
|
uart0_rts = "/pinctrl/uart0/uart0-rts"; |
|
uart1_xfer = "/pinctrl/uart1/uart1-xfer"; |
|
uart2a_xfer = "/pinctrl/uart2a/uart2a-xfer"; |
|
uart2b_xfer = "/pinctrl/uart2b/uart2b-xfer"; |
|
uart2c_xfer = "/pinctrl/uart2c/uart2c-xfer"; |
|
uart3_xfer = "/pinctrl/uart3/uart3-xfer"; |
|
uart3_cts = "/pinctrl/uart3/uart3-cts"; |
|
uart3_rts = "/pinctrl/uart3/uart3-rts"; |
|
uart4_xfer = "/pinctrl/uart4/uart4-xfer"; |
|
uarthdcp_xfer = "/pinctrl/uarthdcp/uarthdcp-xfer"; |
|
pwm0_pin = "/pinctrl/pwm0/pwm0-pin"; |
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pwm0_pin_pull_down = "/pinctrl/pwm0/pwm0-pin-pull-down"; |
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vop0_pwm_pin = "/pinctrl/pwm0/vop0-pwm-pin"; |
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vop1_pwm_pin = "/pinctrl/pwm0/vop1-pwm-pin"; |
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pwm1_pin = "/pinctrl/pwm1/pwm1-pin"; |
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pwm1_pin_pull_down = "/pinctrl/pwm1/pwm1-pin-pull-down"; |
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pwm2_pin = "/pinctrl/pwm2/pwm2-pin"; |
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pwm2_pin_pull_down = "/pinctrl/pwm2/pwm2-pin-pull-down"; |
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pwm3a_pin = "/pinctrl/pwm3a/pwm3a-pin"; |
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pwm3b_pin = "/pinctrl/pwm3b/pwm3b-pin"; |
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hdmi_i2c_xfer = "/pinctrl/hdmi/hdmi-i2c-xfer"; |
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hdmi_cec = "/pinctrl/hdmi/hdmi-cec"; |
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pcie_clkreqn_cpm = "/pinctrl/pcie/pci-clkreqn-cpm"; |
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pcie_clkreqnb_cpm = "/pinctrl/pcie/pci-clkreqnb-cpm"; |
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pwrbtn_pin = "/pinctrl/buttons/pwrbtn-pin"; |
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lidbtn_pin = "/pinctrl/buttons/lidbtn-pin"; |
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dc_det_pin = "/pinctrl/dc-charger/dc-det-pin"; |
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hp_det_pin = "/pinctrl/es8316/hp-det-pin"; |
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fusb0_int_pin = "/pinctrl/fusb302x/fusb0-int-pin"; |
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lcdvcc_en_pin = "/pinctrl/lcd-panel/lcdvcc-en-pin"; |
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panel_en_pin = "/pinctrl/lcd-panel/panel-en-pin"; |
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lcd_panel_reset_pin = "/pinctrl/lcd-panel/lcd-panel-reset-pin"; |
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pwr_led_pin = "/pinctrl/leds/pwr-led-pin"; |
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slp_led_pin = "/pinctrl/leds/slp-led-pin"; |
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pmic_int_l_pin = "/pinctrl/pmic/pmic-int-l-pin"; |
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vsel1_pin = "/pinctrl/pmic/vsel1-pin"; |
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vsel2_pin = "/pinctrl/pmic/vsel2-pin"; |
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sdmmc0_pwr_h_pin = "/pinctrl/sdcard/sdmmc0-pwr-h-pin"; |
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wifi_enable_h_pin = "/pinctrl/sdio-pwrseq/wifi-enable-h-pin"; |
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vcc5v0_typec0_en_pin = "/pinctrl/usb-typec/vcc5v0-typec0-en-pin"; |
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pwr_5v_pin = "/pinctrl/usb2/pwr-5v-pin"; |
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vcc5v0_host_en_pin = "/pinctrl/usb2/vcc5v0-host-en-pin"; |
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bt_wake_pin = "/pinctrl/wireless-bluetooth/bt-wake-pin"; |
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bt_host_wake_pin = "/pinctrl/wireless-bluetooth/bt-host-wake-pin"; |
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bt_reset_pin = "/pinctrl/wireless-bluetooth/bt-reset-pin"; |
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cluster0_opp = "/opp-table-0"; |
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cluster1_opp = "/opp-table-1"; |
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gpu_opp_table = "/opp-table-2"; |
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backlight = "/edp-backlight"; |
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bat = "/battery"; |
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edp_panel = "/edp-panel"; |
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panel_in_edp = "/edp-panel/ports/port@0/endpoint@0"; |
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green_led = "/leds/led-0"; |
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red_led = "/leds/led-1"; |
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sdio_pwrseq = "/sdio-pwrseq"; |
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speaker_amp = "/speaker-amplifier"; |
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vcc_sysin = "/vcc-sysin"; |
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vcc_12v = "/vcc-12v"; |
|
vcc3v3_sys = "/vcc3v3-sys"; |
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wifi_bat = "/vcc3v3-sys"; |
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vcc5v0_usb = "/vcc5v0-usb-regulator"; |
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pa_5v = "/vcc5v0-usb-regulator"; |
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vdd_log = "/vdd-log"; |
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vcc_0v9 = "/vcc-0v9"; |
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vcca1v8_s3 = "/vcc1v8-s3"; |
|
vcc3v0_sd = "/vcc3v0-sd"; |
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vcc3v3_panel = "/vcc3v3-panel"; |
|
vcc3v3_ssd = "/vcc3v3-ssd"; |
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vcc5v0_otg = "/vcc5v0-otg"; |
|
vbus_5vout = "/vbus-5vout"; |
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vbus_typec = "/vbus-5vout"; |
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vcca0v9_s3 = "/vcca0v9-s3"; |
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mains_charger = "/dc-charger"; |
|
}; |
|
}; |
