Skip to content

Instantly share code, notes, and snippets.

@skochinsky

skochinsky/arm64_sysregs_ios.py

Forked from bazad/arm64_sysregs_ios.py
Created December 8, 2020 23:02
Show Gist options
  • Star 0 You must be signed in to star a gist
  • Fork 0 You must be signed in to fork a gist
  • Save skochinsky/d2d3d74191dd8294f46b3fbaf04458de to your computer and use it in GitHub Desktop.
Save skochinsky/d2d3d74191dd8294f46b3fbaf04458de to your computer and use it in GitHub Desktop.
Download ZIP
Label iOS arm64 system registers in IDA Pro
Raw
arm64_sysregs_ios.py
#
# arm64_sysregs_ios.py
# Brandon Azad
#
# Based on https://github.com/gdelugre/ida-arm-system-highlight by Guillaume Delugre.
#
import idautils
import idc
# AArch64 PSTATE accesses (op0 = 0b00, CRn = 0b0100).
PSTATE_ACCESS = {
0b011 : 'UAO',
0b100 : 'PAN',
0b101 : 'SPSel',
0b110 : 'DAIFSet',
0b111 : 'DAIFClr',
}
# AArch64 system registers (op0 = 0b01, 0b10, 0b11).
SYSTEM_REGISTERS = {
# SysReg_xml_v86A-2020-03
'S1_0_c7_c1_0' : ( 'IC IALLUIS', 'Instruction Cache Invalidate All to PoU, Inner Shareable' ),
'S1_0_c7_c5_0' : ( 'IC IALLU', 'Instruction Cache Invalidate All to PoU' ),
'S1_0_c7_c6_1' : ( 'DC IVAC', 'Data or unified Cache line Invalidate by VA to PoC' ),
'S1_0_c7_c6_2' : ( 'DC ISW', 'Data or unified Cache line Invalidate by Set/Way' ),
'S1_0_c7_c6_3' : ( 'DC IGVAC', 'Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by VA to PoC' ),
'S1_0_c7_c6_4' : ( 'DC IGSW', 'Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by Set/Way' ),
'S1_0_c7_c6_5' : ( 'DC IGDVAC', 'Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by VA to PoC' ),
'S1_0_c7_c6_6' : ( 'DC IGDSW', 'Data, Allocation Tag or unified Cache line Invalidate of Data and Allocation Tags by Set/Way' ),
'S1_0_c7_c8_0' : ( 'AT S1E1R', 'Address Translate Stage 1 EL1 Read' ),
'S1_0_c7_c8_1' : ( 'AT S1E1W', 'Address Translate Stage 1 EL1 Write' ),
'S1_0_c7_c8_2' : ( 'AT S1E0R', 'Address Translate Stage 1 EL0 Read' ),
'S1_0_c7_c8_3' : ( 'AT S1E0W', 'Address Translate Stage 1 EL0 Write' ),
'S1_0_c7_c9_0' : ( 'AT S1E1RP', 'Address Translate Stage 1 EL1 Read PAN' ),
'S1_0_c7_c9_1' : ( 'AT S1E1WP', 'Address Translate Stage 1 EL1 Write PAN' ),
'S1_0_c7_c10_2' : ( 'DC CSW', 'Data or unified Cache line Clean by Set/Way' ),
'S1_0_c7_c10_4' : ( 'DC CGSW', 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by Set/Way' ),
'S1_0_c7_c10_6' : ( 'DC CGDSW', 'Data, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by Set/Way' ),
'S1_0_c7_c14_2' : ( 'DC CISW', 'Data or unified Cache line Clean and Invalidate by Set/Way' ),
'S1_0_c7_c14_4' : ( 'DC CIGSW', 'Data, Allocation Tag or unified Cache line Clean and Invalidate of Allocation Tags by Set/Way' ),
'S1_0_c7_c14_6' : ( 'DC CIGDSW', 'Data, Allocation Tag or unified Cache line Clean and Invalidate of Data and Allocation Tags by Set/Way' ),
'S1_0_c8_c1_0' : ( 'TLBI VMALLE1OS', 'TLB Invalidate by VMID, All at stage 1, EL1, Outer Shareable' ),
'S1_0_c8_c1_1' : ( 'TLBI VAE1OS', 'TLB Invalidate by VA, EL1, Outer Shareable' ),
'S1_0_c8_c1_2' : ( 'TLBI ASIDE1OS', 'TLB Invalidate by ASID, EL1, Outer Shareable' ),
'S1_0_c8_c1_3' : ( 'TLBI VAAE1OS', 'TLB Invalidate by VA, All ASID, EL1, Outer Shareable' ),
'S1_0_c8_c1_5' : ( 'TLBI VALE1OS', 'TLB Invalidate by VA, Last level, EL1, Outer Shareable' ),
'S1_0_c8_c1_7' : ( 'TLBI VAALE1OS', 'TLB Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable' ),
'S1_0_c8_c2_1' : ( 'TLBI RVAE1IS', 'TLB Range Invalidate by VA, EL1, Inner Shareable' ),
'S1_0_c8_c2_3' : ( 'TLBI RVAAE1IS', 'TLB Range Invalidate by VA, All ASID, EL1, Inner Shareable' ),
'S1_0_c8_c2_5' : ( 'TLBI RVALE1IS', 'TLB Range Invalidate by VA, Last level, EL1, Inner Shareable' ),
'S1_0_c8_c2_7' : ( 'TLBI RVAALE1IS', 'TLB Range Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable' ),
'S1_0_c8_c3_0' : ( 'TLBI VMALLE1IS', 'TLB Invalidate by VMID, All at stage 1, EL1, Inner Shareable' ),
'S1_0_c8_c3_1' : ( 'TLBI VAE1IS', 'TLB Invalidate by VA, EL1, Inner Shareable' ),
'S1_0_c8_c3_2' : ( 'TLBI ASIDE1IS', 'TLB Invalidate by ASID, EL1, Inner Shareable' ),
'S1_0_c8_c3_3' : ( 'TLBI VAAE1IS', 'TLB Invalidate by VA, All ASID, EL1, Inner Shareable' ),
'S1_0_c8_c3_5' : ( 'TLBI VALE1IS', 'TLB Invalidate by VA, Last level, EL1, Inner Shareable' ),
'S1_0_c8_c3_7' : ( 'TLBI VAALE1IS', 'TLB Invalidate by VA, All ASID, Last Level, EL1, Inner Shareable' ),
'S1_0_c8_c5_1' : ( 'TLBI RVAE1OS', 'TLB Range Invalidate by VA, EL1, Outer Shareable' ),
'S1_0_c8_c5_3' : ( 'TLBI RVAAE1OS', 'TLB Range Invalidate by VA, All ASID, EL1, Outer Shareable' ),
'S1_0_c8_c5_5' : ( 'TLBI RVALE1OS', 'TLB Range Invalidate by VA, Last level, EL1, Outer Shareable' ),
'S1_0_c8_c5_7' : ( 'TLBI RVAALE1OS', 'TLB Range Invalidate by VA, All ASID, Last Level, EL1, Outer Shareable' ),
'S1_0_c8_c6_1' : ( 'TLBI RVAE1', 'TLB Range Invalidate by VA, EL1' ),
'S1_0_c8_c6_3' : ( 'TLBI RVAAE1', 'TLB Range Invalidate by VA, All ASID, EL1' ),
'S1_0_c8_c6_5' : ( 'TLBI RVALE1', 'TLB Range Invalidate by VA, Last level, EL1' ),
'S1_0_c8_c6_7' : ( 'TLBI RVAALE1', 'TLB Range Invalidate by VA, All ASID, Last level, EL1' ),
'S1_0_c8_c7_0' : ( 'TLBI VMALLE1', 'TLB Invalidate by VMID, All at stage 1, EL1' ),
'S1_0_c8_c7_1' : ( 'TLBI VAE1', 'TLB Invalidate by VA, EL1' ),
'S1_0_c8_c7_2' : ( 'TLBI ASIDE1', 'TLB Invalidate by ASID, EL1' ),
'S1_0_c8_c7_3' : ( 'TLBI VAAE1', 'TLB Invalidate by VA, All ASID, EL1' ),
'S1_0_c8_c7_5' : ( 'TLBI VALE1', 'TLB Invalidate by VA, Last level, EL1' ),
'S1_0_c8_c7_7' : ( 'TLBI VAALE1', 'TLB Invalidate by VA, All ASID, Last level, EL1' ),
'S1_3_c7_c3_4' : ( 'CFP RCTX', 'Control Flow Prediction Restriction by Context' ),
'S1_3_c7_c3_5' : ( 'DVP RCTX', 'Data Value Prediction Restriction by Context' ),
'S1_3_c7_c3_7' : ( 'CPP RCTX', 'Cache Prefetch Prediction Restriction by Context' ),
'S1_3_c7_c4_1' : ( 'DC ZVA', 'Data Cache Zero by VA' ),
'S1_3_c7_c4_3' : ( 'DC GVA', 'Data Cache set Allocation Tag by VA' ),
'S1_3_c7_c4_4' : ( 'DC GZVA', 'Data Cache set Allocation Tags and Zero by VA' ),
'S1_3_c7_c5_1' : ( 'IC IVAU', 'Instruction Cache line Invalidate by VA to PoU' ),
'S1_3_c7_c10_1' : ( 'DC CVAC', 'Data or unified Cache line Clean by VA to PoC' ),
'S1_3_c7_c10_3' : ( 'DC CGVAC', 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoC' ),
'S1_3_c7_c10_5' : ( 'DC CGDVAC', 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoC' ),
'S1_3_c7_c11_1' : ( 'DC CVAU', 'Data or unified Cache line Clean by VA to PoU' ),
'S1_3_c7_c12_1' : ( 'DC CVAP', 'Data or unified Cache line Clean by VA to PoP' ),
'S1_3_c7_c12_3' : ( 'DC CGVAP', 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoP' ),
'S1_3_c7_c12_5' : ( 'DC CGDVAP', 'Data, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by VA to PoP' ),
'S1_3_c7_c13_1' : ( 'DC CVADP', 'Data or unified Cache line Clean by VA to PoDP' ),
'S1_3_c7_c13_3' : ( 'DC CGVADP', 'Clean of Allocation Tags by VA to PoDP' ),
'S1_3_c7_c13_5' : ( 'DC CGDVADP', 'Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoDP' ),
'S1_3_c7_c14_1' : ( 'DC CIVAC', 'Data or unified Cache line Clean and Invalidate by VA to PoC' ),
'S1_3_c7_c14_3' : ( 'DC CIGVAC', 'Data, Allocation Tag or unified Cache line Clean and Invalidate of Allocation Tags by VA to PoC' ),
'S1_3_c7_c14_5' : ( 'DC CIGDVAC', 'Data, Allocation Tag or unified Cache line Clean and Invalidate of Data and Allocation Tags by VA to PoC' ),
'S1_4_c7_c8_0' : ( 'AT S1E2R', 'Address Translate Stage 1 EL2 Read' ),
'S1_4_c7_c8_1' : ( 'AT S1E2W', 'Address Translate Stage 1 EL2 Write' ),
'S1_4_c7_c8_4' : ( 'AT S12E1R', 'Address Translate Stages 1 and 2 EL1 Read' ),
'S1_4_c7_c8_5' : ( 'AT S12E1W', 'Address Translate Stages 1 and 2 EL1 Write' ),
'S1_4_c7_c8_6' : ( 'AT S12E0R', 'Address Translate Stages 1 and 2 EL0 Read' ),
'S1_4_c7_c8_7' : ( 'AT S12E0W', 'Address Translate Stages 1 and 2 EL0 Write' ),
'S1_4_c8_c0_1' : ( 'TLBI IPAS2E1IS', 'TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable' ),
'S1_4_c8_c0_2' : ( 'TLBI RIPAS2E1IS', 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Inner Shareable' ),
'S1_4_c8_c0_5' : ( 'TLBI IPAS2LE1IS', 'TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable' ),
'S1_4_c8_c0_6' : ( 'TLBI RIPAS2LE1IS', 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Inner Shareable' ),
'S1_4_c8_c1_0' : ( 'TLBI ALLE2OS', 'TLB Invalidate All, EL2, Outer Shareable' ),
'S1_4_c8_c1_1' : ( 'TLBI VAE2OS', 'TLB Invalidate by VA, EL2, Outer Shareable' ),
'S1_4_c8_c1_4' : ( 'TLBI ALLE1OS', 'TLB Invalidate All, EL1, Outer Shareable' ),
'S1_4_c8_c1_5' : ( 'TLBI VALE2OS', 'TLB Invalidate by VA, Last level, EL2, Outer Shareable' ),
'S1_4_c8_c1_6' : ( 'TLBI VMALLS12E1OS', 'TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Outer Shareable' ),
'S1_4_c8_c2_1' : ( 'TLBI RVAE2IS', 'TLB Range Invalidate by VA, EL2, Inner Shareable' ),
'S1_4_c8_c2_5' : ( 'TLBI RVALE2IS', 'TLB Range Invalidate by VA, Last level, EL2, Inner Shareable' ),
'S1_4_c8_c3_0' : ( 'TLBI ALLE2IS', 'TLB Invalidate All, EL2, Inner Shareable' ),
'S1_4_c8_c3_1' : ( 'TLBI VAE2IS', 'TLB Invalidate by VA, EL2, Inner Shareable' ),
'S1_4_c8_c3_4' : ( 'TLBI ALLE1IS', 'TLB Invalidate All, EL1, Inner Shareable' ),
'S1_4_c8_c3_5' : ( 'TLBI VALE2IS', 'TLB Invalidate by VA, Last level, EL2, Inner Shareable' ),
'S1_4_c8_c3_6' : ( 'TLBI VMALLS12E1IS', 'TLB Invalidate by VMID, All at Stage 1 and 2, EL1, Inner Shareable' ),
'S1_4_c8_c4_0' : ( 'TLBI IPAS2E1OS', 'TLB Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable' ),
'S1_4_c8_c4_1' : ( 'TLBI IPAS2E1', 'TLB Invalidate by Intermediate Physical Address, Stage 2, EL1' ),
'S1_4_c8_c4_2' : ( 'TLBI RIPAS2E1', 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1' ),
'S1_4_c8_c4_3' : ( 'TLBI RIPAS2E1OS', 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, EL1, Outer Shareable' ),
'S1_4_c8_c4_4' : ( 'TLBI IPAS2LE1OS', 'TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable' ),
'S1_4_c8_c4_5' : ( 'TLBI IPAS2LE1', 'TLB Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1' ),
'S1_4_c8_c4_6' : ( 'TLBI RIPAS2LE1', 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1' ),
'S1_4_c8_c4_7' : ( 'TLBI RIPAS2LE1OS', 'TLB Range Invalidate by Intermediate Physical Address, Stage 2, Last level, EL1, Outer Shareable' ),
'S1_4_c8_c5_1' : ( 'TLBI RVAE2OS', 'TLB Range Invalidate by VA, EL2, Outer Shareable' ),
'S1_4_c8_c5_5' : ( 'TLBI RVALE2OS', 'TLB Range Invalidate by VA, Last level, EL2, Outer Shareable' ),
'S1_4_c8_c6_1' : ( 'TLBI RVAE2', 'TLB Range Invalidate by VA, EL2' ),
'S1_4_c8_c6_5' : ( 'TLBI RVALE2', 'TLB Range Invalidate by VA, Last level, EL2' ),
'S1_4_c8_c7_0' : ( 'TLBI ALLE2', 'TLB Invalidate All, EL2' ),
'S1_4_c8_c7_1' : ( 'TLBI VAE2', 'TLB Invalidate by VA, EL2' ),
'S1_4_c8_c7_4' : ( 'TLBI ALLE1', 'TLB Invalidate All, EL1' ),
'S1_4_c8_c7_5' : ( 'TLBI VALE2', 'TLB Invalidate by VA, Last level, EL2' ),
'S1_4_c8_c7_6' : ( 'TLBI VMALLS12E1', 'TLB Invalidate by VMID, All at Stage 1 and 2, EL1' ),
'S1_6_c7_c8_0' : ( 'AT S1E3R', 'Address Translate Stage 1 EL3 Read' ),
'S1_6_c7_c8_1' : ( 'AT S1E3W', 'Address Translate Stage 1 EL3 Write' ),
'S1_6_c8_c1_0' : ( 'TLBI ALLE3OS', 'TLB Invalidate All, EL3, Outer Shareable' ),
'S1_6_c8_c1_1' : ( 'TLBI VAE3OS', 'TLB Invalidate by VA, EL3, Outer Shareable' ),
'S1_6_c8_c1_5' : ( 'TLBI VALE3OS', 'TLB Invalidate by VA, Last level, EL3, Outer Shareable' ),
'S1_6_c8_c2_1' : ( 'TLBI RVAE3IS', 'TLB Range Invalidate by VA, EL3, Inner Shareable' ),
'S1_6_c8_c2_5' : ( 'TLBI RVALE3IS', 'TLB Range Invalidate by VA, Last level, EL3, Inner Shareable' ),
'S1_6_c8_c3_0' : ( 'TLBI ALLE3IS', 'TLB Invalidate All, EL3, Inner Shareable' ),
'S1_6_c8_c3_1' : ( 'TLBI VAE3IS', 'TLB Invalidate by VA, EL3, Inner Shareable' ),
'S1_6_c8_c3_5' : ( 'TLBI VALE3IS', 'TLB Invalidate by VA, Last level, EL3, Inner Shareable' ),
'S1_6_c8_c5_1' : ( 'TLBI RVAE3OS', 'TLB Range Invalidate by VA, EL3, Outer Shareable' ),
'S1_6_c8_c5_5' : ( 'TLBI RVALE3OS', 'TLB Range Invalidate by VA, Last level, EL3, Outer Shareable' ),
'S1_6_c8_c6_1' : ( 'TLBI RVAE3', 'TLB Range Invalidate by VA, EL3' ),
'S1_6_c8_c6_5' : ( 'TLBI RVALE3', 'TLB Range Invalidate by VA, Last level, EL3' ),
'S1_6_c8_c7_0' : ( 'TLBI ALLE3', 'TLB Invalidate All, EL3' ),
'S1_6_c8_c7_1' : ( 'TLBI VAE3', 'TLB Invalidate by VA, EL3' ),
'S1_6_c8_c7_5' : ( 'TLBI VALE3', 'TLB Invalidate by VA, Last level, EL3' ),
'S2_0_c0_c0_2' : ( 'OSDTRRX_EL1', 'OS Lock Data Transfer Register, Receive' ),
'S2_0_c0_c0_4' : ( 'DBGBVR0_EL1', 'Debug Breakpoint Value Register 0' ),
'S2_0_c0_c0_5' : ( 'DBGBCR0_EL1', 'Debug Breakpoint Control Register 0' ),
'S2_0_c0_c0_6' : ( 'DBGWVR0_EL1', 'Debug Watchpoint Value Register 0' ),
'S2_0_c0_c0_7' : ( 'DBGWCR0_EL1', 'Debug Watchpoint Control Register 0' ),
'S2_0_c0_c1_4' : ( 'DBGBVR1_EL1', 'Debug Breakpoint Value Register 1' ),
'S2_0_c0_c1_5' : ( 'DBGBCR1_EL1', 'Debug Breakpoint Control Register 1' ),
'S2_0_c0_c1_6' : ( 'DBGWVR1_EL1', 'Debug Watchpoint Value Register 1' ),
'S2_0_c0_c1_7' : ( 'DBGWCR1_EL1', 'Debug Watchpoint Control Register 1' ),
'S2_0_c0_c2_0' : ( 'MDCCINT_EL1', 'Monitor DCC Interrupt Enable Register' ),
'S2_0_c0_c2_2' : ( 'MDSCR_EL1', 'Monitor Debug System Control Register' ),
'S2_0_c0_c2_4' : ( 'DBGBVR2_EL1', 'Debug Breakpoint Value Register 2' ),
'S2_0_c0_c2_5' : ( 'DBGBCR2_EL1', 'Debug Breakpoint Control Register 2' ),
'S2_0_c0_c2_6' : ( 'DBGWVR2_EL1', 'Debug Watchpoint Value Register 2' ),
'S2_0_c0_c2_7' : ( 'DBGWCR2_EL1', 'Debug Watchpoint Control Register 2' ),
'S2_0_c0_c3_2' : ( 'OSDTRTX_EL1', 'OS Lock Data Transfer Register, Transmit' ),
'S2_0_c0_c3_4' : ( 'DBGBVR3_EL1', 'Debug Breakpoint Value Register 3' ),
'S2_0_c0_c3_5' : ( 'DBGBCR3_EL1', 'Debug Breakpoint Control Register 3' ),
'S2_0_c0_c3_6' : ( 'DBGWVR3_EL1', 'Debug Watchpoint Value Register 3' ),
'S2_0_c0_c3_7' : ( 'DBGWCR3_EL1', 'Debug Watchpoint Control Register 3' ),
'S2_0_c0_c4_4' : ( 'DBGBVR4_EL1', 'Debug Breakpoint Value Register 4' ),
'S2_0_c0_c4_5' : ( 'DBGBCR4_EL1', 'Debug Breakpoint Control Register 4' ),
'S2_0_c0_c4_6' : ( 'DBGWVR4_EL1', 'Debug Watchpoint Value Register 4' ),
'S2_0_c0_c4_7' : ( 'DBGWCR4_EL1', 'Debug Watchpoint Control Register 4' ),
'S2_0_c0_c5_4' : ( 'DBGBVR5_EL1', 'Debug Breakpoint Value Register 5' ),
'S2_0_c0_c5_5' : ( 'DBGBCR5_EL1', 'Debug Breakpoint Control Register 5' ),
'S2_0_c0_c5_6' : ( 'DBGWVR5_EL1', 'Debug Watchpoint Value Register 5' ),
'S2_0_c0_c5_7' : ( 'DBGWCR5_EL1', 'Debug Watchpoint Control Register 5' ),
'S2_0_c0_c6_2' : ( 'OSECCR_EL1', 'OS Lock Exception Catch Control Register' ),
'S2_0_c0_c6_4' : ( 'DBGBVR6_EL1', 'Debug Breakpoint Value Register 6' ),
'S2_0_c0_c6_5' : ( 'DBGBCR6_EL1', 'Debug Breakpoint Control Register 6' ),
'S2_0_c0_c6_6' : ( 'DBGWVR6_EL1', 'Debug Watchpoint Value Register 6' ),
'S2_0_c0_c6_7' : ( 'DBGWCR6_EL1', 'Debug Watchpoint Control Register 6' ),
'S2_0_c0_c7_4' : ( 'DBGBVR7_EL1', 'Debug Breakpoint Value Register 7' ),
'S2_0_c0_c7_5' : ( 'DBGBCR7_EL1', 'Debug Breakpoint Control Register 7' ),
'S2_0_c0_c7_6' : ( 'DBGWVR7_EL1', 'Debug Watchpoint Value Register 7' ),
'S2_0_c0_c7_7' : ( 'DBGWCR7_EL1', 'Debug Watchpoint Control Register 7' ),
'S2_0_c0_c8_4' : ( 'DBGBVR8_EL1', 'Debug Breakpoint Value Register 8' ),
'S2_0_c0_c8_5' : ( 'DBGBCR8_EL1', 'Debug Breakpoint Control Register 8' ),
'S2_0_c0_c8_6' : ( 'DBGWVR8_EL1', 'Debug Watchpoint Value Register 8' ),
'S2_0_c0_c8_7' : ( 'DBGWCR8_EL1', 'Debug Watchpoint Control Register 8' ),
'S2_0_c0_c9_4' : ( 'DBGBVR9_EL1', 'Debug Breakpoint Value Register 9' ),
'S2_0_c0_c9_5' : ( 'DBGBCR9_EL1', 'Debug Breakpoint Control Register 9' ),
'S2_0_c0_c9_6' : ( 'DBGWVR9_EL1', 'Debug Watchpoint Value Register 9' ),
'S2_0_c0_c9_7' : ( 'DBGWCR9_EL1', 'Debug Watchpoint Control Register 9' ),
'S2_0_c0_c10_4' : ( 'DBGBVR10_EL1', 'Debug Breakpoint Value Register 10' ),
'S2_0_c0_c10_5' : ( 'DBGBCR10_EL1', 'Debug Breakpoint Control Register 10' ),
'S2_0_c0_c10_6' : ( 'DBGWVR10_EL1', 'Debug Watchpoint Value Register 10' ),
'S2_0_c0_c10_7' : ( 'DBGWCR10_EL1', 'Debug Watchpoint Control Register 10' ),
'S2_0_c0_c11_4' : ( 'DBGBVR11_EL1', 'Debug Breakpoint Value Register 11' ),
'S2_0_c0_c11_5' : ( 'DBGBCR11_EL1', 'Debug Breakpoint Control Register 11' ),
'S2_0_c0_c11_6' : ( 'DBGWVR11_EL1', 'Debug Watchpoint Value Register 11' ),
'S2_0_c0_c11_7' : ( 'DBGWCR11_EL1', 'Debug Watchpoint Control Register 11' ),
'S2_0_c0_c12_4' : ( 'DBGBVR12_EL1', 'Debug Breakpoint Value Register 12' ),
'S2_0_c0_c12_5' : ( 'DBGBCR12_EL1', 'Debug Breakpoint Control Register 12' ),
'S2_0_c0_c12_6' : ( 'DBGWVR12_EL1', 'Debug Watchpoint Value Register 12' ),
'S2_0_c0_c12_7' : ( 'DBGWCR12_EL1', 'Debug Watchpoint Control Register 12' ),
'S2_0_c0_c13_4' : ( 'DBGBVR13_EL1', 'Debug Breakpoint Value Register 13' ),
'S2_0_c0_c13_5' : ( 'DBGBCR13_EL1', 'Debug Breakpoint Control Register 13' ),
'S2_0_c0_c13_6' : ( 'DBGWVR13_EL1', 'Debug Watchpoint Value Register 13' ),
'S2_0_c0_c13_7' : ( 'DBGWCR13_EL1', 'Debug Watchpoint Control Register 13' ),
'S2_0_c0_c14_4' : ( 'DBGBVR14_EL1', 'Debug Breakpoint Value Register 14' ),
'S2_0_c0_c14_5' : ( 'DBGBCR14_EL1', 'Debug Breakpoint Control Register 14' ),
'S2_0_c0_c14_6' : ( 'DBGWVR14_EL1', 'Debug Watchpoint Value Register 14' ),
'S2_0_c0_c14_7' : ( 'DBGWCR14_EL1', 'Debug Watchpoint Control Register 14' ),
'S2_0_c0_c15_4' : ( 'DBGBVR15_EL1', 'Debug Breakpoint Value Register 15' ),
'S2_0_c0_c15_5' : ( 'DBGBCR15_EL1', 'Debug Breakpoint Control Register 15' ),
'S2_0_c0_c15_6' : ( 'DBGWVR15_EL1', 'Debug Watchpoint Value Register 15' ),
'S2_0_c0_c15_7' : ( 'DBGWCR15_EL1', 'Debug Watchpoint Control Register 15' ),
'S2_0_c1_c0_0' : ( 'MDRAR_EL1', 'Monitor Debug ROM Address Register' ),
'S2_0_c1_c0_4' : ( 'OSLAR_EL1', 'OS Lock Access Register' ),
'S2_0_c1_c1_4' : ( 'OSLSR_EL1', 'OS Lock Status Register' ),
'S2_0_c1_c3_4' : ( 'OSDLR_EL1', 'OS Double Lock Register' ),
'S2_0_c1_c4_4' : ( 'DBGPRCR_EL1', 'Debug Power Control Register' ),
'S2_0_c7_c8_6' : ( 'DBGCLAIMSET_EL1', 'Debug CLAIM Tag Set register' ),
'S2_0_c7_c9_6' : ( 'DBGCLAIMCLR_EL1', 'Debug CLAIM Tag Clear register' ),
'S2_0_c7_c14_6' : ( 'DBGAUTHSTATUS_EL1', 'Debug Authentication Status register' ),
'S2_3_c0_c1_0' : ( 'MDCCSR_EL0', 'Monitor DCC Status Register' ),
'S2_3_c0_c4_0' : ( 'DBGDTR_EL0', 'Debug Data Transfer Register, half-duplex' ),
'S2_3_c0_c5_0' : ( 'DBGDTRRX_EL0', 'Debug Data Transfer Register, Receive' ),
'S2_3_c0_c5_0' : ( 'DBGDTRTX_EL0', 'Debug Data Transfer Register, Transmit' ),
'S2_4_c0_c7_0' : ( 'DBGVCR32_EL2', 'Debug Vector Catch Register' ),
'S3_0_c0_c0_0' : ( 'MIDR_EL1', 'Main ID Register' ),
'S3_0_c0_c0_5' : ( 'MPIDR_EL1', 'Multiprocessor Affinity Register' ),
'S3_0_c0_c0_6' : ( 'REVIDR_EL1', 'Revision ID Register' ),
'S3_0_c0_c1_0' : ( 'ID_PFR0_EL1', 'AArch32 Processor Feature Register 0' ),
'S3_0_c0_c1_1' : ( 'ID_PFR1_EL1', 'AArch32 Processor Feature Register 1' ),
'S3_0_c0_c1_2' : ( 'ID_DFR0_EL1', 'AArch32 Debug Feature Register 0' ),
'S3_0_c0_c1_3' : ( 'ID_AFR0_EL1', 'AArch32 Auxiliary Feature Register 0' ),
'S3_0_c0_c1_4' : ( 'ID_MMFR0_EL1', 'AArch32 Memory Model Feature Register 0' ),
'S3_0_c0_c1_5' : ( 'ID_MMFR1_EL1', 'AArch32 Memory Model Feature Register 1' ),
'S3_0_c0_c1_6' : ( 'ID_MMFR2_EL1', 'AArch32 Memory Model Feature Register 2' ),
'S3_0_c0_c1_7' : ( 'ID_MMFR3_EL1', 'AArch32 Memory Model Feature Register 3' ),
'S3_0_c0_c2_0' : ( 'ID_ISAR0_EL1', 'AArch32 Instruction Set Attribute Register 0' ),
'S3_0_c0_c2_1' : ( 'ID_ISAR1_EL1', 'AArch32 Instruction Set Attribute Register 1' ),
'S3_0_c0_c2_2' : ( 'ID_ISAR2_EL1', 'AArch32 Instruction Set Attribute Register 2' ),
'S3_0_c0_c2_3' : ( 'ID_ISAR3_EL1', 'AArch32 Instruction Set Attribute Register 3' ),
'S3_0_c0_c2_4' : ( 'ID_ISAR4_EL1', 'AArch32 Instruction Set Attribute Register 4' ),
'S3_0_c0_c2_5' : ( 'ID_ISAR5_EL1', 'AArch32 Instruction Set Attribute Register 5' ),
'S3_0_c0_c2_6' : ( 'ID_MMFR4_EL1', 'AArch32 Memory Model Feature Register 4' ),
'S3_0_c0_c2_7' : ( 'ID_ISAR6_EL1', 'AArch32 Instruction Set Attribute Register 6' ),
'S3_0_c0_c3_0' : ( 'MVFR0_EL1', 'AArch32 Media and VFP Feature Register 0' ),
'S3_0_c0_c3_1' : ( 'MVFR1_EL1', 'AArch32 Media and VFP Feature Register 1' ),
'S3_0_c0_c3_2' : ( 'MVFR2_EL1', 'AArch32 Media and VFP Feature Register 2' ),
'S3_0_c0_c3_4' : ( 'ID_PFR2_EL1', 'AArch32 Processor Feature Register 2' ),
'S3_0_c0_c3_5' : ( 'ID_DFR1_EL1', 'Debug Feature Register 1' ),
'S3_0_c0_c3_6' : ( 'ID_MMFR5_EL1', 'AArch32 Memory Model Feature Register 5' ),
'S3_0_c0_c4_0' : ( 'ID_AA64PFR0_EL1', 'AArch64 Processor Feature Register 0' ),
'S3_0_c0_c4_1' : ( 'ID_AA64PFR1_EL1', 'AArch64 Processor Feature Register 1' ),
'S3_0_c0_c4_4' : ( 'ID_AA64ZFR0_EL1', 'SVE Feature ID register 0' ),
'S3_0_c0_c5_0' : ( 'ID_AA64DFR0_EL1', 'AArch64 Debug Feature Register 0' ),
'S3_0_c0_c5_1' : ( 'ID_AA64DFR1_EL1', 'AArch64 Debug Feature Register 1' ),
'S3_0_c0_c5_4' : ( 'ID_AA64AFR0_EL1', 'AArch64 Auxiliary Feature Register 0' ),
'S3_0_c0_c5_5' : ( 'ID_AA64AFR1_EL1', 'AArch64 Auxiliary Feature Register 1' ),
'S3_0_c0_c6_0' : ( 'ID_AA64ISAR0_EL1', 'AArch64 Instruction Set Attribute Register 0' ),
'S3_0_c0_c6_1' : ( 'ID_AA64ISAR1_EL1', 'AArch64 Instruction Set Attribute Register 1' ),
'S3_0_c0_c7_0' : ( 'ID_AA64MMFR0_EL1', 'AArch64 Memory Model Feature Register 0' ),
'S3_0_c0_c7_1' : ( 'ID_AA64MMFR1_EL1', 'AArch64 Memory Model Feature Register 1' ),
'S3_0_c0_c7_2' : ( 'ID_AA64MMFR2_EL1', 'AArch64 Memory Model Feature Register 2' ),
'S3_0_c1_c0_0' : ( 'SCTLR_EL1', 'System Control Register (EL1)' ),
'S3_0_c1_c0_1' : ( 'ACTLR_EL1', 'Auxiliary Control Register (EL1)' ),
'S3_0_c1_c0_2' : ( 'CPACR_EL1', 'Architectural Feature Access Control Register' ),
'S3_0_c1_c0_5' : ( 'RGSR_EL1', 'Random Allocation Tag Seed Register.' ),
'S3_0_c1_c0_6' : ( 'GCR_EL1', 'Tag Control Register.' ),
'S3_0_c1_c2_0' : ( 'ZCR_EL1', 'SVE Control Register for EL1' ),
'S3_0_c1_c2_1' : ( 'TRFCR_EL1', 'Trace Filter Control Register (EL1)' ),
'S3_0_c2_c0_0' : ( 'TTBR0_EL1', 'Translation Table Base Register 0 (EL1)' ),
'S3_0_c2_c0_1' : ( 'TTBR1_EL1', 'Translation Table Base Register 1 (EL1)' ),
'S3_0_c2_c0_2' : ( 'TCR_EL1', 'Translation Control Register (EL1)' ),
'S3_0_c2_c1_0' : ( 'APIAKeyLo_EL1', 'Pointer Authentication Key A for Instruction (bits[63:0]) ' ),
'S3_0_c2_c1_1' : ( 'APIAKeyHi_EL1', 'Pointer Authentication Key A for Instruction (bits[127:64]) ' ),
'S3_0_c2_c1_2' : ( 'APIBKeyLo_EL1', 'Pointer Authentication Key B for Instruction (bits[63:0]) ' ),
'S3_0_c2_c1_3' : ( 'APIBKeyHi_EL1', 'Pointer Authentication Key B for Instruction (bits[127:64]) ' ),
'S3_0_c2_c2_0' : ( 'APDAKeyLo_EL1', 'Pointer Authentication Key A for Data (bits[63:0]) ' ),
'S3_0_c2_c2_1' : ( 'APDAKeyHi_EL1', 'Pointer Authentication Key A for Data (bits[127:64]) ' ),
'S3_0_c2_c2_2' : ( 'APDBKeyLo_EL1', 'Pointer Authentication Key B for Data (bits[63:0]) ' ),
'S3_0_c2_c2_3' : ( 'APDBKeyHi_EL1', 'Pointer Authentication Key B for Data (bits[127:64]) ' ),
'S3_0_c2_c3_0' : ( 'APGAKeyLo_EL1', 'Pointer Authentication Key A for Code (bits[63:0]) ' ),
'S3_0_c2_c3_1' : ( 'APGAKeyHi_EL1', 'Pointer Authentication Key A for Code (bits[127:64]) ' ),
'S3_0_c4_c0_0' : ( 'SPSR_EL1', 'Saved Program Status Register (EL1)' ),
'S3_0_c4_c0_1' : ( 'ELR_EL1', 'Exception Link Register (EL1)' ),
'S3_0_c4_c1_0' : ( 'SP_EL0', 'Stack Pointer (EL0)' ),
'S3_0_c4_c2_0' : ( 'SPSel', 'Stack Pointer Select' ),
'S3_0_c4_c2_2' : ( 'CurrentEL', 'Current Exception Level' ),
'S3_0_c4_c2_3' : ( 'PAN', 'Privileged Access Never' ),
'S3_0_c4_c2_4' : ( 'UAO', 'User Access Override' ),
'S3_0_c4_c6_0' : ( 'ICC_PMR_EL1', 'Interrupt Controller Interrupt Priority Mask Register' ),
'S3_0_c4_c6_0' : ( 'ICV_PMR_EL1', 'Interrupt Controller Virtual Interrupt Priority Mask Register' ),
'S3_0_c5_c1_0' : ( 'AFSR0_EL1', 'Auxiliary Fault Status Register 0 (EL1)' ),
'S3_0_c5_c1_1' : ( 'AFSR1_EL1', 'Auxiliary Fault Status Register 1 (EL1)' ),
'S3_0_c5_c2_0' : ( 'ESR_EL1', 'Exception Syndrome Register (EL1)' ),
'S3_0_c5_c3_0' : ( 'ERRIDR_EL1', 'Error Record ID Register' ),
'S3_0_c5_c3_1' : ( 'ERRSELR_EL1', 'Error Record Select Register' ),
'S3_0_c5_c4_0' : ( 'ERXFR_EL1', 'Selected Error Record Feature Register' ),
'S3_0_c5_c4_1' : ( 'ERXCTLR_EL1', 'Selected Error Record Control Register' ),
'S3_0_c5_c4_2' : ( 'ERXSTATUS_EL1', 'Selected Error Record Primary Status Register' ),
'S3_0_c5_c4_3' : ( 'ERXADDR_EL1', 'Selected Error Record Address Register' ),
'S3_0_c5_c4_4' : ( 'ERXPFGF_EL1', 'Selected Pseudo-fault Generation Feature register' ),
'S3_0_c5_c4_5' : ( 'ERXPFGCTL_EL1', 'Selected Pseudo-fault Generation Control register' ),
'S3_0_c5_c4_6' : ( 'ERXPFGCDN_EL1', 'Selected Pseudo-fault Generation Countdown register' ),
'S3_0_c5_c5_0' : ( 'ERXMISC0_EL1', 'Selected Error Record Miscellaneous Register 0' ),
'S3_0_c5_c5_1' : ( 'ERXMISC1_EL1', 'Selected Error Record Miscellaneous Register 1' ),
'S3_0_c5_c5_2' : ( 'ERXMISC2_EL1', 'Selected Error Record Miscellaneous Register 2' ),
'S3_0_c5_c5_3' : ( 'ERXMISC3_EL1', 'Selected Error Record Miscellaneous Register 3' ),
'S3_0_c5_c6_0' : ( 'TFSR_EL1', 'Tag Fault Status Register (EL1)' ),
'S3_0_c5_c6_1' : ( 'TFSRE0_EL1', 'Tag Fault Status Register (EL0).' ),
'S3_0_c6_c0_0' : ( 'FAR_EL1', 'Fault Address Register (EL1)' ),
'S3_0_c7_c4_0' : ( 'PAR_EL1', 'Physical Address Register' ),
'S3_0_c9_c9_0' : ( 'PMSCR_EL1', 'Statistical Profiling Control Register (EL1)' ),
'S3_0_c9_c9_2' : ( 'PMSICR_EL1', 'Sampling Interval Counter Register' ),
'S3_0_c9_c9_3' : ( 'PMSIRR_EL1', 'Sampling Interval Reload Register' ),
'S3_0_c9_c9_4' : ( 'PMSFCR_EL1', 'Sampling Filter Control Register' ),
'S3_0_c9_c9_5' : ( 'PMSEVFR_EL1', 'Sampling Event Filter Register' ),
'S3_0_c9_c9_6' : ( 'PMSLATFR_EL1', 'Sampling Latency Filter Register' ),
'S3_0_c9_c9_7' : ( 'PMSIDR_EL1', 'Sampling Profiling ID Register' ),
'S3_0_c9_c10_0' : ( 'PMBLIMITR_EL1', 'Profiling Buffer Limit Address Register' ),
'S3_0_c9_c10_1' : ( 'PMBPTR_EL1', 'Profiling Buffer Write Pointer Register' ),
'S3_0_c9_c10_3' : ( 'PMBSR_EL1', 'Profiling Buffer Status/syndrome Register' ),
'S3_0_c9_c10_7' : ( 'PMBIDR_EL1', 'Profiling Buffer ID Register' ),
'S3_0_c9_c14_1' : ( 'PMINTENSET_EL1', 'Performance Monitors Interrupt Enable Set register' ),
'S3_0_c9_c14_2' : ( 'PMINTENCLR_EL1', 'Performance Monitors Interrupt Enable Clear register' ),
'S3_0_c9_c14_6' : ( 'PMMIR_EL1', 'Performance Monitors Machine Identification Register' ),
'S3_0_c10_c2_0' : ( 'MAIR_EL1', 'Memory Attribute Indirection Register (EL1)' ),
'S3_0_c10_c3_0' : ( 'AMAIR_EL1', 'Auxiliary Memory Attribute Indirection Register (EL1)' ),
'S3_0_c10_c4_0' : ( 'LORSA_EL1', 'LORegion Start Address (EL1)' ),
'S3_0_c10_c4_1' : ( 'LOREA_EL1', 'LORegion End Address (EL1)' ),
'S3_0_c10_c4_2' : ( 'LORN_EL1', 'LORegion Number (EL1)' ),
'S3_0_c10_c4_3' : ( 'LORC_EL1', 'LORegion Control (EL1)' ),
'S3_0_c10_c4_4' : ( 'MPAMIDR_EL1', 'MPAM ID Register (EL1)' ),
'S3_0_c10_c4_7' : ( 'LORID_EL1', 'LORegionID (EL1)' ),
'S3_0_c10_c5_0' : ( 'MPAM1_EL1', 'MPAM1 Register (EL1)' ),
'S3_0_c10_c5_1' : ( 'MPAM0_EL1', 'MPAM0 Register (EL1)' ),
'S3_0_c12_c0_0' : ( 'VBAR_EL1', 'Vector Base Address Register (EL1)' ),
'S3_0_c12_c0_1' : ( 'RVBAR_EL1', 'Reset Vector Base Address Register (if EL2 and EL3 not implemented)' ),
'S3_0_c12_c0_2' : ( 'RMR_EL1', 'Reset Management Register (EL1)' ),
'S3_0_c12_c1_0' : ( 'ISR_EL1', 'Interrupt Status Register' ),
'S3_0_c12_c1_1' : ( 'DISR_EL1', 'Deferred Interrupt Status Register' ),
'S3_0_c12_c8_0' : ( 'ICC_IAR0_EL1', 'Interrupt Controller Interrupt Acknowledge Register 0' ),
'S3_0_c12_c8_0' : ( 'ICV_IAR0_EL1', 'Interrupt Controller Virtual Interrupt Acknowledge Register 0' ),
'S3_0_c12_c8_1' : ( 'ICC_EOIR0_EL1', 'Interrupt Controller End Of Interrupt Register 0' ),
'S3_0_c12_c8_1' : ( 'ICV_EOIR0_EL1', 'Interrupt Controller Virtual End Of Interrupt Register 0' ),
'S3_0_c12_c8_2' : ( 'ICC_HPPIR0_EL1', 'Interrupt Controller Highest Priority Pending Interrupt Register 0' ),
'S3_0_c12_c8_2' : ( 'ICV_HPPIR0_EL1', 'Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0' ),
'S3_0_c12_c8_3' : ( 'ICC_BPR0_EL1', 'Interrupt Controller Binary Point Register 0' ),
'S3_0_c12_c8_3' : ( 'ICV_BPR0_EL1', 'Interrupt Controller Virtual Binary Point Register 0' ),
'S3_0_c12_c8_4' : ( 'ICC_AP0R0_EL1', 'Interrupt Controller Active Priorities Group 0 Register 0' ),
'S3_0_c12_c8_4' : ( 'ICV_AP0R0_EL1', 'Interrupt Controller Virtual Active Priorities Group 0 Register 0' ),
'S3_0_c12_c8_5' : ( 'ICC_AP0R1_EL1', 'Interrupt Controller Active Priorities Group 0 Register 1' ),
'S3_0_c12_c8_5' : ( 'ICV_AP0R1_EL1', 'Interrupt Controller Virtual Active Priorities Group 0 Register 1' ),
'S3_0_c12_c8_6' : ( 'ICC_AP0R2_EL1', 'Interrupt Controller Active Priorities Group 0 Register 2' ),
'S3_0_c12_c8_6' : ( 'ICV_AP0R2_EL1', 'Interrupt Controller Virtual Active Priorities Group 0 Register 2' ),
'S3_0_c12_c8_7' : ( 'ICC_AP0R3_EL1', 'Interrupt Controller Active Priorities Group 0 Register 3' ),
'S3_0_c12_c8_7' : ( 'ICV_AP0R3_EL1', 'Interrupt Controller Virtual Active Priorities Group 0 Register 3' ),
'S3_0_c12_c9_0' : ( 'ICC_AP1R0_EL1', 'Interrupt Controller Active Priorities Group 1 Register 0' ),
'S3_0_c12_c9_0' : ( 'ICV_AP1R0_EL1', 'Interrupt Controller Virtual Active Priorities Group 1 Register 0' ),
'S3_0_c12_c9_1' : ( 'ICC_AP1R1_EL1', 'Interrupt Controller Active Priorities Group 1 Register 1' ),
'S3_0_c12_c9_1' : ( 'ICV_AP1R1_EL1', 'Interrupt Controller Virtual Active Priorities Group 1 Register 1' ),
'S3_0_c12_c9_2' : ( 'ICC_AP1R2_EL1', 'Interrupt Controller Active Priorities Group 1 Register 2' ),
'S3_0_c12_c9_2' : ( 'ICV_AP1R2_EL1', 'Interrupt Controller Virtual Active Priorities Group 1 Register 2' ),
'S3_0_c12_c9_3' : ( 'ICC_AP1R3_EL1', 'Interrupt Controller Active Priorities Group 1 Register 3' ),
'S3_0_c12_c9_3' : ( 'ICV_AP1R3_EL1', 'Interrupt Controller Virtual Active Priorities Group 1 Register 3' ),
'S3_0_c12_c11_1' : ( 'ICC_DIR_EL1', 'Interrupt Controller Deactivate Interrupt Register' ),
'S3_0_c12_c11_1' : ( 'ICV_DIR_EL1', 'Interrupt Controller Deactivate Virtual Interrupt Register' ),
'S3_0_c12_c11_3' : ( 'ICC_RPR_EL1', 'Interrupt Controller Running Priority Register' ),
'S3_0_c12_c11_3' : ( 'ICV_RPR_EL1', 'Interrupt Controller Virtual Running Priority Register' ),
'S3_0_c12_c11_5' : ( 'ICC_SGI1R_EL1', 'Interrupt Controller Software Generated Interrupt Group 1 Register' ),
'S3_0_c12_c11_6' : ( 'ICC_ASGI1R_EL1', 'Interrupt Controller Alias Software Generated Interrupt Group 1 Register' ),
'S3_0_c12_c11_7' : ( 'ICC_SGI0R_EL1', 'Interrupt Controller Software Generated Interrupt Group 0 Register' ),
'S3_0_c12_c12_0' : ( 'ICC_IAR1_EL1', 'Interrupt Controller Interrupt Acknowledge Register 1' ),
'S3_0_c12_c12_0' : ( 'ICV_IAR1_EL1', 'Interrupt Controller Virtual Interrupt Acknowledge Register 1' ),
'S3_0_c12_c12_1' : ( 'ICC_EOIR1_EL1', 'Interrupt Controller End Of Interrupt Register 1' ),
'S3_0_c12_c12_1' : ( 'ICV_EOIR1_EL1', 'Interrupt Controller Virtual End Of Interrupt Register 1' ),
'S3_0_c12_c12_2' : ( 'ICC_HPPIR1_EL1', 'Interrupt Controller Highest Priority Pending Interrupt Register 1' ),
'S3_0_c12_c12_2' : ( 'ICV_HPPIR1_EL1', 'Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1' ),
'S3_0_c12_c12_3' : ( 'ICC_BPR1_EL1', 'Interrupt Controller Binary Point Register 1' ),
'S3_0_c12_c12_3' : ( 'ICV_BPR1_EL1', 'Interrupt Controller Virtual Binary Point Register 1' ),
'S3_0_c12_c12_4' : ( 'ICC_CTLR_EL1', 'Interrupt Controller Control Register (EL1)' ),
'S3_0_c12_c12_4' : ( 'ICV_CTLR_EL1', 'Interrupt Controller Virtual Control Register' ),
'S3_0_c12_c12_5' : ( 'ICC_SRE_EL1', 'Interrupt Controller System Register Enable register (EL1)' ),
'S3_0_c12_c12_6' : ( 'ICC_IGRPEN0_EL1', 'Interrupt Controller Interrupt Group 0 Enable register' ),
'S3_0_c12_c12_6' : ( 'ICV_IGRPEN0_EL1', 'Interrupt Controller Virtual Interrupt Group 0 Enable register' ),
'S3_0_c12_c12_7' : ( 'ICC_IGRPEN1_EL1', 'Interrupt Controller Interrupt Group 1 Enable register' ),
'S3_0_c12_c12_7' : ( 'ICV_IGRPEN1_EL1', 'Interrupt Controller Virtual Interrupt Group 1 Enable register' ),
'S3_0_c13_c0_1' : ( 'CONTEXTIDR_EL1', 'Context ID Register (EL1)' ),
'S3_0_c13_c0_4' : ( 'TPIDR_EL1', 'EL1 Software Thread ID Register' ),
'S3_0_c13_c0_7' : ( 'SCXTNUM_EL1', 'EL1 Read/Write Software Context Number' ),
'S3_0_c14_c1_0' : ( 'CNTKCTL_EL1', 'Counter-timer Kernel Control register' ),
'S3_1_c0_c0_0' : ( 'CCSIDR_EL1', 'Current Cache Size ID Register' ),
'S3_1_c0_c0_1' : ( 'CLIDR_EL1', 'Cache Level ID Register' ),
'S3_1_c0_c0_2' : ( 'CCSIDR2_EL1', 'Current Cache Size ID Register 2' ),
'S3_1_c0_c0_4' : ( 'GMID_EL1', ' Multiple tag transfer ID register' ),
'S3_1_c0_c0_7' : ( 'AIDR_EL1', 'Auxiliary ID Register' ),
'S3_2_c0_c0_0' : ( 'CSSELR_EL1', 'Cache Size Selection Register' ),
'S3_3_c0_c0_1' : ( 'CTR_EL0', 'Cache Type Register' ),
'S3_3_c0_c0_7' : ( 'DCZID_EL0', 'Data Cache Zero ID register' ),
'S3_3_c2_c4_0' : ( 'RNDR', 'Random Number' ),
'S3_3_c2_c4_1' : ( 'RNDRRS', 'Reseeded Random Number' ),
'S3_3_c4_c2_0' : ( 'NZCV', 'Condition Flags' ),
'S3_3_c4_c2_1' : ( 'DAIF', 'Interrupt Mask Bits' ),
'S3_3_c4_c2_5' : ( 'DIT', 'Data Independent Timing' ),
'S3_3_c4_c2_6' : ( 'SSBS', 'Speculative Store Bypass Safe' ),
'S3_3_c4_c2_7' : ( 'TCO', 'Tag Check Override' ),
'S3_3_c4_c4_0' : ( 'FPCR', 'Floating-point Control Register' ),
'S3_3_c4_c4_1' : ( 'FPSR', 'Floating-point Status Register' ),
'S3_3_c4_c5_0' : ( 'DSPSR_EL0', 'Debug Saved Program Status Register' ),
'S3_3_c4_c5_1' : ( 'DLR_EL0', 'Debug Link Register' ),
'S3_3_c9_c12_0' : ( 'PMCR_EL0', 'Performance Monitors Control Register' ),
'S3_3_c9_c12_1' : ( 'PMCNTENSET_EL0', 'Performance Monitors Count Enable Set register' ),
'S3_3_c9_c12_2' : ( 'PMCNTENCLR_EL0', 'Performance Monitors Count Enable Clear register' ),
'S3_3_c9_c12_3' : ( 'PMOVSCLR_EL0', 'Performance Monitors Overflow Flag Status Clear Register' ),
'S3_3_c9_c12_4' : ( 'PMSWINC_EL0', 'Performance Monitors Software Increment register' ),
'S3_3_c9_c12_5' : ( 'PMSELR_EL0', 'Performance Monitors Event Counter Selection Register' ),
'S3_3_c9_c12_6' : ( 'PMCEID0_EL0', 'Performance Monitors Common Event Identification register 0' ),
'S3_3_c9_c12_7' : ( 'PMCEID1_EL0', 'Performance Monitors Common Event Identification register 1' ),
'S3_3_c9_c13_0' : ( 'PMCCNTR_EL0', 'Performance Monitors Cycle Count Register' ),
'S3_3_c9_c13_1' : ( 'PMXEVTYPER_EL0', 'Performance Monitors Selected Event Type Register' ),
'S3_3_c9_c13_2' : ( 'PMXEVCNTR_EL0', 'Performance Monitors Selected Event Count Register' ),
'S3_3_c9_c14_0' : ( 'PMUSERENR_EL0', 'Performance Monitors User Enable Register' ),
'S3_3_c9_c14_3' : ( 'PMOVSSET_EL0', 'Performance Monitors Overflow Flag Status Set register' ),
'S3_3_c13_c0_2' : ( 'TPIDR_EL0', 'EL0 Read/Write Software Thread ID Register' ),
'S3_3_c13_c0_3' : ( 'TPIDRRO_EL0', 'EL0 Read-Only Software Thread ID Register' ),
'S3_3_c13_c0_7' : ( 'SCXTNUM_EL0', 'EL0 Read/Write Software Context Number' ),
'S3_3_c13_c2_0' : ( 'AMCR_EL0', 'Activity Monitors Control Register' ),
'S3_3_c13_c2_1' : ( 'AMCFGR_EL0', 'Activity Monitors Configuration Register' ),
'S3_3_c13_c2_2' : ( 'AMCGCR_EL0', 'Activity Monitors Counter Group Configuration Register' ),
'S3_3_c13_c2_3' : ( 'AMUSERENR_EL0', 'Activity Monitors User Enable Register' ),
'S3_3_c13_c2_4' : ( 'AMCNTENCLR0_EL0', 'Activity Monitors Count Enable Clear Register 0' ),
'S3_3_c13_c2_5' : ( 'AMCNTENSET0_EL0', 'Activity Monitors Count Enable Set Register 0' ),
'S3_3_c13_c2_6' : ( 'AMCG1IDR_EL0', 'Activity Monitors Counter Group 1 Identification Register' ),
'S3_3_c13_c3_0' : ( 'AMCNTENCLR1_EL0', 'Activity Monitors Count Enable Clear Register 1' ),
'S3_3_c13_c3_1' : ( 'AMCNTENSET1_EL0', 'Activity Monitors Count Enable Set Register 1' ),
'S3_3_c13_c4_0' : ( 'AMEVCNTR00_EL0', 'Activity Monitors Event Counter Register 0 0' ),
'S3_3_c13_c4_1' : ( 'AMEVCNTR01_EL0', 'Activity Monitors Event Counter Register 0 1' ),
'S3_3_c13_c4_2' : ( 'AMEVCNTR02_EL0', 'Activity Monitors Event Counter Register 0 2' ),
'S3_3_c13_c4_3' : ( 'AMEVCNTR03_EL0', 'Activity Monitors Event Counter Register 0 3' ),
'S3_3_c13_c4_4' : ( 'AMEVCNTR04_EL0', 'Activity Monitors Event Counter Register 0 4' ),
'S3_3_c13_c4_5' : ( 'AMEVCNTR05_EL0', 'Activity Monitors Event Counter Register 0 5' ),
'S3_3_c13_c4_6' : ( 'AMEVCNTR06_EL0', 'Activity Monitors Event Counter Register 0 6' ),
'S3_3_c13_c4_7' : ( 'AMEVCNTR07_EL0', 'Activity Monitors Event Counter Register 0 7' ),
'S3_3_c13_c5_0' : ( 'AMEVCNTR08_EL0', 'Activity Monitors Event Counter Register 0 8' ),
'S3_3_c13_c5_1' : ( 'AMEVCNTR09_EL0', 'Activity Monitors Event Counter Register 0 9' ),
'S3_3_c13_c5_2' : ( 'AMEVCNTR010_EL0', 'Activity Monitors Event Counter Register 0 10' ),
'S3_3_c13_c5_3' : ( 'AMEVCNTR011_EL0', 'Activity Monitors Event Counter Register 0 11' ),
'S3_3_c13_c5_4' : ( 'AMEVCNTR012_EL0', 'Activity Monitors Event Counter Register 0 12' ),
'S3_3_c13_c5_5' : ( 'AMEVCNTR013_EL0', 'Activity Monitors Event Counter Register 0 13' ),
'S3_3_c13_c5_6' : ( 'AMEVCNTR014_EL0', 'Activity Monitors Event Counter Register 0 14' ),
'S3_3_c13_c5_7' : ( 'AMEVCNTR015_EL0', 'Activity Monitors Event Counter Register 0 15' ),
'S3_3_c13_c6_0' : ( 'AMEVTYPER00_EL0', 'Activity Monitors Event Type Register 0 0' ),
'S3_3_c13_c6_1' : ( 'AMEVTYPER01_EL0', 'Activity Monitors Event Type Register 0 1' ),
'S3_3_c13_c6_2' : ( 'AMEVTYPER02_EL0', 'Activity Monitors Event Type Register 0 2' ),
'S3_3_c13_c6_3' : ( 'AMEVTYPER03_EL0', 'Activity Monitors Event Type Register 0 3' ),
'S3_3_c13_c6_4' : ( 'AMEVTYPER04_EL0', 'Activity Monitors Event Type Register 0 4' ),
'S3_3_c13_c6_5' : ( 'AMEVTYPER05_EL0', 'Activity Monitors Event Type Register 0 5' ),
'S3_3_c13_c6_6' : ( 'AMEVTYPER06_EL0', 'Activity Monitors Event Type Register 0 6' ),
'S3_3_c13_c6_7' : ( 'AMEVTYPER07_EL0', 'Activity Monitors Event Type Register 0 7' ),
'S3_3_c13_c7_0' : ( 'AMEVTYPER08_EL0', 'Activity Monitors Event Type Register 0 8' ),
'S3_3_c13_c7_1' : ( 'AMEVTYPER09_EL0', 'Activity Monitors Event Type Register 0 9' ),
'S3_3_c13_c7_2' : ( 'AMEVTYPER010_EL0', 'Activity Monitors Event Type Register 0 10' ),
'S3_3_c13_c7_3' : ( 'AMEVTYPER011_EL0', 'Activity Monitors Event Type Register 0 11' ),
'S3_3_c13_c7_4' : ( 'AMEVTYPER012_EL0', 'Activity Monitors Event Type Register 0 12' ),
'S3_3_c13_c7_5' : ( 'AMEVTYPER013_EL0', 'Activity Monitors Event Type Register 0 13' ),
'S3_3_c13_c7_6' : ( 'AMEVTYPER014_EL0', 'Activity Monitors Event Type Register 0 14' ),
'S3_3_c13_c7_7' : ( 'AMEVTYPER015_EL0', 'Activity Monitors Event Type Register 0 15' ),
'S3_3_c13_c12_0' : ( 'AMEVCNTR10_EL0', 'Activity Monitors Event Counter Register 1 0' ),
'S3_3_c13_c12_1' : ( 'AMEVCNTR11_EL0', 'Activity Monitors Event Counter Register 1 1' ),
'S3_3_c13_c12_2' : ( 'AMEVCNTR12_EL0', 'Activity Monitors Event Counter Register 1 2' ),
'S3_3_c13_c12_3' : ( 'AMEVCNTR13_EL0', 'Activity Monitors Event Counter Register 1 3' ),
'S3_3_c13_c12_4' : ( 'AMEVCNTR14_EL0', 'Activity Monitors Event Counter Register 1 4' ),
'S3_3_c13_c12_5' : ( 'AMEVCNTR15_EL0', 'Activity Monitors Event Counter Register 1 5' ),
'S3_3_c13_c12_6' : ( 'AMEVCNTR16_EL0', 'Activity Monitors Event Counter Register 1 6' ),
'S3_3_c13_c12_7' : ( 'AMEVCNTR17_EL0', 'Activity Monitors Event Counter Register 1 7' ),
'S3_3_c13_c13_0' : ( 'AMEVCNTR18_EL0', 'Activity Monitors Event Counter Register 1 8' ),
'S3_3_c13_c13_1' : ( 'AMEVCNTR19_EL0', 'Activity Monitors Event Counter Register 1 9' ),
'S3_3_c13_c13_2' : ( 'AMEVCNTR110_EL0', 'Activity Monitors Event Counter Register 1 10' ),
'S3_3_c13_c13_3' : ( 'AMEVCNTR111_EL0', 'Activity Monitors Event Counter Register 1 11' ),
'S3_3_c13_c13_4' : ( 'AMEVCNTR112_EL0', 'Activity Monitors Event Counter Register 1 12' ),
'S3_3_c13_c13_5' : ( 'AMEVCNTR113_EL0', 'Activity Monitors Event Counter Register 1 13' ),
'S3_3_c13_c13_6' : ( 'AMEVCNTR114_EL0', 'Activity Monitors Event Counter Register 1 14' ),
'S3_3_c13_c13_7' : ( 'AMEVCNTR115_EL0', 'Activity Monitors Event Counter Register 1 15' ),
'S3_3_c13_c14_0' : ( 'AMEVTYPER10_EL0', 'Activity Monitors Event Type Register 1 0' ),
'S3_3_c13_c14_1' : ( 'AMEVTYPER11_EL0', 'Activity Monitors Event Type Register 1 1' ),
'S3_3_c13_c14_2' : ( 'AMEVTYPER12_EL0', 'Activity Monitors Event Type Register 1 2' ),
'S3_3_c13_c14_3' : ( 'AMEVTYPER13_EL0', 'Activity Monitors Event Type Register 1 3' ),
'S3_3_c13_c14_4' : ( 'AMEVTYPER14_EL0', 'Activity Monitors Event Type Register 1 4' ),
'S3_3_c13_c14_5' : ( 'AMEVTYPER15_EL0', 'Activity Monitors Event Type Register 1 5' ),
'S3_3_c13_c14_6' : ( 'AMEVTYPER16_EL0', 'Activity Monitors Event Type Register 1 6' ),
'S3_3_c13_c14_7' : ( 'AMEVTYPER17_EL0', 'Activity Monitors Event Type Register 1 7' ),
'S3_3_c13_c15_0' : ( 'AMEVTYPER18_EL0', 'Activity Monitors Event Type Register 1 8' ),
'S3_3_c13_c15_1' : ( 'AMEVTYPER19_EL0', 'Activity Monitors Event Type Register 1 9' ),
'S3_3_c13_c15_2' : ( 'AMEVTYPER110_EL0', 'Activity Monitors Event Type Register 1 10' ),
'S3_3_c13_c15_3' : ( 'AMEVTYPER111_EL0', 'Activity Monitors Event Type Register 1 11' ),
'S3_3_c13_c15_4' : ( 'AMEVTYPER112_EL0', 'Activity Monitors Event Type Register 1 12' ),
'S3_3_c13_c15_5' : ( 'AMEVTYPER113_EL0', 'Activity Monitors Event Type Register 1 13' ),
'S3_3_c13_c15_6' : ( 'AMEVTYPER114_EL0', 'Activity Monitors Event Type Register 1 14' ),
'S3_3_c13_c15_7' : ( 'AMEVTYPER115_EL0', 'Activity Monitors Event Type Register 1 15' ),
'S3_3_c14_c0_0' : ( 'CNTFRQ_EL0', 'Counter-timer Frequency register' ),
'S3_3_c14_c0_1' : ( 'CNTPCT_EL0', 'Counter-timer Physical Count register' ),
'S3_3_c14_c0_2' : ( 'CNTVCT_EL0', 'Counter-timer Virtual Count register' ),
'S3_3_c14_c0_5' : ( 'CNTPCTSS_EL0', 'Counter-timer Self-Synchronized Physical Count register' ),
'S3_3_c14_c0_6' : ( 'CNTVCTSS_EL0', 'Counter-timer Self-Synchronized Virtual Count register' ),
'S3_3_c14_c2_0' : ( 'CNTP_TVAL_EL0', 'Counter-timer Physical Timer TimerValue register' ),
'S3_3_c14_c2_1' : ( 'CNTP_CTL_EL0', 'Counter-timer Physical Timer Control register' ),
'S3_3_c14_c2_2' : ( 'CNTP_CVAL_EL0', 'Counter-timer Physical Timer CompareValue register' ),
'S3_3_c14_c3_0' : ( 'CNTV_TVAL_EL0', 'Counter-timer Virtual Timer TimerValue register' ),
'S3_3_c14_c3_1' : ( 'CNTV_CTL_EL0', 'Counter-timer Virtual Timer Control register' ),
'S3_3_c14_c3_2' : ( 'CNTV_CVAL_EL0', 'Counter-timer Virtual Timer CompareValue register' ),
'S3_3_c14_c8_0' : ( 'PMEVCNTR0_EL0', 'Performance Monitors Event Count Register 0' ),
'S3_3_c14_c8_1' : ( 'PMEVCNTR1_EL0', 'Performance Monitors Event Count Register 1' ),
'S3_3_c14_c8_2' : ( 'PMEVCNTR2_EL0', 'Performance Monitors Event Count Register 2' ),
'S3_3_c14_c8_3' : ( 'PMEVCNTR3_EL0', 'Performance Monitors Event Count Register 3' ),
'S3_3_c14_c8_4' : ( 'PMEVCNTR4_EL0', 'Performance Monitors Event Count Register 4' ),
'S3_3_c14_c8_5' : ( 'PMEVCNTR5_EL0', 'Performance Monitors Event Count Register 5' ),
'S3_3_c14_c8_6' : ( 'PMEVCNTR6_EL0', 'Performance Monitors Event Count Register 6' ),
'S3_3_c14_c8_7' : ( 'PMEVCNTR7_EL0', 'Performance Monitors Event Count Register 7' ),
'S3_3_c14_c9_0' : ( 'PMEVCNTR8_EL0', 'Performance Monitors Event Count Register 8' ),
'S3_3_c14_c9_1' : ( 'PMEVCNTR9_EL0', 'Performance Monitors Event Count Register 9' ),
'S3_3_c14_c9_2' : ( 'PMEVCNTR10_EL0', 'Performance Monitors Event Count Register 10' ),
'S3_3_c14_c9_3' : ( 'PMEVCNTR11_EL0', 'Performance Monitors Event Count Register 11' ),
'S3_3_c14_c9_4' : ( 'PMEVCNTR12_EL0', 'Performance Monitors Event Count Register 12' ),
'S3_3_c14_c9_5' : ( 'PMEVCNTR13_EL0', 'Performance Monitors Event Count Register 13' ),
'S3_3_c14_c9_6' : ( 'PMEVCNTR14_EL0', 'Performance Monitors Event Count Register 14' ),
'S3_3_c14_c9_7' : ( 'PMEVCNTR15_EL0', 'Performance Monitors Event Count Register 15' ),
'S3_3_c14_c10_0' : ( 'PMEVCNTR16_EL0', 'Performance Monitors Event Count Register 16' ),
'S3_3_c14_c10_1' : ( 'PMEVCNTR17_EL0', 'Performance Monitors Event Count Register 17' ),
'S3_3_c14_c10_2' : ( 'PMEVCNTR18_EL0', 'Performance Monitors Event Count Register 18' ),
'S3_3_c14_c10_3' : ( 'PMEVCNTR19_EL0', 'Performance Monitors Event Count Register 19' ),
'S3_3_c14_c10_4' : ( 'PMEVCNTR20_EL0', 'Performance Monitors Event Count Register 20' ),
'S3_3_c14_c10_5' : ( 'PMEVCNTR21_EL0', 'Performance Monitors Event Count Register 21' ),
'S3_3_c14_c10_6' : ( 'PMEVCNTR22_EL0', 'Performance Monitors Event Count Register 22' ),
'S3_3_c14_c10_7' : ( 'PMEVCNTR23_EL0', 'Performance Monitors Event Count Register 23' ),
'S3_3_c14_c11_0' : ( 'PMEVCNTR24_EL0', 'Performance Monitors Event Count Register 24' ),
'S3_3_c14_c11_1' : ( 'PMEVCNTR25_EL0', 'Performance Monitors Event Count Register 25' ),
'S3_3_c14_c11_2' : ( 'PMEVCNTR26_EL0', 'Performance Monitors Event Count Register 26' ),
'S3_3_c14_c11_3' : ( 'PMEVCNTR27_EL0', 'Performance Monitors Event Count Register 27' ),
'S3_3_c14_c11_4' : ( 'PMEVCNTR28_EL0', 'Performance Monitors Event Count Register 28' ),
'S3_3_c14_c11_5' : ( 'PMEVCNTR29_EL0', 'Performance Monitors Event Count Register 29' ),
'S3_3_c14_c11_6' : ( 'PMEVCNTR30_EL0', 'Performance Monitors Event Count Register 30' ),
'S3_3_c14_c11_7' : ( 'PMEVCNTR31_EL0', 'Performance Monitors Event Count Register 31' ),
'S3_3_c14_c12_0' : ( 'PMEVTYPER0_EL0', 'Performance Monitors Event Type Register 0' ),
'S3_3_c14_c12_1' : ( 'PMEVTYPER1_EL0', 'Performance Monitors Event Type Register 1' ),
'S3_3_c14_c12_2' : ( 'PMEVTYPER2_EL0', 'Performance Monitors Event Type Register 2' ),
'S3_3_c14_c12_3' : ( 'PMEVTYPER3_EL0', 'Performance Monitors Event Type Register 3' ),
'S3_3_c14_c12_4' : ( 'PMEVTYPER4_EL0', 'Performance Monitors Event Type Register 4' ),
'S3_3_c14_c12_5' : ( 'PMEVTYPER5_EL0', 'Performance Monitors Event Type Register 5' ),
'S3_3_c14_c12_6' : ( 'PMEVTYPER6_EL0', 'Performance Monitors Event Type Register 6' ),
'S3_3_c14_c12_7' : ( 'PMEVTYPER7_EL0', 'Performance Monitors Event Type Register 7' ),
'S3_3_c14_c13_0' : ( 'PMEVTYPER8_EL0', 'Performance Monitors Event Type Register 8' ),
'S3_3_c14_c13_1' : ( 'PMEVTYPER9_EL0', 'Performance Monitors Event Type Register 9' ),
'S3_3_c14_c13_2' : ( 'PMEVTYPER10_EL0', 'Performance Monitors Event Type Register 10' ),
'S3_3_c14_c13_3' : ( 'PMEVTYPER11_EL0', 'Performance Monitors Event Type Register 11' ),
'S3_3_c14_c13_4' : ( 'PMEVTYPER12_EL0', 'Performance Monitors Event Type Register 12' ),
'S3_3_c14_c13_5' : ( 'PMEVTYPER13_EL0', 'Performance Monitors Event Type Register 13' ),
'S3_3_c14_c13_6' : ( 'PMEVTYPER14_EL0', 'Performance Monitors Event Type Register 14' ),
'S3_3_c14_c13_7' : ( 'PMEVTYPER15_EL0', 'Performance Monitors Event Type Register 15' ),
'S3_3_c14_c14_0' : ( 'PMEVTYPER16_EL0', 'Performance Monitors Event Type Register 16' ),
'S3_3_c14_c14_1' : ( 'PMEVTYPER17_EL0', 'Performance Monitors Event Type Register 17' ),
'S3_3_c14_c14_2' : ( 'PMEVTYPER18_EL0', 'Performance Monitors Event Type Register 18' ),
'S3_3_c14_c14_3' : ( 'PMEVTYPER19_EL0', 'Performance Monitors Event Type Register 19' ),
'S3_3_c14_c14_4' : ( 'PMEVTYPER20_EL0', 'Performance Monitors Event Type Register 20' ),
'S3_3_c14_c14_5' : ( 'PMEVTYPER21_EL0', 'Performance Monitors Event Type Register 21' ),
'S3_3_c14_c14_6' : ( 'PMEVTYPER22_EL0', 'Performance Monitors Event Type Register 22' ),
'S3_3_c14_c14_7' : ( 'PMEVTYPER23_EL0', 'Performance Monitors Event Type Register 23' ),
'S3_3_c14_c15_0' : ( 'PMEVTYPER24_EL0', 'Performance Monitors Event Type Register 24' ),
'S3_3_c14_c15_1' : ( 'PMEVTYPER25_EL0', 'Performance Monitors Event Type Register 25' ),
'S3_3_c14_c15_2' : ( 'PMEVTYPER26_EL0', 'Performance Monitors Event Type Register 26' ),
'S3_3_c14_c15_3' : ( 'PMEVTYPER27_EL0', 'Performance Monitors Event Type Register 27' ),
'S3_3_c14_c15_4' : ( 'PMEVTYPER28_EL0', 'Performance Monitors Event Type Register 28' ),
'S3_3_c14_c15_5' : ( 'PMEVTYPER29_EL0', 'Performance Monitors Event Type Register 29' ),
'S3_3_c14_c15_6' : ( 'PMEVTYPER30_EL0', 'Performance Monitors Event Type Register 30' ),
'S3_3_c14_c15_7' : ( 'PMCCFILTR_EL0', 'Performance Monitors Cycle Count Filter Register' ),
'S3_3_c14_c15_7' : ( 'PMEVTYPER31_EL0', 'Performance Monitors Event Type Register 31' ),
'S3_4_c0_c0_0' : ( 'VPIDR_EL2', 'Virtualization Processor ID Register' ),
'S3_4_c0_c0_5' : ( 'VMPIDR_EL2', 'Virtualization Multiprocessor ID Register' ),
'S3_4_c1_c0_0' : ( 'SCTLR_EL2', 'System Control Register (EL2)' ),
'S3_4_c1_c0_1' : ( 'ACTLR_EL2', 'Auxiliary Control Register (EL2)' ),
'S3_4_c1_c1_0' : ( 'HCR_EL2', 'Hypervisor Configuration Register' ),
'S3_4_c1_c1_1' : ( 'MDCR_EL2', 'Monitor Debug Configuration Register (EL2)' ),
'S3_4_c1_c1_2' : ( 'CPTR_EL2', 'Architectural Feature Trap Register (EL2)' ),
'S3_4_c1_c1_3' : ( 'HSTR_EL2', 'Hypervisor System Trap Register' ),
'S3_4_c1_c1_4' : ( 'HFGRTR_EL2', 'Hypervisor Fine-Grained Read Trap Register' ),
'S3_4_c1_c1_5' : ( 'HFGWTR_EL2', 'Hypervisor Fine-Grained Write Trap Register' ),
'S3_4_c1_c1_6' : ( 'HFGITR_EL2', 'Hypervisor Fine-Grained Instruction Trap Register' ),
'S3_4_c1_c1_7' : ( 'HACR_EL2', 'Hypervisor Auxiliary Control Register' ),
'S3_4_c1_c2_0' : ( 'ZCR_EL2', 'SVE Control Register for EL2' ),
'S3_4_c1_c2_1' : ( 'TRFCR_EL2', 'Trace Filter Control Register (EL2)' ),
'S3_4_c1_c3_1' : ( 'SDER32_EL2', 'AArch32 Secure Debug Enable Register' ),
'S3_4_c2_c0_0' : ( 'TTBR0_EL2', 'Translation Table Base Register 0 (EL2)' ),
'S3_4_c2_c0_1' : ( 'TTBR1_EL2', 'Translation Table Base Register 1 (EL2)' ),
'S3_4_c2_c0_2' : ( 'TCR_EL2', 'Translation Control Register (EL2)' ),
'S3_4_c2_c1_0' : ( 'VTTBR_EL2', 'Virtualization Translation Table Base Register' ),
'S3_4_c2_c1_2' : ( 'VTCR_EL2', 'Virtualization Translation Control Register' ),
'S3_4_c2_c2_0' : ( 'VNCR_EL2', 'Virtual Nested Control Register' ),
'S3_4_c2_c6_0' : ( 'VSTTBR_EL2', 'Virtualization Secure Translation Table Base Register' ),
'S3_4_c2_c6_2' : ( 'VSTCR_EL2', 'Virtualization Secure Translation Control Register' ),
'S3_4_c3_c0_0' : ( 'DACR32_EL2', 'Domain Access Control Register' ),
'S3_4_c3_c1_4' : ( 'HDFGRTR_EL2', 'Hypervisor Debug Fine-Grained Read Trap Register' ),
'S3_4_c3_c1_5' : ( 'HDFGWTR_EL2', 'Hypervisor Debug Fine-Grained Write Trap Register' ),
'S3_4_c3_c1_6' : ( 'HAFGRTR_EL2', 'Hypervisor Activity Monitors Fine-Grained Read Trap Register' ),
'S3_4_c4_c0_0' : ( 'SPSR_EL2', 'Saved Program Status Register (EL2)' ),
'S3_4_c4_c0_1' : ( 'ELR_EL2', 'Exception Link Register (EL2)' ),
'S3_4_c4_c1_0' : ( 'SP_EL1', 'Stack Pointer (EL1)' ),
'S3_4_c4_c3_0' : ( 'SPSR_irq', 'Saved Program Status Register (IRQ mode)' ),
'S3_4_c4_c3_1' : ( 'SPSR_abt', 'Saved Program Status Register (Abort mode)' ),
'S3_4_c4_c3_2' : ( 'SPSR_und', 'Saved Program Status Register (Undefined mode)' ),
'S3_4_c4_c3_3' : ( 'SPSR_fiq', 'Saved Program Status Register (FIQ mode)' ),
'S3_4_c5_c0_1' : ( 'IFSR32_EL2', 'Instruction Fault Status Register (EL2)' ),
'S3_4_c5_c1_0' : ( 'AFSR0_EL2', 'Auxiliary Fault Status Register 0 (EL2)' ),
'S3_4_c5_c1_1' : ( 'AFSR1_EL2', 'Auxiliary Fault Status Register 1 (EL2)' ),
'S3_4_c5_c2_0' : ( 'ESR_EL2', 'Exception Syndrome Register (EL2)' ),
'S3_4_c5_c2_3' : ( 'VSESR_EL2', 'Virtual SError Exception Syndrome Register' ),
'S3_4_c5_c3_0' : ( 'FPEXC32_EL2', 'Floating-Point Exception Control register' ),
'S3_4_c5_c6_0' : ( 'TFSR_EL2', 'Tag Fault Status Register (EL2)' ),
'S3_4_c6_c0_0' : ( 'FAR_EL2', 'Fault Address Register (EL2)' ),
'S3_4_c6_c0_4' : ( 'HPFAR_EL2', 'Hypervisor IPA Fault Address Register' ),
'S3_4_c9_c9_0' : ( 'PMSCR_EL2', 'Statistical Profiling Control Register (EL2)' ),
'S3_4_c10_c2_0' : ( 'MAIR_EL2', 'Memory Attribute Indirection Register (EL2)' ),
'S3_4_c10_c3_0' : ( 'AMAIR_EL2', 'Auxiliary Memory Attribute Indirection Register (EL2)' ),
'S3_4_c10_c4_0' : ( 'MPAMHCR_EL2', 'MPAM Hypervisor Control Register (EL2)' ),
'S3_4_c10_c4_1' : ( 'MPAMVPMV_EL2', 'MPAM Virtual Partition Mapping Valid Register' ),
'S3_4_c10_c5_0' : ( 'MPAM2_EL2', 'MPAM2 Register (EL2)' ),
'S3_4_c10_c6_0' : ( 'MPAMVPM0_EL2', 'MPAM Virtual PARTID Mapping Register 0' ),
'S3_4_c10_c6_1' : ( 'MPAMVPM1_EL2', 'MPAM Virtual PARTID Mapping Register 1' ),
'S3_4_c10_c6_2' : ( 'MPAMVPM2_EL2', 'MPAM Virtual PARTID Mapping Register 2' ),
'S3_4_c10_c6_3' : ( 'MPAMVPM3_EL2', 'MPAM Virtual PARTID Mapping Register 3' ),
'S3_4_c10_c6_4' : ( 'MPAMVPM4_EL2', 'MPAM Virtual PARTID Mapping Register 4' ),
'S3_4_c10_c6_5' : ( 'MPAMVPM5_EL2', 'MPAM Virtual PARTID Mapping Register 5' ),
'S3_4_c10_c6_6' : ( 'MPAMVPM6_EL2', 'MPAM Virtual PARTID Mapping Register 6' ),
'S3_4_c10_c6_7' : ( 'MPAMVPM7_EL2', 'MPAM Virtual PARTID Mapping Register 7' ),
'S3_4_c12_c0_0' : ( 'VBAR_EL2', 'Vector Base Address Register (EL2)' ),
'S3_4_c12_c0_1' : ( 'RVBAR_EL2', 'Reset Vector Base Address Register (if EL3 not implemented)' ),
'S3_4_c12_c0_2' : ( 'RMR_EL2', 'Reset Management Register (EL2)' ),
'S3_4_c12_c1_1' : ( 'VDISR_EL2', 'Virtual Deferred Interrupt Status Register' ),
'S3_4_c12_c8_0' : ( 'ICH_AP0R0_EL2', 'Interrupt Controller Hyp Active Priorities Group 0 Register 0' ),
'S3_4_c12_c8_1' : ( 'ICH_AP0R1_EL2', 'Interrupt Controller Hyp Active Priorities Group 0 Register 1' ),
'S3_4_c12_c8_2' : ( 'ICH_AP0R2_EL2', 'Interrupt Controller Hyp Active Priorities Group 0 Register 2' ),
'S3_4_c12_c8_3' : ( 'ICH_AP0R3_EL2', 'Interrupt Controller Hyp Active Priorities Group 0 Register 3' ),
'S3_4_c12_c9_0' : ( 'ICH_AP1R0_EL2', 'Interrupt Controller Hyp Active Priorities Group 1 Register 0' ),
'S3_4_c12_c9_1' : ( 'ICH_AP1R1_EL2', 'Interrupt Controller Hyp Active Priorities Group 1 Register 1' ),
'S3_4_c12_c9_2' : ( 'ICH_AP1R2_EL2', 'Interrupt Controller Hyp Active Priorities Group 1 Register 2' ),
'S3_4_c12_c9_3' : ( 'ICH_AP1R3_EL2', 'Interrupt Controller Hyp Active Priorities Group 1 Register 3' ),
'S3_4_c12_c9_5' : ( 'ICC_SRE_EL2', 'Interrupt Controller System Register Enable register (EL2)' ),
'S3_4_c12_c11_0' : ( 'ICH_HCR_EL2', 'Interrupt Controller Hyp Control Register' ),
'S3_4_c12_c11_1' : ( 'ICH_VTR_EL2', 'Interrupt Controller VGIC Type Register' ),
'S3_4_c12_c11_2' : ( 'ICH_MISR_EL2', 'Interrupt Controller Maintenance Interrupt State Register' ),
'S3_4_c12_c11_3' : ( 'ICH_EISR_EL2', 'Interrupt Controller End of Interrupt Status Register' ),
'S3_4_c12_c11_5' : ( 'ICH_ELRSR_EL2', 'Interrupt Controller Empty List Register Status Register' ),
'S3_4_c12_c11_7' : ( 'ICH_VMCR_EL2', 'Interrupt Controller Virtual Machine Control Register' ),
'S3_4_c12_c12_0' : ( 'ICH_LR0_EL2', 'Interrupt Controller List Register 0' ),
'S3_4_c12_c12_1' : ( 'ICH_LR1_EL2', 'Interrupt Controller List Register 1' ),
'S3_4_c12_c12_2' : ( 'ICH_LR2_EL2', 'Interrupt Controller List Register 2' ),
'S3_4_c12_c12_3' : ( 'ICH_LR3_EL2', 'Interrupt Controller List Register 3' ),
'S3_4_c12_c12_4' : ( 'ICH_LR4_EL2', 'Interrupt Controller List Register 4' ),
'S3_4_c12_c12_5' : ( 'ICH_LR5_EL2', 'Interrupt Controller List Register 5' ),
'S3_4_c12_c12_6' : ( 'ICH_LR6_EL2', 'Interrupt Controller List Register 6' ),
'S3_4_c12_c12_7' : ( 'ICH_LR7_EL2', 'Interrupt Controller List Register 7' ),
'S3_4_c12_c13_0' : ( 'ICH_LR8_EL2', 'Interrupt Controller List Register 8' ),
'S3_4_c12_c13_1' : ( 'ICH_LR9_EL2', 'Interrupt Controller List Register 9' ),
'S3_4_c12_c13_2' : ( 'ICH_LR10_EL2', 'Interrupt Controller List Register 10' ),
'S3_4_c12_c13_3' : ( 'ICH_LR11_EL2', 'Interrupt Controller List Register 11' ),
'S3_4_c12_c13_4' : ( 'ICH_LR12_EL2', 'Interrupt Controller List Register 12' ),
'S3_4_c12_c13_5' : ( 'ICH_LR13_EL2', 'Interrupt Controller List Register 13' ),
'S3_4_c12_c13_6' : ( 'ICH_LR14_EL2', 'Interrupt Controller List Register 14' ),
'S3_4_c12_c13_7' : ( 'ICH_LR15_EL2', 'Interrupt Controller List Register 15' ),
'S3_4_c13_c0_1' : ( 'CONTEXTIDR_EL2', 'Context ID Register (EL2)' ),
'S3_4_c13_c0_2' : ( 'TPIDR_EL2', 'EL2 Software Thread ID Register' ),
'S3_4_c13_c0_7' : ( 'SCXTNUM_EL2', 'EL2 Read/Write Software Context Number' ),
'S3_4_c13_c8_0' : ( 'AMEVCNTVOFF00_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 0' ),
'S3_4_c13_c8_1' : ( 'AMEVCNTVOFF01_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 1' ),
'S3_4_c13_c8_2' : ( 'AMEVCNTVOFF02_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 2' ),
'S3_4_c13_c8_3' : ( 'AMEVCNTVOFF03_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 3' ),
'S3_4_c13_c8_4' : ( 'AMEVCNTVOFF04_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 4' ),
'S3_4_c13_c8_5' : ( 'AMEVCNTVOFF05_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 5' ),
'S3_4_c13_c8_6' : ( 'AMEVCNTVOFF06_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 6' ),
'S3_4_c13_c8_7' : ( 'AMEVCNTVOFF07_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 7' ),
'S3_4_c13_c9_0' : ( 'AMEVCNTVOFF08_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 8' ),
'S3_4_c13_c9_1' : ( 'AMEVCNTVOFF09_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 9' ),
'S3_4_c13_c9_2' : ( 'AMEVCNTVOFF010_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 10' ),
'S3_4_c13_c9_3' : ( 'AMEVCNTVOFF011_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 11' ),
'S3_4_c13_c9_4' : ( 'AMEVCNTVOFF012_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 12' ),
'S3_4_c13_c9_5' : ( 'AMEVCNTVOFF013_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 13' ),
'S3_4_c13_c9_6' : ( 'AMEVCNTVOFF014_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 14' ),
'S3_4_c13_c9_7' : ( 'AMEVCNTVOFF015_EL2', 'Activity Monitors Event Counter Virtual Offset Register 0 15' ),
'S3_4_c13_c10_0' : ( 'AMEVCNTVOFF10_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 0' ),
'S3_4_c13_c10_1' : ( 'AMEVCNTVOFF11_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 1' ),
'S3_4_c13_c10_2' : ( 'AMEVCNTVOFF12_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 2' ),
'S3_4_c13_c10_3' : ( 'AMEVCNTVOFF13_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 3' ),
'S3_4_c13_c10_4' : ( 'AMEVCNTVOFF14_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 4' ),
'S3_4_c13_c10_5' : ( 'AMEVCNTVOFF15_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 5' ),
'S3_4_c13_c10_6' : ( 'AMEVCNTVOFF16_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 6' ),
'S3_4_c13_c10_7' : ( 'AMEVCNTVOFF17_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 7' ),
'S3_4_c13_c11_0' : ( 'AMEVCNTVOFF18_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 8' ),
'S3_4_c13_c11_1' : ( 'AMEVCNTVOFF19_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 9' ),
'S3_4_c13_c11_2' : ( 'AMEVCNTVOFF110_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 10' ),
'S3_4_c13_c11_3' : ( 'AMEVCNTVOFF111_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 11' ),
'S3_4_c13_c11_4' : ( 'AMEVCNTVOFF112_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 12' ),
'S3_4_c13_c11_5' : ( 'AMEVCNTVOFF113_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 13' ),
'S3_4_c13_c11_6' : ( 'AMEVCNTVOFF114_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 14' ),
'S3_4_c13_c11_7' : ( 'AMEVCNTVOFF115_EL2', 'Activity Monitors Event Counter Virtual Offset Register 1 15' ),
'S3_4_c14_c0_3' : ( 'CNTVOFF_EL2', 'Counter-timer Virtual Offset register' ),
'S3_4_c14_c0_6' : ( 'CNTPOFF_EL2', 'Counter-timer Physical Offset register' ),
'S3_4_c14_c1_0' : ( 'CNTHCTL_EL2', 'Counter-timer Hypervisor Control register' ),
'S3_4_c14_c2_0' : ( 'CNTHP_TVAL_EL2', 'Counter-timer Physical Timer TimerValue register (EL2)' ),
'S3_4_c14_c2_1' : ( 'CNTHP_CTL_EL2', 'Counter-timer Hypervisor Physical Timer Control register' ),
'S3_4_c14_c2_2' : ( 'CNTHP_CVAL_EL2', 'Counter-timer Physical Timer CompareValue register (EL2)' ),
'S3_4_c14_c3_0' : ( 'CNTHV_TVAL_EL2', 'Counter-timer Virtual Timer TimerValue Register (EL2)' ),
'S3_4_c14_c3_1' : ( 'CNTHV_CTL_EL2', 'Counter-timer Virtual Timer Control register (EL2)' ),
'S3_4_c14_c3_2' : ( 'CNTHV_CVAL_EL2', 'Counter-timer Virtual Timer CompareValue register (EL2)' ),
'S3_4_c14_c4_0' : ( 'CNTHVS_TVAL_EL2', 'Counter-timer Secure Virtual Timer TimerValue register (EL2)' ),
'S3_4_c14_c4_1' : ( 'CNTHVS_CTL_EL2', 'Counter-timer Secure Virtual Timer Control register (EL2)' ),
'S3_4_c14_c4_2' : ( 'CNTHVS_CVAL_EL2', 'Counter-timer Secure Virtual Timer CompareValue register (EL2)' ),
'S3_4_c14_c5_0' : ( 'CNTHPS_TVAL_EL2', 'Counter-timer Secure Physical Timer TimerValue register (EL2)' ),
'S3_4_c14_c5_1' : ( 'CNTHPS_CTL_EL2', 'Counter-timer Secure Physical Timer Control register (EL2)' ),
'S3_4_c14_c5_2' : ( 'CNTHPS_CVAL_EL2', 'Counter-timer Secure Physical Timer CompareValue register (EL2)' ),
'S3_6_c1_c0_0' : ( 'SCTLR_EL3', 'System Control Register (EL3)' ),
'S3_6_c1_c0_1' : ( 'ACTLR_EL3', 'Auxiliary Control Register (EL3)' ),
'S3_6_c1_c1_0' : ( 'SCR_EL3', 'Secure Configuration Register' ),
'S3_6_c1_c1_1' : ( 'SDER32_EL3', 'AArch32 Secure Debug Enable Register' ),
'S3_6_c1_c1_2' : ( 'CPTR_EL3', 'Architectural Feature Trap Register (EL3)' ),
'S3_6_c1_c2_0' : ( 'ZCR_EL3', 'SVE Control Register for EL3' ),
'S3_6_c1_c3_1' : ( 'MDCR_EL3', 'Monitor Debug Configuration Register (EL3)' ),
'S3_6_c2_c0_0' : ( 'TTBR0_EL3', 'Translation Table Base Register 0 (EL3)' ),
'S3_6_c2_c0_2' : ( 'TCR_EL3', 'Translation Control Register (EL3)' ),
'S3_6_c4_c0_0' : ( 'SPSR_EL3', 'Saved Program Status Register (EL3)' ),
'S3_6_c4_c0_1' : ( 'ELR_EL3', 'Exception Link Register (EL3)' ),
'S3_6_c4_c1_0' : ( 'SP_EL2', 'Stack Pointer (EL2)' ),
'S3_6_c5_c1_0' : ( 'AFSR0_EL3', 'Auxiliary Fault Status Register 0 (EL3)' ),
'S3_6_c5_c1_1' : ( 'AFSR1_EL3', 'Auxiliary Fault Status Register 1 (EL3)' ),
'S3_6_c5_c2_0' : ( 'ESR_EL3', 'Exception Syndrome Register (EL3)' ),
'S3_6_c5_c6_0' : ( 'TFSR_EL3', 'Tag Fault Status Register (EL3)' ),
'S3_6_c6_c0_0' : ( 'FAR_EL3', 'Fault Address Register (EL3)' ),
'S3_6_c10_c2_0' : ( 'MAIR_EL3', 'Memory Attribute Indirection Register (EL3)' ),
'S3_6_c10_c3_0' : ( 'AMAIR_EL3', 'Auxiliary Memory Attribute Indirection Register (EL3)' ),
'S3_6_c10_c5_0' : ( 'MPAM3_EL3', 'MPAM3 Register (EL3)' ),
'S3_6_c12_c0_0' : ( 'VBAR_EL3', 'Vector Base Address Register (EL3)' ),
'S3_6_c12_c0_1' : ( 'RVBAR_EL3', 'Reset Vector Base Address Register (if EL3 implemented)' ),
'S3_6_c12_c0_2' : ( 'RMR_EL3', 'Reset Management Register (EL3)' ),
'S3_6_c12_c12_4' : ( 'ICC_CTLR_EL3', 'Interrupt Controller Control Register (EL3)' ),
'S3_6_c12_c12_5' : ( 'ICC_SRE_EL3', 'Interrupt Controller System Register Enable register (EL3)' ),
'S3_6_c12_c12_7' : ( 'ICC_IGRPEN1_EL3', 'Interrupt Controller Interrupt Group 1 Enable register (EL3)' ),
'S3_6_c13_c0_2' : ( 'TPIDR_EL3', 'EL3 Software Thread ID Register' ),
'S3_6_c13_c0_7' : ( 'SCXTNUM_EL3', 'EL3 Read/Write Software Context Number' ),
'S3_7_c14_c2_0' : ( 'CNTPS_TVAL_EL1', 'Counter-timer Physical Secure Timer TimerValue register' ),
'S3_7_c14_c2_1' : ( 'CNTPS_CTL_EL1', 'Counter-timer Physical Secure Timer Control register' ),
'S3_7_c14_c2_2' : ( 'CNTPS_CVAL_EL1', 'Counter-timer Physical Secure Timer CompareValue register' ),
# Apple system registers.
'S3_0_c15_c0_0' : ( 'HID0', '' ),
'S3_0_c15_c0_1' : ( 'EHID0', '' ),
'S3_0_c15_c1_0' : ( 'HID1', '' ),
'S3_0_c15_c1_1' : ( 'EHID1', '' ),
'S3_0_c15_c2_0' : ( 'HID2', '' ),
'S3_0_c15_c2_1' : ( 'EHID2', '' ),
'S3_0_c15_c3_0' : ( 'HID3', '' ),
'S3_0_c15_c3_1' : ( 'EHID3', '' ),
'S3_0_c15_c4_0' : ( 'HID4', '' ),
'S3_0_c15_c4_1' : ( 'EHID4', '' ),
'S3_0_c15_c5_0' : ( 'HID5', '' ),
'S3_0_c15_c5_1' : ( 'EHID5', '' ),
'S3_0_c15_c6_0' : ( 'HID6', '' ),
'S3_0_c15_c7_0' : ( 'HID7', '' ),
'S3_0_c15_c8_0' : ( 'HID8', '' ),
'S3_0_c15_c9_0' : ( 'HID9', '' ),
'S3_0_c15_c10_0' : ( 'HID10', '' ),
'S3_0_c15_c10_1' : ( 'EHID10', '' ),
'S3_0_c15_c11_0' : ( 'HID11', '' ),
'S3_0_c15_c11_1' : ( 'EHID11', '' ),
'S3_0_c15_c14_0' : ( 'HID13', '' ),
'S3_0_c15_c15_0' : ( 'HID14', '' ),
'S3_0_c15_c15_2' : ( 'HID16', '' ),
'S3_1_c15_c0_0' : ( 'PMCR0', 'Apple Performance Monitor Control Register 0' ),
'S3_1_c15_c1_0' : ( 'PMCR1', 'Controls which execution modes count events' ),
'S3_1_c15_c2_0' : ( 'PMCR2', 'Controls watchpoint registers' ),
'S3_1_c15_c3_0' : ( 'PMCR3', 'Controls breakpoints and address matching' ),
'S3_1_c15_c4_0' : ( 'PMCR4', 'Controls opcode matching' ),
'S3_1_c15_c5_0' : ( 'PMESR0', '' ),
'S3_1_c15_c6_0' : ( 'PMESR1', '' ),
'S3_1_c15_c7_0' : ( 'OPMAT0', '' ),
'S3_1_c15_c8_0' : ( 'OPMAT1', '' ),
'S3_1_c15_c9_0' : ( 'OPMSK0', '' ),
'S3_1_c15_c10_0' : ( 'OPMSK1', '' ),
'S3_1_c15_c13_0' : ( 'PMSR', '' ),
'S3_2_c15_c0_0' : ( 'PMC0', '48-bit cycles counter' ),
'S3_2_c15_c1_0' : ( 'PMC1', '48-bit instructions counter' ),
'S3_2_c15_c2_0' : ( 'PMC2', '' ),
'S3_2_c15_c3_0' : ( 'PMC3', '' ),
'S3_2_c15_c4_0' : ( 'PMC4', '' ),
'S3_2_c15_c5_0' : ( 'PMC5', '' ),
'S3_2_c15_c6_0' : ( 'PMC6', '' ),
'S3_2_c15_c7_0' : ( 'PMC7', '' ),
'S3_2_c15_c9_0' : ( 'PMC8', '' ),
'S3_2_c15_c10_0' : ( 'PMC9', '' ),
'S3_2_c15_c12_0' : ( 'PMTRHLD6', '' ),
'S3_2_c15_c13_0' : ( 'PMTRHLD4', '' ),
'S3_2_c15_c14_0' : ( 'PMTRHLD2', '' ),
'S3_2_c15_c15_0' : ( 'PMMMAP', '' ),
'S3_3_c15_c0_0' : ( 'LSU_ERR_STS', 'LSU Error Status' ),
'S3_3_c15_c1_0' : ( 'LSU_ERR_CTL', 'LSU Error Control' ),
'S3_3_c15_c2_0' : ( 'E_LSU_ERR_STS', 'LSU Error Status' ),
'S3_3_c15_c7_0' : ( 'L2_CRAMCONFIG', 'LSU Error Status' ),
'S3_3_c15_c8_0' : ( 'LLC_ERR_STS', 'LLC Error Status' ),
'S3_3_c15_c8_1' : ( 'L2E_ERR_STS', '' ),
'S3_3_c15_c9_0' : ( 'LLC_ERR_ADR', 'LLC Error Address' ),
'S3_3_c15_c9_1' : ( 'L2E_ERR_ADR', '' ),
'S3_3_c15_c10_0' : ( 'LLC_ERR_INF', 'LLC Error Information' ),
'S3_3_c15_c10_1' : ( 'L2E_ERR_INF', '' ),
'S3_4_c15_c0_0' : ( 'FED_ERR_STS', 'FED Error Status' ),
'S3_4_c15_c0_2' : ( 'E_FED_ERR_STS', 'FED Error Status' ),
'S3_4_c15_c0_4' : ( 'APCTL_EL1/MIGSTS', '' ),
'S3_4_c15_c1_0' : ( 'KERNELKEYLO_EL1', 'PAC Kernel Key (bits[63:0])' ),
'S3_4_c15_c1_1' : ( 'KERNELKEYHI_EL1', 'PAC Kernel Key (bits[127:64])' ),
'S3_4_c15_c1_2' : ( 'VMSA_LOCK_EL1', 'VMSA Lock' ),
'S3_4_c15_c1_6' : ( 'CTRR_B_UPR_EL1', 'CTRR Upper Range B' ),
'S3_4_c15_c1_7' : ( 'CTRR_B_LWR_EL1', 'CTRR Lower Range B' ),
'S3_4_c15_c2_0' : ( 'APRR_0', 'APRR Register 0' ),
'S3_4_c15_c2_1' : ( 'APRR_1', 'APRR Register 1' ),
'S3_4_c15_c2_2' : ( 'CTRR_LOCK', 'CTRR Lockdown' ),
'S3_4_c15_c2_3' : ( 'CTRR_A_LWR_EL1', 'CTRR Lower Range' ),
'S3_4_c15_c2_4' : ( 'CTRR_A_UPR_EL1', 'CTRR Upper Range' ),
'S3_4_c15_c2_5' : ( 'CTRR_CTL_EL1', 'CTRR Control Register' ),
'S3_4_c15_c2_6' : ( 'APRR_6', 'APRR Register 6' ),
'S3_4_c15_c2_7' : ( 'APRR_7', 'APRR Register 7' ),
'S3_4_c15_c11_0' : ( 'ACC_CTRR_A_LWR_EL2', '' ),
'S3_4_c15_c11_1' : ( 'ACC_CTRR_A_UPR_EL2', '' ),
'S3_4_c15_c11_4' : ( 'ACC_CTRR_CTL_EL2', '' ),
'S3_4_c15_c11_5' : ( 'ACC_CTRR_LOCK_EL2', '' ),
'S3_5_c15_c0_0' : ( 'IPI_RR_LOCAL', '' ),
'S3_5_c15_c0_1' : ( 'IPI_RR_GLOBAL', '' ),
'S3_5_c15_c0_5' : ( 'DPC_ERR_STS', '' ),
'S3_5_c15_c1_1' : ( 'IPI_SR', '' ),
'S3_5_c15_c3_1' : ( 'IPI_CR', '' ),
'S3_5_c15_c4_0' : ( 'ACC_CFG/CYC_CFG', '' ),
'S3_5_c15_c5_0' : ( 'CYC_OVRD', '' ),
'S3_5_c15_c6_0' : ( 'ACC_OVRD', '' ),
'S3_5_c15_c6_1' : ( 'ACC_EBLK_OVRD', '' ),
'S3_6_c15_c0_0' : ( 'MMU_ERR_STS', 'MMU Error Status' ),
'S3_6_c15_c2_0' : ( 'E_MMU_ERR_STS', 'MMU Error Status' ),
'S3_6_c15_c12_4' : ( 'APSTS_EL1', '' ),
'S3_7_c15_c0_4' : ( 'UPMCR0', 'Controls which counters are enabled and how interrupts are generated for overflows' ),
'S3_7_c15_c0_5' : ( 'UPMC8', '' ),
'S3_7_c15_c1_4' : ( 'UPMESR0', 'Event selection register for counters 0-7' ),
'S3_7_c15_c1_5' : ( 'UPMC9', '' ),
'S3_7_c15_c2_5' : ( 'UPMC10', '' ),
'S3_7_c15_c3_4' : ( 'UPMECM0', 'Event core masks for counters 0-3' ),
'S3_7_c15_c3_5' : ( 'UPMC11', '' ),
'S3_7_c15_c4_4' : ( 'UPMECM1', 'Event core masks for counters 4-7' ),
'S3_7_c15_c4_5' : ( 'UPMC12', '' ),
'S3_7_c15_c5_4' : ( 'UPMPCM', '' ),
'S3_7_c15_c5_5' : ( 'UPMC13', '' ),
'S3_7_c15_c6_4' : ( 'UPMSR', '' ),
'S3_7_c15_c6_5' : ( 'UPMC14', '' ),
'S3_7_c15_c7_4' : ( 'UPMC0', '' ),
'S3_7_c15_c7_5' : ( 'UPMC15', '' ),
'S3_7_c15_c8_4' : ( 'UPMC1', '' ),
'S3_7_c15_c8_5' : ( 'UPMECM2', 'Event core masks for counters 8-11' ),
'S3_7_c15_c9_4' : ( 'UPMC2', '' ),
'S3_7_c15_c9_5' : ( 'UPMECM3', 'Event core masks for counters 12-15' ),
'S3_7_c15_c10_4' : ( 'UPMC3', '' ),
'S3_7_c15_c11_4' : ( 'UPMC4', '' ),
'S3_7_c15_c11_5' : ( 'UPMESR1', 'Event selection register for counters 8-15' ),
'S3_7_c15_c12_4' : ( 'UPMC5', '' ),
'S3_7_c15_c13_4' : ( 'UPMC6', '' ),
'S3_7_c15_c14_4' : ( 'UPMC7', '' ),
}
def add_comment(ea, comment):
existing = idc.get_cmt(ea, 0)
if not existing:
idc.set_cmt(ea, comment, 0)
def unknown(ea, category, value):
print('{:x} UNKNOWN {} {}'.format(ea, category, value))
def pstate_insn(ea, op2, CRm):
pstate = PSTATE_ACCESS.get(op2)
if pstate:
add_comment(ea, '{} {:#x}'.format(pstate, CRm))
else:
unknown(ea, 'PSTATE', '{:b}'.format(op2))
def sysreg_insn(ea, L, op0, op1, CRn, CRm, op2):
sr = 'S{}_{}_c{}_c{}_{}'.format(op0, op1, CRn, CRm, op2)
reg = SYSTEM_REGISTERS.get(sr)
if reg:
name = reg[0]
description = reg[1]
direction = '<' if L else '>' # L=0 => Transfer to system register.
comment = '[{}] {}'.format(direction, name)
if description:
comment += ' {}'.format(description)
add_comment(ea, comment)
else:
unknown(ea, 'SYSREG', sr)
def process_msr(ea, mnem):
insn = idc.get_wide_dword(ea)
assert(insn & 0xFFC00000 == 0xD5000000)
L = (insn >> 21) & 0x1
op0 = (insn >> 19) & 0x3
op1 = (insn >> 16) & 0x7
CRn = (insn >> 12) & 0xf
CRm = (insn >> 8) & 0xf
op2 = (insn >> 5) & 0x7
Rt = (insn >> 0) & 0x1f
if L == 0b0 and op0 == 0b00 and CRn == 0b0100 and Rt == 0b11111:
pstate_insn(ea, op2, CRm)
elif op0 != 0b00:
sysreg_insn(ea, L, op0, op1, CRn, CRm, op2)
else:
unknown(ea, mnem, '{:08x}'.format(insn))
SYSTEM_INSTRUCTIONS = {
'MSR' : process_msr,
'MRS' : process_msr,
'SYS' : process_msr,
}
def arm64_sysregs_ios():
for ea in idautils.Heads():
mnem = idc.print_insn_mnem(ea)
process_func = SYSTEM_INSTRUCTIONS.get(mnem)
if process_func:
process_func(ea, mnem)
arm64_sysregs_ios()
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment