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Researching and Lecturing

Stefan Marr smarr

Researching and Lecturing
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One thing that surprises newer programmers is that the older 8-bit microcomputers from the 70s and 80s were designed to run at the speed of random memory access to DRAM and ROM. The C64 was released in 1982 when I was born and its 6502 CPU ran at 1 MHz (give or take depending on NTSC vs PAL). It had a 2-stage pipelined design that was designed to overlap execution and instruction fetch for the current and next instruction. Cycle counting was simple to understand and master since it was based almost entirely on the number of memory accesses (1 cycle each), with a 1-cycle penalty for taken branches because of the pipelined instruction fetch for the next sequential instruction. So, the entire architecture was based on keeping the memory subsystem busy 100% of the time by issuing a read or write every cycle. One-byte instructions with no memory operands like INX still take the minimum 2 cycles per instruction and end up redundantly issuing the same memory request two cycles in a row.

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Last active November 25, 2016 04:53
Truffle/Graal at SPLASH'16

Truffle and Graal-related Presentations at SPLASH'16


  • [AST Specialisation and Partial Evaluation for Easy High-Performance Metaprogramming][7] ([PDF][7pdf])
    Chris Seaton, Oracle Labs
    Sun 30 Oct 2016, 11:30-12:00 - Meta'16