genearete chunk size of each slab class

slabtbl.v

`include "slabtbl.vh"

module slabtbl (
	input	CLK,
	input	RST,
	input	request,
	output	reg complate
);

parameter integer maxslabsize = `PAGE_SIZE / `GROW_FACTOR;

reg[`MAX_CHUNK_WIDTH-1:0]  slabclass[`MAX_NSLABS_WIDTH-1:0];
reg[`MAX_NSLABS_WIDTH-1:0] id    = 0; // tmp id
reg[`MAX_NSLABS_WIDTH-1:0] maxid = 0;

function [`MAX_CHUNK_WIDTH-1:0] chunksize;
	input   integer id;
	integer i;
	begin
	   if (id == 0)
			chunksize = 48 + 48;
		else begin
			chunksize = slabclass[id-1] * `GROW_FACTOR;
			if (chunksize % 8)
				chunksize = chunksize + 8 - (chunksize % 8);
			$display("chunksize: %d, MAX: %d", chunksize, maxslabsize);
		end
	end
endfunction

always @(posedge CLK) begin
	if (RST) begin
		complate <= 0;
		id       <= 0;
		maxid    <= 0;
	end else begin
		if (request) begin
			$display("maxid: %d, id: %d, slabclass[id]: %d", maxid, id, slabclass[id][`MAX_CHUNK_WIDTH-1:0]);
			if (slabclass[id][`MAX_CHUNK_WIDTH-1:0] > maxslabsize) begin
				maxid    <= id;
				complate <= 1;
			end else if (!maxid)
				id <= id + 1;
		end
	end
end

always @(id)
	slabclass[id][`MAX_CHUNK_WIDTH-1:0] <= chunksize(id);

endmodule

slabtbl.vh

`define		dbg            1 // debug mode

`define		PAGE_SIZE          1048576 // byte
`define		NSLABS             42
`define		GROW_FACTOR        1.25
`define		MIN_CHUNK_SIZE     96
`define		MAX_HASHKEY_WIDTH  11     // 250 words
`define		MAX_VALUE_WIDTH     32    // 32 bit
`define		MAX_HASH_WIDTH     32     // 32 bit
`define		MAX_CHUNK_WIDTH    32     // 32 bit
`define		MAX_NSLABS_WIDTH   256    // 256

tb_slabtbl.v

`include "slabtbl.vh"

module sim();

reg    tb_request;

wire   CLK;
wire   RST;
wire   tb_complate;

clock clock (
  .CLK(CLK),
	.RST(RST)
);

slabtbl slabtbl (
	.CLK(CLK),
	.RST(RST),
	.request(tb_request),
	.complate(tb_complate)
);

initial begin
        $dumpfile("slabtbl.vcd");
        $dumpvars(0, sim.slabtbl);
end

initial begin
	#100 tb_request = 1;
	#1000	$finish();
end

always @(posedge CLK) begin
	if (RST)
		tb_request   <= 0;
	else begin
		if (tb_complate) begin
			tb_request <= 0;
//			$display("class0: %d", slabtbl.slabclass[0][`MAX_CHUNK_WIDTH-1:0]);
		end
	end
end

endmodule // sim()

module clock (
	output reg CLK,
	output reg RST
);

initial CLK = 0;
initial RST = 0;
always #(`STEP / 2) begin
	CLK <= ~CLK;
	RST <= 0;
end

endmodule // clock()