Compiling MBDK model

gistfile1.txt

Warning: The model 'adac250_test' does not have continuous states, hence Simulink is using the solver 'VariableStepDiscrete'
instead of solver 'ode45'. You can disable this diagnostic by explicitly specifying a discrete solver in the solver tab of the
Configuration Parameters dialog, or by setting the 'Automatic solver parameter selection' diagnostic to 'none' in the Diagnostics
tab of the Configuration Parameters dialog 
> In C:\Xilinx\14.7\ISE_DS\ISE\sysgen\bin\nt64\xlCompileGenerateMdl.p>xlCompileGenerateMdl at 203
  In C:\Xilinx\14.7\ISE_DS\ISE\sysgen\bin\nt64\xlGenerateButton.p>xlGenerateButton at 325
  In C:\Xilinx\14.7\ISE_DS\ISE\sysgen\bin\nt64\xlSysgenGUI.p>xlSysgenGUI at 51 
Warning: Inconsistent sample times. Sample time ([0, 0]) of signal driving input port 1 of 'adac250_test/Record Readout/ADC -
A/adac250_0_adc_a_data' differs from the expected sample time (1) at this input port. 
> In C:\Xilinx\14.7\ISE_DS\ISE\sysgen\bin\nt64\xlCompileGenerateMdl.p>xlCompileGenerateMdl at 203
  In C:\Xilinx\14.7\ISE_DS\ISE\sysgen\bin\nt64\xlGenerateButton.p>xlGenerateButton at 325
  In C:\Xilinx\14.7\ISE_DS\ISE\sysgen\bin\nt64\xlSysgenGUI.p>xlSysgenGUI at 51 
Warning: Inconsistent sample times. Sample time ([0, 0]) of signal driving input port 1 of 'adac250_test/Record Readout/ADC
-B/adac250_0_adc_b_data' differs from the expected sample time (1) at this input port. 
> In C:\Xilinx\14.7\ISE_DS\ISE\sysgen\bin\nt64\xlCompileGenerateMdl.p>xlCompileGenerateMdl at 203
  In C:\Xilinx\14.7\ISE_DS\ISE\sysgen\bin\nt64\xlGenerateButton.p>xlGenerateButton at 325
  In C:\Xilinx\14.7\ISE_DS\ISE\sysgen\bin\nt64\xlSysgenGUI.p>xlSysgenGUI at 51 
Warning: Buffer too small, using bufsize = 100 instead. 
 
Xilinx Platform Studio 
Xilinx EDK 14.7 Build EDK_P.20131013 
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. 
 
XPS% Loading xmp file mbdk_adac250_test.xmp 
 
Overriding IP level properties ... 
INFO:EDK - IPNAME: microblaze, INSTANCE:main_cpu - tcl is overriding PARAMETER 
   C_ENDIANNESS value to 1 - 
   C:\Nutaq\BAS\sdk\fpga\NutaqIPLib\pcores\microblaze_v8_50_c\data\microblaze_v2 
   _1_0.mpd line 198  
INFO:EDK - IPNAME: microblaze, INSTANCE:main_cpu - tcl is overriding PARAMETER 
   C_ICACHE_USE_FSL value to 0 - 
   C:\Nutaq\BAS\sdk\fpga\NutaqIPLib\pcores\microblaze_v8_50_c\data\microblaze_v2 
   _1_0.mpd line 339  
INFO:EDK - IPNAME: microblaze, INSTANCE:main_cpu - tcl is overriding PARAMETER 
   C_DCACHE_USE_FSL value to 0 - 
   C:\Nutaq\BAS\sdk\fpga\NutaqIPLib\pcores\microblaze_v8_50_c\data\microblaze_v2 
   _1_0.mpd line 369  
INFO:EDK - IPNAME: axi_interconnect, INSTANCE:AXI_Lite - tcl is overriding 
   PARAMETER C_BASEFAMILY value to virtex6 - 
   C:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_ 
   06_a\data\axi_interconnect_v2_1_0.mpd line 81  
INFO:EDK - IPNAME: axi2axi_connector, INSTANCE:axi2axi_0x7 - tcl is overriding 
   PARAMETER C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE value to 1 - 
   C:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi2axi_connector_v1 
   _00_a\data\axi2axi_connector_v2_1_0.mpd line 89  
INFO:EDK - IPNAME: axi2axi_connector, INSTANCE:axi2axi_0x7 - tcl is overriding 
   PARAMETER C_INTERCONNECT_S_AXI_READ_ACCEPTANCE value to 1 - 
   C:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi2axi_connector_v1 
   _00_a\data\axi2axi_connector_v2_1_0.mpd line 90  
INFO:EDK - IPNAME: axi2axi_connector, INSTANCE:axi2axi_0x7 - tcl is overriding 
   PARAMETER C_INTERCONNECT_M_AXI_WRITE_ISSUING value to 1 - 
   C:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi2axi_connector_v1 
   _00_a\data\axi2axi_connector_v2_1_0.mpd line 106  
INFO:EDK - IPNAME: axi2axi_connector, INSTANCE:axi2axi_0x7 - tcl is overriding 
   PARAMETER C_INTERCONNECT_M_AXI_READ_ISSUING value to 1 - 
   C:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi2axi_connector_v1 
   _00_a\data\axi2axi_connector_v2_1_0.mpd line 107  
INFO:EDK - IPNAME: axi2axi_connector, INSTANCE:axi2axi_0x7 - tcl is overriding 
   PARAMETER C_M_AXI_PROTOCOL value to AXI4LITE - 
   C:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi2axi_connector_v1 
   _00_a\data\axi2axi_connector_v2_1_0.mpd line 93  
INFO:EDK - IPNAME: axi_interconnect, INSTANCE:AXI_Lite_0x7 - tcl is overriding 
   PARAMETER C_BASEFAMILY value to virtex6 - 
   C:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_ 
   06_a\data\axi_interconnect_v2_1_0.mpd line 81  
INFO:EDK - IPNAME: axi_interconnect, INSTANCE:AXI_Lite_0x8 - tcl is overriding 
   PARAMETER C_BASEFAMILY value to virtex6 - 
   C:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_ 
   06_a\data\axi_interconnect_v2_1_0.mpd line 81  
INFO:EDK - IPNAME: axi_interconnect, INSTANCE:AXI_MM - tcl is overriding 
   PARAMETER C_BASEFAMILY value to virtex6 - 
   C:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_ 
   06_a\data\axi_interconnect_v2_1_0.mpd line 81  
 Device number is xc6vlx240t 
INFO:EDK - IPNAME: axi_ethernet, INSTANCE:eth0 - tcl is overriding PARAMETER 
   C_DEVICE value to xc6vlx240t - 
   C:\Nutaq\BAS\sdk\fpga\NutaqIPLib\pcores\axi_ethernet_v3_01_a\data\axi_etherne 
   t_v2_1_0.mpd line 99  
INFO:EDK - IPNAME: axi_ethernet, INSTANCE:eth0 - tcl is overriding PARAMETER 
   C_USE_GTH value to 0 - 
   C:\Nutaq\BAS\sdk\fpga\NutaqIPLib\pcores\axi_ethernet_v3_01_a\data\axi_etherne 
   t_v2_1_0.mpd line 112  
INFO:EDK - IPNAME: axi_intc, INSTANCE:irq_Ctlr - tcl is overriding PARAMETER 
   C_NUM_INTR_INPUTS value to 9 - 
   C:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_04_a\dat 
   a\axi_intc_v2_1_0.mpd line 85  
 
Computing clock values... 
INFO:EDK - Cannot determine the input clock associated with port : 
   lyt_axi_adac250_0:o_AdcDataClk_p. Clock DRCs will not be performed on this 
   core and cores connected to it.  
INFO:EDK - Cannot determine the input clock associated with port : 
   mbdk_wrapper:o_DesignClk_p. Clock DRCs will not be performed on this core and 
   cores connected to it.  
INFO:EDK - Cannot determine the input clock associated with port : 
   mbdk_wrapper:o_DesignClk_p. Clock DRCs will not be performed on this core and 
   cores connected to it.  
INFO:EDK - Cannot determine the input clock associated with port : 
   mbdk_wrapper:o_DesignClk_p. Clock DRCs will not be performed on this core and 
   cores connected to it.  
INFO:EDK - Cannot determine the input clock associated with port : 
   mbdk_wrapper:o_DesignClk_p. Clock DRCs will not be performed on this core and 
   cores connected to it.  
INFO:EDK - Cannot determine the input clock associated with port : 
   i_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this core and 
   cores connected to it.  
INFO:EDK - Cannot determine the input clock associated with port : 
   d_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this core and 
   cores connected to it.  
INFO:EDK - Cannot determine the input clock associated with port : 
   lyt_axi_adac250_0:o_AdcDataClk_p. Clock DRCs will not be performed on this 
   core and cores connected to it.  
 
Performing IP level DRCs on properties... 
 
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC... 
Address Map for Processor main_cpu 
  (0000000000-0x00007fff) d_bram_ctrl	d_lmb 
  (0000000000-0x00007fff) i_bram_ctrl	i_lmb 
  (0x70000000-0x7000ffff) 
axi_perseus6010_regs	AXI_Lite->axi2axi_0x7->AXI_Lite_0x7 
  (0x71000000-0x7100ffff) axi_emac_rtdex	AXI_Lite->axi2axi_0x7->AXI_Lite_0x7 
  (0x73000000-0x7300ffff) RECORD_PLAYBACK	AXI_Lite->axi2axi_0x7->AXI_Lite_0x7 
  (0x74000000-0x7400ffff) IIC_DDR3	AXI_Lite->axi2axi_0x7->AXI_Lite_0x7 
  (0x75000000-0x75000fff) axi_sysmon_adc_0	AXI_Lite->axi2axi_0x7->AXI_Lite_0x7 
  (0x80000000-0x8000ffff) debug_module	AXI_Lite->axi2axi_0x8->AXI_Lite_0x8 
  (0x81600000-0x8160ffff) axi_iic_FMC	AXI_Lite->axi2axi_0x8->AXI_Lite_0x8 
  (0x81800000-0x8180ffff) irq_Ctlr	AXI_Lite->axi2axi_0x8->AXI_Lite_0x8 
  (0x81c00000-0x81c7ffff) eth0	AXI_Lite->axi2axi_0x8->AXI_Lite_0x8 
  (0x83600000-0x8360ffff) watchdog	AXI_Lite->axi2axi_0x8->AXI_Lite_0x8 
  (0x83c00000-0x83c0ffff) timer	AXI_Lite->axi2axi_0x8->AXI_Lite_0x8 
  (0x84000000-0x8400ffff) fp_uart	AXI_Lite->axi2axi_0x8->AXI_Lite_0x8 
  (0x84600000-0x8460ffff) eDMA	AXI_Lite->axi2axi_0x8->AXI_Lite_0x8 
  (0x85000000-0x8500ffff) lyt_axi_adac250_0	AXI_Lite->axi2axi_0x8->AXI_Lite_0x8 
  (0x90000000-0x97ffffff) DDR3_SDRAM	AXI_MM 
  (0xa0000000-0xa3ffffff) Flash	AXI_Lite 
INFO:EDK - IPNAME: lmb_v10, INSTANCE:i_lmb - tool is overriding PARAMETER 
   C_LMB_NUM_SLAVES value to 1 - 
   C:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data 
   \lmb_v10_v2_1_0.mpd line 82  
INFO:EDK - IPNAME: lmb_v10, INSTANCE:d_lmb - tool is overriding PARAMETER 
   C_LMB_NUM_SLAVES value to 1 - 
   C:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data 
   \lmb_v10_v2_1_0.mpd line 82  
INFO:EDK - IPNAME: bram_block, INSTANCE:bram_block0 - tool is overriding 
   PARAMETER C_MEMSIZE value to 0x8000 - 
   C:\Xilinx\14.7\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\d 
   ata\bram_block_v2_1_0.mpd line 78  
 
Checking platform address map ... 
 
XPS% Evaluating file C:\Nutaq\BAS\sdk\fpga\mbdk\flow\generate_edk_netlist.tcl 
"****************************************************" 
"Creating system netlist for hardware specification.." 
"****************************************************" 
platgen -p xc6vlx240tff1759-1 -lang vhdl -intstyle default -lp C:/Nutaq/BAS/sdk/fpga/   -msg __xps/ise/xmsgprops.lst mbdk_adac250_test.mhs 
 
Release 14.7 - platgen Xilinx EDK 14.7 Build EDK_P.20131013 
 (nt64) 
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. 
 
 
Command Line: platgen -p xc6vlx240tff1759-1 -lang vhdl -intstyle default -lp 
C:/Nutaq/BAS/sdk/fpga/ -msg __xps/ise/xmsgprops.lst mbdk_adac250_test.mhs  
 
ERROR:EDK - INFO:Security:71 - If a license for part 'xc6vlx240t' is available, 
   it will be possible to use 'XPS_TDP' instead of 'XPS'. 
   INFO:Security:61 - The XILINXD_LICENSE_FILE environment variable is not set. 
   INFO:Security:63 - The LM_LICENSE_FILE environment variable is not set. 
   INFO:Security:68 - For more information or for assistance in obtaining  
    a license, please run the Xilinx License Configuration Manager 
          (xlcm or "Manage Xilinx Licenses".) 
   INFO:Security:68a - user is spike, on host SPIKE-WIN7. 
   WARNING:Security:9b - No 'XPS' feature version 2013.10 was available for part 
   'xc6vlx240t'. 
   ERROR:Security:12 - No 'xc6vlx240t' feature version 2013.10 was available 
   (-5), 
        so 'XPS_TDP' may not be used. 
 
   No such feature exists. 
   Feature:       XPS 
   License path:  
   C:/.Xilinx\Xilinx-webpack.lic;C:/.Xilinx\Xilinx.lic;C:\Xilinx\14.7\ISE_DS\ISE 
   /coregen/core_licenses\Xilinx.lic;C:\Xilinx\14.7\ISE_DS\ISE/coregen/core_lice 
   nses\XilinxFree.lic;C:\Xilinx\14.7\ISE_DS\EDK/data/core_licenses\Xilinx.lic; 
   FLEXnet Licensing error:-5,357 
   For further information, refer to the FLEXnet Licensing documentation, 
   available at "www.flexerasoftware.com".No such feature exists. 
   Feature:       xc6vlx240t 
   License path:  
   C:/.Xilinx\Xilinx-webpack.lic;C:/.Xilinx\Xilinx.lic;C:\Xilinx\14.7\ISE_DS\ISE 
   /coregen/core_licenses\Xilinx.lic;C:\Xilinx\14.7\ISE_DS\ISE/coregen/core_lice 
   nses\XilinxFree.lic;C:\Xilinx\14.7\ISE_DS\EDK/data/core_licenses\Xilinx.lic; 
   FLEXnet Licensing error:-5,357 
   For further information, refer to the FLEXnet Licensing documentation, 
   available at "www.flexerasoftware.com". 
ERROR:EDK:440 - platgen failed with errors! 
make: *** [implementation/mbdk_adac250_test_pps_sync_wrapper.ngc] Error 2 
ERROR:EDK -   
   Error while running "make -f mbdk_adac250_test.make netlist". 
>>