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FPGAプログラミング大全 Xilinx編 Basys4 DDR用制約ファイル
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## 出典: | |
## 小林優. FPGAプログラミング大全 Xilinx編, 秀和システム, 2016. | |
## ISBN: 978-4-7980-4753-9 | |
## http://www.shuwasystem.co.jp/support/7980html/4753.html | |
## Nexys4 DDR constraints file | |
## chapter: ? | |
## project: ????? | |
#Clock signal | |
set_property PACKAGE_PIN E3 [get_ports {CLK}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {CLK}] | |
create_clock -add -name sys_clk_pin -period 10.00 \ | |
-waveform {0 5} [get_ports {CLK}] | |
#Reset | |
set_property PACKAGE_PIN M18 [get_ports {RST}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {RST}] | |
##LEDs | |
set_property PACKAGE_PIN H17 [get_ports {LED[0]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}] | |
set_property PACKAGE_PIN K15 [get_ports {LED[1]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}] | |
set_property PACKAGE_PIN J13 [get_ports {LED[2]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}] | |
set_property PACKAGE_PIN N14 [get_ports {LED[3]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}] | |
##Buttons | |
set_property PACKAGE_PIN M17 [get_ports {BTN[0]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {BTN[0]}] | |
set_property PACKAGE_PIN N17 [get_ports {BTN[1]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {BTN[1]}] | |
set_property PACKAGE_PIN P17 [get_ports {BTN[2]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {BTN[2]}] | |
##VGAs | |
set_property PACKAGE_PIN A3 [get_ports {VGA_R[0]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_R[0]}] | |
set_property PACKAGE_PIN B4 [get_ports {VGA_R[1]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_R[1]}] | |
set_property PACKAGE_PIN C5 [get_ports {VGA_R[2]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_R[2]}] | |
set_property PACKAGE_PIN A4 [get_ports {VGA_R[3]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_R[3]}] | |
set_property PACKAGE_PIN C6 [get_ports {VGA_G[0]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_G[0]}] | |
set_property PACKAGE_PIN A5 [get_ports {VGA_G[1]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_G[1]}] | |
set_property PACKAGE_PIN B6 [get_ports {VGA_G[2]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_G[2]}] | |
set_property PACKAGE_PIN A6 [get_ports {VGA_G[3]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_G[3]}] | |
set_property PACKAGE_PIN B7 [get_ports {VGA_B[0]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_B[0]}] | |
set_property PACKAGE_PIN C7 [get_ports {VGA_B[1]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_B[1]}] | |
set_property PACKAGE_PIN D7 [get_ports {VGA_B[2]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_B[2]}] | |
set_property PACKAGE_PIN D8 [get_ports {VGA_B[3]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_B[3]}] | |
set_property PACKAGE_PIN B11 [get_ports {VGA_HS}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_HS}] | |
set_property PACKAGE_PIN B12 [get_ports {VGA_VS}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_VS}] | |
##Uart | |
set_property PACKAGE_PIN C4 [get_ports {RXD}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {RXD}] | |
set_property PACKAGE_PIN D4 [get_ports {TXD}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {TXD}] | |
##Switches | |
set_property PACKAGE_PIN J15 [get_ports {SW[0]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {SW[0]}] | |
set_property PACKAGE_PIN L16 [get_ports {SW[1]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {SW[1]}] | |
set_property PACKAGE_PIN M13 [get_ports {SW[2]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {SW[2]}] | |
set_property PACKAGE_PIN R15 [get_ports {SW[3]}] | |
set_property IOSTANDARD LVCMOS33 [get_ports {SW[3]}] |
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