main.c

#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>

typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
typedef int8_t i8;
typedef int16_t i16;

static bool read_file(const char *path, size_t *size, u8 **data) {
        bool ret = false;

        FILE *input = fopen(path, "r");
        if (!input) {
                return ret;
        }

        if (fseek(input, 0, SEEK_END)) {
                goto cleanup;
        }

        long pos = ftell(input);
        if (pos < 0) {
                goto cleanup;
        }
        *size = pos; // FIXME possible overflow if sizeof(size_t) < sizeof(long)

        if (fseek(input, 0, SEEK_SET)) {
                goto cleanup;
        }

        *data = malloc(*size * sizeof(u8));
        if (!*data) {
                goto cleanup;
        }

        if (fread(*data, sizeof(u8), *size, input) != *size) {
                goto cleanup;
        }

        ret = true;

cleanup:
        fclose(input);

        return ret;
}

struct common_firmware_header {
        u32 size_bytes;
        u32 header_size_bytes;
        u16 header_version_major;
        u16 header_version_minor;
        u16 ip_version_major;
        u16 ip_version_minor;
        u32 ucode_version;
        u32 ucode_size_bytes;
        u32 ucode_array_offset_bytes;
        u32 crc32;
};

static void print_common_firmware_header(struct common_firmware_header hdr) {
        printf("size_bytes: %u\n", hdr.size_bytes);
        printf("header_size_bytes: %u\n", hdr.header_size_bytes);
        printf("header_version_major: %u\n", hdr.header_version_major);
        printf("header_version_minor: %u\n", hdr.header_version_minor);
        printf("ip_version_major: %u\n", hdr.ip_version_major);
        printf("ip_version_minor: %u\n", hdr.ip_version_minor);
        printf("ucode_version: 0x%08x\n", hdr.ucode_version);
        printf("ucode_size_bytes: %u\n", hdr.ucode_size_bytes);
        printf("ucode_array_offset_bytes: %u\n", hdr.ucode_array_offset_bytes);
        printf("crc32: 0x%08x\n", hdr.crc32);
        printf("\n");
}

struct smc_firmware_header_v1_0 {
        struct common_firmware_header header;
        u32 ucode_start_addr;
};

struct smc_firmware_header_v2_0 {
        struct smc_firmware_header_v1_0 v1_0;
        u32 ppt_offset_bytes;
        u32 ppt_size_bytes;
};

static void print_smc_firmware_header_v2_0(struct smc_firmware_header_v2_0 hdr) {
        printf("ucode_start_addr: %u\n", hdr.v1_0.ucode_start_addr);
        printf("ppt_offset_bytes: %u\n", hdr.ppt_offset_bytes);
        printf("ppt_size_bytes: %u\n", hdr.ppt_size_bytes);
        printf("\n");
}

struct smc_soft_pptable_entry {
        u32 id;
        u32 ppt_offset_bytes;
        u32 ppt_size_bytes;
};

static void print_smc_soft_pptable_entry(struct smc_soft_pptable_entry entry) {
        printf("id: %u\n", entry.id);
        printf("ppt_offset_bytes: %u\n", entry.ppt_offset_bytes);
        printf("ppt_size_bytes: %u\n", entry.ppt_size_bytes);
        printf("\n");
}

struct smc_firmware_header_v2_1 {
        struct smc_firmware_header_v1_0 v1_0;
        u32 pptable_count;
        u32 pptable_entry_offset;
};

static void print_smc_firmware_header_v2_1(struct smc_firmware_header_v2_1 hdr) {
        printf("ucode_start_addr: %u\n", hdr.v1_0.ucode_start_addr);
        printf("pptable_count: %u\n", hdr.pptable_count);
        printf("pptable_entry_offset: %u\n", hdr.pptable_entry_offset);
        printf("pptable_entry_offset: 0x%08x\n", hdr.pptable_entry_offset);
        printf("\n");
}

struct atom_common_table_header {
        u16 structuresize;
        u8 format_revision;
        u8 content_revision;
};

const char *const ppclock_names[11] = {
        "gfxclk",
        "vclk",
        "dclk",
        "eclk",
        "socclk",
        "uclk",
        "dcefclk",
        "dispclk",
        "pixclk",
        "phyclk",
        "dtbclk",
};

struct smu_11_0_power_saving_clock_table {
        u8 revision;
        u8 reserve[3];
        u32 count;
        u32 max[16];
        u32 min[16];
} __attribute((packed));

static void print_smu_11_0_power_saving_clock_table(struct smu_11_0_power_saving_clock_table psct) {
        printf("revision: %u\n", psct.revision);
        printf("count: %u\n", psct.count);
        for (u8 i = 0; i < 11; i++) {
                printf("%s: %u - %u\n", ppclock_names[i], psct.min[i], psct.max[i]);
        }
        printf("\n");
}

struct smu_11_0_overdrive_table {
        u8 revision;
        u8 reserve[3];
        u32 feature_count;
        u32 setting_count;
        u8 cap[32];
        u32 max[32];
        u32 min[32];
} __attribute((packed));

static void print_smu_11_0_overdrive_table(struct smu_11_0_overdrive_table ot) {
        printf("revision: %u\n", ot.revision);
        printf("feature_count: %u\n", ot.feature_count);
        printf("setting_count: %u\n", ot.setting_count);
        /*for (u8 i = 0; i < 14; i++) {
                printf("%u\n", ot.cap[i]);
        }
        for (u8 i = 0; i < 30; i++) {
                printf("%u - %u\n", ot.min[i], ot.max[i]);
        }*/
        printf("\n");
}

struct smu_11_0_powerplay_table {
        struct atom_common_table_header header;
        u8 table_revision;
        u16 table_size;
        u32 golden_pp_id;
        u32 golden_revision;
        u16 format_id;
        u32 platform_caps;
        u8 thermal_controller_type;
        u16 small_power_limit1;
        u16 small_power_limit2;
        u16 boost_power_limit;
        u16 od_turbo_power_limit;
        u16 od_power_save_power_limit;
        u16 software_shutdown_temp;
        u16 reserve[6];
        struct smu_11_0_power_saving_clock_table power_saving_clock;
        struct smu_11_0_overdrive_table overdrive_table;
        u32 version;
        u32 features_to_run[2];
        u16 socket_power_limit_ac[4];
        u16 socket_power_limit_ac_tau[4];
        u16 socket_power_limit_dc[4];
        u16 socket_power_limit_dc_tau[4];
        u16 tdc_limit_soc;
        u16 tdc_limit_soc_tau;
        u16 tdc_limit_gfx;
        u16 tdc_limit_gfx_tau;
        u16 temp_limit[10];
        u32 fit_limit;
        u16 ppm_power_limit;
        u16 ppm_temperature_threshold;
        u32 throttler_control_mask;
        u32 fwd_state_mask;
        u16 ulv_voltage_offset_soc;
        u16 ulv_voltage_offset_gfx;
        u8 gcea_link_mgr_idle_threshold;
        u8 padding_rlc_ulv_params[3];
        u8 ulv_smnclk_did;
        u8 ulv_mp1clk_did;
        u8 ulv_gfxclk_bypass;
        u8 padding234;
        u16 min_voltage_ulv_gfx;
        u16 min_voltage_ulv_soc;
        u16 min_voltage_gfx;
        u16 min_voltage_soc;
        u16 max_voltage_gfx;
        u16 max_voltage_soc;
        u16 load_line_resistance_gfx;
        u16 load_line_resistance_soc;
        struct {
                u8 voltage_mode;
                u8 snap_to_discrete;
                u8 num_discrete_level;
                u8 padding;
                struct {
                        u32 m;
                        u32 b;
                } conversion_to_avfs_clk;
                struct {
                        u32 a;
                        u32 b;
                        u32 c;
                } ss_curve;
        } dpm_descriptor[9];
        u16 freq_table_gfx[16];
        u16 freq_table_vclk[8];
        u16 freq_table_dclk[8];
        u16 freq_table_socclk[8];
        u16 freq_table_uclk[4];
        u16 freq_table_dcefclk[8];
        u16 freq_table_dispclk[8];
        u16 freq_table_pixclk[8];
        u16 freq_table_phyclk[8];
        u32 padding_clks[16];
        u16 dc_mode_max_freq[9];
        u16 padding8_clks;
        u8 freq_table_uclk_div[4];
        u16 mp0_clk_freq[2];
        u16 mp0_dpm_voltage[2];
        u16 mem_vddci_voltage[4];
        u16 mem_mvdd_voltage[4];
        u16 gfxclk_fgfxoff_entry;
        u16 gfxclk_finit;
        u16 gfxclk_fidle;
        u16 gfxclk_slewrate;
        u16 gfxclk_fopt;
        u8 padding567[2];
        u16 gfxclk_ds_max_freq;
        u8 gfxclk_source;
        u8 padding456;
        u8 lowest_uclk_reserved_for_ulv;
        u8 padding_uclk[3];
        u8 memory_type;
        u8 memory_channels;
        u8 padding_mem[2];
        u8 pcie_gen_speed[2];
        u8 pcie_lane_count[2];
        u16 lclk_freq[2];
} __attribute__((packed));

static void print_smu_11_0_powerplay_table(struct smu_11_0_powerplay_table pptable) {
        printf("structuresize: %u\n", pptable.header.structuresize);
        printf("format_revision: %u\n", pptable.header.format_revision);
        printf("content_revision: %u\n", pptable.header.content_revision);
        printf("table_revision: %u\n", pptable.table_revision);
        printf("table_size: %u\n", pptable.table_size);
        printf("golden_pp_id: %u\n", pptable.golden_pp_id);
        printf("golden_revision: %u\n", pptable.golden_revision);
        printf("format_id: %u\n", pptable.format_id);
        printf("platform_caps: %u\n", pptable.platform_caps);
        printf("thermal_controller_type: %u\n", pptable.thermal_controller_type);
        printf("small_power_limit1: %u\n", pptable.small_power_limit1);
        printf("small_power_limit2: %u\n", pptable.small_power_limit2);
        printf("boost_power_limit: %u\n", pptable.boost_power_limit);
        printf("od_turbo_power_limit: %u\n", pptable.od_turbo_power_limit);
        printf("od_power_save_power_limit: %u\n", pptable.od_power_save_power_limit);
        printf("software_shutdown_temp: %u\n", pptable.software_shutdown_temp);
        printf("\n");
        print_smu_11_0_power_saving_clock_table(pptable.power_saving_clock);
        print_smu_11_0_overdrive_table(pptable.overdrive_table);
        printf("version: %u\n", pptable.version);
        printf("features_to_run[0]: 0x%08x\n", pptable.features_to_run[0]);
        printf("features_to_run[1]: 0x%08x\n", pptable.features_to_run[1]);
        printf("\n");
        for (u8 i = 0; i < 4; i++) {
                printf("socket_power_limit_ac[%u]: ", i);
                printf("%u W - ", pptable.socket_power_limit_ac[i]);
                printf("%u ms\n", pptable.socket_power_limit_ac_tau[i]);
        }
        for (u8 i = 0; i < 4; i++) {
                printf("socket_power_limit_dc[%u]: ", i);
                printf("%u W - ", pptable.socket_power_limit_dc[i]);
                printf("%u ms\n", pptable.socket_power_limit_dc_tau[i]);
        }
        /*printf("tdc_limit_gfx: %u A\n", pptable.tdc_limit_soc);
        printf("tdc_limit_soc_tau: %u ms\n", pptable.tdc_limit_soc_tau);
        printf("tdc_limit_gfx: %u A\n", pptable.tdc_limit_gfx);
        printf("tdc_limit_gfx_tau: %u ms\n", pptable.tdc_limit_gfx_tau);
        for (u8 i = 0; i < 10; i++) {
                printf("temp_limit[%u]: %u\n", i, pptable.temp_limit[i]);
        }
        printf("fit_limit: %u\n", pptable.fit_limit);
        printf("ppm_power_limit: %u\n", pptable.ppm_power_limit);
        printf("ppm_temperature_threshold: %u\n", pptable.ppm_temperature_threshold);
        printf("throttler_control_mask: 0x%08x\n", pptable.throttler_control_mask);
        printf("fwd_state_mask: %u\n", pptable.fwd_state_mask);*/
        printf("\n");
        /*printf("min_voltage_gfx: %u\n", pptable.min_voltage_gfx);
        printf("min_voltage_soc: %u\n", pptable.min_voltage_soc);
        printf("max_voltage_gfx: %u\n", pptable.max_voltage_gfx);
        printf("max_voltage_soc: %u\n", pptable.max_voltage_soc);
        printf("load_line_resistance_gfx: %u\n", pptable.load_line_resistance_gfx);
        printf("load_line_resistance_soc: %u\n", pptable.load_line_resistance_soc);
        printf("\n");*/
        for (u8 i = 0; i < 2; i++) {
                printf("freq_table_gfx[%u]: %u\n", i, pptable.freq_table_gfx[i]);
        }
        for (u8 i = 0; i < 2; i++) {
                printf("freq_table_vclk[%u]: %u\n", i, pptable.freq_table_vclk[i]);
        }
        for (u8 i = 0; i < 2; i++) {
                printf("freq_table_dclk[%u]: %u\n", i, pptable.freq_table_dclk[i]);
        }
        for (u8 i = 0; i < 2; i++) {
                printf("freq_table_socclk[%u]: %u\n", i, pptable.freq_table_socclk[i]);
        }
        for (u8 i = 0; i < 4; i++) {
                printf("freq_table_uclk[%u]: %u\n", i, pptable.freq_table_uclk[i]);
        }
        for (u8 i = 0; i < 4; i++) {
                printf("%u\n", pptable.freq_table_uclk_div[i]);
        }
        printf("\n");
        printf("memory_type: %u\n", pptable.memory_type);
        printf("memory_channels: %u\n", pptable.memory_channels);
        printf("\n");
        for (u8 i = 0; i < 2; i++) {
                printf("pcie_gen_speed[%u]: %u\n", i, pptable.pcie_gen_speed[i]);
                printf("pcie_lane_count[%u]: %u\n", i, pptable.pcie_lane_count[i]);
        }
        printf("\n");
}

struct smu_11_0_7_overdrive_table {
        u8 revision;
        u8 reserve[3];
        u32 feature_count;
        u32 setting_count;
        u8 cap[32];
        u32 max[64];
        u32 min[64];
        i16 pm_setting[32];
} __attribute((packed));

static void print_smu_11_0_7_overdrive_table(struct smu_11_0_7_overdrive_table ot) {
        printf("revision: %u\n", ot.revision);
        printf("feature_count: %u\n", ot.feature_count);
        printf("setting_count: %u\n", ot.setting_count);
        /*for (u8 i = 0; i < 32; i++) {
                printf("%u\n", ot.cap[i]);
        }
        for (u8 i = 0; i < 64; i++) {
                printf("%u - %u\n", ot.min[i], ot.max[i]);
        }
        for (u8 i = 0; i < 32; i++) {
                printf("%d\n", ot.pm_setting[i]);
        }*/
        printf("\n");
}

struct quadratic_int {
        u32 a;
        u32 b;
        u32 c;
};

struct linear_int {
        u32 m;
        u32 b;
};

struct droop_int {
        u32 a;
        u32 b;
        u32 c;
};

struct smu_11_0_7_powerplay_table {
        struct atom_common_table_header header;
        u8 table_revision;
        u16 table_size;
        u32 golden_pp_id;
        u32 golden_revision;
        u16 format_id;
        u32 platform_caps;
        u8 thermal_controller_type;
        u16 small_power_limit1;
        u16 small_power_limit2;
        u16 boost_power_limit;
        u16 software_shutdown_temp;
        u16 reserve[8];
        struct smu_11_0_power_saving_clock_table power_saving_clock;
        struct smu_11_0_7_overdrive_table overdrive_table;
        u32 version;
        u32 features_to_run[2];
        u16 socket_power_limit_ac[4];
        u16 socket_power_limit_ac_tau[4];
        u16 socket_power_limit_dc[4];
        u16 socket_power_limit_dc_tau[4];
        u16 tdc_limit[2];
        u16 tdc_limit_tau[2];
        u16 temperature_limit[10];
        u32 fit_limit;
        u8 total_power_config;
        u8 total_power_padding[3];
        u32 apcc_plus_residency_limit;
        u16 smnclk_dpm_freq[2];
        u16 smnclk_dpm_voltage[2];
        u32 padding_apcc[4];
        u32 throttler_control_mask;
        u32 fw_d_state_mask;
        u16 ulv_voltage_offset_soc;
        u16 ulv_voltage_offset_gfx;
        u16 min_voltage_ulv_gfx;
        u16 min_voltage_ulv_soc;
        u16 soc_liv_min;
        u16 padding_liv_min;
        u8 gcea_link_mgr_idle_threshold;
        u8 padding_rlc_ulv_params[3];
        u16 min_voltage_gfx;
        u16 min_voltage_soc;
        u16 max_voltage_gfx;
        u16 max_voltage_soc;
        u16 load_line_resistance_gfx;
        u16 load_line_resistance_soc;
        u16 vddgfx_tvmin;
        u16 vddsoc_tvmin;
        u16 vddgfx_vmin_hi_temp;
        u16 vddgfx_vmin_lo_temp;
        u16 vddsoc_vmin_hi_temp;
        u16 vddsoc_vmin_lo_temp;
        u16 vddgfx_tvmin_hysteresis;
        u16 vddsoc_tvmin_hysteresis;
        struct {
                u8 voltage_mode;
                u8 snap_to_discrete;
                u8 num_discrete_level;
                u8 padding;
                struct linear_int conversion_to_avfs_clk;
                struct quadratic_int ss_curve;
                u16 ss_fmin;
                u16 padding_16;
        } dpm_descriptor[13];
        u16 freq_table_gfx[16];
        u16 freq_table_vclk[8];
        u16 freq_table_dclk[8];
        u16 freq_table_socclk[8];
        u16 freq_table_uclk[4];
        u16 freq_table_dcefclk[8];
        u16 freq_table_dispclk[8];
        u16 freq_table_pixclk[8];
        u16 freq_table_phyclk[8];
        u16 freq_table_dtbclk[8];
        u16 freq_table_fclk[8];
        u32 padding_clks[16];
        u32 dc_mode_max_freq[13];
        u8 freq_table_uclk_div[4];
        u16 fclk_boost_freq;
        u16 fclk_param_padding;
        u16 mp0clk_freq[2];
        u16 mp0_dpm_voltage[2];
        u16 mem_vddci_voltage[4];
        u16 mem_mvdd_voltage[4];
        u16 gfxclk_fgfxoff_entry;
        u16 gfxclk_finit;
        u16 gfxclk_fidle;
        u8 gfxclk_source;
        u8 gfxclk_padding;
        u8 gfx_gpo_sub_feature_mask;
        u8 gfx_gpo_enabled_work_policy_mask;
        u8 gfx_gpo_disabled_work_policy_mask;
        u8 gfx_gpo_padding;
        u32 gfx_gpo_voting_allow;
        u32 gfx_gpo_padding32[4];
        u16 gfx_dcs_fopt;
        u16 gfx_fclk_fopt;
        u16 gfx_dcs_uclk_fopt;
        u16 dcs_gfx_off_voltage;
        u16 dcs_min_gfx_off_time;
        u16 dcs_max_gfx_off_time;
        u32 dcs_min_credit_accum;
        u16 dcs_exit_hysteresis;
        u16 dcs_timeout;
        u32 dcs_param_padding[5];
        u16 flops_per_byte_table[16];
        u8 lowest_uclk_reserved_for_ulv;
        u8 padding_mem[3];
        u8 uclk_dpm_pstates[4];
        struct {
                u16 fmin;
                u16 fmax;
        } uclk_dpm_src_freq_range;
        struct {
                u16 fmin;
                u16 fmax;
        } uclk_dpm_targ_freq_range;
        u16 uclk_dpm_midstep_freq;
        u16 uclk_midstep_padding;
        u8 pcie_gen_speed[2];
        u8 pcie_lane_count[2];
        u16 lclk_freq[2];
        u16 fan_stop_temp;
        u16 fan_start_temp;
        u16 fan_gain[10];
        u16 fan_pwm_min;
        u16 fan_acoustic_limit_rpm;
        u16 fan_throttling_rpm;
        u16 fan_maximum_rpm;
        u16 mgpu_fan_boost_limit_rpm;
        u16 fan_target_temperature;
        u16 fan_target_gfxclk;
        u16 fan_padding16;
        u8 fan_temp_input_select;
        u8 fan_padding;
        u8 fan_zero_rpm_enable;
        u8 fan_tach_edge_per_rev;
        i16 fuzzy_fan_error_set_delta;
        i16 fuzzy_fan_error_rate_set_delta;
        i16 fuzzy_fan_pwm_set_delta;
        u16 fuzzy_fan_reserved;
        u8 override_avfs_gb[2];
        u8 d_btc_gb_gfx_dfll_model_select;
        u8 padding8_avfs;
        struct quadratic_int q_avfs_gb[2];
        struct droop_int d_btc_gb_gfx_pll;
        struct droop_int d_btc_gb_gfx_dfll;
        struct droop_int d_btc_gb_soc;
        struct linear_int q_aging_gb[2];
        struct {
                u32 fset[5];
                u32 vdroop[5];
        } piecewise_linear_droop_int_gfx_dfll;
        struct quadratic_int q_static_voltage_offset[2];
        u16 dc_tol[2];
        u8 dc_btc_enabled[2];
        u8 padding8_gfx_btc[2];
        u16 dc_btc_min[2];
        u16 dc_btc_max[2];
        u16 dc_btc_gb[2];
        u8 xgmi_dpm_pstates[2];
        u8 xgmi_dpm_spare[2];
        u32 debug_overrides;
        struct quadratic_int reserved_equation0;
        struct quadratic_int reserved_equation1;
        struct quadratic_int reserved_equation2;
        struct quadratic_int reserved_equation3;
        u8 customer_variant;
        u8 vc_btc_enabled;
        u16 vc_btc_vmin_t0;
        u16 vc_btc_fixed_vmin_aging_offset;
        u16 vc_btc_vmin_2_psm_degration_gb;
        u32 vc_btc_psm_a;
        u32 vc_btc_psm_b;
        u32 vc_btc_vmin_a;
        u32 vc_btc_vmin_b;
        u32 sku_reserved[9];
        u32 gaming_clk[6];
        struct {
                u8 enabled;
                u8 speed;
                u8 slave_address;
                u8 controller_port;
                u8 controller_name;
                u8 thermal_throttler;
                u8 i2c_protocol;
                u8 padding_config;
        } i2c_controllers[16];
        u8 gpio_scl;
        u8 gpio_sda;
        u8 fch_usb_pd_slave_addr;
        u8 i2c_spare;
        u8 vdd_gfx_vr_mapping;
        u8 vdd_soc_vr_mapping;
        u8 vdd_mem0_vr_mapping;
        u8 vdd_mem1_vr_mapping;
        u8 gfx_ulv_phase_shedding_mask;
        u8 soc_ulv_phase_shedding_mask;
        u8 vddci_ulv_phase_shedding_mask;
        u8 mvdd_ulv_phase_shedding_mask;
        u16 gfx_max_current;
        i8 gfx_offset;
        u8 padding_telemetry_gfx;
        u16 soc_max_current;
        i8 soc_offset;
        u8 padding_telemetry_soc;
        u16 mem0_max_current;
        i8 mem0_offset;
        u8 padding_telemetry_mem0;
        u16 mem1_max_current;
        i8 mem1_offset;
        u8 padding_telemetry_mem1;
        u32 mvdd_ratio;
        u8 ac_dc_gpio;
        u8 ac_dc_polarity;
        u8 vr0_hot_gpio;
        u8 vr0_hot_polarity;
        u8 vr1_hot_gpio;
        u8 vr1_hot_polarity;
        u8 gthr_gpio;
        u8 gthr_polarity;
        u8 led_pin0;
        u8 led_pin1;
        u8 led_pin2;
        u8 led_enable_mask;
        u8 led_pcie;
        u8 led_error;
        u8 led_spare1[2];
        u8 pll_gfxclk_spread_enabled;
        u8 pll_gfxclk_spread_percent;
        u16 pll_gfxclk_spread_freq;
        u8 dfll_gfxclk_spread_enabled;
        u8 dfll_gfxclk_spread_percent;
        u16 dfll_gfxclk_spread_freq;
        u16 uclk_spread_padding;
        u16 uclk_spread_freq;
        u8 fclk_spread_enabled;
        u8 fclk_spread_percent;
        u16 fclk_spread_freq;
        u32 memory_channel_enabled;
        u8 dram_bit_width;
        u8 padding_mem1[3];
        u16 total_board_power;
        u16 board_power_padding;
        u8 xgmi_link_speed[4];
        u8 xgmi_link_width[4];
        u16 xgmi_fclk_freq[4];
        u16 xgmi_soc_voltage[4];
        u8 hsr_enabled;
        u8 vddq_off_enabled;
        u8 padding_umc_flags[2];
        u8 uclk_spread_percent[16];
        u32 board_reserved[11];
        u32 mmhub_padding[8];
} __attribute((packed));

static void print_smu_11_0_7_powerplay_table(struct smu_11_0_7_powerplay_table pptable) {
        printf("structuresize: %u\n", pptable.header.structuresize);
        printf("format_revision: %u\n", pptable.header.format_revision);
        printf("content_revision: %u\n", pptable.header.content_revision);
        printf("table_revision: %u\n", pptable.table_revision);
        printf("table_size: %u\n", pptable.table_size);
        printf("golden_pp_id: %u\n", pptable.golden_pp_id);
        printf("golden_revision: %u\n", pptable.golden_revision);
        printf("format_id: %u\n", pptable.format_id);
        printf("platform_caps: %u\n", pptable.platform_caps);
        printf("thermal_controller_type: %u\n", pptable.thermal_controller_type);
        printf("small_power_limit1: %u\n", pptable.small_power_limit1);
        printf("small_power_limit2: %u\n", pptable.small_power_limit2);
        printf("boost_power_limit: %u\n", pptable.boost_power_limit);
        printf("software_shutdown_temp: %u\n", pptable.software_shutdown_temp);
        printf("\n");
        print_smu_11_0_power_saving_clock_table(pptable.power_saving_clock);
        print_smu_11_0_7_overdrive_table(pptable.overdrive_table);
        printf("version: %u\n", pptable.version);
        printf("features_to_run[0]: 0x%08x\n", pptable.features_to_run[0]);
        printf("features_to_run[1]: 0x%08x\n", pptable.features_to_run[1]);
        printf("\n");
        for (u8 i = 0; i < 4; i++) {
                printf("socket_power_limit_ac[%u]: ", i);
                printf("%u W - ", pptable.socket_power_limit_ac[i]);
                printf("%u ms\n", pptable.socket_power_limit_ac_tau[i]);
        }
        for (u8 i = 0; i < 4; i++) {
                printf("socket_power_limit_dc[%u]: ", i);
                printf("%u W - ", pptable.socket_power_limit_dc[i]);
                printf("%u ms\n", pptable.socket_power_limit_dc_tau[i]);
        }
        printf("\n");
        printf("fw_d_state_mask: 0x%08x\n", pptable.fw_d_state_mask);
        printf("\n");
        for (u8 i = 0; i < 2; i++) {
                printf("freq_table_gfx[%u]: %u\n", i, pptable.freq_table_gfx[i]);
        }
        for (u8 i = 0; i < 2; i++) {
                printf("freq_table_vclk[%u]: %u\n", i, pptable.freq_table_vclk[i]);
        }
        for (u8 i = 0; i < 2; i++) {
                printf("freq_table_dclk[%u]: %u\n", i, pptable.freq_table_dclk[i]);
        }
        for (u8 i = 0; i < 2; i++) {
                printf("freq_table_socclk[%u]: %u\n", i, pptable.freq_table_socclk[i]);
        }
        for (u8 i = 0; i < 4; i++) {
                printf("freq_table_uclk[%u]: %u\n", i, pptable.freq_table_uclk[i]);
        }
        for (u8 i = 0; i < 4; i++) {
                printf("freq_table_uclk_div[%u]: %u\n", i, pptable.freq_table_uclk_div[i]);
        }
        printf("\n");
        for (u8 i = 0; i < 2; i++) {
                printf("pcie_gen_speed[%u]: %u\n", i, pptable.pcie_gen_speed[i]);
                printf("pcie_lane_count[%u]: %u\n", i, pptable.pcie_lane_count[i]);
        }
        printf("\n");
        printf("0x%08x\n", pptable.memory_channel_enabled);
        printf("%u\n", pptable.dram_bit_width);
        printf("%u\n", pptable.total_board_power);
        printf("%zu\n", sizeof(struct smu_11_0_7_powerplay_table));
        printf("\n");
}

int main(int argc, char **argv) {
        int ret = 1;

        if (argc != 2) {
                return ret;
        }

        size_t size;
        u8 *data = NULL;
        if (!read_file(argv[1], &size, &data)) {
                goto cleanup;
        }

        if (size == 1674 || size == 1494) {
                struct smu_11_0_powerplay_table pptable = *(struct smu_11_0_powerplay_table *)data;
                print_smu_11_0_powerplay_table(pptable);
        } else if (size == 2470) {
                struct smu_11_0_7_powerplay_table pptable =
                        *(struct smu_11_0_7_powerplay_table *)data;
                print_smu_11_0_7_powerplay_table(pptable);
        }

        ret = 0;

cleanup:
        free(data);

        return ret;
}