gistfile1.txt

➜ ./proxyclient/tools/run_guest.py -r build/m1n1_system.bin
TTY> CPU init (MIDR: 0x611f0320)...
TTY>   CPU part: 0x32 rev: 0x10
TTY>   CPU: M2 Blizzard
TTY>
TTY> boot_args at 0x804694088
TTY>   revision:     2
TTY>   version:      2
TTY>   virt_base:    0x19fb4000
TTY>   phys_base:    0x801fb4000
TTY>   mem_size:     0x5cf074000
TTY>   top_of_kdata: 0x804698000
TTY>   video:
TTY>     base:       0xdd4114000
TTY>     display:    0x0
TTY>     stride:     0x2d00
TTY>     width:      2880
TTY>     height:     1864
TTY>     depth:      30bpp
TTY>     density:    1
TTY>   machine_type: 0
TTY>   devtree:      0x1be90000
TTY>   devtree_size: 0x5c000
TTY>   cmdline:      -v
TTY>   boot_flags:   0x0
TTY>   mem_size_act: 0x600000000
TTY>
TTY>
TTY>
TTY> m1n1 v1.3.1
TTY> Copyright The Asahi Linux Contributors
TTY> Licensed under the MIT license
TTY>
TTY> Running in EL2
TTY>
TTY> Device info:
TTY>   Model: Mac14,15
TTY>   Target: J415
TTY>   Board-ID: 0x2e
TTY>   Chip-ID: 0x8112
TTY>
TTY> OS FW version: 13.5 (iBoot-8422.141.2)
TTY> System FW version: 13.5 (iBoot-8422.141.2)
TTY> Heap base: 0x804698000
TTY> MCC: Initializing T8103 MCC...
TTY> MCC: Initialized T8103 MCC (8 channels)
TTY> MMU: Initializing...
TTY> MMU: RAM base: 0x800000000
TTY> MMU: Top of normal RAM: 0xdd1028000
TTY> MMU: Unmapping TZ0 region at 0xdd1028000..0xdd2e10000
TTY> MMU: TZ1 region has bad bounds 0x800000..0x800000 (iBoot bug?)
TTY> MMU: Unmapping TZ2 region at 0xdda608000..0xdffe08000
TTY> MMU: Adding Device-nGnRE mapping at 0x400000000 (0x80000000)
TTY> MMU: Adding Device-nGnRE mapping at 0x480000000 (0x80000000)
TTY> MMU: Adding Device-nGnRE mapping at 0x580000000 (0x80000000)
TTY> MMU: Adding Device-nGnRE mapping at 0x600000000 (0x80000000)
TTY> MMU: Adding Device-nGnRE mapping at 0x6a0000000 (0x20000000)
TTY> MMU: Adding Device-nGnRE mapping at 0x6c0000000 (0x40000000)
TTY> MMU: Adding Normal-NC mapping at 0xdfff3c000 (0x24000)
TTY> MMU: Adding Normal-NC mapping at 0xdfff0c000 (0xc000)
TTY> MMU: Adding Normal-NC mapping at 0xdffec4000 (0x24000)
TTY> MMU: Adding Normal-NC mapping at 0xdffe94000 (0xc000)
TTY> MMU: Adding Normal-NC mapping at 0xdfffb8000 (0x4000)
TTY> MMU: Adding Normal-NC mapping at 0xdfff74000 (0x4000)
TTY> MMU: SCTLR_EL1: 30100180 -> 30901085
TTY> MMU: running with MMU and caches enabled!
TTY> AIC: Version 2 @ 0x23b0c0000
TTY> AIC: AIC2 with 1/8 dies, 1152/4096 IRQs, reg_size:08004 die_stride:04a00
TTY> WDT registers @ 0x23d2b0000
TTY> WDT disabled
TTY> pmgr: Cleaning up device states...
TTY> pmgr: Enabling 0.AUDIO_P, parent of active device DPA0
TTY> pmgr: Enabling 0.ANS, parent of active device APCIE_ST
TTY> pmgr: initialized, 303 devices on 1 dies found.
TTY> display: Display is internal
TTY> display: Display is already initialized (2880x1864)
TTY> fb init: 2880x1864 (30) [s=2880] @0xdd4114000
TTY> fb console: max rows 54, max cols 74
TTY> fb: display logo
TTY> Initialization complete.
TTY> Boot policy: sip0 = 127
TTY> Bringing up USB for early debug...
TTY> dart: dart /arm-io/dart-usb0 at 0x382f80000 is a t8110
TTY> USB0: initialized at 0x805e8a830
TTY> dart: dart /arm-io/dart-usb1 at 0x502f80000 is a t8110
TTY> USB1: initialized at 0x805e8ab60
TTY> Waiting for proxy connection... . Connected!
Fetching ADT (0x0005C000 bytes)...
Disable iodev 4
Disable iodev 5
Disable iodev 6
Disable iodev 7
Disable iodev 8
Disable iodev 9
Disable iodev 10
Initializing hypervisor over iodev 3
TTY> Starting secondary CPUs...
TTY> Starting CPU 1 (0:0:1)...   Started.
TTY> Starting CPU 2 (0:0:2)...   Started.
TTY> Starting CPU 3 (0:0:3)...   Started.
TTY> Starting CPU 4 (0:1:0)...   Started.
TTY> Starting CPU 5 (0:1:1)...   Started.
TTY> Starting CPU 6 (0:1:2)...   Started.
TTY> Starting CPU 7 (0:1:3)...   Started.
TTY> HV: Initializing for 36-bit PA range
TTY> HV: ECV enabled
Mapping MMIO range: 0x200000000 .. 0x300000000
Mapping MMIO range: 0x380000000 .. 0x500000000
Mapping MMIO range: 0x500000000 .. 0x680000000
Mapping MMIO range: 0x400000000 .. 0x480000000
Mapping MMIO range: 0x480000000 .. 0x500000000
Mapping MMIO range: 0x580000000 .. 0x600000000
Mapping MMIO range: 0x600000000 .. 0x680000000
Mapping MMIO range: 0x680000000 .. 0x700000000
Mapping MMIO range: 0x6a0000000 .. 0x6c0000000
Mapping MMIO range: 0x6c0000000 .. 0x700000000
Mapping MMIO range: 0x700000000 .. 0x780000000
Removing ADT node /arm-io/dart-usb0
Removing ADT node /arm-io/atc-phy0
Removing ADT node /arm-io/usb-drd0
Removing ADT node /arm-io/acio0
Removing ADT node /arm-io/acio-cpu0
Removing ADT node /arm-io/dart-acio0
Removing ADT node /arm-io/apciec0
Removing ADT node /arm-io/dart-apciec0
Removing ADT node /arm-io/apciec0-piodma
Removing ADT node /arm-io/i2c0/hpmBusManager/hpm0
Removing ADT node /arm-io/atc0-dpxbar
Removing ADT node /arm-io/atc0-dpphy
Removing ADT node /arm-io/atc0-dpin0
Removing ADT node /arm-io/atc0-dpin1
Removing ADT node /arm-io/atc-phy0
Total region size: 0x784000 bytes
Physical memory: 0x816814000 .. 0xdd1028000
Guest region start: 0x8178c8000
Mapping guest physical memory...
Unmapping TZ carveouts...
  Unmap [0xdd1028000..0xdd2e0ffff]
  Unmap [0xdda608000..0xdffe07fff]
Loading kernel image (0x1280d5 bytes)...
......................................................
Copying SEPFW (0x614000 bytes)...
Copying TrustCache (0x58000 bytes)...
Copying preoslog (0x40000 bytes)...
Adjusting addresses in ADT...
Setting up bootargs at 0x818048000...
Setting secondary CPU RVBARs...
  cpu1: [0x210150000] = 0x8178c8000
  cpu2: [0x210250000] = 0x8178c8000
  cpu3: [0x210350000] = 0x8178c8000
  cpu4: [0x211050000] = 0x8178c8000
  cpu5: [0x211150000] = 0x8178c8000
  cpu6: [0x211250000] = 0x8178c8000
  cpu7: [0x211350000] = 0x8178c8000
Disabling other iodevs...
 - 0
 - 1
 - 2
 - 4
 - 5
 - 6
 - 7
 - 8
 - 9
 - 10
Doing essential MMIO remaps...
Updating page tables...
PT[200000000:235200000] -> HW:HW
PT[235200000:235204000] -> RESERVED VUART
PT[235204000:23b7001a8] -> HW:HW
PT[23b7001a8:23b7001ac] -> RESERVED PMGR HACK
PT[23b7001ac:23b7001b0] -> HW:HW
PT[23b7001b0:23b7001b4] -> RESERVED PMGR HACK
PT[23b7001b4:23b7001b8] -> HW:HW
PT[23b7001b8:23b7001bc] -> RESERVED PMGR HACK
PT[23b7001bc:23b700210] -> HW:HW
PT[23b700210:23b700214] -> RESERVED PMGR HACK
PT[23b700214:23b700260] -> HW:HW
PT[23b700260:23b700264] -> RESERVED PMGR HACK
PT[23b700264:23b700458] -> HW:HW
PT[23b700458:23b70045c] -> RESERVED PMGR HACK
PT[23b70045c:23b734000] -> HW:HW
PT[23b734000:23b734020] -> RESERVED CPU_START
PT[23b734020:23d280088] -> HW:HW
PT[23d280088:23d28008c] -> RESERVED PMGR HACK
PT[23d28008c:23d280098] -> HW:HW
PT[23d280098:23d28009c] -> RESERVED PMGR HACK
PT[23d28009c:23d29c044] -> HW:HW
PT[23d29c044:23d29c048] -> RESERVED PMGR HACK
PT[23d29c048:23d29c05c] -> HW:HW
PT[23d29c05c:23d29c060] -> RESERVED PMGR HACK
PT[23d29c060:300000000] -> HW:HW
PT[380000000:780000000] -> HW:HW
PT[800000000:801fb4000] -> HW:RAM-LOW
PT[816814000:dd1028000] -> HW:RAM-HIGH
PT[dd1028000:dd2e10000] -> *UNMAPPED*
PT[dd2e10000:dda608000] -> HW:RAM-HIGH
PT[dda608000:dffe08000] -> *UNMAPPED*
PT[dffe08000:e00000000] -> HW:RAM-HIGH
Uploading ADT (0x53078 bytes)...
Improving logo...
Shutting down framebuffer...
Enabling SPRR...
Enabling GXF...
Jumping to entrypoint at 0x8178c8800
[cpu0] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu0] Pass: mrs x0, EHID0_EL1 = 7180080106000000 (EHID0_EL1)
[cpu0] Pass: msr EHID0_EL1, x0 = 7180080106000000 (OK) (EHID0_EL1)
[cpu0] Pass: mrs x0, EHID9_EL1 = 20420010f31 (EHID9_EL1)
[cpu0] Pass: msr EHID9_EL1, x0 = 20420010f31 (OK) (EHID9_EL1)
[cpu0] Pass: mrs x0, EHID9_EL1 = 20420010f31 (EHID9_EL1)
[cpu0] Pass: msr EHID9_EL1, x0 = 20420010f31 (OK) (EHID9_EL1)
[cpu0] Pass: mrs x0, EHID18_EL1 = 400000000 (EHID18_EL1)
[cpu0] Pass: msr EHID18_EL1, x0 = 400000000 (OK) (EHID18_EL1)
[cpu0] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu0] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b700210+0:32 = 0x2ff -> 0x2ff
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b700210+0:32 = 0x2ff -> 0x2ff
[cpu0] PMGR R 23b700260+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23b700210+0:32 = 0x2ff -> 0x2ff
[cpu0] PMGR R 23b700210+0:32 = 0x2ff -> 0x2ff
[cpu0] PMGR R 23b700210+0:32 = 0x2ff -> 0x2ff
[cpu0] PMGR R 23b700210+0:32 = 0x2ff -> 0x2ff
[cpu0] PMGR R 23b700210+0:32 = 0x2ff -> 0x2ff
[cpu0] PMGR R 23b700210+0:32 = 0x2ff -> 0x2ff
[cpu0] PMGR R 23b700210+0:32 = 0x2ff -> 0x2ff
[cpu0] PMGR R 23b700210+0:32 = 0x2ff -> 0x2ff
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b700458+0:32 = 0x20ff -> 0x20ff
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23d280088+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23d280098+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23d280088+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23b700458+0:32 = 0x20ff -> 0x20ff
[cpu0] CPUSTART W 23b734000+4:32 = 0x2
[cpu0] CPUSTART W 23b734000+8:32 = 0x2
[cpu0] Starting guest secondary 0:0:1
[cpu0]  CPU #1: RVBAR = 0x8178c8000
TTY> HV: Initializing secondary 1
TTY> HV: Entering guest secondary 1 at 0x8178c8000
[cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK
[cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK
[cpu1] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu1] Pass: mrs x0, EHID0_EL1 = 7180080106000000 (EHID0_EL1)
[cpu1] Pass: msr EHID0_EL1, x0 = 7180080106000000 (OK) (EHID0_EL1)
[cpu1] Pass: mrs x0, EHID9_EL1 = 20420010f31 (EHID9_EL1)
[cpu1] Pass: msr EHID9_EL1, x0 = 20420010f31 (OK) (EHID9_EL1)
[cpu1] Pass: mrs x0, EHID9_EL1 = 20420010f31 (EHID9_EL1)
[cpu1] Pass: msr EHID9_EL1, x0 = 20420010f31 (OK) (EHID9_EL1)
[cpu1] Pass: mrs x0, EHID18_EL1 = 400000000 (EHID18_EL1)
[cpu1] Pass: msr EHID18_EL1, x0 = 400000000 (OK) (EHID18_EL1)
[cpu1] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu1] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0] CPUSTART W 23b734000+4:32 = 0x4
[cpu0] CPUSTART W 23b734000+8:32 = 0x4
[cpu0] Starting guest secondary 0:0:2
[cpu0]  CPU #2: RVBAR = 0x8178c8000
TTY> HV: Initializing secondary 2
TTY> HV: Entering guest secondary 2 at 0x8178c8000
[cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK
[cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK
[cpu2] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu2] Pass: mrs x0, EHID0_EL1 = 7180080106000000 (EHID0_EL1)
[cpu2] Pass: msr EHID0_EL1, x0 = 7180080106000000 (OK) (EHID0_EL1)
[cpu2] Pass: mrs x0, EHID9_EL1 = 20420010f31 (EHID9_EL1)
[cpu2] Pass: msr EHID9_EL1, x0 = 20420010f31 (OK) (EHID9_EL1)
[cpu2] Pass: mrs x0, EHID9_EL1 = 20420010f31 (EHID9_EL1)
[cpu2] Pass: msr EHID9_EL1, x0 = 20420010f31 (OK) (EHID9_EL1)
[cpu2] Pass: mrs x0, EHID18_EL1 = 400000000 (EHID18_EL1)
[cpu2] Pass: msr EHID18_EL1, x0 = 400000000 (OK) (EHID18_EL1)
[cpu2] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu2] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0] CPUSTART W 23b734000+4:32 = 0x8
[cpu0] CPUSTART W 23b734000+8:32 = 0x8
[cpu0] Starting guest secondary 0:0:3
[cpu0]  CPU #3: RVBAR = 0x8178c8000
TTY> HV: Initializing secondary 3
TTY> HV: Entering guest secondary 3 at 0x8178c8000
[cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK
[cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK
[cpu3] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu3] Pass: mrs x0, EHID0_EL1 = 7180080106000000 (EHID0_EL1)
[cpu3] Pass: msr EHID0_EL1, x0 = 7180080106000000 (OK) (EHID0_EL1)
[cpu3] Pass: mrs x0, EHID9_EL1 = 20420010f31 (EHID9_EL1)
[cpu3] Pass: msr EHID9_EL1, x0 = 20420010f31 (OK) (EHID9_EL1)
[cpu3] Pass: mrs x0, EHID9_EL1 = 20420010f31 (EHID9_EL1)
[cpu3] Pass: msr EHID9_EL1, x0 = 20420010f31 (OK) (EHID9_EL1)
[cpu3] Pass: mrs x0, EHID18_EL1 = 400000000 (EHID18_EL1)
[cpu3] Pass: msr EHID18_EL1, x0 = 400000000 (OK) (EHID18_EL1)
[cpu3] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu3] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0] CPUSTART W 23b734000+4:32 = 0x10
[cpu0] CPUSTART W 23b734000+c:32 = 0x1
[cpu0] Starting guest secondary 0:1:0
[cpu0]  CPU #4: RVBAR = 0x8178c8000
TTY> HV: Initializing secondary 4
TTY> HV: Entering guest secondary 4 at 0x8178c8000
[cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK
[cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK
[cpu4] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu4] Pass: mrs x0, HID13_EL1 = 11111110004408 (HID13_EL1)
[cpu4] Pass: msr HID13_EL1, x0 = c011111110004408 (OK) (HID13_EL1)
[cpu4] Pass: mrs x0, HID14_EL1 = 500000bb8 (HID14_EL1)
[cpu4] Pass: msr HID14_EL1, x0 = 500000bb8 (OK) (HID14_EL1)
[cpu4] Pass: mrs x0, HID1_EL1 = 1000040002c00000 (HID1_EL1)
[cpu4] Pass: msr HID1_EL1, x0 = 1000040002c00000 (OK) (HID1_EL1)
[cpu4] Pass: mrs x0, HID1_EL1 = 1000040002c00000 (HID1_EL1)
[cpu4] Pass: msr HID1_EL1, x0 = 1000040002c00000 (OK) (HID1_EL1)
[cpu4] Pass: mrs x0, HID11_EL1 = 804000010000000 (HID11_EL1)
[cpu4] Pass: msr HID11_EL1, x0 = 804000010000000 (OK) (HID11_EL1)
[cpu4] Pass: mrs x0, HID9_EL1 = 84c020000 (HID9_EL1)
[cpu4] Pass: msr HID9_EL1, x0 = 84c020000 (OK) (HID9_EL1)
[cpu4] Pass: mrs x0, HID13_EL1 = c011111110004408 (HID13_EL1)
[cpu4] Pass: msr HID13_EL1, x0 = 11111110004408 (OK) (HID13_EL1)
[cpu4] Pass: mrs x0, s3_0_c15_c0_3 = 222221f22222221a (s3_0_c15_c0_3)
[cpu4] Pass: msr s3_0_c15_c0_3, x0 = 222221f22222221a (OK) (s3_0_c15_c0_3)
[cpu4] Pass: mrs x0, s3_0_c15_c0_4 = 22222221f22 (s3_0_c15_c0_4)
[cpu4] Pass: msr s3_0_c15_c0_4, x0 = 22222221f22 (OK) (s3_0_c15_c0_4)
[cpu4] Pass: mrs x1, HID3_EL1 = f980000008001fe0 (HID3_EL1)
[cpu4] Pass: msr HID3_EL1, x1 = f980000008001fe0 (OK) (HID3_EL1)
[cpu4] Pass: mrs x0, HID3_EL1 = f980000008001fe0 (HID3_EL1)
[cpu4] Pass: msr HID3_EL1, x0 = f980000008001fe0 (OK) (HID3_EL1)
[cpu4] Pass: mrs x0, HID18_EL1 = 28000000 (HID18_EL1)
[cpu4] Pass: msr HID18_EL1, x0 = 28000000 (OK) (HID18_EL1)
[cpu4] Pass: mrs x0, HID16_EL1 = 200000440001000 (HID16_EL1)
[cpu4] Pass: msr HID16_EL1, x0 = 200000440001000 (OK) (HID16_EL1)
[cpu4] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu4] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0] CPUSTART W 23b734000+4:32 = 0x20
[cpu0] CPUSTART W 23b734000+c:32 = 0x2
[cpu0] Starting guest secondary 0:1:1
[cpu0]  CPU #5: RVBAR = 0x8178c8000
TTY> HV: Initializing secondary 5
TTY> HV: Entering guest secondary 5 at 0x8178c8000
[cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK
[cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK
[cpu5] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu5] Pass: mrs x0, HID13_EL1 = 11111110004408 (HID13_EL1)
[cpu5] Pass: msr HID13_EL1, x0 = c011111110004408 (OK) (HID13_EL1)
[cpu5] Pass: mrs x0, HID14_EL1 = 500000bb8 (HID14_EL1)
[cpu5] Pass: msr HID14_EL1, x0 = 500000bb8 (OK) (HID14_EL1)
[cpu5] Pass: mrs x0, HID1_EL1 = 1000040002c00000 (HID1_EL1)
[cpu5] Pass: msr HID1_EL1, x0 = 1000040002c00000 (OK) (HID1_EL1)
[cpu5] Pass: mrs x0, HID1_EL1 = 1000040002c00000 (HID1_EL1)
[cpu5] Pass: msr HID1_EL1, x0 = 1000040002c00000 (OK) (HID1_EL1)
[cpu5] Pass: mrs x0, HID11_EL1 = 804000010000000 (HID11_EL1)
[cpu5] Pass: msr HID11_EL1, x0 = 804000010000000 (OK) (HID11_EL1)
[cpu5] Pass: mrs x0, HID9_EL1 = 84c020000 (HID9_EL1)
[cpu5] Pass: msr HID9_EL1, x0 = 84c020000 (OK) (HID9_EL1)
[cpu5] Pass: mrs x0, HID13_EL1 = c011111110004408 (HID13_EL1)
[cpu5] Pass: msr HID13_EL1, x0 = 11111110004408 (OK) (HID13_EL1)
[cpu5] Pass: mrs x0, s3_0_c15_c0_3 = 222221f22222221a (s3_0_c15_c0_3)
[cpu5] Pass: msr s3_0_c15_c0_3, x0 = 222221f22222221a (OK) (s3_0_c15_c0_3)
[cpu5] Pass: mrs x0, s3_0_c15_c0_4 = 22222221f22 (s3_0_c15_c0_4)
[cpu5] Pass: msr s3_0_c15_c0_4, x0 = 22222221f22 (OK) (s3_0_c15_c0_4)
[cpu5] Pass: mrs x1, HID3_EL1 = f980000008001fe0 (HID3_EL1)
[cpu5] Pass: msr HID3_EL1, x1 = f980000008001fe0 (OK) (HID3_EL1)
[cpu5] Pass: mrs x0, HID3_EL1 = f980000008001fe0 (HID3_EL1)
[cpu5] Pass: msr HID3_EL1, x0 = f980000008001fe0 (OK) (HID3_EL1)
[cpu5] Pass: mrs x0, HID18_EL1 = 28000000 (HID18_EL1)
[cpu5] Pass: msr HID18_EL1, x0 = 28000000 (OK) (HID18_EL1)
[cpu5] Pass: mrs x0, HID16_EL1 = 200000440001000 (HID16_EL1)
[cpu5] Pass: msr HID16_EL1, x0 = 200000440001000 (OK) (HID16_EL1)
[cpu5] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu5] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0] CPUSTART W 23b734000+4:32 = 0x40
[cpu0] CPUSTART W 23b734000+c:32 = 0x4
[cpu0] Starting guest secondary 0:1:2
[cpu0]  CPU #6: RVBAR = 0x8178c8000
TTY> HV: Initializing secondary 6
TTY> HV: Entering guest secondary 6 at 0x8178c8000
[cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK
[cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK
[cpu6] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu6] Pass: mrs x0, HID13_EL1 = 11111110004408 (HID13_EL1)
[cpu6] Pass: msr HID13_EL1, x0 = c011111110004408 (OK) (HID13_EL1)
[cpu6] Pass: mrs x0, HID14_EL1 = 500000bb8 (HID14_EL1)
[cpu6] Pass: msr HID14_EL1, x0 = 500000bb8 (OK) (HID14_EL1)
[cpu6] Pass: mrs x0, HID1_EL1 = 1000040002c00000 (HID1_EL1)
[cpu6] Pass: msr HID1_EL1, x0 = 1000040002c00000 (OK) (HID1_EL1)
[cpu6] Pass: mrs x0, HID1_EL1 = 1000040002c00000 (HID1_EL1)
[cpu6] Pass: msr HID1_EL1, x0 = 1000040002c00000 (OK) (HID1_EL1)
[cpu6] Pass: mrs x0, HID11_EL1 = 804000010000000 (HID11_EL1)
[cpu6] Pass: msr HID11_EL1, x0 = 804000010000000 (OK) (HID11_EL1)
[cpu6] Pass: mrs x0, HID9_EL1 = 84c020000 (HID9_EL1)
[cpu6] Pass: msr HID9_EL1, x0 = 84c020000 (OK) (HID9_EL1)
[cpu6] Pass: mrs x0, HID13_EL1 = c011111110004408 (HID13_EL1)
[cpu6] Pass: msr HID13_EL1, x0 = 11111110004408 (OK) (HID13_EL1)
[cpu6] Pass: mrs x0, s3_0_c15_c0_3 = 222221f22222221a (s3_0_c15_c0_3)
[cpu6] Pass: msr s3_0_c15_c0_3, x0 = 222221f22222221a (OK) (s3_0_c15_c0_3)
[cpu6] Pass: mrs x0, s3_0_c15_c0_4 = 22222221f22 (s3_0_c15_c0_4)
[cpu6] Pass: msr s3_0_c15_c0_4, x0 = 22222221f22 (OK) (s3_0_c15_c0_4)
[cpu6] Pass: mrs x1, HID3_EL1 = f980000008001fe0 (HID3_EL1)
[cpu6] Pass: msr HID3_EL1, x1 = f980000008001fe0 (OK) (HID3_EL1)
[cpu6] Pass: mrs x0, HID3_EL1 = f980000008001fe0 (HID3_EL1)
[cpu6] Pass: msr HID3_EL1, x0 = f980000008001fe0 (OK) (HID3_EL1)
[cpu6] Pass: mrs x0, HID18_EL1 = 28000000 (HID18_EL1)
[cpu6] Pass: msr HID18_EL1, x0 = 28000000 (OK) (HID18_EL1)
[cpu6] Pass: mrs x0, HID16_EL1 = 200000440001000 (HID16_EL1)
[cpu6] Pass: msr HID16_EL1, x0 = 200000440001000 (OK) (HID16_EL1)
[cpu6] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu6] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0] CPUSTART W 23b734000+4:32 = 0x80
[cpu0] CPUSTART W 23b734000+c:32 = 0x8
[cpu0] Starting guest secondary 0:1:3
[cpu0]  CPU #7: RVBAR = 0x8178c8000
TTY> HV: Initializing secondary 7
TTY> HV: Entering guest secondary 7 at 0x8178c8000
[cpu0] PT[23d29c044:23d29c048] -> RESERVED PMGR HACK
[cpu0] PT[23d29c048:23d29c04c] -> RESERVED CPU STATE HACK
[cpu7] Pass: msr OSLAR_EL1, x0 = 0 (OK) (OSLAR_EL1)
[cpu7] Pass: mrs x0, HID13_EL1 = 11111110004408 (HID13_EL1)
[cpu7] Pass: msr HID13_EL1, x0 = c011111110004408 (OK) (HID13_EL1)
[cpu7] Pass: mrs x0, HID14_EL1 = 500000bb8 (HID14_EL1)
[cpu7] Pass: msr HID14_EL1, x0 = 500000bb8 (OK) (HID14_EL1)
[cpu7] Pass: mrs x0, HID1_EL1 = 1000040002c00000 (HID1_EL1)
[cpu7] Pass: msr HID1_EL1, x0 = 1000040002c00000 (OK) (HID1_EL1)
[cpu7] Pass: mrs x0, HID1_EL1 = 1000040002c00000 (HID1_EL1)
[cpu7] Pass: msr HID1_EL1, x0 = 1000040002c00000 (OK) (HID1_EL1)
[cpu7] Pass: mrs x0, HID11_EL1 = 804000010000000 (HID11_EL1)
[cpu7] Pass: msr HID11_EL1, x0 = 804000010000000 (OK) (HID11_EL1)
[cpu7] Pass: mrs x0, HID9_EL1 = 84c020000 (HID9_EL1)
[cpu7] Pass: msr HID9_EL1, x0 = 84c020000 (OK) (HID9_EL1)
[cpu7] Pass: mrs x0, HID13_EL1 = c011111110004408 (HID13_EL1)
[cpu7] Pass: msr HID13_EL1, x0 = 11111110004408 (OK) (HID13_EL1)
[cpu7] Pass: mrs x0, s3_0_c15_c0_3 = 222221f22222221a (s3_0_c15_c0_3)
[cpu7] Pass: msr s3_0_c15_c0_3, x0 = 222221f22222221a (OK) (s3_0_c15_c0_3)
[cpu7] Pass: mrs x0, s3_0_c15_c0_4 = 22222221f22 (s3_0_c15_c0_4)
[cpu7] Pass: msr s3_0_c15_c0_4, x0 = 22222221f22 (OK) (s3_0_c15_c0_4)
[cpu7] Pass: mrs x1, HID3_EL1 = f980000008001fe0 (HID3_EL1)
[cpu7] Pass: msr HID3_EL1, x1 = f980000008001fe0 (OK) (HID3_EL1)
[cpu7] Pass: mrs x0, HID3_EL1 = f980000008001fe0 (HID3_EL1)
[cpu7] Pass: msr HID3_EL1, x0 = f980000008001fe0 (OK) (HID3_EL1)
[cpu7] Pass: mrs x0, HID18_EL1 = 28000000 (HID18_EL1)
[cpu7] Pass: msr HID18_EL1, x0 = 28000000 (OK) (HID18_EL1)
[cpu7] Pass: mrs x0, HID16_EL1 = 200000440001000 (HID16_EL1)
[cpu7] Pass: msr HID16_EL1, x0 = 200000440001000 (OK) (HID16_EL1)
[cpu7] Pass: mrs x1, ACC_CFG_EL1 = d (ACC_CFG_EL1)
[cpu7] Skip: msr ACC_CFG_EL1, x1 = d
[cpu0] PMGR R 23b7001b0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001b0+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001b0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001b8+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001a8+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001a8+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001a8+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001a8+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001b0+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001b0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001b8+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b700210+0:32 = 0x2ff -> 0x2ff
[cpu0] PMGR W 23b700210+0:32 = 0x2ff: Dangerous write
[cpu0] PMGR R 23b700210+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23b700260+0:32 = 0xff -> 0xff
[cpu0] PMGR W 23b700260+0:32 = 0xff: Dangerous write
[cpu0] PMGR R 23b700260+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23b7001b0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001b0+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001b0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001b8+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b700210+0:32 = 0xff -> 0xff
[cpu0] PMGR W 23b700210+0:32 = 0xff: Dangerous write
[cpu0] PMGR R 23b700210+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23b700260+0:32 = 0xff -> 0xff
[cpu0] PMGR W 23b700260+0:32 = 0xff: Dangerous write
[cpu0] PMGR R 23b700260+0:32 = 0xff -> 0xff
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001a8+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001a8+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] PMGR W 23b7001a8+0:32 = 0xf0000ff: Dangerous write
[cpu0] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu0] Shadow: msr MDSCR_EL1, x1 = 1000
[cpu1] Shadow: msr MDSCR_EL1, x1 = 1000
[cpu2] Shadow: msr MDSCR_EL1, x1 = 1000
[cpu3] Shadow: msr MDSCR_EL1, x1 = 1000
[cpu4] Shadow: msr MDSCR_EL1, x1 = 1000
[cpu5] Shadow: msr MDSCR_EL1, x1 = 1000
[cpu6] Shadow: msr MDSCR_EL1, x1 = 1000
[cpu7] Shadow: msr MDSCR_EL1, x1 = 1000
[cpu0] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu0] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu1] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu1] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu2] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu2] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu3] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu3] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu4] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu4] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu5] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu5] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu6] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu6] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu7] Pass: msr OSDLR_EL1, x31 = 0 (OK) (OSDLR_EL1)
[cpu7] Pass: msr OSLAR_EL1, x31 = 0 (OK) (OSLAR_EL1)
[cpu0] Shadow: msr DBGBCR15_EL1, x2 = 0
[cpu0] Shadow: msr DBGBVR15_EL1, x2 = 0
[cpu0] Shadow: msr s2_0_c0_c1_5, x2 = 0
[cpu0] Shadow: msr s2_0_c0_c1_4, x2 = 0
[cpu0] Shadow: msr s2_0_c0_c2_5, x2 = 0
[cpu0] Shadow: msr s2_0_c0_c2_4, x2 = 0
[cpu0] Shadow: msr s2_0_c0_c3_5, x2 = 0
[cpu0] Shadow: msr s2_0_c0_c3_4, x2 = 0
[cpu0] Shadow: msr s2_0_c0_c4_5, x2 = 0
[cpu0] Shadow: msr s2_0_c0_c4_4, x2 = 0
[cpu0] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu0] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu0] Shadow: msr DBGWCR15_EL1, x2 = 0
[cpu0] Shadow: msr DBGWVR15_EL1, x2 = 0
[cpu0] Shadow: msr s2_0_c0_c1_7, x2 = 0
[cpu0] Shadow: msr s2_0_c0_c1_6, x2 = 0
[cpu0] Shadow: msr s2_0_c0_c2_7, x2 = 0
[cpu0] Shadow: msr s2_0_c0_c2_6, x2 = 0
[cpu0] Shadow: msr s2_0_c0_c3_7, x2 = 0
[cpu0] Shadow: msr s2_0_c0_c3_6, x2 = 0
[cpu1] Shadow: msr DBGBCR15_EL1, x2 = 0
[cpu1] Shadow: msr DBGBVR15_EL1, x2 = 0
[cpu1] Shadow: msr s2_0_c0_c1_5, x2 = 0
[cpu1] Shadow: msr s2_0_c0_c1_4, x2 = 0
[cpu1] Shadow: msr s2_0_c0_c2_5, x2 = 0
[cpu1] Shadow: msr s2_0_c0_c2_4, x2 = 0
[cpu1] Shadow: msr s2_0_c0_c3_5, x2 = 0
[cpu1] Shadow: msr s2_0_c0_c3_4, x2 = 0
[cpu1] Shadow: msr s2_0_c0_c4_5, x2 = 0
[cpu1] Shadow: msr s2_0_c0_c4_4, x2 = 0
[cpu1] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu1] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu1] Shadow: msr DBGWCR15_EL1, x2 = 0
[cpu1] Shadow: msr DBGWVR15_EL1, x2 = 0
[cpu1] Shadow: msr s2_0_c0_c1_7, x2 = 0
[cpu1] Shadow: msr s2_0_c0_c1_6, x2 = 0
[cpu1] Shadow: msr s2_0_c0_c2_7, x2 = 0
[cpu1] Shadow: msr s2_0_c0_c2_6, x2 = 0
[cpu1] Shadow: msr s2_0_c0_c3_7, x2 = 0
[cpu1] Shadow: msr s2_0_c0_c3_6, x2 = 0
[cpu2] Shadow: msr DBGBCR15_EL1, x2 = 0
[cpu2] Shadow: msr DBGBVR15_EL1, x2 = 0
[cpu2] Shadow: msr s2_0_c0_c1_5, x2 = 0
[cpu2] Shadow: msr s2_0_c0_c1_4, x2 = 0
[cpu2] Shadow: msr s2_0_c0_c2_5, x2 = 0
[cpu2] Shadow: msr s2_0_c0_c2_4, x2 = 0
[cpu2] Shadow: msr s2_0_c0_c3_5, x2 = 0
[cpu2] Shadow: msr s2_0_c0_c3_4, x2 = 0
[cpu2] Shadow: msr s2_0_c0_c4_5, x2 = 0
[cpu2] Shadow: msr s2_0_c0_c4_4, x2 = 0
[cpu2] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu2] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu2] Shadow: msr DBGWCR15_EL1, x2 = 0
[cpu2] Shadow: msr DBGWVR15_EL1, x2 = 0
[cpu2] Shadow: msr s2_0_c0_c1_7, x2 = 0
[cpu2] Shadow: msr s2_0_c0_c1_6, x2 = 0
[cpu2] Shadow: msr s2_0_c0_c2_7, x2 = 0
[cpu2] Shadow: msr s2_0_c0_c2_6, x2 = 0
[cpu2] Shadow: msr s2_0_c0_c3_7, x2 = 0
[cpu2] Shadow: msr s2_0_c0_c3_6, x2 = 0
[cpu3] Shadow: msr DBGBCR15_EL1, x2 = 0
[cpu3] Shadow: msr DBGBVR15_EL1, x2 = 0
[cpu3] Shadow: msr s2_0_c0_c1_5, x2 = 0
[cpu3] Shadow: msr s2_0_c0_c1_4, x2 = 0
[cpu3] Shadow: msr s2_0_c0_c2_5, x2 = 0
[cpu3] Shadow: msr s2_0_c0_c2_4, x2 = 0
[cpu3] Shadow: msr s2_0_c0_c3_5, x2 = 0
[cpu3] Shadow: msr s2_0_c0_c3_4, x2 = 0
[cpu3] Shadow: msr s2_0_c0_c4_5, x2 = 0
[cpu3] Shadow: msr s2_0_c0_c4_4, x2 = 0
[cpu3] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu3] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu3] Shadow: msr DBGWCR15_EL1, x2 = 0
[cpu3] Shadow: msr DBGWVR15_EL1, x2 = 0
[cpu3] Shadow: msr s2_0_c0_c1_7, x2 = 0
[cpu3] Shadow: msr s2_0_c0_c1_6, x2 = 0
[cpu3] Shadow: msr s2_0_c0_c2_7, x2 = 0
[cpu3] Shadow: msr s2_0_c0_c2_6, x2 = 0
[cpu3] Shadow: msr s2_0_c0_c3_7, x2 = 0
[cpu3] Shadow: msr s2_0_c0_c3_6, x2 = 0
[cpu4] Shadow: msr DBGBCR15_EL1, x2 = 0
[cpu4] Shadow: msr DBGBVR15_EL1, x2 = 0
[cpu4] Shadow: msr s2_0_c0_c1_5, x2 = 0
[cpu4] Shadow: msr s2_0_c0_c1_4, x2 = 0
[cpu4] Shadow: msr s2_0_c0_c2_5, x2 = 0
[cpu4] Shadow: msr s2_0_c0_c2_4, x2 = 0
[cpu4] Shadow: msr s2_0_c0_c3_5, x2 = 0
[cpu4] Shadow: msr s2_0_c0_c3_4, x2 = 0
[cpu4] Shadow: msr s2_0_c0_c4_5, x2 = 0
[cpu4] Shadow: msr s2_0_c0_c4_4, x2 = 0
[cpu4] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu4] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu4] Shadow: msr DBGWCR15_EL1, x2 = 0
[cpu4] Shadow: msr DBGWVR15_EL1, x2 = 0
[cpu4] Shadow: msr s2_0_c0_c1_7, x2 = 0
[cpu4] Shadow: msr s2_0_c0_c1_6, x2 = 0
[cpu4] Shadow: msr s2_0_c0_c2_7, x2 = 0
[cpu4] Shadow: msr s2_0_c0_c2_6, x2 = 0
[cpu4] Shadow: msr s2_0_c0_c3_7, x2 = 0
[cpu4] Shadow: msr s2_0_c0_c3_6, x2 = 0
[cpu5] Shadow: msr DBGBCR15_EL1, x2 = 0
[cpu5] Shadow: msr DBGBVR15_EL1, x2 = 0
[cpu5] Shadow: msr s2_0_c0_c1_5, x2 = 0
[cpu5] Shadow: msr s2_0_c0_c1_4, x2 = 0
[cpu5] Shadow: msr s2_0_c0_c2_5, x2 = 0
[cpu5] Shadow: msr s2_0_c0_c2_4, x2 = 0
[cpu5] Shadow: msr s2_0_c0_c3_5, x2 = 0
[cpu5] Shadow: msr s2_0_c0_c3_4, x2 = 0
[cpu5] Shadow: msr s2_0_c0_c4_5, x2 = 0
[cpu5] Shadow: msr s2_0_c0_c4_4, x2 = 0
[cpu5] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu5] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu5] Shadow: msr DBGWCR15_EL1, x2 = 0
[cpu5] Shadow: msr DBGWVR15_EL1, x2 = 0
[cpu5] Shadow: msr s2_0_c0_c1_7, x2 = 0
[cpu5] Shadow: msr s2_0_c0_c1_6, x2 = 0
[cpu5] Shadow: msr s2_0_c0_c2_7, x2 = 0
[cpu5] Shadow: msr s2_0_c0_c2_6, x2 = 0
[cpu5] Shadow: msr s2_0_c0_c3_7, x2 = 0
[cpu5] Shadow: msr s2_0_c0_c3_6, x2 = 0
[cpu6] Shadow: msr DBGBCR15_EL1, x2 = 0
[cpu6] Shadow: msr DBGBVR15_EL1, x2 = 0
[cpu6] Shadow: msr s2_0_c0_c1_5, x2 = 0
[cpu6] Shadow: msr s2_0_c0_c1_4, x2 = 0
[cpu6] Shadow: msr s2_0_c0_c2_5, x2 = 0
[cpu6] Shadow: msr s2_0_c0_c2_4, x2 = 0
[cpu6] Shadow: msr s2_0_c0_c3_5, x2 = 0
[cpu6] Shadow: msr s2_0_c0_c3_4, x2 = 0
[cpu6] Shadow: msr s2_0_c0_c4_5, x2 = 0
[cpu6] Shadow: msr s2_0_c0_c4_4, x2 = 0
[cpu6] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu6] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu6] Shadow: msr DBGWCR15_EL1, x2 = 0
[cpu6] Shadow: msr DBGWVR15_EL1, x2 = 0
[cpu6] Shadow: msr s2_0_c0_c1_7, x2 = 0
[cpu6] Shadow: msr s2_0_c0_c1_6, x2 = 0
[cpu6] Shadow: msr s2_0_c0_c2_7, x2 = 0
[cpu6] Shadow: msr s2_0_c0_c2_6, x2 = 0
[cpu6] Shadow: msr s2_0_c0_c3_7, x2 = 0
[cpu6] Shadow: msr s2_0_c0_c3_6, x2 = 0
[cpu7] Shadow: msr DBGBCR15_EL1, x2 = 0
[cpu7] Shadow: msr DBGBVR15_EL1, x2 = 0
[cpu7] Shadow: msr s2_0_c0_c1_5, x2 = 0
[cpu7] Shadow: msr s2_0_c0_c1_4, x2 = 0
[cpu7] Shadow: msr s2_0_c0_c2_5, x2 = 0
[cpu7] Shadow: msr s2_0_c0_c2_4, x2 = 0
[cpu7] Shadow: msr s2_0_c0_c3_5, x2 = 0
[cpu7] Shadow: msr s2_0_c0_c3_4, x2 = 0
[cpu7] Shadow: msr s2_0_c0_c4_5, x2 = 0
[cpu7] Shadow: msr s2_0_c0_c4_4, x2 = 0
[cpu7] Pass: msr s2_0_c0_c5_5, x2 = 0 (OK) (s2_0_c0_c5_5)
[cpu7] Pass: msr s2_0_c0_c5_4, x2 = 0 (OK) (s2_0_c0_c5_4)
[cpu7] Shadow: msr DBGWCR15_EL1, x2 = 0
[cpu7] Shadow: msr DBGWVR15_EL1, x2 = 0
[cpu7] Shadow: msr s2_0_c0_c1_7, x2 = 0
[cpu7] Shadow: msr s2_0_c0_c1_6, x2 = 0
[cpu7] Shadow: msr s2_0_c0_c2_7, x2 = 0
[cpu7] Shadow: msr s2_0_c0_c2_6, x2 = 0
[cpu7] Shadow: msr s2_0_c0_c3_7, x2 = 0
[cpu7] Shadow: msr s2_0_c0_c3_6, x2 = 0
[cpu3] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu3] PMGR R 23b7001a8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu3] PMGR W 23b7001a8+0:32 = 0x1f0000ff: Dangerous write
[cpu3] PMGR R 23b7001b0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu3] PMGR R 23b7001b0+0:32 = 0xf0000ff -> 0xf0000ff
[cpu3] PMGR W 23b7001b0+0:32 = 0x1f0000ff: Dangerous write
[cpu3] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu3] PMGR R 23b7001b8+0:32 = 0xf0000ff -> 0xf0000ff
[cpu3] PMGR W 23b7001b8+0:32 = 0x1f0000ff: Dangerous write
[cpu3] PMGR R 23b700210+0:32 = 0xff -> 0xff
[cpu3] PMGR R 23b700210+0:32 = 0xff -> 0xff
[cpu3] PMGR W 23b700210+0:32 = 0x100000ff: Dangerous write
[cpu3] PMGR R 23b700260+0:32 = 0xff -> 0xff
[cpu3] PMGR R 23b700260+0:32 = 0xff -> 0xff
[cpu3] PMGR W 23b700260+0:32 = 0x100000ff: Dangerous write
[cpu3] PMGR R 23b700458+0:32 = 0x20ff -> 0x20ff
[cpu3] PMGR R 23b700458+0:32 = 0x20ff -> 0x20ff
[cpu3] PMGR W 23b700458+0:32 = 0x100020ff: Dangerous write
[cpu3] PMGR R 23d280088+0:32 = 0xff -> 0xff
[cpu3] PMGR R 23d280088+0:32 = 0xff -> 0xff
[cpu3] PMGR W 23d280088+0:32 = 0x100000ff: Dangerous write
[cpu3] PMGR R 23d280098+0:32 = 0xff -> 0xff
[cpu3] PMGR R 23d280098+0:32 = 0xff -> 0xff
[cpu3] PMGR W 23d280098+0:32 = 0x100000ff: Dangerous write
[cpu7] PMGR R 23d280098+0:32 = 0xff -> 0x100000ff
[cpu7] PMGR W 23d280098+0:32 = 0xf0: Dangerous write
[cpu7] PMGR R 23d280098+0:32 = 0xff -> 0x0