gistfile1.py

from myhdl import *

def SRL16E(
  CLK, CE,
  D,
  A,
  Q):

  reg = Signal(intbv()[16:0])

  @always_comb
  def comb():
    Q.next = reg[A]

  @always(CLK.posedge)
  def seq():
    if CE:
      reg.next = concat(reg[16:1], D)

  return instances()


def convert():
  CLK = Signal(False)
  CE = Signal(False)
  D = Signal(False)
  Q = Signal(False)
  A = Signal(intbv()[4:0])
  toVerilog(SRL16E, CLK, CE, D, A, Q)

convert()

gistfile2.v

// File: SRL16E.v
// Generated by MyHDL 0.7
// Date: Wed May 22 18:41:54 2013


`timescale 1ns/10ps

module SRL16E (
    CLK,
    CE,
    D,
    A,
    Q
);


input CLK;
input CE;
input D;
input [3:0] A;
output Q;
wire Q;

reg [15:0] reg;





always @(posedge CLK) begin: SRL16E_SEQ
    if (CE) begin
        reg <= {reg[16-1:1], D};
    end
end



assign Q = reg[A];

endmodule