example.v

module top (input btn1, output led1, output led2, output led3);
  reg [2:0] cnt;
  initial begin
    cnt = 3'b000;
  end
  always @(posedge btn1) begin
      if(cnt == 0)cnt = 3'b001;
      else cnt = cnt << 1;

      {led3, led2, led1} = cnt;
  end
endmodule