Search paths for RTL files and write vim-hdl project file

create_hdlcc_project.py

#!/usr/bin/env python3

import sys
import os
import os.path as p
import argparse
import re
import time

try:
    import argcomplete
    _HAS_ARGCOMPLETE = True
except ImportError: # pragma: no cover
    _HAS_ARGCOMPLETE = False

def parseArguments():
    """
    Parse command line args
    """
    parser = argparse.ArgumentParser()

    # Options
    parser.add_argument('--output', '-o', action='store', default='/dev/stdout')

    parser.add_argument('--vhdl-lib', action='store',
                        default='xil_defaultlib')
    parser.add_argument('--verilog-lib', action='store',
                        default='xil_defaultlib')
    parser.add_argument('--system-verilog-lib', action='store',
                        default='xil_defaultlib')

    parser.add_argument('--no-vhdl', action='store_true')
    parser.add_argument('--no-verilog', action='store_true')
    parser.add_argument('--no-sv', action='store_true')

    parser.add_argument('paths', action='store', nargs='*',
                        default=[os.curdir,])

    if _HAS_ARGCOMPLETE: # pragma: no cover
        argcomplete.autocomplete(parser)

    args = parser.parse_args()

    args.include_vhdl = not args.no_vhdl
    args.include_verilog = not args.no_verilog
    args.include_system_verilog = not args.no_sv

    return args

def main():
    args = parseArguments()
    vhd_files = 0
    v_files = 0
    sv_files = 0
    total = 0
    if p.exists(args.output) and args.output != '/dev/stdout':
        suffix = time.strftime("%Y%m%d_%H%M%S",
                               time.gmtime(p.getmtime(args.output)))
        backup = "%s.%s" % (args.output, suffix)
        print("Path '%s' exists, renaming it to '%s'" % (args.output, backup))
        os.rename(args.output, backup)
    with open(args.output, 'w') as fd:
        fd.write("# Created in %s with:\n" % time.strftime("%H:%M:%S %d/%m/%Y"))
        fd.write("# %s\n" % (' '.join(sys.argv)))
        fd.write("#\n\n")
        for source, extension in iterFiles(args):
            total += 1
            if args.output != '/dev/stdout':
                sys.stdout.write('\rProcessed %d files' % total)

            flags = ''
            if (p.basename(source).split('.')[0].endswith('_tb') or
                    p.basename(source).startswith('tb_')):
                flags = '-2008'

            if extension in ('vhdl', 'vhd'):
                source_type = 'vhdl'
                lib = args.vhdl_lib
                vhd_files += 1
            elif extension == 'v':
                source_type = 'verilog'
                lib = args.verilog_lib
                v_files += 1
            elif extension == 'sv':
                source_type = 'systemverilog'
                lib = args.system_verilog_lib
                sv_files += 1
            else:
                assert False, ("Unknown extension '{1}' for file "
                               "'{0}'".format(source, extension))

            fd.write("{source_type} {lib} {path} {flags}\n".format(
                source_type=source_type, lib=lib, path=source, flags=flags))
        fd.write("# Found: VHDL: {0}, Verilog: {1}, SystemVerilog: {2}\n".
                 format(vhd_files, v_files, sv_files))

    if vhd_files + v_files + sv_files:
        sys.stdout.write('\n')

def shouldAdd(path):
    try:
        open(path, 'r').read(1)
        return True
    except UnicodeDecodeError:
        sys.stderr.write("Skipping '{0}'\n".format(path))
        return False

def iterFiles(args):
    for path in args.paths:
        for dirpath, _, filenames in os.walk(path):
            for filename in filenames:
                extension = filename.split('.')[-1].lower()

                if extension not in ('vhdl', 'vhd', 'v', 'sv'):
                    continue

                path = p.join(dirpath, filename)

                if extension in ('vhdl', 'vhd') and not args.include_vhdl:
                    continue
                if extension == 'v' and not args.include_verilog:
                    continue
                if extension == 'sv' and not args.include_system_verilog:
                    continue

                if shouldAdd(path):
                    yield path, extension

if __name__ == '__main__':
    main()

Thanks for providing this script. Manually maintaining the configuration is a nightmare. I think this script should be referred from the READMEs of vim-hdl and hdlcc.