Make sure all buses reserve at least one bus number

gistfile1.txt

Root of issue was that XHCI controller wasn't visible:

[  320.557898] pci_bus 0000:3a: [bus 3a] partially hidden behind bridge 0000:02 [bus 02-39]
[  320.557899] pci_bus 0000:3a: [bus 3a] partially hidden behind bridge 0000:01 [bus 01-39]

It was missing from PCI tree:
-[0000:00]-+-00.0
           +-02.0
           +-04.0
           +-08.0
           +-12.0
           +-14.0
           +-14.2
           +-15.0
           +-15.1
           +-16.0
           +-16.3
           +-17.0
           +-1b.0-[01-39]----00.0-[02-39]--+-00.0-[03]--
           |                               +-01.0-[04-38]--
           |                               \-02.0-[39]----00.0
           +-1c.0-[3a]----00.0
           +-1c.4-[3b]----00.0
           +-1f.0
           +-1f.3
           +-1f.4
           \-1f.5