Khadas VIM3 TS050 patches for mainline kernel

0071-panel-khadas.patch

diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
index 80737731af3f..1a9d898fdb0b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
@@ -395,15 +395,17 @@
 &mipi_dsi {
 	status = "okay";
 
-	assigned-clocks = <&clkc CLKID_GP0_PLL>,
+	assigned-clocks = <&clkc CLKID_GP0_PLL_DCO>,
+	          <&clkc CLKID_GP0_PLL>,
 			  <&clkc CLKID_MIPI_DSI_PXCLK_SEL>,
 			  <&clkc CLKID_MIPI_DSI_PXCLK>;
-	assigned-clock-parents = <0>,
+	assigned-clock-parents = <0>, <0>,
 				 <&clkc CLKID_GP0_PLL>,
 				 <0>;
-	assigned-clock-rates = <720000000>,
+	assigned-clock-rates = <3840000000>,
+	               <960000000>,
 			       <0>,
-			       <720000000>;
+			       <960000000>;
 
 	panel@0 {
 		compatible = "khadas,ts050";

diff --git a/drivers/gpu/drm/panel/panel-khadas-ts050.c b/drivers/gpu/drm/panel/panel-khadas-ts050.c
index 80737731af3f..1a9d898fdb0b 100644
--- a/drivers/gpu/drm/panel/panel-khadas-ts050.c
+++ b/drivers/gpu/drm/panel/panel-khadas-ts050.c
@@ -568,8 +568,8 @@
 	{0xfb, 0x01},
 	/* Select CMD1 */
 	{0xff, 0x00},
-	{0xd3, 0x05}, /* RGBMIPICTRL: VSYNC back porch = 5 */
-	{0xd4, 0x04}, /* RGBMIPICTRL: VSYNC front porch = 4 */
+	{ 0xD3, 0x22 }, /* RGBMIPICTRL: VSYNC back porch = 34 */
+	{ 0xD4, 0x04 }, /* RGBMIPICTRL: VSYNC front porch = 4 */
 };
 
 static inline
@@ -717,15 +717,15 @@
 }
 
 static const struct drm_display_mode default_mode = {
-	.clock = 120000,
-	.hdisplay = 1088,
-	.hsync_start = 1088 + 104,
-	.hsync_end = 1088 + 104 + 4,
-	.htotal = 1088 + 104 + 4 + 127,
+	.clock = 120000,
+	.hdisplay = 1080,
+	.hsync_start = 1080 + 88,
+	.hsync_end = 1080 + 88 + 4,
+	.htotal = 1080 + 88 + 4 + 126,
 	.vdisplay = 1920,
 	.vsync_start = 1920 + 4,
 	.vsync_end = 1920 + 4 + 2,
-	.vtotal = 1920 + 4 + 2 + 3,
+	.vtotal = 1920 + 4 + 2 + 32,
 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
 };

diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
index 80737731af3f..1a9d898fdb0b 100644
--- a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
+++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
@@ -145,7 +213,22 @@
 					 bpp, mipi_dsi->dsi_device->lanes,
 					 &mipi_dsi->phy_opts.mipi_dphy);
 
+	/*
+	 * phy_mipi_dphy_get_default_config sets
+	 * `hs_clk_rate = pixel_clock * bpp / lanes`
+	 * Ex:
+	 *  clock = 120000KHz
+	 *  bpp = 24
+	 *  lanes= 4 => hs_clk_rate = 720MHz
+	 *
+	 * Khadas VIM3 works ok with 960MHz (good picture quality)
+	 *  and does not with 720MHz (bad picture quality)
+	 *  => force x8 relationship between `mode->clock` and `hs_clk_rate`
+	 */
+	mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate = mode->clock * 1000 * 8;
+
 	*lane_mbps = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate / 1000000;
+	pr_err("Set lane_mbps %u from rate %lu clock %d\n", *lane_mbps, mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate, mode->clock);
 
 	return 0;
 }

0072-meson-clk-pll.patch

diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index 80737731af3f..1a9d898fdb0b 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -90,6 +90,7 @@
 #define CLKID_VCLK2_VENCL			97
 #define CLKID_VCLK2_OTHER1			98
 #define CLKID_FCLK_DIV2P5			99
+#define CLKID_GP0_PLL_DCO			103
 #define CLKID_DMA				105
 #define CLKID_EFUSE				106
 #define CLKID_ROM_BOOT				107

diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index 80737731af3f..1a9d898fdb0b 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -156,7 +156,7 @@
 #define CLKID_FCLK_DIV2P5_DIV			100
 #define CLKID_FIXED_PLL_DCO			101
 #define CLKID_SYS_PLL_DCO			102
-#define CLKID_GP0_PLL_DCO			103
+//#define CLKID_GP0_PLL_DCO			103 /*moved to dt-bindings */
 #define CLKID_HIFI_PLL_DCO			104
 #define CLKID_VPU_0_DIV				111
 #define CLKID_VPU_1_DIV				114

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 80737731af3f..1a9d898fdb0b 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -1603,7 +1603,7 @@
 };
 
 static const struct pll_mult_range g12a_gp0_pll_mult_range = {
-	.min = 120,
+	.min = 128, /* was 120, which gives 2.88GHz, but the valid range is >=3GHz */
 	.max = 255,
 };