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svmlegacy/Intel Core i5-3320M corefreq -s

Created February 14, 2021 05:04
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Intel Core i5-3320M corefreq -s
Processor [Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz]
|- Architecture [IvyBridge]
|- Vendor ID [GenuineIntel]
|- Microcode [0x00000021]
|- Signature [ 06_3A]
|- Stepping [ 9]
|- Online CPU [ 4/ 4]
|- Base Clock [ 99.772]
|- Frequency (MHz) Ratio
Min 1197.27 < 12 >
Max 2594.08 < 26 >
|- Factory [100.000]
2600 [ 26 ]
|- Performance
|- P-State
TGT 1297.04 < 13 >
|- Turbo Boost [ LOCK]
1C 3292.49 < 33 >
2C 3092.94 < 31 >
3C 3092.94 < 31 >
4C 3092.94 < 31 >
|- Uncore [ LOCK]
Min 1197.27 [ 12 ]
Max 2594.08 [ 26 ]
|- TDP Level [ 0:0 ]
|- Programmable [ UNLOCK]
|- Configuration [ LOCK]
|- Turbo Activation [ UNLOCK]
Nominal 2594.08 [ 26 ]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [N] AES [Y] AVX/AVX2 [Y/N]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNMI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] BMI1/BMI2 [N/N] CLWB [N] CLFLUSH/O [Y/N]
|- CLAC-STAC [N] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [N] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [N] RDTSCP [Y]
|- SEP [Y] SHA [N] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] SGX [N] RDPID [N]
Features
|- 1 GB Pages Support 1GB-PAGES [Missing]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast-String Operation Fast-Strings [Capable]
|- Fused Multiply Add FMA | FMA4 [Missing]
|- Hardware Lock Elision HLE [Missing]
|- Instruction Based Sampling IBS [Missing]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Process Context Identifiers PCID [Capable]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Resource Director Technology/PQE RDT-A [Missing]
|- Resource Director Technology/PQM RDT-M [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Capable]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Access Prevention SMAP [Missing]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Missing]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Extended xAPIC Support x2APIC [ xAPIC]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Capable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Capable]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [Missing]
|- Architectural - Buffer Overwriting MD-CLEAR [Capable]
|- Architectural - Rogue Data Cache Load RDCL_NO [Missing]
|- Architectural - Enhanced IBRS IBRS_ALL [Missing]
|- Architectural - Return Stack Buffer Alternate RSBA [Missing]
|- Architectural - Speculative Store Bypass SSB_NO [Missing]
|- Architectural - Microarchitectural Data Sampling MDS_NO [Missing]
|- Architectural - TSX Asynchronous Abort TAA_NO [Missing]
|- Architectural - Page Size Change MCE PSCHANGE_MC_NO [Missing]
|- Architectural - Split Locked Access Exception SPLA [Missing]
Technologies
|- System Management Mode SMM-Dual [OFF]
|- Hyper-Threading HTT [ ON]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [ ON]
|- Turbo Boost TURBO < ON>
|- Race To Halt Optimization R2H <OFF>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [ ON]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [ 3]
|- Counters: General Fixed
| 4 x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E <OFF>
|- C1 Auto Demotion C1A < ON>
|- C3 Auto Demotion C3A < ON>
|- C1 UnDemotion C1U < ON>
|- C3 UnDemotion C3U < ON>
|- C6 Core Demotion CC6 <OFF>
|- C6 Module Demotion MC6 <OFF>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware-Controlled Performance States HWP [OFF]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-States
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT < C7>
|- I/O MWAIT Redirection IOMWAIT < Enable>
|- Max C-State Inclusion RANGE < C7>
|- Core C-States
|- C-States Base Address BAR [ 0x414 ]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 1 1 2 0 0 0
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Capable]
Power, Current & Thermal
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint < 6>
|- Energy Policy HWP EPP [ 0]
|- Junction Temperature TjMax [ 1:105C]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Capable]
|- Package Thermal Management PTM [Capable]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [ 35 W]
|- Minimum Power Min [ 24 W]
|- Maximum Power Max [Missing]
|- Package Power Tracking PPT [ 43 W]
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000015259]
|- Window second [ 0.000976562]
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Corefreq 1.83.8

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