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svmlegacy/Celeron G3900 Corefreq

Created June 12, 2021 17:43
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Celeron G3900 Corefreq
$ ./corefreq-cli -s
Processor [Intel(R) Celeron(R) CPU G3900 @ 2.80GHz]
|- Architecture [Skylake/S]
|- Vendor ID [GenuineIntel]
|- Microcode [ 214]
|- Signature [ 06_5E]
|- Stepping [ 3]
|- Online CPU [ 2/ 2]
|- Base Clock [100.286]
|- Frequency (MHz) Ratio
Min 802.29 < 8 >
Max 2808.00 < 28 >
|- Factory [100.000]
2800 [ 28 ]
|- Performance
|- OSPM
TGT 802.29 < 8 >
|- HWP
Min AUTO < 0 >
Max AUTO < 0 >
TGT AUTO < 0 >
|- Turbo Boost [ UNLOCK]
1C 2808.00 < 28 >
2C 2808.00 < 28 >
3C 2808.00 < 28 >
4C 2808.00 < 28 >
|- Uncore [ LOCK]
Min 802.29 [ 8 ]
Max 2808.00 [ 28 ]
|- TDP Level [ 0:3 ]
|- Programmable [ UNLOCK]
|- Configuration [ LOCK]
|- Turbo Activation [ UNLOCK]
Nominal 2808.00 [ 28 ]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [N] AES [Y] AVX/AVX2 [N/N]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNMI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] BMI1/BMI2 [N/N] CLWB [N] CLFLUSH/O [Y/Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [N] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/N] MONITOR/X [Y/N] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [N] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] SGX [Y] RDPID [N]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast-String Operation Fast-Strings [Capable]
|- Fused Multiply Add FMA | FMA4 [Missing]
|- Hardware Lock Elision HLE [Missing]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Process Context Identifiers PCID [Capable]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Resource Director Technology/PQE RDT-A [Missing]
|- Resource Director Technology/PQM RDT-M [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Missing]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable]
|- TSX Force Abort MSR Register TSX-ABORT [Capable]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Missing]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Extended xAPIC Support x2APIC [ x2APIC]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Capable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Capable]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [Missing]
|- Architectural - Buffer Overwriting MD-CLEAR [Capable]
|- Architectural - Rogue Data Cache Load RDCL_NO [Missing]
|- Architectural - Enhanced IBRS IBRS_ALL [Missing]
|- Architectural - Return Stack Buffer Alternate RSBA [Missing]
|- Architectural - Speculative Store Bypass SSB_NO [Missing]
|- Architectural - Microarchitectural Data Sampling MDS_NO [Missing]
|- Architectural - TSX Asynchronous Abort TAA_NO [Missing]
|- Architectural - Page Size Change MCE PSCHANGE_MC_NO [Missing]
|- Architectural - Split Locked Access Exception SPLA [Missing]
Technologies
|- System Management Mode SMM-Dual [ ON]
|- Hyper-Threading HTT [OFF]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [OFF]
|- Turbo Boost TURBO <OFF>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [ ON]
|- Hypervisor [OFF]
Performance Monitoring
|- Version PM [ 4]
|- Counters: General Fixed
| 8 x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E <OFF>
|- C1 Auto Demotion C1A < ON>
|- C3 Auto Demotion C3A < ON>
|- C1 UnDemotion C1U < ON>
|- C3 UnDemotion C3U < ON>
|- Frequency ID control FID [OFF]
|- Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware-Controlled Performance States HWP < ON>
|- Capabilities (MHz) Ratio
Lowest 100.29 [ 1 ]
Efficient 802.29 [ 8 ]
Guaranteed 2808.00 [ 28 ]
Highest 2808.00 [ 28 ]
|- Hardware Duty Cycling HDC [ ON]
|- Package C-State
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT [ 2]
|- I/O MWAIT Redirection IOMWAIT [Disable]
|- Max C-State Inclusion RANGE [ 8]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 1 2 4 1 0 0
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Capable]
Power & Thermal
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint < 6>
|- Energy Policy HWP EPP < 128>
|- Junction Temperature TjMax [ 0:100]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Capable]
|- Package Thermal Management PTM [Capable]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [ 54]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Units
$ ./corefreq-cli -M
Controller #0 Single Channel
Bus Rate 8000 MT/s Bus Speed 8023 MT/s DRAM Speed 2133 MHz
Cha CL RCD RP RAS RRD RFC WR RTPr WTPr FAW B2B CWL Rate
#0 15 15 15 35 0 374 0 8 34 0 0 13 2N
ddWR drWR srWR ddRW drRW srRW ddRR drRR srRR ddWW drWW srWW ECC
#0 0 0 0 0 0 0 0 0 0 0 0 0 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 1 65536 1024 8192
$ ./corefreq-cli -B
[ 0] American Megatrends Inc.
[ 1] 0807
[ 2] 03/16/2018
[ 3] ASUSTeK COMPUTER INC.
[ 4] G11CD-K
[ 5] 0807
[ 6] H---C---0---
[ 7]
[ 8] Gaming
[ 9] G11CD-K
[10] Rev 1.xx
[11] 1---0---3---4--
$ ./corefreq-cli -k
Linux:
|- Release [5.7.6-arch1-1]
|- Version [#1 SMP PREEMPT Thu, 25 Jun 2020 00:14:47 +0000]
|- Machine [x86_64]
Memory:
|- Total RAM 8025204 KB
|- Shared RAM 117752 KB
|- Free RAM 7480612 KB
|- Buffer RAM 58948 KB
|- Total High 0 KB
|- Free High 0 KB
CPU-Freq driver [ intel_pstate]
Governor [ Missing]
CPU-Idle driver [ intel_idle]
|- Idle Limit [ C8]
|- State POLL C1 C1E C3 C6 C7s C8
|- CPUIDLE MWAIT 0 MWAIT 0 MWAIT 0 MWAIT 0 MWAIT 0 MWAIT 0
|- Power -1 0 0 0 0 0 0
|- Latency 0 2 10 70 85 124 200
|- Residency 0 2 20 100 200 800 800
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