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taiyoslime/cpu_7_4.v

Last active June 13, 2020 08:38
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ハードウェア設計論 課題7-4
Raw
cpu_7_4.v
module CPU(CK, RST, IA, ID, DA, DD, RW);
input CK, RST;
input [15:0] ID;
output RW;
output [15:0] IA, DA;
inout [15:0] DD;
reg FLAG, RW;
reg [1:0] STAGE;
reg [15:0] PC;
reg [15:0] INST;
reg [15:0] PCC, PCi;
reg [15:0] FUA, FUB, FUC;
reg [15:0] LSUA, LSUB, LSUC;
reg [15:0] RF[0:14];
wire [7:0] IMM;
wire [15:0] ABUS, BBUS, CBUS;
wire [3:0] OPCODE, OPR1, OPR2, OPR3;
wire [15:0] RF01, RF02, RF03, RF04, RF05;
assign RF00 = RF[0];
assign RF01 = RF[1];
assign RF02 = RF[2];
assign RF03 = RF[3];
assign RF04 = RF[4];
assign RF05 = RF[5];
assign RF06 = RF[6];
assign RF07 = RF[7];
assign RF08 = RF[8];
assign RF09 = RF[9];
assign RF10 = RF[10];
assign RF11 = RF[11];
assign RF12 = RF[12];
assign RF13 = RF[13];
assign RF14 = RF[14];
assign IA = PC;
assign OPCODE = INST[15:12];
assign OPR1 = INST[11:8];
assign OPR2 = INST[7:4];
assign OPR3 = INST[3:0];
assign IMM = INST[7:0];
assign DD = ((RW == 0)? LSUA : 'b z); // storeでrw<=0にして書き込む
assign DA = LSUB;
assign ABUS = (OPR2 != 0 ? RF[OPR2] : 0);
assign BBUS = (OPR3 != 0 ? RF[OPR3] : 0);
assign CBUS = (OPCODE[3] == 0 ? FUC : (OPCODE[3:1]=='b 101 ? LSUC : (OPCODE=='b 1100 ? {8'b 0,IMM} : OPCODE=='b 1000 ? PCC : 'b z)));
always @(posedge CK) begin
if (RST == 1) begin
PC <= 0;
STAGE <= 0;
RW <= 1;
end else begin
// Fetch
if(STAGE == 0) begin
INST <= ID;
STAGE <= 1;
// Decode
end else if(STAGE == 1) begin
if( OPCODE[3] == 0 ) begin // 0xxx
FUA <= ABUS;
FUB <= BBUS;
end
if( OPCODE[3:1] == 'b 101) begin // 101x
LSUA <= ABUS;
LSUB <= BBUS;
end
if( (OPCODE[3:0] == 'b 1000) || (OPCODE[3:0] == 'b 1001 && FLAG == 1)) begin
PCi <= BBUS;
end else begin
PCi <= PC + 1;
end
STAGE <= 2;
// Exec
end else if(STAGE == 2) begin
if ( OPCODE[3] == 0) begin // 0xxx
case (OPCODE[2:0])
'b 000: FUC <= FUA + FUB;
'b 001: FUC <= FUA - FUB;
'b 010: FUC <= FUA >> FUB;
'b 011: FUC <= FUA << FUB;
'b 100: FUC <= FUA | FUB;
'b 110: FUC <= ~FUA;
'b 111: FUC <= FUA ^ FUB;
endcase
end
if ( OPCODE[3:1] == 'b 101) begin //101x
if(OPCODE[0] == 1) begin
RW <= 1;
LSUC <= DD;
end else begin
RW <= 0;
// DD <= LSUA;
end
if (OPCODE[3:0] == 'b 1000) begin
PCC <= PC + 1;
end
end
STAGE <= 3;
// Write
end else if(STAGE == 3) begin
if( OPCODE[3] == 0) begin
if (CBUS == 0) FLAG <= 1;
else FLAG <= 0;
end
RF[OPR1] <= CBUS;
PC <= PCi;
RW <= 1;
STAGE <= 0;
// debug
// $monitor(PC, RF[0], RF[1],RF[2],RF[3], RF[4],RF[5], RF[6], RF[7], DD, DA, RW);
end
end
end
endmodule
Raw
simcpu_7_4.v
DMEM[0]= 17;
DMEM[1]= 19;
// 独自に書いたためスライドのものとやや違います
// 計算を保持するためのレジスタを確保，0初期化
IMEM[0]='b 1100_0001_0000_0000; // IMM R1, [0]
// DMEMからのロード
// R4にDMEMのアドレス0を書き込み，1011(LD)でR2にロード
IMEM[1]='b 1100_0100_0000_0000; // IMM R4, [0]
IMEM[2]='b 1011_0010_0000_0100; // LD R2, R4
// R4にDMEMのアドレス1を書き込み，1011(LD)でR3にロード
IMEM[3]='b 1100_0100_0000_0001; // IMM R4, [1]
IMEM[4]='b 1011_0011_0000_0100; // LD R3, R4
// ループ毎に減らす数 = 1 R4に保存
IMEM[5]='b 1100_0100_0000_0001; // IMM R4, [1]
// DA = 2として浮かせる
IMEM[6]='b 1100_0111_0000_0010; // IMM R7, [2]
// 繰り返し抜けのアドレス 13
IMEM[7]='b 1100_0101_0000_1101; // IMM R5, [13]
// 繰り返し先頭のアドレス 9
IMEM[8]='b 1100_0110_0000_1001; // IMM R6, [9] 繰り返し頭のアドレス
// 丁度R3回分R2をR1に追加する
//
// R1 = R1 + R2
IMEM[9]='b 0000_0001_0001_0010; // ADD R1, R1, R2
// R3 = R3 - R4（ループカウンタのデクリメント）
IMEM[10]='b 0001_0011_0011_0100; // SUB R3, R3, R4
// flag == 1，すなわち前の演算結果であるCBUSのデータが0 (=R3が0)の時にR5(=13)に飛ぶ
IMEM[11]='b 1001_0000_0000_0101; // BREAK flag, R5
// R6(=9)にジャンプ
IMEM[12]='b 1000_0000_0000_0110; // JMP R0, R6
IMEM[13]='b 1010_0000_0001_0111; // ST R1, R7
// テストベンチにて (DA == 'b 10 && DD == DMEM[0] * DMEM[1] && RW == 0) を終了条件とし実行した時の
// PC , RF[0] ~ RF[7], DD, DA, RW のダンプ結果は以下の通り
/*
1 x 0 x x x x x x x x 1
2 x 0 x x 0 x x x x x 1
2 x 0 x x 0 x x x x 0 1
2 x 0 x x 0 x x x 17 0 1
3 x 0 17 x 0 x x x 17 0 1
4 x 0 17 x 1 x x x 17 0 1
4 x 0 17 x 1 x x x 17 1 1
4 x 0 17 x 1 x x x 19 1 1
5 x 0 17 19 1 x x x 19 1 1
6 x 0 17 19 1 x x x 19 1 1
7 x 0 17 19 1 x x 2 19 1 1
8 x 0 17 19 1 13 x 2 19 1 1
9 x 0 17 19 1 13 9 2 19 1 1
10 x 17 17 19 1 13 9 2 19 1 1
11 x 17 17 18 1 13 9 2 19 1 1
12 z 17 17 18 1 13 9 2 19 1 1
9 x 17 17 18 1 13 9 2 19 1 1
10 x 34 17 18 1 13 9 2 19 1 1
11 x 34 17 17 1 13 9 2 19 1 1
12 z 34 17 17 1 13 9 2 19 1 1
9 x 34 17 17 1 13 9 2 19 1 1
10 x 51 17 17 1 13 9 2 19 1 1
11 x 51 17 16 1 13 9 2 19 1 1
12 z 51 17 16 1 13 9 2 19 1 1
9 x 51 17 16 1 13 9 2 19 1 1
10 x 68 17 16 1 13 9 2 19 1 1
11 x 68 17 15 1 13 9 2 19 1 1
12 z 68 17 15 1 13 9 2 19 1 1
9 x 68 17 15 1 13 9 2 19 1 1
10 x 85 17 15 1 13 9 2 19 1 1
11 x 85 17 14 1 13 9 2 19 1 1
12 z 85 17 14 1 13 9 2 19 1 1
9 x 85 17 14 1 13 9 2 19 1 1
10 x 102 17 14 1 13 9 2 19 1 1
11 x 102 17 13 1 13 9 2 19 1 1
12 z 102 17 13 1 13 9 2 19 1 1
9 x 102 17 13 1 13 9 2 19 1 1
10 x 119 17 13 1 13 9 2 19 1 1
11 x 119 17 12 1 13 9 2 19 1 1
12 z 119 17 12 1 13 9 2 19 1 1
9 x 119 17 12 1 13 9 2 19 1 1
10 x 136 17 12 1 13 9 2 19 1 1
11 x 136 17 11 1 13 9 2 19 1 1
12 z 136 17 11 1 13 9 2 19 1 1
9 x 136 17 11 1 13 9 2 19 1 1
10 x 153 17 11 1 13 9 2 19 1 1
11 x 153 17 10 1 13 9 2 19 1 1
12 z 153 17 10 1 13 9 2 19 1 1
9 x 153 17 10 1 13 9 2 19 1 1
10 x 170 17 10 1 13 9 2 19 1 1
11 x 170 17 9 1 13 9 2 19 1 1
12 z 170 17 9 1 13 9 2 19 1 1
9 x 170 17 9 1 13 9 2 19 1 1
10 x 187 17 9 1 13 9 2 19 1 1
11 x 187 17 8 1 13 9 2 19 1 1
12 z 187 17 8 1 13 9 2 19 1 1
9 x 187 17 8 1 13 9 2 19 1 1
10 x 204 17 8 1 13 9 2 19 1 1
11 x 204 17 7 1 13 9 2 19 1 1
12 z 204 17 7 1 13 9 2 19 1 1
9 x 204 17 7 1 13 9 2 19 1 1
10 x 221 17 7 1 13 9 2 19 1 1
11 x 221 17 6 1 13 9 2 19 1 1
12 z 221 17 6 1 13 9 2 19 1 1
9 x 221 17 6 1 13 9 2 19 1 1
10 x 238 17 6 1 13 9 2 19 1 1
11 x 238 17 5 1 13 9 2 19 1 1
12 z 238 17 5 1 13 9 2 19 1 1
9 x 238 17 5 1 13 9 2 19 1 1
10 x 255 17 5 1 13 9 2 19 1 1
11 x 255 17 4 1 13 9 2 19 1 1
12 z 255 17 4 1 13 9 2 19 1 1
9 x 255 17 4 1 13 9 2 19 1 1
10 x 272 17 4 1 13 9 2 19 1 1
11 x 272 17 3 1 13 9 2 19 1 1
12 z 272 17 3 1 13 9 2 19 1 1
9 x 272 17 3 1 13 9 2 19 1 1
10 x 289 17 3 1 13 9 2 19 1 1
11 x 289 17 2 1 13 9 2 19 1 1
12 z 289 17 2 1 13 9 2 19 1 1
9 x 289 17 2 1 13 9 2 19 1 1
10 x 306 17 2 1 13 9 2 19 1 1
11 x 306 17 1 1 13 9 2 19 1 1
12 z 306 17 1 1 13 9 2 19 1 1
9 x 306 17 1 1 13 9 2 19 1 1
10 x 323 17 1 1 13 9 2 19 1 1
11 x 323 17 0 1 13 9 2 19 1 1
13 z 323 17 0 1 13 9 2 19 1 1
13 z 323 17 0 1 13 9 2 19 2 1
13 z 323 17 0 1 13 9 2 x 2 1
13 z 323 17 0 1 13 9 2 323 2 0
*/
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