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tanakamura/build.tcl

Created May 13, 2016 13:03
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build.tcl
set output_dir ./out
file mkdir $output_dir
read_verilog top.v
synth_design -top top -part xc7z020clg484-1 -flatten rebuilt
opt_design
place_design
phys_opt_design
route_design
write_verilog -force $output_dir/netlist.v
write_xdc -no_fixed_only -force $output_dir/impl.xdc
write_bitstream -force $output_dir/result.bit
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