Verilog simulation by using iVerilog

iVerilog.mk

# Makefile for iVerilog testing
SRC_DIR := src
TEST_DIR := test
SIM_DIR := sim

TESTS := $(sort $(patsubst $(TEST_DIR)/%.v,$(SIM_DIR)/%.vcd,$(wildcard $(TEST_DIR)/test_*.v)))
VERILOGS := $(sort $(wildcard $(SRC_DIR)/*.v))

.PHONY: $(SIM_DIR)/test_%.sim
$(SIM_DIR)/test_%.sim: $(TEST_DIR)/test_%.v
	iverilog -o $@ -s test_$* $< $(VERILOGS)

.PHONY: $(SIM_DIR)/test_%.vcd
$(SIM_DIR)/test_%.vcd: $(SIM_DIR)/test_%.sim
	vvp -l $(patsubst %.sim,%.log,$<) $<

.PHONY: all
all: test

.PHONY: test
test: $(TESTS)

.PHONY: wave
%: $(SIM_DIR)/test_%.vcd
	gtkwave $< &

.PHONY: clean
clean:
	rm -rf sim/*.sim sim/test_*.vcd sim/*.log