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tannergooding/JitDump_CreateElement.UInt16_Diff.txt

Created January 7, 2019 18:23
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JitDump_CreateElement.UInt16_Diff.txt
Beginning test case CreateElement.UInt16 at 1/7/2019 10:23:08 AM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro
Beginning scenario: RunBasicScenario
****** START compiling System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct (MethodHash=1e6cb80c)
Generating code for Windows x86
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Stack probing is DISABLED
IL to import:
IL_0000 28 d3 40 00 06 call 0x60040D3
IL_0005 2c 4a brfalse.s 74 (IL_0051)
IL_0007 02 ldarg.0
IL_0008 28 38 3c 00 06 call 0x6003C38
IL_000d 0a stloc.0
IL_000e 06 ldloc.0
IL_000f 03 ldarg.1
IL_0010 17 ldc.i4.1
IL_0011 28 3b 41 00 06 call 0x600413B
IL_0016 0a stloc.0
IL_0017 06 ldloc.0
IL_0018 04 ldarg.2
IL_0019 18 ldc.i4.2
IL_001a 28 3b 41 00 06 call 0x600413B
IL_001f 0a stloc.0
IL_0020 06 ldloc.0
IL_0021 05 ldarg.3
IL_0022 19 ldc.i4.3
IL_0023 28 3b 41 00 06 call 0x600413B
IL_0028 0a stloc.0
IL_0029 06 ldloc.0
IL_002a 0e 04 ldarg.s 0x4
IL_002c 1a ldc.i4.4
IL_002d 28 3b 41 00 06 call 0x600413B
IL_0032 0a stloc.0
IL_0033 06 ldloc.0
IL_0034 0e 05 ldarg.s 0x5
IL_0036 1b ldc.i4.5
IL_0037 28 3b 41 00 06 call 0x600413B
IL_003c 0a stloc.0
IL_003d 06 ldloc.0
IL_003e 0e 06 ldarg.s 0x6
IL_0040 1c ldc.i4.6
IL_0041 28 3b 41 00 06 call 0x600413B
IL_0046 0a stloc.0
IL_0047 06 ldloc.0
IL_0048 0e 07 ldarg.s 0x7
IL_004a 1d ldc.i4.7
IL_004b 28 3b 41 00 06 call 0x600413B
IL_0050 2a ret
IL_0051 02 ldarg.0
IL_0052 03 ldarg.1
IL_0053 04 ldarg.2
IL_0054 05 ldarg.3
IL_0055 0e 04 ldarg.s 0x4
IL_0057 0e 05 ldarg.s 0x5
IL_0059 0e 06 ldarg.s 0x6
IL_005b 0e 07 ldarg.s 0x7
IL_005d 28 4c 3c 00 06 call 0x6003C4C
IL_0062 2a ret
HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type UInt16
Found type Hardware Intrinsic SIMD Vector128<ushort>
Known type Vector128<ushort>
'__retBuf' passed in register ecx
Arg #1 passed in register(s) edx
Known type Vector128<ushort>
; Initial local variable assignments
;
; V00 RetBuf byref
; V01 arg0 ushort
; V02 arg1 ushort
; V03 arg2 ushort
; V04 arg3 ushort
; V05 arg4 ushort
; V06 arg5 ushort
; V07 arg6 ushort
; V08 arg7 ushort
; V09 loc0 simd16
*************** In compInitDebuggingInfo() for System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 10
VarNum LVNum Name Beg End
0: 00h 00h V00 RetBuf 000h 063h
1: 01h 01h V01 arg0 000h 063h
2: 02h 02h V02 arg1 000h 063h
3: 03h 03h V03 arg2 000h 063h
4: 04h 04h V04 arg3 000h 063h
5: 05h 05h V05 arg4 000h 063h
6: 06h 06h V06 arg5 000h 063h
7: 07h 07h V07 arg6 000h 063h
8: 08h 08h V08 arg7 000h 063h
9: 09h 09h V09 loc0 000h 063h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct
Jump targets:
IL_0051
New Basic Block BB01 [0000] created.
BB01 [000..007)
New Basic Block BB02 [0001] created.
BB02 [007..051)
New Basic Block BB03 [0002] created.
BB03 [051..063)
CLFLG_MINOPT set for method System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct
IL Code Size,Instr 99, 50, Basic Block count 3, Local Variable Num,Ref count 10, 30 for method System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct
IL Code Size,Instr 99, 50, Basic Block count 3, Local Variable Num,Ref count 10, 30 for method System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct
OPTIONS: opts.MinOpts() == true
Basic block list for 'System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond )
BB02 [0001] 1 1 [007..051) (return)
BB03 [0002] 1 1 [051..063) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct'
[ 0] 0 (0x000) call 060040D3
In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0
[ 1] 5 (0x005) brfalse.s
[000005] ------------ * STMT void (IL 0x000... ???)
[000004] ------------ \--* JTRUE void
[000002] ------------ | /--* CNS_INT int 0
[000003] ------------ \--* EQ int
[000001] ------------ \--* CNS_INT int 1
impImportBlockPending for BB02
impImportBlockPending for BB03
Importing BB03 (PC=081) of 'System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct'
[ 0] 81 (0x051) ldarg.0
[ 1] 82 (0x052) ldarg.1
[ 2] 83 (0x053) ldarg.2
[ 3] 84 (0x054) ldarg.3
[ 4] 85 (0x055) ldarg.s 4
[ 5] 87 (0x057) ldarg.s 5
[ 6] 89 (0x059) ldarg.s 6
[ 7] 91 (0x05b) ldarg.s 7
[ 8] 93 (0x05d) call 06003C4C
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Known type Vector128<ushort>
[ 1] 98 (0x062) ret
[000026] ------------ * STMT void (IL 0x051... ???)
[000015] S-C-G------- \--* CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
[000024] ------------ arg0 +--* LCL_VAR byref V00 RetBuf
[000007] ------------ arg1 +--* LCL_VAR ushort V01 arg0
[000008] ------------ arg2 +--* LCL_VAR ushort V02 arg1
[000009] ------------ arg3 +--* LCL_VAR ushort V03 arg2
[000010] ------------ arg4 +--* LCL_VAR ushort V04 arg3
[000011] ------------ arg5 +--* LCL_VAR ushort V05 arg4
[000012] ------------ arg6 +--* LCL_VAR ushort V06 arg5
[000013] ------------ arg7 +--* LCL_VAR ushort V07 arg6
[000014] ------------ arg8 \--* LCL_VAR ushort V08 arg7
[000028] ------------ * STMT void (IL ???... ???)
[000027] ------------ \--* RETURN void
Importing BB02 (PC=007) of 'System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct'
[ 0] 7 (0x007) ldarg.0
[ 1] 8 (0x008) call 06003C38
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Known type Vector128<ushort>
[ 1] 13 (0x00d) stloc.0
[000035] ------------ * STMT void (IL 0x007... ???)
[000031] ------------ | /--* HWIntrinsic simd16 ushort CreateScalarUnsafe
[000030] ------------ | | \--* LCL_VAR ushort V01 arg0
[000034] -A---------- \--* ASG simd16 (copy)
[000032] D----------- \--* LCL_VAR simd16 V09 loc0
[ 0] 14 (0x00e) ldloc.0
[ 1] 15 (0x00f) ldarg.1
[ 2] 16 (0x010) ldc.i4.1 1
[ 3] 17 (0x011) call 0600413B
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Known type Vector128<ushort>
Known type Vector128<ushort>
[ 1] 22 (0x016) stloc.0
[000046] ------------ * STMT void (IL 0x00E... ???)
[000042] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000039] ------------ | | | /--* LIST void
[000038] ------------ | | | | \--* CNS_INT int 1
[000040] ------------ | | | /--* LIST void
[000037] ------------ | | | | \--* LCL_VAR ushort V02 arg1
[000041] ------------ | | \--* LIST void
[000036] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000045] -A---------- \--* ASG simd16 (copy)
[000043] D----------- \--* LCL_VAR simd16 V09 loc0
[ 0] 23 (0x017) ldloc.0
[ 1] 24 (0x018) ldarg.2
[ 2] 25 (0x019) ldc.i4.2 2
[ 3] 26 (0x01a) call 0600413B
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Known type Vector128<ushort>
Known type Vector128<ushort>
[ 1] 31 (0x01f) stloc.0
[000057] ------------ * STMT void (IL 0x017... ???)
[000053] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000050] ------------ | | | /--* LIST void
[000049] ------------ | | | | \--* CNS_INT int 2
[000051] ------------ | | | /--* LIST void
[000048] ------------ | | | | \--* LCL_VAR ushort V03 arg2
[000052] ------------ | | \--* LIST void
[000047] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000056] -A---------- \--* ASG simd16 (copy)
[000054] D----------- \--* LCL_VAR simd16 V09 loc0
[ 0] 32 (0x020) ldloc.0
[ 1] 33 (0x021) ldarg.3
[ 2] 34 (0x022) ldc.i4.3 3
[ 3] 35 (0x023) call 0600413B
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Known type Vector128<ushort>
Known type Vector128<ushort>
[ 1] 40 (0x028) stloc.0
[000068] ------------ * STMT void (IL 0x020... ???)
[000064] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000061] ------------ | | | /--* LIST void
[000060] ------------ | | | | \--* CNS_INT int 3
[000062] ------------ | | | /--* LIST void
[000059] ------------ | | | | \--* LCL_VAR ushort V04 arg3
[000063] ------------ | | \--* LIST void
[000058] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000067] -A---------- \--* ASG simd16 (copy)
[000065] D----------- \--* LCL_VAR simd16 V09 loc0
[ 0] 41 (0x029) ldloc.0
[ 1] 42 (0x02a) ldarg.s 4
[ 2] 44 (0x02c) ldc.i4.4 4
[ 3] 45 (0x02d) call 0600413B
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Known type Vector128<ushort>
Known type Vector128<ushort>
[ 1] 50 (0x032) stloc.0
[000079] ------------ * STMT void (IL 0x029... ???)
[000075] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000072] ------------ | | | /--* LIST void
[000071] ------------ | | | | \--* CNS_INT int 4
[000073] ------------ | | | /--* LIST void
[000070] ------------ | | | | \--* LCL_VAR ushort V05 arg4
[000074] ------------ | | \--* LIST void
[000069] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000078] -A---------- \--* ASG simd16 (copy)
[000076] D----------- \--* LCL_VAR simd16 V09 loc0
[ 0] 51 (0x033) ldloc.0
[ 1] 52 (0x034) ldarg.s 5
[ 2] 54 (0x036) ldc.i4.5 5
[ 3] 55 (0x037) call 0600413B
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Known type Vector128<ushort>
Known type Vector128<ushort>
[ 1] 60 (0x03c) stloc.0
[000090] ------------ * STMT void (IL 0x033... ???)
[000086] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000083] ------------ | | | /--* LIST void
[000082] ------------ | | | | \--* CNS_INT int 5
[000084] ------------ | | | /--* LIST void
[000081] ------------ | | | | \--* LCL_VAR ushort V06 arg5
[000085] ------------ | | \--* LIST void
[000080] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000089] -A---------- \--* ASG simd16 (copy)
[000087] D----------- \--* LCL_VAR simd16 V09 loc0
[ 0] 61 (0x03d) ldloc.0
[ 1] 62 (0x03e) ldarg.s 6
[ 2] 64 (0x040) ldc.i4.6 6
[ 3] 65 (0x041) call 0600413B
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Known type Vector128<ushort>
Known type Vector128<ushort>
[ 1] 70 (0x046) stloc.0
[000101] ------------ * STMT void (IL 0x03D... ???)
[000097] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000094] ------------ | | | /--* LIST void
[000093] ------------ | | | | \--* CNS_INT int 6
[000095] ------------ | | | /--* LIST void
[000092] ------------ | | | | \--* LCL_VAR ushort V07 arg6
[000096] ------------ | | \--* LIST void
[000091] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000100] -A---------- \--* ASG simd16 (copy)
[000098] D----------- \--* LCL_VAR simd16 V09 loc0
[ 0] 71 (0x047) ldloc.0
[ 1] 72 (0x048) ldarg.s 7
[ 2] 74 (0x04a) ldc.i4.7 7
[ 3] 75 (0x04b) call 0600413B
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Known type Vector128<ushort>
Known type Vector128<ushort>
[ 1] 80 (0x050) ret
[000112] ------------ * STMT void (IL 0x047... ???)
[000108] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000105] ------------ | | | /--* LIST void
[000104] ------------ | | | | \--* CNS_INT int 7
[000106] ------------ | | | /--* LIST void
[000103] ------------ | | | | \--* LCL_VAR ushort V08 arg7
[000107] ------------ | | \--* LIST void
[000102] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000111] -A---------- \--* ASG simd16 (copy)
[000110] ------------ \--* BLK(16) simd16
[000109] ------------ \--* LCL_VAR byref V00 RetBuf
[000114] ------------ * STMT void (IL ???... ???)
[000113] ------------ \--* RETURN void
*************** in fgTransformIndirectCalls(root)
-- no candidates to transform
New BlockSet epoch 1, # of blocks (including unused BB00): 4, bitset array size: 1 (short)
*************** In fgMorph()
*************** In fgDebugCheckBBlist
*************** In Allocate Objects
Trees before Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i
BB02 [0001] 1 1 [007..051) (return) i
BB03 [0002] 1 1 [051..063) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000005] ------------ * STMT void (IL 0x000...0x005)
[000004] ------------ \--* JTRUE void
[000002] ------------ | /--* CNS_INT int 0
[000003] ------------ \--* EQ int
[000001] ------------ \--* CNS_INT int 1
------------ BB02 [007..051) (return), preds={} succs={}
***** BB02, stmt 2
[000035] ------------ * STMT void (IL 0x007...0x00D)
[000031] ------------ | /--* HWIntrinsic simd16 ushort CreateScalarUnsafe
[000030] ------------ | | \--* LCL_VAR ushort V01 arg0
[000034] -A---------- \--* ASG simd16 (copy)
[000032] D----------- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 3
[000046] ------------ * STMT void (IL 0x00E...0x016)
[000042] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000039] ------------ | | | /--* LIST void
[000038] ------------ | | | | \--* CNS_INT int 1
[000040] ------------ | | | /--* LIST void
[000037] ------------ | | | | \--* LCL_VAR ushort V02 arg1
[000041] ------------ | | \--* LIST void
[000036] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000045] -A---------- \--* ASG simd16 (copy)
[000043] D----------- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 4
[000057] ------------ * STMT void (IL 0x017...0x01F)
[000053] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000050] ------------ | | | /--* LIST void
[000049] ------------ | | | | \--* CNS_INT int 2
[000051] ------------ | | | /--* LIST void
[000048] ------------ | | | | \--* LCL_VAR ushort V03 arg2
[000052] ------------ | | \--* LIST void
[000047] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000056] -A---------- \--* ASG simd16 (copy)
[000054] D----------- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 5
[000068] ------------ * STMT void (IL 0x020...0x028)
[000064] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000061] ------------ | | | /--* LIST void
[000060] ------------ | | | | \--* CNS_INT int 3
[000062] ------------ | | | /--* LIST void
[000059] ------------ | | | | \--* LCL_VAR ushort V04 arg3
[000063] ------------ | | \--* LIST void
[000058] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000067] -A---------- \--* ASG simd16 (copy)
[000065] D----------- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 6
[000079] ------------ * STMT void (IL 0x029...0x032)
[000075] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000072] ------------ | | | /--* LIST void
[000071] ------------ | | | | \--* CNS_INT int 4
[000073] ------------ | | | /--* LIST void
[000070] ------------ | | | | \--* LCL_VAR ushort V05 arg4
[000074] ------------ | | \--* LIST void
[000069] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000078] -A---------- \--* ASG simd16 (copy)
[000076] D----------- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 7
[000090] ------------ * STMT void (IL 0x033...0x03C)
[000086] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000083] ------------ | | | /--* LIST void
[000082] ------------ | | | | \--* CNS_INT int 5
[000084] ------------ | | | /--* LIST void
[000081] ------------ | | | | \--* LCL_VAR ushort V06 arg5
[000085] ------------ | | \--* LIST void
[000080] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000089] -A---------- \--* ASG simd16 (copy)
[000087] D----------- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 8
[000101] ------------ * STMT void (IL 0x03D...0x046)
[000097] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000094] ------------ | | | /--* LIST void
[000093] ------------ | | | | \--* CNS_INT int 6
[000095] ------------ | | | /--* LIST void
[000092] ------------ | | | | \--* LCL_VAR ushort V07 arg6
[000096] ------------ | | \--* LIST void
[000091] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000100] -A---------- \--* ASG simd16 (copy)
[000098] D----------- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 9
[000112] ------------ * STMT void (IL 0x047...0x050)
[000108] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000105] ------------ | | | /--* LIST void
[000104] ------------ | | | | \--* CNS_INT int 7
[000106] ------------ | | | /--* LIST void
[000103] ------------ | | | | \--* LCL_VAR ushort V08 arg7
[000107] ------------ | | \--* LIST void
[000102] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000111] -A---------- \--* ASG simd16 (copy)
[000110] ------------ \--* BLK(16) simd16
[000109] ------------ \--* LCL_VAR byref V00 RetBuf
***** BB02, stmt 10
[000114] ------------ * STMT void (IL ???... ???)
[000113] ------------ \--* RETURN void
------------ BB03 [051..063) (return), preds={} succs={}
***** BB03, stmt 11
[000026] ------------ * STMT void (IL 0x051...0x062)
[000015] S-C-G------- \--* CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
[000024] ------------ arg0 +--* LCL_VAR byref V00 RetBuf
[000007] ------------ arg1 +--* LCL_VAR ushort V01 arg0
[000008] ------------ arg2 +--* LCL_VAR ushort V02 arg1
[000009] ------------ arg3 +--* LCL_VAR ushort V03 arg2
[000010] ------------ arg4 +--* LCL_VAR ushort V04 arg3
[000011] ------------ arg5 +--* LCL_VAR ushort V05 arg4
[000012] ------------ arg6 +--* LCL_VAR ushort V06 arg5
[000013] ------------ arg7 +--* LCL_VAR ushort V07 arg6
[000014] ------------ arg8 \--* LCL_VAR ushort V08 arg7
***** BB03, stmt 12
[000028] ------------ * STMT void (IL ???... ???)
[000027] ------------ \--* RETURN void
-------------------------------------------------------------------------------------------------------------------
*** ObjectAllocationPhase: no newobjs in this method; punting
*************** Exiting Allocate Objects
Trees after Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i
BB02 [0001] 1 1 [007..051) (return) i
BB03 [0002] 1 1 [051..063) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000005] ------------ * STMT void (IL 0x000...0x005)
[000004] ------------ \--* JTRUE void
[000002] ------------ | /--* CNS_INT int 0
[000003] ------------ \--* EQ int
[000001] ------------ \--* CNS_INT int 1
------------ BB02 [007..051) (return), preds={} succs={}
***** BB02, stmt 2
[000035] ------------ * STMT void (IL 0x007...0x00D)
[000031] ------------ | /--* HWIntrinsic simd16 ushort CreateScalarUnsafe
[000030] ------------ | | \--* LCL_VAR ushort V01 arg0
[000034] -A---------- \--* ASG simd16 (copy)
[000032] D----------- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 3
[000046] ------------ * STMT void (IL 0x00E...0x016)
[000042] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000039] ------------ | | | /--* LIST void
[000038] ------------ | | | | \--* CNS_INT int 1
[000040] ------------ | | | /--* LIST void
[000037] ------------ | | | | \--* LCL_VAR ushort V02 arg1
[000041] ------------ | | \--* LIST void
[000036] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000045] -A---------- \--* ASG simd16 (copy)
[000043] D----------- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 4
[000057] ------------ * STMT void (IL 0x017...0x01F)
[000053] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000050] ------------ | | | /--* LIST void
[000049] ------------ | | | | \--* CNS_INT int 2
[000051] ------------ | | | /--* LIST void
[000048] ------------ | | | | \--* LCL_VAR ushort V03 arg2
[000052] ------------ | | \--* LIST void
[000047] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000056] -A---------- \--* ASG simd16 (copy)
[000054] D----------- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 5
[000068] ------------ * STMT void (IL 0x020...0x028)
[000064] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000061] ------------ | | | /--* LIST void
[000060] ------------ | | | | \--* CNS_INT int 3
[000062] ------------ | | | /--* LIST void
[000059] ------------ | | | | \--* LCL_VAR ushort V04 arg3
[000063] ------------ | | \--* LIST void
[000058] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000067] -A---------- \--* ASG simd16 (copy)
[000065] D----------- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 6
[000079] ------------ * STMT void (IL 0x029...0x032)
[000075] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000072] ------------ | | | /--* LIST void
[000071] ------------ | | | | \--* CNS_INT int 4
[000073] ------------ | | | /--* LIST void
[000070] ------------ | | | | \--* LCL_VAR ushort V05 arg4
[000074] ------------ | | \--* LIST void
[000069] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000078] -A---------- \--* ASG simd16 (copy)
[000076] D----------- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 7
[000090] ------------ * STMT void (IL 0x033...0x03C)
[000086] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000083] ------------ | | | /--* LIST void
[000082] ------------ | | | | \--* CNS_INT int 5
[000084] ------------ | | | /--* LIST void
[000081] ------------ | | | | \--* LCL_VAR ushort V06 arg5
[000085] ------------ | | \--* LIST void
[000080] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000089] -A---------- \--* ASG simd16 (copy)
[000087] D----------- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 8
[000101] ------------ * STMT void (IL 0x03D...0x046)
[000097] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000094] ------------ | | | /--* LIST void
[000093] ------------ | | | | \--* CNS_INT int 6
[000095] ------------ | | | /--* LIST void
[000092] ------------ | | | | \--* LCL_VAR ushort V07 arg6
[000096] ------------ | | \--* LIST void
[000091] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000100] -A---------- \--* ASG simd16 (copy)
[000098] D----------- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 9
[000112] ------------ * STMT void (IL 0x047...0x050)
[000108] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000105] ------------ | | | /--* LIST void
[000104] ------------ | | | | \--* CNS_INT int 7
[000106] ------------ | | | /--* LIST void
[000103] ------------ | | | | \--* LCL_VAR ushort V08 arg7
[000107] ------------ | | \--* LIST void
[000102] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000111] -A---------- \--* ASG simd16 (copy)
[000110] ------------ \--* BLK(16) simd16
[000109] ------------ \--* LCL_VAR byref V00 RetBuf
***** BB02, stmt 10
[000114] ------------ * STMT void (IL ???... ???)
[000113] ------------ \--* RETURN void
------------ BB03 [051..063) (return), preds={} succs={}
***** BB03, stmt 11
[000026] ------------ * STMT void (IL 0x051...0x062)
[000015] S-C-G------- \--* CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
[000024] ------------ arg0 +--* LCL_VAR byref V00 RetBuf
[000007] ------------ arg1 +--* LCL_VAR ushort V01 arg0
[000008] ------------ arg2 +--* LCL_VAR ushort V02 arg1
[000009] ------------ arg3 +--* LCL_VAR ushort V03 arg2
[000010] ------------ arg4 +--* LCL_VAR ushort V04 arg3
[000011] ------------ arg5 +--* LCL_VAR ushort V05 arg4
[000012] ------------ arg6 +--* LCL_VAR ushort V06 arg5
[000013] ------------ arg7 +--* LCL_VAR ushort V07 arg6
[000014] ------------ arg8 \--* LCL_VAR ushort V08 arg7
***** BB03, stmt 12
[000028] ------------ * STMT void (IL ???... ???)
[000027] ------------ \--* RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** After fgAddInternal()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i
BB02 [0001] 1 1 [007..051) (return) i
BB03 [0002] 1 1 [051..063) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** In fgCloneFinally()
No EH in this method, no cloning.
*************** In fgPromoteStructs()
promotion opt flag not enabled
*************** In fgMarkAddressExposedLocals()
LocalAddressVisitor visiting statement:
[000005] ------------ * STMT void (IL 0x000...0x005)
[000004] ------------ \--* JTRUE void
[000002] ------------ | /--* CNS_INT int 0
[000003] ------------ \--* EQ int
[000001] ------------ \--* CNS_INT int 1
LocalAddressVisitor visiting statement:
[000035] ------------ * STMT void (IL 0x007...0x00D)
[000031] ------------ | /--* HWIntrinsic simd16 ushort CreateScalarUnsafe
[000030] ------------ | | \--* LCL_VAR ushort V01 arg0
[000034] -A---------- \--* ASG simd16 (copy)
[000032] D----------- \--* LCL_VAR simd16 V09 loc0
LocalAddressVisitor visiting statement:
[000046] ------------ * STMT void (IL 0x00E...0x016)
[000042] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000039] ------------ | | | /--* LIST void
[000038] ------------ | | | | \--* CNS_INT int 1
[000040] ------------ | | | /--* LIST void
[000037] ------------ | | | | \--* LCL_VAR ushort V02 arg1
[000041] ------------ | | \--* LIST void
[000036] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000045] -A---------- \--* ASG simd16 (copy)
[000043] D----------- \--* LCL_VAR simd16 V09 loc0
LocalAddressVisitor visiting statement:
[000057] ------------ * STMT void (IL 0x017...0x01F)
[000053] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000050] ------------ | | | /--* LIST void
[000049] ------------ | | | | \--* CNS_INT int 2
[000051] ------------ | | | /--* LIST void
[000048] ------------ | | | | \--* LCL_VAR ushort V03 arg2
[000052] ------------ | | \--* LIST void
[000047] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000056] -A---------- \--* ASG simd16 (copy)
[000054] D----------- \--* LCL_VAR simd16 V09 loc0
LocalAddressVisitor visiting statement:
[000068] ------------ * STMT void (IL 0x020...0x028)
[000064] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000061] ------------ | | | /--* LIST void
[000060] ------------ | | | | \--* CNS_INT int 3
[000062] ------------ | | | /--* LIST void
[000059] ------------ | | | | \--* LCL_VAR ushort V04 arg3
[000063] ------------ | | \--* LIST void
[000058] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000067] -A---------- \--* ASG simd16 (copy)
[000065] D----------- \--* LCL_VAR simd16 V09 loc0
LocalAddressVisitor visiting statement:
[000079] ------------ * STMT void (IL 0x029...0x032)
[000075] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000072] ------------ | | | /--* LIST void
[000071] ------------ | | | | \--* CNS_INT int 4
[000073] ------------ | | | /--* LIST void
[000070] ------------ | | | | \--* LCL_VAR ushort V05 arg4
[000074] ------------ | | \--* LIST void
[000069] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000078] -A---------- \--* ASG simd16 (copy)
[000076] D----------- \--* LCL_VAR simd16 V09 loc0
LocalAddressVisitor visiting statement:
[000090] ------------ * STMT void (IL 0x033...0x03C)
[000086] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000083] ------------ | | | /--* LIST void
[000082] ------------ | | | | \--* CNS_INT int 5
[000084] ------------ | | | /--* LIST void
[000081] ------------ | | | | \--* LCL_VAR ushort V06 arg5
[000085] ------------ | | \--* LIST void
[000080] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000089] -A---------- \--* ASG simd16 (copy)
[000087] D----------- \--* LCL_VAR simd16 V09 loc0
LocalAddressVisitor visiting statement:
[000101] ------------ * STMT void (IL 0x03D...0x046)
[000097] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000094] ------------ | | | /--* LIST void
[000093] ------------ | | | | \--* CNS_INT int 6
[000095] ------------ | | | /--* LIST void
[000092] ------------ | | | | \--* LCL_VAR ushort V07 arg6
[000096] ------------ | | \--* LIST void
[000091] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000100] -A---------- \--* ASG simd16 (copy)
[000098] D----------- \--* LCL_VAR simd16 V09 loc0
LocalAddressVisitor visiting statement:
[000112] ------------ * STMT void (IL 0x047...0x050)
[000108] ------------ | /--* HWIntrinsic simd16 ushort Insert
[000105] ------------ | | | /--* LIST void
[000104] ------------ | | | | \--* CNS_INT int 7
[000106] ------------ | | | /--* LIST void
[000103] ------------ | | | | \--* LCL_VAR ushort V08 arg7
[000107] ------------ | | \--* LIST void
[000102] ------------ | | \--* LCL_VAR simd16 V09 loc0
[000111] -A---------- \--* ASG simd16 (copy)
[000110] ------------ \--* BLK(16) simd16
[000109] ------------ \--* LCL_VAR byref V00 RetBuf
LocalAddressVisitor visiting statement:
[000114] ------------ * STMT void (IL ???... ???)
[000113] ------------ \--* RETURN void
LocalAddressVisitor visiting statement:
[000026] ------------ * STMT void (IL 0x051...0x062)
[000015] S-C-G------- \--* CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
[000024] ------------ arg0 +--* LCL_VAR byref V00 RetBuf
[000007] ------------ arg1 +--* LCL_VAR ushort V01 arg0
[000008] ------------ arg2 +--* LCL_VAR ushort V02 arg1
[000009] ------------ arg3 +--* LCL_VAR ushort V03 arg2
[000010] ------------ arg4 +--* LCL_VAR ushort V04 arg3
[000011] ------------ arg5 +--* LCL_VAR ushort V05 arg4
[000012] ------------ arg6 +--* LCL_VAR ushort V06 arg5
[000013] ------------ arg7 +--* LCL_VAR ushort V07 arg6
[000014] ------------ arg8 \--* LCL_VAR ushort V08 arg7
LocalAddressVisitor visiting statement:
[000028] ------------ * STMT void (IL ???... ???)
[000027] ------------ \--* RETURN void
*************** In fgMorphBlocks()
Morphing BB01 of 'System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct'
fgMorphTree BB01, stmt 1 (before)
[000004] ------------ * JTRUE void
[000002] ------------ | /--* CNS_INT int 0
[000003] ------------ \--* EQ int
[000001] ------------ \--* CNS_INT int 1
Morphing BB02 of 'System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct'
fgMorphTree BB02, stmt 2 (before)
[000031] ------------ /--* HWIntrinsic simd16 ushort CreateScalarUnsafe
[000030] ------------ | \--* LCL_VAR ushort V01 arg0
[000034] -A---------- * ASG simd16 (copy)
[000032] D----------- \--* LCL_VAR simd16 V09 loc0
fgMorphCopyBlock:block assignment to morph:
[000031] -----+------ /--* HWIntrinsic simd16 ushort CreateScalarUnsafe
[000115] -----+------ | \--* CAST int <- ushort <- int
[000030] -----+------ | \--* LCL_VAR int V01 arg0
[000034] -A---------- * ASG simd16 (copy)
[000032] D----+-N---- \--* LCL_VAR simd16 V09 loc0
with no promoted structs this requires a CopyBlock.
Local V09 should not be enregistered because: written in a block op
fgMorphTree BB02, stmt 2 (after)
[000031] -----+------ /--* HWIntrinsic simd16 ushort CreateScalarUnsafe
[000115] -----+------ | \--* CAST int <- ushort <- int
[000030] -----+------ | \--* LCL_VAR int V01 arg0
[000034] -A---+------ * ASG simd16 (copy)
[000032] D----+-N---- \--* LCL_VAR simd16 V09 loc0
fgMorphTree BB02, stmt 3 (before)
[000042] ------------ /--* HWIntrinsic simd16 ushort Insert
[000039] ------------ | | /--* LIST void
[000038] ------------ | | | \--* CNS_INT int 1
[000040] ------------ | | /--* LIST void
[000037] ------------ | | | \--* LCL_VAR ushort V02 arg1
[000041] ------------ | \--* LIST void
[000036] ------------ | \--* LCL_VAR simd16 V09 loc0
[000045] -A---------- * ASG simd16 (copy)
[000043] D----------- \--* LCL_VAR simd16 V09 loc0
fgMorphCopyBlock:block assignment to morph:
[000042] -----+------ /--* HWIntrinsic simd16 ushort Insert
[000039] ------------ | | /--* LIST void
[000038] -----+------ | | | \--* CNS_INT int 1
[000040] ------------ | | /--* LIST void
[000116] -----+------ | | | \--* CAST int <- ushort <- int
[000037] -----+------ | | | \--* LCL_VAR int V02 arg1
[000041] -----+------ | \--* LIST void
[000036] -----+------ | \--* LCL_VAR simd16 V09 loc0
[000045] -A---------- * ASG simd16 (copy)
[000043] D----+-N---- \--* LCL_VAR simd16 V09 loc0
with no promoted structs this requires a CopyBlock.
Local V09 should not be enregistered because: written in a block op
fgMorphTree BB02, stmt 3 (after)
[000042] -----+------ /--* HWIntrinsic simd16 ushort Insert
[000039] ------------ | | /--* LIST void
[000038] -----+------ | | | \--* CNS_INT int 1
[000040] ------------ | | /--* LIST void
[000116] -----+------ | | | \--* CAST int <- ushort <- int
[000037] -----+------ | | | \--* LCL_VAR int V02 arg1
[000041] -----+------ | \--* LIST void
[000036] -----+------ | \--* LCL_VAR simd16 V09 loc0
[000045] -A---+------ * ASG simd16 (copy)
[000043] D----+-N---- \--* LCL_VAR simd16 V09 loc0
fgMorphTree BB02, stmt 4 (before)
[000053] ------------ /--* HWIntrinsic simd16 ushort Insert
[000050] ------------ | | /--* LIST void
[000049] ------------ | | | \--* CNS_INT int 2
[000051] ------------ | | /--* LIST void
[000048] ------------ | | | \--* LCL_VAR ushort V03 arg2
[000052] ------------ | \--* LIST void
[000047] ------------ | \--* LCL_VAR simd16 V09 loc0
[000056] -A---------- * ASG simd16 (copy)
[000054] D----------- \--* LCL_VAR simd16 V09 loc0
fgMorphCopyBlock:block assignment to morph:
[000053] -----+------ /--* HWIntrinsic simd16 ushort Insert
[000050] ------------ | | /--* LIST void
[000049] -----+------ | | | \--* CNS_INT int 2
[000051] ------------ | | /--* LIST void
[000117] -----+------ | | | \--* CAST int <- ushort <- int
[000048] -----+------ | | | \--* LCL_VAR int V03 arg2
[000052] -----+------ | \--* LIST void
[000047] -----+------ | \--* LCL_VAR simd16 V09 loc0
[000056] -A---------- * ASG simd16 (copy)
[000054] D----+-N---- \--* LCL_VAR simd16 V09 loc0
with no promoted structs this requires a CopyBlock.
Local V09 should not be enregistered because: written in a block op
fgMorphTree BB02, stmt 4 (after)
[000053] -----+------ /--* HWIntrinsic simd16 ushort Insert
[000050] ------------ | | /--* LIST void
[000049] -----+------ | | | \--* CNS_INT int 2
[000051] ------------ | | /--* LIST void
[000117] -----+------ | | | \--* CAST int <- ushort <- int
[000048] -----+------ | | | \--* LCL_VAR int V03 arg2
[000052] -----+------ | \--* LIST void
[000047] -----+------ | \--* LCL_VAR simd16 V09 loc0
[000056] -A---+------ * ASG simd16 (copy)
[000054] D----+-N---- \--* LCL_VAR simd16 V09 loc0
fgMorphTree BB02, stmt 5 (before)
[000064] ------------ /--* HWIntrinsic simd16 ushort Insert
[000061] ------------ | | /--* LIST void
[000060] ------------ | | | \--* CNS_INT int 3
[000062] ------------ | | /--* LIST void
[000059] ------------ | | | \--* LCL_VAR ushort V04 arg3
[000063] ------------ | \--* LIST void
[000058] ------------ | \--* LCL_VAR simd16 V09 loc0
[000067] -A---------- * ASG simd16 (copy)
[000065] D----------- \--* LCL_VAR simd16 V09 loc0
fgMorphCopyBlock:block assignment to morph:
[000064] -----+------ /--* HWIntrinsic simd16 ushort Insert
[000061] ------------ | | /--* LIST void
[000060] -----+------ | | | \--* CNS_INT int 3
[000062] ------------ | | /--* LIST void
[000118] -----+------ | | | \--* CAST int <- ushort <- int
[000059] -----+------ | | | \--* LCL_VAR int V04 arg3
[000063] -----+------ | \--* LIST void
[000058] -----+------ | \--* LCL_VAR simd16 V09 loc0
[000067] -A---------- * ASG simd16 (copy)
[000065] D----+-N---- \--* LCL_VAR simd16 V09 loc0
with no promoted structs this requires a CopyBlock.
Local V09 should not be enregistered because: written in a block op
fgMorphTree BB02, stmt 5 (after)
[000064] -----+------ /--* HWIntrinsic simd16 ushort Insert
[000061] ------------ | | /--* LIST void
[000060] -----+------ | | | \--* CNS_INT int 3
[000062] ------------ | | /--* LIST void
[000118] -----+------ | | | \--* CAST int <- ushort <- int
[000059] -----+------ | | | \--* LCL_VAR int V04 arg3
[000063] -----+------ | \--* LIST void
[000058] -----+------ | \--* LCL_VAR simd16 V09 loc0
[000067] -A---+------ * ASG simd16 (copy)
[000065] D----+-N---- \--* LCL_VAR simd16 V09 loc0
fgMorphTree BB02, stmt 6 (before)
[000075] ------------ /--* HWIntrinsic simd16 ushort Insert
[000072] ------------ | | /--* LIST void
[000071] ------------ | | | \--* CNS_INT int 4
[000073] ------------ | | /--* LIST void
[000070] ------------ | | | \--* LCL_VAR ushort V05 arg4
[000074] ------------ | \--* LIST void
[000069] ------------ | \--* LCL_VAR simd16 V09 loc0
[000078] -A---------- * ASG simd16 (copy)
[000076] D----------- \--* LCL_VAR simd16 V09 loc0
fgMorphCopyBlock:block assignment to morph:
[000075] -----+------ /--* HWIntrinsic simd16 ushort Insert
[000072] ------------ | | /--* LIST void
[000071] -----+------ | | | \--* CNS_INT int 4
[000073] ------------ | | /--* LIST void
[000119] -----+------ | | | \--* CAST int <- ushort <- int
[000070] -----+------ | | | \--* LCL_VAR int V05 arg4
[000074] -----+------ | \--* LIST void
[000069] -----+------ | \--* LCL_VAR simd16 V09 loc0
[000078] -A---------- * ASG simd16 (copy)
[000076] D----+-N---- \--* LCL_VAR simd16 V09 loc0
with no promoted structs this requires a CopyBlock.
Local V09 should not be enregistered because: written in a block op
fgMorphTree BB02, stmt 6 (after)
[000075] -----+------ /--* HWIntrinsic simd16 ushort Insert
[000072] ------------ | | /--* LIST void
[000071] -----+------ | | | \--* CNS_INT int 4
[000073] ------------ | | /--* LIST void
[000119] -----+------ | | | \--* CAST int <- ushort <- int
[000070] -----+------ | | | \--* LCL_VAR int V05 arg4
[000074] -----+------ | \--* LIST void
[000069] -----+------ | \--* LCL_VAR simd16 V09 loc0
[000078] -A---+------ * ASG simd16 (copy)
[000076] D----+-N---- \--* LCL_VAR simd16 V09 loc0
fgMorphTree BB02, stmt 7 (before)
[000086] ------------ /--* HWIntrinsic simd16 ushort Insert
[000083] ------------ | | /--* LIST void
[000082] ------------ | | | \--* CNS_INT int 5
[000084] ------------ | | /--* LIST void
[000081] ------------ | | | \--* LCL_VAR ushort V06 arg5
[000085] ------------ | \--* LIST void
[000080] ------------ | \--* LCL_VAR simd16 V09 loc0
[000089] -A---------- * ASG simd16 (copy)
[000087] D----------- \--* LCL_VAR simd16 V09 loc0
fgMorphCopyBlock:block assignment to morph:
[000086] -----+------ /--* HWIntrinsic simd16 ushort Insert
[000083] ------------ | | /--* LIST void
[000082] -----+------ | | | \--* CNS_INT int 5
[000084] ------------ | | /--* LIST void
[000120] -----+------ | | | \--* CAST int <- ushort <- int
[000081] -----+------ | | | \--* LCL_VAR int V06 arg5
[000085] -----+------ | \--* LIST void
[000080] -----+------ | \--* LCL_VAR simd16 V09 loc0
[000089] -A---------- * ASG simd16 (copy)
[000087] D----+-N---- \--* LCL_VAR simd16 V09 loc0
with no promoted structs this requires a CopyBlock.
Local V09 should not be enregistered because: written in a block op
fgMorphTree BB02, stmt 7 (after)
[000086] -----+------ /--* HWIntrinsic simd16 ushort Insert
[000083] ------------ | | /--* LIST void
[000082] -----+------ | | | \--* CNS_INT int 5
[000084] ------------ | | /--* LIST void
[000120] -----+------ | | | \--* CAST int <- ushort <- int
[000081] -----+------ | | | \--* LCL_VAR int V06 arg5
[000085] -----+------ | \--* LIST void
[000080] -----+------ | \--* LCL_VAR simd16 V09 loc0
[000089] -A---+------ * ASG simd16 (copy)
[000087] D----+-N---- \--* LCL_VAR simd16 V09 loc0
fgMorphTree BB02, stmt 8 (before)
[000097] ------------ /--* HWIntrinsic simd16 ushort Insert
[000094] ------------ | | /--* LIST void
[000093] ------------ | | | \--* CNS_INT int 6
[000095] ------------ | | /--* LIST void
[000092] ------------ | | | \--* LCL_VAR ushort V07 arg6
[000096] ------------ | \--* LIST void
[000091] ------------ | \--* LCL_VAR simd16 V09 loc0
[000100] -A---------- * ASG simd16 (copy)
[000098] D----------- \--* LCL_VAR simd16 V09 loc0
fgMorphCopyBlock:block assignment to morph:
[000097] -----+------ /--* HWIntrinsic simd16 ushort Insert
[000094] ------------ | | /--* LIST void
[000093] -----+------ | | | \--* CNS_INT int 6
[000095] ------------ | | /--* LIST void
[000121] -----+------ | | | \--* CAST int <- ushort <- int
[000092] -----+------ | | | \--* LCL_VAR int V07 arg6
[000096] -----+------ | \--* LIST void
[000091] -----+------ | \--* LCL_VAR simd16 V09 loc0
[000100] -A---------- * ASG simd16 (copy)
[000098] D----+-N---- \--* LCL_VAR simd16 V09 loc0
with no promoted structs this requires a CopyBlock.
Local V09 should not be enregistered because: written in a block op
fgMorphTree BB02, stmt 8 (after)
[000097] -----+------ /--* HWIntrinsic simd16 ushort Insert
[000094] ------------ | | /--* LIST void
[000093] -----+------ | | | \--* CNS_INT int 6
[000095] ------------ | | /--* LIST void
[000121] -----+------ | | | \--* CAST int <- ushort <- int
[000092] -----+------ | | | \--* LCL_VAR int V07 arg6
[000096] -----+------ | \--* LIST void
[000091] -----+------ | \--* LCL_VAR simd16 V09 loc0
[000100] -A---+------ * ASG simd16 (copy)
[000098] D----+-N---- \--* LCL_VAR simd16 V09 loc0
fgMorphTree BB02, stmt 9 (before)
[000108] ------------ /--* HWIntrinsic simd16 ushort Insert
[000105] ------------ | | /--* LIST void
[000104] ------------ | | | \--* CNS_INT int 7
[000106] ------------ | | /--* LIST void
[000103] ------------ | | | \--* LCL_VAR ushort V08 arg7
[000107] ------------ | \--* LIST void
[000102] ------------ | \--* LCL_VAR simd16 V09 loc0
[000111] -A---------- * ASG simd16 (copy)
[000110] ------------ \--* BLK(16) simd16
[000109] ------------ \--* LCL_VAR byref V00 RetBuf
fgMorphCopyBlock:block assignment to morph:
[000108] -----+------ /--* HWIntrinsic simd16 ushort Insert
[000105] ------------ | | /--* LIST void
[000104] -----+------ | | | \--* CNS_INT int 7
[000106] ------------ | | /--* LIST void
[000122] -----+------ | | | \--* CAST int <- ushort <- int
[000103] -----+------ | | | \--* LCL_VAR int V08 arg7
[000107] -----+------ | \--* LIST void
[000102] -----+------ | \--* LCL_VAR simd16 V09 loc0
[000111] -A-X-------- * ASG simd16 (copy)
[000110] ---X-+-N---- \--* BLK(16) simd16
[000109] -----+------ \--* LCL_VAR byref V00 RetBuf
with no promoted structs this requires a CopyBlock.
fgMorphTree BB02, stmt 9 (after)
[000108] -----+------ /--* HWIntrinsic simd16 ushort Insert
[000105] ------------ | | /--* LIST void
[000104] -----+------ | | | \--* CNS_INT int 7
[000106] ------------ | | /--* LIST void
[000122] -----+------ | | | \--* CAST int <- ushort <- int
[000103] -----+------ | | | \--* LCL_VAR int V08 arg7
[000107] -----+------ | \--* LIST void
[000102] -----+------ | \--* LCL_VAR simd16 V09 loc0
[000111] -A-X-+------ * ASG simd16 (copy)
[000110] ---X-+-N---- \--* IND simd16
[000109] -----+------ \--* LCL_VAR byref V00 RetBuf
fgMorphTree BB02, stmt 10 (before)
[000113] ------------ * RETURN void
Morphing BB03 of 'System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct'
fgMorphTree BB03, stmt 11 (before)
[000015] S-C-G------- * CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
[000024] ------------ arg0 +--* LCL_VAR byref V00 RetBuf
[000007] ------------ arg1 +--* LCL_VAR ushort V01 arg0
[000008] ------------ arg2 +--* LCL_VAR ushort V02 arg1
[000009] ------------ arg3 +--* LCL_VAR ushort V03 arg2
[000010] ------------ arg4 +--* LCL_VAR ushort V04 arg3
[000011] ------------ arg5 +--* LCL_VAR ushort V05 arg4
[000012] ------------ arg6 +--* LCL_VAR ushort V06 arg5
[000013] ------------ arg7 +--* LCL_VAR ushort V07 arg6
[000014] ------------ arg8 \--* LCL_VAR ushort V08 arg7
Initializing arg info for 15.CALL:
fgArgTabEntry[arg 0 24.LCL_VAR, 1 reg: ecx, align=1]
fgArgTabEntry[arg 1 7.LCL_VAR, 1 reg: edx, align=1]
fgArgTabEntry[arg 2 8.LCL_VAR, numSlots=1, slotNum=0, align=1]
fgArgTabEntry[arg 3 9.LCL_VAR, numSlots=1, slotNum=1, align=1]
fgArgTabEntry[arg 4 10.LCL_VAR, numSlots=1, slotNum=2, align=1]
fgArgTabEntry[arg 5 11.LCL_VAR, numSlots=1, slotNum=3, align=1]
fgArgTabEntry[arg 6 12.LCL_VAR, numSlots=1, slotNum=4, align=1]
fgArgTabEntry[arg 7 13.LCL_VAR, numSlots=1, slotNum=5, align=1]
fgArgTabEntry[arg 8 14.LCL_VAR, numSlots=1, slotNum=6, align=1]
Morphing args for 15.CALL:
Sorting the arguments:
Deferred argument ('edx'):
( 4, 4) [000123] ------------ * CAST int <- ushort <- int
( 3, 2) [000007] ------------ \--* LCL_VAR int V01 arg0
Replaced with placeholder node:
[000131] ----------L- * ARGPLACE int
Deferred argument ('ecx'):
[000024] -----+------ * LCL_VAR byref V00 RetBuf
Replaced with placeholder node:
[000133] ----------L- * ARGPLACE byref
Shuffled argument table: edx ecx
fgArgTabEntry[arg 8 130.CAST, numSlots=1, slotNum=6, align=1, processed]
fgArgTabEntry[arg 1 123.CAST, 1 reg: edx, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 2 124.CAST, numSlots=1, slotNum=0, align=1, processed]
fgArgTabEntry[arg 3 125.CAST, numSlots=1, slotNum=1, align=1, processed]
fgArgTabEntry[arg 4 126.CAST, numSlots=1, slotNum=2, align=1, processed]
fgArgTabEntry[arg 5 127.CAST, numSlots=1, slotNum=3, align=1, processed]
fgArgTabEntry[arg 6 128.CAST, numSlots=1, slotNum=4, align=1, processed]
fgArgTabEntry[arg 7 129.CAST, numSlots=1, slotNum=5, align=1, processed]
fgArgTabEntry[arg 0 24.LCL_VAR, 1 reg: ecx, align=1, lateArgInx=1, processed]
fgMorphTree BB03, stmt 11 (after)
[000015] S-CXG+------ * CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
( 4, 4) [000124] ------------ arg2 on STK +--* CAST int <- ushort <- int
( 3, 2) [000008] ------------ | \--* LCL_VAR int V02 arg1
( 4, 4) [000125] ------------ arg3 on STK +--* CAST int <- ushort <- int
( 3, 2) [000009] ------------ | \--* LCL_VAR int V03 arg2
( 4, 4) [000126] ------------ arg4 on STK +--* CAST int <- ushort <- int
( 3, 2) [000010] ------------ | \--* LCL_VAR int V04 arg3
( 4, 4) [000127] ------------ arg5 on STK +--* CAST int <- ushort <- int
( 3, 2) [000011] ------------ | \--* LCL_VAR int V05 arg4
( 4, 4) [000128] ------------ arg6 on STK +--* CAST int <- ushort <- int
( 3, 2) [000012] ------------ | \--* LCL_VAR int V06 arg5
( 4, 4) [000129] ------------ arg7 on STK +--* CAST int <- ushort <- int
( 3, 2) [000013] ------------ | \--* LCL_VAR int V07 arg6
( 4, 4) [000130] ------------ arg8 on STK +--* CAST int <- ushort <- int
( 3, 2) [000014] ------------ | \--* LCL_VAR int V08 arg7
( 4, 4) [000123] ------------ arg1 in edx +--* CAST int <- ushort <- int
( 3, 2) [000007] ------------ | \--* LCL_VAR int V01 arg0
[000024] -----+------ arg0 in ecx \--* LCL_VAR byref V00 RetBuf
fgMorphTree BB03, stmt 12 (before)
[000027] ------------ * RETURN void
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i
BB02 [0001] 1 1 [007..051) (return) i
BB03 [0002] 1 1 [051..063) (return) i gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
*************** In fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i
BB02 [0001] 1 1 [007..051) (return) i
BB03 [0002] 1 1 [051..063) (return) i gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [007..051) (return) i
BB03 [0002] 1 BB01 1 [051..063) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeBlockAndEdgeWeights()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [007..051) (return) i
BB03 [0002] 1 BB01 1 [051..063) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
-- not optimizing, so not computing edge weights
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*************** In fgFindOperOrder()
*************** In fgSetBlockOrder()
The biggest BB has 31 tree nodes
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [007..051) (return) i
BB03 [0002] 1 BB01 1 [051..063) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 5) [000005] ------------ * STMT void (IL 0x000...0x005)
N004 ( 5, 5) [000004] ------------ \--* JTRUE void
N002 ( 1, 1) [000001] ------------ | /--* CNS_INT int 1
N003 ( 3, 3) [000003] J------N---- \--* EQ int
N001 ( 1, 1) [000002] ------------ \--* CNS_INT int 0
------------ BB02 [007..051) (return), preds={BB01} succs={}
***** BB02, stmt 2
( 9, 8) [000035] ------------ * STMT void (IL 0x007...0x00D)
N003 ( 5, 5) [000031] ------------ | /--* HWIntrinsic simd16 ushort CreateScalarUnsafe
N002 ( 4, 4) [000115] ------------ | | \--* CAST int <- ushort <- int
N001 ( 3, 2) [000030] ------------ | | \--* LCL_VAR int V01 arg0
N005 ( 9, 8) [000034] -A------R--- \--* ASG simd16 (copy)
N004 ( 3, 2) [000032] D------N---- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 3
( 15, 13) [000046] ------------ * STMT void (IL 0x00E...0x016)
N008 ( 11, 10) [000042] ------------ | /--* HWIntrinsic simd16 ushort Insert
N005 ( 1, 1) [000039] ------------ | | | /--* LIST void
N004 ( 1, 1) [000038] ------------ | | | | \--* CNS_INT int 1
N006 ( 6, 6) [000040] ------------ | | | /--* LIST void
N003 ( 4, 4) [000116] ------------ | | | | \--* CAST int <- ushort <- int
N002 ( 3, 2) [000037] ------------ | | | | \--* LCL_VAR int V02 arg1
N007 ( 10, 9) [000041] ------------ | | \--* LIST void
N001 ( 3, 2) [000036] ------------ | | \--* LCL_VAR simd16 V09 loc0
N010 ( 15, 13) [000045] -A------R--- \--* ASG simd16 (copy)
N009 ( 3, 2) [000043] D------N---- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 4
( 15, 13) [000057] ------------ * STMT void (IL 0x017...0x01F)
N008 ( 11, 10) [000053] ------------ | /--* HWIntrinsic simd16 ushort Insert
N005 ( 1, 1) [000050] ------------ | | | /--* LIST void
N004 ( 1, 1) [000049] ------------ | | | | \--* CNS_INT int 2
N006 ( 6, 6) [000051] ------------ | | | /--* LIST void
N003 ( 4, 4) [000117] ------------ | | | | \--* CAST int <- ushort <- int
N002 ( 3, 2) [000048] ------------ | | | | \--* LCL_VAR int V03 arg2
N007 ( 10, 9) [000052] ------------ | | \--* LIST void
N001 ( 3, 2) [000047] ------------ | | \--* LCL_VAR simd16 V09 loc0
N010 ( 15, 13) [000056] -A------R--- \--* ASG simd16 (copy)
N009 ( 3, 2) [000054] D------N---- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 5
( 15, 13) [000068] ------------ * STMT void (IL 0x020...0x028)
N008 ( 11, 10) [000064] ------------ | /--* HWIntrinsic simd16 ushort Insert
N005 ( 1, 1) [000061] ------------ | | | /--* LIST void
N004 ( 1, 1) [000060] ------------ | | | | \--* CNS_INT int 3
N006 ( 6, 6) [000062] ------------ | | | /--* LIST void
N003 ( 4, 4) [000118] ------------ | | | | \--* CAST int <- ushort <- int
N002 ( 3, 2) [000059] ------------ | | | | \--* LCL_VAR int V04 arg3
N007 ( 10, 9) [000063] ------------ | | \--* LIST void
N001 ( 3, 2) [000058] ------------ | | \--* LCL_VAR simd16 V09 loc0
N010 ( 15, 13) [000067] -A------R--- \--* ASG simd16 (copy)
N009 ( 3, 2) [000065] D------N---- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 6
( 15, 13) [000079] ------------ * STMT void (IL 0x029...0x032)
N008 ( 11, 10) [000075] ------------ | /--* HWIntrinsic simd16 ushort Insert
N005 ( 1, 1) [000072] ------------ | | | /--* LIST void
N004 ( 1, 1) [000071] ------------ | | | | \--* CNS_INT int 4
N006 ( 6, 6) [000073] ------------ | | | /--* LIST void
N003 ( 4, 4) [000119] ------------ | | | | \--* CAST int <- ushort <- int
N002 ( 3, 2) [000070] ------------ | | | | \--* LCL_VAR int V05 arg4
N007 ( 10, 9) [000074] ------------ | | \--* LIST void
N001 ( 3, 2) [000069] ------------ | | \--* LCL_VAR simd16 V09 loc0
N010 ( 15, 13) [000078] -A------R--- \--* ASG simd16 (copy)
N009 ( 3, 2) [000076] D------N---- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 7
( 15, 13) [000090] ------------ * STMT void (IL 0x033...0x03C)
N008 ( 11, 10) [000086] ------------ | /--* HWIntrinsic simd16 ushort Insert
N005 ( 1, 1) [000083] ------------ | | | /--* LIST void
N004 ( 1, 1) [000082] ------------ | | | | \--* CNS_INT int 5
N006 ( 6, 6) [000084] ------------ | | | /--* LIST void
N003 ( 4, 4) [000120] ------------ | | | | \--* CAST int <- ushort <- int
N002 ( 3, 2) [000081] ------------ | | | | \--* LCL_VAR int V06 arg5
N007 ( 10, 9) [000085] ------------ | | \--* LIST void
N001 ( 3, 2) [000080] ------------ | | \--* LCL_VAR simd16 V09 loc0
N010 ( 15, 13) [000089] -A------R--- \--* ASG simd16 (copy)
N009 ( 3, 2) [000087] D------N---- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 8
( 15, 13) [000101] ------------ * STMT void (IL 0x03D...0x046)
N008 ( 11, 10) [000097] ------------ | /--* HWIntrinsic simd16 ushort Insert
N005 ( 1, 1) [000094] ------------ | | | /--* LIST void
N004 ( 1, 1) [000093] ------------ | | | | \--* CNS_INT int 6
N006 ( 6, 6) [000095] ------------ | | | /--* LIST void
N003 ( 4, 4) [000121] ------------ | | | | \--* CAST int <- ushort <- int
N002 ( 3, 2) [000092] ------------ | | | | \--* LCL_VAR int V07 arg6
N007 ( 10, 9) [000096] ------------ | | \--* LIST void
N001 ( 3, 2) [000091] ------------ | | \--* LCL_VAR simd16 V09 loc0
N010 ( 15, 13) [000100] -A------R--- \--* ASG simd16 (copy)
N009 ( 3, 2) [000098] D------N---- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 9
( 18, 15) [000112] ------------ * STMT void (IL 0x047...0x050)
N008 ( 11, 10) [000108] ------------ | /--* HWIntrinsic simd16 ushort Insert
N005 ( 1, 1) [000105] ------------ | | | /--* LIST void
N004 ( 1, 1) [000104] ------------ | | | | \--* CNS_INT int 7
N006 ( 6, 6) [000106] ------------ | | | /--* LIST void
N003 ( 4, 4) [000122] ------------ | | | | \--* CAST int <- ushort <- int
N002 ( 3, 2) [000103] ------------ | | | | \--* LCL_VAR int V08 arg7
N007 ( 10, 9) [000107] ------------ | | \--* LIST void
N001 ( 3, 2) [000102] ------------ | | \--* LCL_VAR simd16 V09 loc0
N011 ( 18, 15) [000111] -A-X----R--- \--* ASG simd16 (copy)
N010 ( 6, 4) [000110] ---X---N---- \--* IND simd16
N009 ( 3, 2) [000109] ------------ \--* LCL_VAR byref V00 RetBuf
***** BB02, stmt 10
( 0, 0) [000114] ------------ * STMT void (IL ???... ???)
N001 ( 0, 0) [000113] ------------ \--* RETURN void
------------ BB03 [051..063) (return), preds={BB01} succs={}
***** BB03, stmt 11
( 70, 41) [000026] ------------ * STMT void (IL 0x051...0x062)
N031 ( 70, 41) [000015] S-CXG------- \--* CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
N004 ( 4, 4) [000124] ------------ arg2 on STK +--* CAST int <- ushort <- int
N003 ( 3, 2) [000008] ------------ | \--* LCL_VAR int V02 arg1
N006 ( 4, 4) [000125] ------------ arg3 on STK +--* CAST int <- ushort <- int
N005 ( 3, 2) [000009] ------------ | \--* LCL_VAR int V03 arg2
N008 ( 4, 4) [000126] ------------ arg4 on STK +--* CAST int <- ushort <- int
N007 ( 3, 2) [000010] ------------ | \--* LCL_VAR int V04 arg3
N010 ( 4, 4) [000127] ------------ arg5 on STK +--* CAST int <- ushort <- int
N009 ( 3, 2) [000011] ------------ | \--* LCL_VAR int V05 arg4
N012 ( 4, 4) [000128] ------------ arg6 on STK +--* CAST int <- ushort <- int
N011 ( 3, 2) [000012] ------------ | \--* LCL_VAR int V06 arg5
N014 ( 4, 4) [000129] ------------ arg7 on STK +--* CAST int <- ushort <- int
N013 ( 3, 2) [000013] ------------ | \--* LCL_VAR int V07 arg6
N016 ( 4, 4) [000130] ------------ arg8 on STK +--* CAST int <- ushort <- int
N015 ( 3, 2) [000014] ------------ | \--* LCL_VAR int V08 arg7
N027 ( 4, 4) [000123] ------------ arg1 in edx +--* CAST int <- ushort <- int
N026 ( 3, 2) [000007] ------------ | \--* LCL_VAR int V01 arg0
N028 ( 3, 2) [000024] ------------ arg0 in ecx \--* LCL_VAR byref V00 RetBuf
***** BB03, stmt 12
( 0, 0) [000028] ------------ * STMT void (IL ???... ???)
N001 ( 0, 0) [000027] ------------ \--* RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** In IR Rationalize
Trees before IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [007..051) (return) i
BB03 [0002] 1 BB01 1 [051..063) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 5, 5) [000005] ------------ * STMT void (IL 0x000...0x005)
N004 ( 5, 5) [000004] ------------ \--* JTRUE void
N002 ( 1, 1) [000001] ------------ | /--* CNS_INT int 1
N003 ( 3, 3) [000003] J------N---- \--* EQ int
N001 ( 1, 1) [000002] ------------ \--* CNS_INT int 0
------------ BB02 [007..051) (return), preds={BB01} succs={}
***** BB02, stmt 2
( 9, 8) [000035] ------------ * STMT void (IL 0x007...0x00D)
N003 ( 5, 5) [000031] ------------ | /--* HWIntrinsic simd16 ushort CreateScalarUnsafe
N002 ( 4, 4) [000115] ------------ | | \--* CAST int <- ushort <- int
N001 ( 3, 2) [000030] ------------ | | \--* LCL_VAR int V01 arg0
N005 ( 9, 8) [000034] -A------R--- \--* ASG simd16 (copy)
N004 ( 3, 2) [000032] D------N---- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 3
( 15, 13) [000046] ------------ * STMT void (IL 0x00E...0x016)
N008 ( 11, 10) [000042] ------------ | /--* HWIntrinsic simd16 ushort Insert
N005 ( 1, 1) [000039] ------------ | | | /--* LIST void
N004 ( 1, 1) [000038] ------------ | | | | \--* CNS_INT int 1
N006 ( 6, 6) [000040] ------------ | | | /--* LIST void
N003 ( 4, 4) [000116] ------------ | | | | \--* CAST int <- ushort <- int
N002 ( 3, 2) [000037] ------------ | | | | \--* LCL_VAR int V02 arg1
N007 ( 10, 9) [000041] ------------ | | \--* LIST void
N001 ( 3, 2) [000036] ------------ | | \--* LCL_VAR simd16 V09 loc0
N010 ( 15, 13) [000045] -A------R--- \--* ASG simd16 (copy)
N009 ( 3, 2) [000043] D------N---- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 4
( 15, 13) [000057] ------------ * STMT void (IL 0x017...0x01F)
N008 ( 11, 10) [000053] ------------ | /--* HWIntrinsic simd16 ushort Insert
N005 ( 1, 1) [000050] ------------ | | | /--* LIST void
N004 ( 1, 1) [000049] ------------ | | | | \--* CNS_INT int 2
N006 ( 6, 6) [000051] ------------ | | | /--* LIST void
N003 ( 4, 4) [000117] ------------ | | | | \--* CAST int <- ushort <- int
N002 ( 3, 2) [000048] ------------ | | | | \--* LCL_VAR int V03 arg2
N007 ( 10, 9) [000052] ------------ | | \--* LIST void
N001 ( 3, 2) [000047] ------------ | | \--* LCL_VAR simd16 V09 loc0
N010 ( 15, 13) [000056] -A------R--- \--* ASG simd16 (copy)
N009 ( 3, 2) [000054] D------N---- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 5
( 15, 13) [000068] ------------ * STMT void (IL 0x020...0x028)
N008 ( 11, 10) [000064] ------------ | /--* HWIntrinsic simd16 ushort Insert
N005 ( 1, 1) [000061] ------------ | | | /--* LIST void
N004 ( 1, 1) [000060] ------------ | | | | \--* CNS_INT int 3
N006 ( 6, 6) [000062] ------------ | | | /--* LIST void
N003 ( 4, 4) [000118] ------------ | | | | \--* CAST int <- ushort <- int
N002 ( 3, 2) [000059] ------------ | | | | \--* LCL_VAR int V04 arg3
N007 ( 10, 9) [000063] ------------ | | \--* LIST void
N001 ( 3, 2) [000058] ------------ | | \--* LCL_VAR simd16 V09 loc0
N010 ( 15, 13) [000067] -A------R--- \--* ASG simd16 (copy)
N009 ( 3, 2) [000065] D------N---- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 6
( 15, 13) [000079] ------------ * STMT void (IL 0x029...0x032)
N008 ( 11, 10) [000075] ------------ | /--* HWIntrinsic simd16 ushort Insert
N005 ( 1, 1) [000072] ------------ | | | /--* LIST void
N004 ( 1, 1) [000071] ------------ | | | | \--* CNS_INT int 4
N006 ( 6, 6) [000073] ------------ | | | /--* LIST void
N003 ( 4, 4) [000119] ------------ | | | | \--* CAST int <- ushort <- int
N002 ( 3, 2) [000070] ------------ | | | | \--* LCL_VAR int V05 arg4
N007 ( 10, 9) [000074] ------------ | | \--* LIST void
N001 ( 3, 2) [000069] ------------ | | \--* LCL_VAR simd16 V09 loc0
N010 ( 15, 13) [000078] -A------R--- \--* ASG simd16 (copy)
N009 ( 3, 2) [000076] D------N---- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 7
( 15, 13) [000090] ------------ * STMT void (IL 0x033...0x03C)
N008 ( 11, 10) [000086] ------------ | /--* HWIntrinsic simd16 ushort Insert
N005 ( 1, 1) [000083] ------------ | | | /--* LIST void
N004 ( 1, 1) [000082] ------------ | | | | \--* CNS_INT int 5
N006 ( 6, 6) [000084] ------------ | | | /--* LIST void
N003 ( 4, 4) [000120] ------------ | | | | \--* CAST int <- ushort <- int
N002 ( 3, 2) [000081] ------------ | | | | \--* LCL_VAR int V06 arg5
N007 ( 10, 9) [000085] ------------ | | \--* LIST void
N001 ( 3, 2) [000080] ------------ | | \--* LCL_VAR simd16 V09 loc0
N010 ( 15, 13) [000089] -A------R--- \--* ASG simd16 (copy)
N009 ( 3, 2) [000087] D------N---- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 8
( 15, 13) [000101] ------------ * STMT void (IL 0x03D...0x046)
N008 ( 11, 10) [000097] ------------ | /--* HWIntrinsic simd16 ushort Insert
N005 ( 1, 1) [000094] ------------ | | | /--* LIST void
N004 ( 1, 1) [000093] ------------ | | | | \--* CNS_INT int 6
N006 ( 6, 6) [000095] ------------ | | | /--* LIST void
N003 ( 4, 4) [000121] ------------ | | | | \--* CAST int <- ushort <- int
N002 ( 3, 2) [000092] ------------ | | | | \--* LCL_VAR int V07 arg6
N007 ( 10, 9) [000096] ------------ | | \--* LIST void
N001 ( 3, 2) [000091] ------------ | | \--* LCL_VAR simd16 V09 loc0
N010 ( 15, 13) [000100] -A------R--- \--* ASG simd16 (copy)
N009 ( 3, 2) [000098] D------N---- \--* LCL_VAR simd16 V09 loc0
***** BB02, stmt 9
( 18, 15) [000112] ------------ * STMT void (IL 0x047...0x050)
N008 ( 11, 10) [000108] ------------ | /--* HWIntrinsic simd16 ushort Insert
N005 ( 1, 1) [000105] ------------ | | | /--* LIST void
N004 ( 1, 1) [000104] ------------ | | | | \--* CNS_INT int 7
N006 ( 6, 6) [000106] ------------ | | | /--* LIST void
N003 ( 4, 4) [000122] ------------ | | | | \--* CAST int <- ushort <- int
N002 ( 3, 2) [000103] ------------ | | | | \--* LCL_VAR int V08 arg7
N007 ( 10, 9) [000107] ------------ | | \--* LIST void
N001 ( 3, 2) [000102] ------------ | | \--* LCL_VAR simd16 V09 loc0
N011 ( 18, 15) [000111] -A-X----R--- \--* ASG simd16 (copy)
N010 ( 6, 4) [000110] ---X---N---- \--* IND simd16
N009 ( 3, 2) [000109] ------------ \--* LCL_VAR byref V00 RetBuf
***** BB02, stmt 10
( 0, 0) [000114] ------------ * STMT void (IL ???... ???)
N001 ( 0, 0) [000113] ------------ \--* RETURN void
------------ BB03 [051..063) (return), preds={BB01} succs={}
***** BB03, stmt 11
( 70, 41) [000026] ------------ * STMT void (IL 0x051...0x062)
N031 ( 70, 41) [000015] S-CXG------- \--* CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
N004 ( 4, 4) [000124] ------------ arg2 on STK +--* CAST int <- ushort <- int
N003 ( 3, 2) [000008] ------------ | \--* LCL_VAR int V02 arg1
N006 ( 4, 4) [000125] ------------ arg3 on STK +--* CAST int <- ushort <- int
N005 ( 3, 2) [000009] ------------ | \--* LCL_VAR int V03 arg2
N008 ( 4, 4) [000126] ------------ arg4 on STK +--* CAST int <- ushort <- int
N007 ( 3, 2) [000010] ------------ | \--* LCL_VAR int V04 arg3
N010 ( 4, 4) [000127] ------------ arg5 on STK +--* CAST int <- ushort <- int
N009 ( 3, 2) [000011] ------------ | \--* LCL_VAR int V05 arg4
N012 ( 4, 4) [000128] ------------ arg6 on STK +--* CAST int <- ushort <- int
N011 ( 3, 2) [000012] ------------ | \--* LCL_VAR int V06 arg5
N014 ( 4, 4) [000129] ------------ arg7 on STK +--* CAST int <- ushort <- int
N013 ( 3, 2) [000013] ------------ | \--* LCL_VAR int V07 arg6
N016 ( 4, 4) [000130] ------------ arg8 on STK +--* CAST int <- ushort <- int
N015 ( 3, 2) [000014] ------------ | \--* LCL_VAR int V08 arg7
N027 ( 4, 4) [000123] ------------ arg1 in edx +--* CAST int <- ushort <- int
N026 ( 3, 2) [000007] ------------ | \--* LCL_VAR int V01 arg0
N028 ( 3, 2) [000024] ------------ arg0 in ecx \--* LCL_VAR byref V00 RetBuf
***** BB03, stmt 12
( 0, 0) [000028] ------------ * STMT void (IL ???... ???)
N001 ( 0, 0) [000027] ------------ \--* RETURN void
-------------------------------------------------------------------------------------------------------------------
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N005 ( 9, 8) [000034] DA---------- * STORE_LCL_VAR simd16 V09 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N010 ( 15, 13) [000045] DA---------- * STORE_LCL_VAR simd16 V09 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N010 ( 15, 13) [000056] DA---------- * STORE_LCL_VAR simd16 V09 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N010 ( 15, 13) [000067] DA---------- * STORE_LCL_VAR simd16 V09 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N010 ( 15, 13) [000078] DA---------- * STORE_LCL_VAR simd16 V09 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N010 ( 15, 13) [000089] DA---------- * STORE_LCL_VAR simd16 V09 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N010 ( 15, 13) [000100] DA---------- * STORE_LCL_VAR simd16 V09 loc0
*************** Exiting IR Rationalize
Trees after IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [007..051) (return) i LIR
BB03 [0002] 1 BB01 1 [051..063) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 5) [000005] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000002] ------------ t2 = CNS_INT int 0
N002 ( 1, 1) [000001] ------------ t1 = CNS_INT int 1
/--* t2 int
+--* t1 int
N003 ( 3, 3) [000003] J------N---- t3 = * EQ int
/--* t3 int
N004 ( 5, 5) [000004] ------------ * JTRUE void
------------ BB02 [007..051) (return), preds={BB01} succs={}
( 9, 8) [000035] ------------ IL_OFFSET void IL offset: 0x7
N001 ( 3, 2) [000030] ------------ t30 = LCL_VAR int V01 arg0
/--* t30 int
N002 ( 4, 4) [000115] ------------ t115 = * CAST int <- ushort <- int
/--* t115 int
N003 ( 5, 5) [000031] ------------ t31 = * HWIntrinsic simd16 ushort CreateScalarUnsafe
/--* t31 simd16
N005 ( 9, 8) [000034] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000046] ------------ IL_OFFSET void IL offset: 0xe
N001 ( 3, 2) [000036] ------------ t36 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V02 arg1
/--* t37 int
N003 ( 4, 4) [000116] ------------ t116 = * CAST int <- ushort <- int
N004 ( 1, 1) [000038] ------------ t38 = CNS_INT int 1
/--* t36 simd16
+--* t116 int
+--* t38 int
N008 ( 11, 10) [000042] ------------ t42 = * HWIntrinsic simd16 ushort Insert
/--* t42 simd16
N010 ( 15, 13) [000045] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000057] ------------ IL_OFFSET void IL offset: 0x17
N001 ( 3, 2) [000047] ------------ t47 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000048] ------------ t48 = LCL_VAR int V03 arg2
/--* t48 int
N003 ( 4, 4) [000117] ------------ t117 = * CAST int <- ushort <- int
N004 ( 1, 1) [000049] ------------ t49 = CNS_INT int 2
/--* t47 simd16
+--* t117 int
+--* t49 int
N008 ( 11, 10) [000053] ------------ t53 = * HWIntrinsic simd16 ushort Insert
/--* t53 simd16
N010 ( 15, 13) [000056] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000068] ------------ IL_OFFSET void IL offset: 0x20
N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V04 arg3
/--* t59 int
N003 ( 4, 4) [000118] ------------ t118 = * CAST int <- ushort <- int
N004 ( 1, 1) [000060] ------------ t60 = CNS_INT int 3
/--* t58 simd16
+--* t118 int
+--* t60 int
N008 ( 11, 10) [000064] ------------ t64 = * HWIntrinsic simd16 ushort Insert
/--* t64 simd16
N010 ( 15, 13) [000067] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000079] ------------ IL_OFFSET void IL offset: 0x29
N001 ( 3, 2) [000069] ------------ t69 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V05 arg4
/--* t70 int
N003 ( 4, 4) [000119] ------------ t119 = * CAST int <- ushort <- int
N004 ( 1, 1) [000071] ------------ t71 = CNS_INT int 4
/--* t69 simd16
+--* t119 int
+--* t71 int
N008 ( 11, 10) [000075] ------------ t75 = * HWIntrinsic simd16 ushort Insert
/--* t75 simd16
N010 ( 15, 13) [000078] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000090] ------------ IL_OFFSET void IL offset: 0x33
N001 ( 3, 2) [000080] ------------ t80 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V06 arg5
/--* t81 int
N003 ( 4, 4) [000120] ------------ t120 = * CAST int <- ushort <- int
N004 ( 1, 1) [000082] ------------ t82 = CNS_INT int 5
/--* t80 simd16
+--* t120 int
+--* t82 int
N008 ( 11, 10) [000086] ------------ t86 = * HWIntrinsic simd16 ushort Insert
/--* t86 simd16
N010 ( 15, 13) [000089] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000101] ------------ IL_OFFSET void IL offset: 0x3d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000092] ------------ t92 = LCL_VAR int V07 arg6
/--* t92 int
N003 ( 4, 4) [000121] ------------ t121 = * CAST int <- ushort <- int
N004 ( 1, 1) [000093] ------------ t93 = CNS_INT int 6
/--* t91 simd16
+--* t121 int
+--* t93 int
N008 ( 11, 10) [000097] ------------ t97 = * HWIntrinsic simd16 ushort Insert
/--* t97 simd16
N010 ( 15, 13) [000100] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 18, 15) [000112] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000102] ------------ t102 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V08 arg7
/--* t103 int
N003 ( 4, 4) [000122] ------------ t122 = * CAST int <- ushort <- int
N004 ( 1, 1) [000104] ------------ t104 = CNS_INT int 7
/--* t102 simd16
+--* t122 int
+--* t104 int
N008 ( 11, 10) [000108] ------------ t108 = * HWIntrinsic simd16 ushort Insert
N009 ( 3, 2) [000109] ------------ t109 = LCL_VAR byref V00 RetBuf
/--* t109 byref
+--* t108 simd16
[000135] -A-X-------- * STOREIND simd16
N001 ( 0, 0) [000113] ------------ RETURN void
------------ BB03 [051..063) (return), preds={BB01} succs={}
( 70, 41) [000026] ------------ IL_OFFSET void IL offset: 0x51
N003 ( 3, 2) [000008] ------------ t8 = LCL_VAR int V02 arg1
/--* t8 int
N004 ( 4, 4) [000124] ------------ t124 = * CAST int <- ushort <- int
N005 ( 3, 2) [000009] ------------ t9 = LCL_VAR int V03 arg2
/--* t9 int
N006 ( 4, 4) [000125] ------------ t125 = * CAST int <- ushort <- int
N007 ( 3, 2) [000010] ------------ t10 = LCL_VAR int V04 arg3
/--* t10 int
N008 ( 4, 4) [000126] ------------ t126 = * CAST int <- ushort <- int
N009 ( 3, 2) [000011] ------------ t11 = LCL_VAR int V05 arg4
/--* t11 int
N010 ( 4, 4) [000127] ------------ t127 = * CAST int <- ushort <- int
N011 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V06 arg5
/--* t12 int
N012 ( 4, 4) [000128] ------------ t128 = * CAST int <- ushort <- int
N013 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V07 arg6
/--* t13 int
N014 ( 4, 4) [000129] ------------ t129 = * CAST int <- ushort <- int
N015 ( 3, 2) [000014] ------------ t14 = LCL_VAR int V08 arg7
/--* t14 int
N016 ( 4, 4) [000130] ------------ t130 = * CAST int <- ushort <- int
N026 ( 3, 2) [000007] ------------ t7 = LCL_VAR int V01 arg0
/--* t7 int
N027 ( 4, 4) [000123] ------------ t123 = * CAST int <- ushort <- int
N028 ( 3, 2) [000024] ------------ t24 = LCL_VAR byref V00 RetBuf
/--* t124 int arg2 on STK
+--* t125 int arg3 on STK
+--* t126 int arg4 on STK
+--* t127 int arg5 on STK
+--* t128 int arg6 on STK
+--* t129 int arg7 on STK
+--* t130 int arg8 on STK
+--* t123 int arg1 in edx
+--* t24 byref arg0 in ecx
N031 ( 70, 41) [000015] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
N001 ( 0, 0) [000027] ------------ RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckBBlist
*************** In Lowering
Trees before Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [007..051) (return) i LIR
BB03 [0002] 1 BB01 1 [051..063) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 5) [000005] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000002] ------------ t2 = CNS_INT int 0
N002 ( 1, 1) [000001] ------------ t1 = CNS_INT int 1
/--* t2 int
+--* t1 int
N003 ( 3, 3) [000003] J------N---- t3 = * EQ int
/--* t3 int
N004 ( 5, 5) [000004] ------------ * JTRUE void
------------ BB02 [007..051) (return), preds={BB01} succs={}
( 9, 8) [000035] ------------ IL_OFFSET void IL offset: 0x7
N001 ( 3, 2) [000030] ------------ t30 = LCL_VAR int V01 arg0
/--* t30 int
N002 ( 4, 4) [000115] ------------ t115 = * CAST int <- ushort <- int
/--* t115 int
N003 ( 5, 5) [000031] ------------ t31 = * HWIntrinsic simd16 ushort CreateScalarUnsafe
/--* t31 simd16
N005 ( 9, 8) [000034] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000046] ------------ IL_OFFSET void IL offset: 0xe
N001 ( 3, 2) [000036] ------------ t36 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V02 arg1
/--* t37 int
N003 ( 4, 4) [000116] ------------ t116 = * CAST int <- ushort <- int
N004 ( 1, 1) [000038] ------------ t38 = CNS_INT int 1
/--* t36 simd16
+--* t116 int
+--* t38 int
N008 ( 11, 10) [000042] ------------ t42 = * HWIntrinsic simd16 ushort Insert
/--* t42 simd16
N010 ( 15, 13) [000045] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000057] ------------ IL_OFFSET void IL offset: 0x17
N001 ( 3, 2) [000047] ------------ t47 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000048] ------------ t48 = LCL_VAR int V03 arg2
/--* t48 int
N003 ( 4, 4) [000117] ------------ t117 = * CAST int <- ushort <- int
N004 ( 1, 1) [000049] ------------ t49 = CNS_INT int 2
/--* t47 simd16
+--* t117 int
+--* t49 int
N008 ( 11, 10) [000053] ------------ t53 = * HWIntrinsic simd16 ushort Insert
/--* t53 simd16
N010 ( 15, 13) [000056] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000068] ------------ IL_OFFSET void IL offset: 0x20
N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V04 arg3
/--* t59 int
N003 ( 4, 4) [000118] ------------ t118 = * CAST int <- ushort <- int
N004 ( 1, 1) [000060] ------------ t60 = CNS_INT int 3
/--* t58 simd16
+--* t118 int
+--* t60 int
N008 ( 11, 10) [000064] ------------ t64 = * HWIntrinsic simd16 ushort Insert
/--* t64 simd16
N010 ( 15, 13) [000067] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000079] ------------ IL_OFFSET void IL offset: 0x29
N001 ( 3, 2) [000069] ------------ t69 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V05 arg4
/--* t70 int
N003 ( 4, 4) [000119] ------------ t119 = * CAST int <- ushort <- int
N004 ( 1, 1) [000071] ------------ t71 = CNS_INT int 4
/--* t69 simd16
+--* t119 int
+--* t71 int
N008 ( 11, 10) [000075] ------------ t75 = * HWIntrinsic simd16 ushort Insert
/--* t75 simd16
N010 ( 15, 13) [000078] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000090] ------------ IL_OFFSET void IL offset: 0x33
N001 ( 3, 2) [000080] ------------ t80 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V06 arg5
/--* t81 int
N003 ( 4, 4) [000120] ------------ t120 = * CAST int <- ushort <- int
N004 ( 1, 1) [000082] ------------ t82 = CNS_INT int 5
/--* t80 simd16
+--* t120 int
+--* t82 int
N008 ( 11, 10) [000086] ------------ t86 = * HWIntrinsic simd16 ushort Insert
/--* t86 simd16
N010 ( 15, 13) [000089] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000101] ------------ IL_OFFSET void IL offset: 0x3d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000092] ------------ t92 = LCL_VAR int V07 arg6
/--* t92 int
N003 ( 4, 4) [000121] ------------ t121 = * CAST int <- ushort <- int
N004 ( 1, 1) [000093] ------------ t93 = CNS_INT int 6
/--* t91 simd16
+--* t121 int
+--* t93 int
N008 ( 11, 10) [000097] ------------ t97 = * HWIntrinsic simd16 ushort Insert
/--* t97 simd16
N010 ( 15, 13) [000100] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 18, 15) [000112] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000102] ------------ t102 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V08 arg7
/--* t103 int
N003 ( 4, 4) [000122] ------------ t122 = * CAST int <- ushort <- int
N004 ( 1, 1) [000104] ------------ t104 = CNS_INT int 7
/--* t102 simd16
+--* t122 int
+--* t104 int
N008 ( 11, 10) [000108] ------------ t108 = * HWIntrinsic simd16 ushort Insert
N009 ( 3, 2) [000109] ------------ t109 = LCL_VAR byref V00 RetBuf
/--* t109 byref
+--* t108 simd16
[000135] -A-X-------- * STOREIND simd16
N001 ( 0, 0) [000113] ------------ RETURN void
------------ BB03 [051..063) (return), preds={BB01} succs={}
( 70, 41) [000026] ------------ IL_OFFSET void IL offset: 0x51
N003 ( 3, 2) [000008] ------------ t8 = LCL_VAR int V02 arg1
/--* t8 int
N004 ( 4, 4) [000124] ------------ t124 = * CAST int <- ushort <- int
N005 ( 3, 2) [000009] ------------ t9 = LCL_VAR int V03 arg2
/--* t9 int
N006 ( 4, 4) [000125] ------------ t125 = * CAST int <- ushort <- int
N007 ( 3, 2) [000010] ------------ t10 = LCL_VAR int V04 arg3
/--* t10 int
N008 ( 4, 4) [000126] ------------ t126 = * CAST int <- ushort <- int
N009 ( 3, 2) [000011] ------------ t11 = LCL_VAR int V05 arg4
/--* t11 int
N010 ( 4, 4) [000127] ------------ t127 = * CAST int <- ushort <- int
N011 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V06 arg5
/--* t12 int
N012 ( 4, 4) [000128] ------------ t128 = * CAST int <- ushort <- int
N013 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V07 arg6
/--* t13 int
N014 ( 4, 4) [000129] ------------ t129 = * CAST int <- ushort <- int
N015 ( 3, 2) [000014] ------------ t14 = LCL_VAR int V08 arg7
/--* t14 int
N016 ( 4, 4) [000130] ------------ t130 = * CAST int <- ushort <- int
N026 ( 3, 2) [000007] ------------ t7 = LCL_VAR int V01 arg0
/--* t7 int
N027 ( 4, 4) [000123] ------------ t123 = * CAST int <- ushort <- int
N028 ( 3, 2) [000024] ------------ t24 = LCL_VAR byref V00 RetBuf
/--* t124 int arg2 on STK
+--* t125 int arg3 on STK
+--* t126 int arg4 on STK
+--* t127 int arg5 on STK
+--* t128 int arg6 on STK
+--* t129 int arg7 on STK
+--* t130 int arg8 on STK
+--* t123 int arg1 in edx
+--* t24 byref arg0 in ecx
N031 ( 70, 41) [000015] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
N001 ( 0, 0) [000027] ------------ RETURN void
-------------------------------------------------------------------------------------------------------------------
No addressing mode:
N009 ( 3, 2) [000109] ------------ * LCL_VAR byref V00 RetBuf
Lower of StoreInd didn't mark the node as self contained for reason: 4
N001 ( 3, 2) [000102] ------------ t102 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V08 arg7
/--* t103 int
N003 ( 4, 4) [000122] ------------ t122 = * CAST int <- ushort <- int
N004 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 7
/--* t102 simd16
+--* t122 int
+--* t104 int
N008 ( 11, 10) [000108] ------------ t108 = * HWIntrinsic simd16 ushort Insert
N009 ( 3, 2) [000109] ------------ t109 = LCL_VAR byref V00 RetBuf
/--* t109 byref
+--* t108 simd16
[000135] -A-X-------- * STOREIND simd16
lowering GT_RETURN
N001 ( 0, 0) [000113] ------------ * RETURN void
============lowering call (before):
N003 ( 3, 2) [000008] ------------ t8 = LCL_VAR int V02 arg1
/--* t8 int
N004 ( 4, 4) [000124] ------------ t124 = * CAST int <- ushort <- int
N005 ( 3, 2) [000009] ------------ t9 = LCL_VAR int V03 arg2
/--* t9 int
N006 ( 4, 4) [000125] ------------ t125 = * CAST int <- ushort <- int
N007 ( 3, 2) [000010] ------------ t10 = LCL_VAR int V04 arg3
/--* t10 int
N008 ( 4, 4) [000126] ------------ t126 = * CAST int <- ushort <- int
N009 ( 3, 2) [000011] ------------ t11 = LCL_VAR int V05 arg4
/--* t11 int
N010 ( 4, 4) [000127] ------------ t127 = * CAST int <- ushort <- int
N011 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V06 arg5
/--* t12 int
N012 ( 4, 4) [000128] ------------ t128 = * CAST int <- ushort <- int
N013 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V07 arg6
/--* t13 int
N014 ( 4, 4) [000129] ------------ t129 = * CAST int <- ushort <- int
N015 ( 3, 2) [000014] ------------ t14 = LCL_VAR int V08 arg7
/--* t14 int
N016 ( 4, 4) [000130] ------------ t130 = * CAST int <- ushort <- int
N026 ( 3, 2) [000007] ------------ t7 = LCL_VAR int V01 arg0
/--* t7 int
N027 ( 4, 4) [000123] ------------ t123 = * CAST int <- ushort <- int
N028 ( 3, 2) [000024] ------------ t24 = LCL_VAR byref V00 RetBuf
/--* t124 int arg2 on STK
+--* t125 int arg3 on STK
+--* t126 int arg4 on STK
+--* t127 int arg5 on STK
+--* t128 int arg6 on STK
+--* t129 int arg7 on STK
+--* t130 int arg8 on STK
+--* t123 int arg1 in edx
+--* t24 byref arg0 in ecx
N031 ( 70, 41) [000015] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000133] ----------L- * ARGPLACE byref
lowering arg : N002 ( 0, 0) [000131] ----------L- * ARGPLACE int
lowering arg : N004 ( 4, 4) [000124] ------------ * CAST int <- ushort <- int
new node is : [000136] ------------ * PUTARG_STK [+0x00] void (1 slots)
lowering arg : N006 ( 4, 4) [000125] ------------ * CAST int <- ushort <- int
new node is : [000137] ------------ * PUTARG_STK [+0x04] void (1 slots)
lowering arg : N008 ( 4, 4) [000126] ------------ * CAST int <- ushort <- int
new node is : [000138] ------------ * PUTARG_STK [+0x08] void (1 slots)
lowering arg : N010 ( 4, 4) [000127] ------------ * CAST int <- ushort <- int
new node is : [000139] ------------ * PUTARG_STK [+0x0c] void (1 slots)
lowering arg : N012 ( 4, 4) [000128] ------------ * CAST int <- ushort <- int
new node is : [000140] ------------ * PUTARG_STK [+0x10] void (1 slots)
lowering arg : N014 ( 4, 4) [000129] ------------ * CAST int <- ushort <- int
new node is : [000141] ------------ * PUTARG_STK [+0x14] void (1 slots)
lowering arg : N016 ( 4, 4) [000130] ------------ * CAST int <- ushort <- int
new node is : [000142] ------------ * PUTARG_STK [+0x18] void (1 slots)
late:
======
lowering arg : N027 ( 4, 4) [000123] ------------ * CAST int <- ushort <- int
new node is : [000143] ------------ * PUTARG_REG int REG edx
lowering arg : N028 ( 3, 2) [000024] ------------ * LCL_VAR byref V00 RetBuf
new node is : [000144] ------------ * PUTARG_REG byref REG ecx
lowering call (after):
N003 ( 3, 2) [000008] ------------ t8 = LCL_VAR int V02 arg1
/--* t8 int
N004 ( 4, 4) [000124] ------------ t124 = * CAST int <- ushort <- int
/--* t124 int
[000136] ------------ * PUTARG_STK [+0x00] void (1 slots)
N005 ( 3, 2) [000009] ------------ t9 = LCL_VAR int V03 arg2
/--* t9 int
N006 ( 4, 4) [000125] ------------ t125 = * CAST int <- ushort <- int
/--* t125 int
[000137] ------------ * PUTARG_STK [+0x04] void (1 slots)
N007 ( 3, 2) [000010] ------------ t10 = LCL_VAR int V04 arg3
/--* t10 int
N008 ( 4, 4) [000126] ------------ t126 = * CAST int <- ushort <- int
/--* t126 int
[000138] ------------ * PUTARG_STK [+0x08] void (1 slots)
N009 ( 3, 2) [000011] ------------ t11 = LCL_VAR int V05 arg4
/--* t11 int
N010 ( 4, 4) [000127] ------------ t127 = * CAST int <- ushort <- int
/--* t127 int
[000139] ------------ * PUTARG_STK [+0x0c] void (1 slots)
N011 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V06 arg5
/--* t12 int
N012 ( 4, 4) [000128] ------------ t128 = * CAST int <- ushort <- int
/--* t128 int
[000140] ------------ * PUTARG_STK [+0x10] void (1 slots)
N013 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V07 arg6
/--* t13 int
N014 ( 4, 4) [000129] ------------ t129 = * CAST int <- ushort <- int
/--* t129 int
[000141] ------------ * PUTARG_STK [+0x14] void (1 slots)
N015 ( 3, 2) [000014] ------------ t14 = LCL_VAR int V08 arg7
/--* t14 int
N016 ( 4, 4) [000130] ------------ t130 = * CAST int <- ushort <- int
/--* t130 int
[000142] ------------ * PUTARG_STK [+0x18] void (1 slots)
N026 ( 3, 2) [000007] ------------ t7 = LCL_VAR int V01 arg0
/--* t7 int
N027 ( 4, 4) [000123] ------------ t123 = * CAST int <- ushort <- int
/--* t123 int
[000143] ------------ t143 = * PUTARG_REG int REG edx
N028 ( 3, 2) [000024] ------------ t24 = LCL_VAR byref V00 RetBuf
/--* t24 byref
[000144] ------------ t144 = * PUTARG_REG byref REG ecx
/--* t143 int arg1 in edx
+--* t144 byref arg0 in ecx
N031 ( 70, 41) [000015] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
lowering GT_RETURN
N001 ( 0, 0) [000027] ------------ * RETURN void
============Lower has completed modifying nodes.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [007..051) (return) i LIR
BB03 [0002] 1 BB01 1 [051..063) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 5) [000005] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000002] ------------ t2 = CNS_INT int 0
N002 ( 1, 1) [000001] -c---------- t1 = CNS_INT int 1
/--* t2 int
+--* t1 int
N003 ( 3, 3) [000003] J------N---- * EQ void
N004 ( 5, 5) [000004] ------------ * JTRUE void
------------ BB02 [007..051) (return), preds={BB01} succs={}
( 9, 8) [000035] ------------ IL_OFFSET void IL offset: 0x7
N001 ( 3, 2) [000030] ------------ t30 = LCL_VAR int V01 arg0
/--* t30 int
N002 ( 4, 4) [000115] ------------ t115 = * CAST int <- ushort <- int
/--* t115 int
N003 ( 5, 5) [000031] ------------ t31 = * HWIntrinsic simd16 ushort CreateScalarUnsafe
/--* t31 simd16
N005 ( 9, 8) [000034] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000046] ------------ IL_OFFSET void IL offset: 0xe
N001 ( 3, 2) [000036] ------------ t36 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V02 arg1
/--* t37 int
N003 ( 4, 4) [000116] ------------ t116 = * CAST int <- ushort <- int
N004 ( 1, 1) [000038] -c---------- t38 = CNS_INT int 1
/--* t36 simd16
+--* t116 int
+--* t38 int
N008 ( 11, 10) [000042] ------------ t42 = * HWIntrinsic simd16 ushort Insert
/--* t42 simd16
N010 ( 15, 13) [000045] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000057] ------------ IL_OFFSET void IL offset: 0x17
N001 ( 3, 2) [000047] ------------ t47 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000048] ------------ t48 = LCL_VAR int V03 arg2
/--* t48 int
N003 ( 4, 4) [000117] ------------ t117 = * CAST int <- ushort <- int
N004 ( 1, 1) [000049] -c---------- t49 = CNS_INT int 2
/--* t47 simd16
+--* t117 int
+--* t49 int
N008 ( 11, 10) [000053] ------------ t53 = * HWIntrinsic simd16 ushort Insert
/--* t53 simd16
N010 ( 15, 13) [000056] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000068] ------------ IL_OFFSET void IL offset: 0x20
N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V04 arg3
/--* t59 int
N003 ( 4, 4) [000118] ------------ t118 = * CAST int <- ushort <- int
N004 ( 1, 1) [000060] -c---------- t60 = CNS_INT int 3
/--* t58 simd16
+--* t118 int
+--* t60 int
N008 ( 11, 10) [000064] ------------ t64 = * HWIntrinsic simd16 ushort Insert
/--* t64 simd16
N010 ( 15, 13) [000067] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000079] ------------ IL_OFFSET void IL offset: 0x29
N001 ( 3, 2) [000069] ------------ t69 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V05 arg4
/--* t70 int
N003 ( 4, 4) [000119] ------------ t119 = * CAST int <- ushort <- int
N004 ( 1, 1) [000071] -c---------- t71 = CNS_INT int 4
/--* t69 simd16
+--* t119 int
+--* t71 int
N008 ( 11, 10) [000075] ------------ t75 = * HWIntrinsic simd16 ushort Insert
/--* t75 simd16
N010 ( 15, 13) [000078] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000090] ------------ IL_OFFSET void IL offset: 0x33
N001 ( 3, 2) [000080] ------------ t80 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V06 arg5
/--* t81 int
N003 ( 4, 4) [000120] ------------ t120 = * CAST int <- ushort <- int
N004 ( 1, 1) [000082] -c---------- t82 = CNS_INT int 5
/--* t80 simd16
+--* t120 int
+--* t82 int
N008 ( 11, 10) [000086] ------------ t86 = * HWIntrinsic simd16 ushort Insert
/--* t86 simd16
N010 ( 15, 13) [000089] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000101] ------------ IL_OFFSET void IL offset: 0x3d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000092] ------------ t92 = LCL_VAR int V07 arg6
/--* t92 int
N003 ( 4, 4) [000121] ------------ t121 = * CAST int <- ushort <- int
N004 ( 1, 1) [000093] -c---------- t93 = CNS_INT int 6
/--* t91 simd16
+--* t121 int
+--* t93 int
N008 ( 11, 10) [000097] ------------ t97 = * HWIntrinsic simd16 ushort Insert
/--* t97 simd16
N010 ( 15, 13) [000100] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 18, 15) [000112] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000102] ------------ t102 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V08 arg7
/--* t103 int
N003 ( 4, 4) [000122] ------------ t122 = * CAST int <- ushort <- int
N004 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 7
/--* t102 simd16
+--* t122 int
+--* t104 int
N008 ( 11, 10) [000108] ------------ t108 = * HWIntrinsic simd16 ushort Insert
N009 ( 3, 2) [000109] ------------ t109 = LCL_VAR byref V00 RetBuf
/--* t109 byref
+--* t108 simd16
[000135] -A-X-------- * STOREIND simd16
N001 ( 0, 0) [000113] ------------ RETURN void
------------ BB03 [051..063) (return), preds={BB01} succs={}
( 70, 41) [000026] ------------ IL_OFFSET void IL offset: 0x51
N003 ( 3, 2) [000008] ------------ t8 = LCL_VAR int V02 arg1
/--* t8 int
N004 ( 4, 4) [000124] ------------ t124 = * CAST int <- ushort <- int
/--* t124 int
[000136] ------------ * PUTARG_STK [+0x00] void (1 slots)
N005 ( 3, 2) [000009] ------------ t9 = LCL_VAR int V03 arg2
/--* t9 int
N006 ( 4, 4) [000125] ------------ t125 = * CAST int <- ushort <- int
/--* t125 int
[000137] ------------ * PUTARG_STK [+0x04] void (1 slots)
N007 ( 3, 2) [000010] ------------ t10 = LCL_VAR int V04 arg3
/--* t10 int
N008 ( 4, 4) [000126] ------------ t126 = * CAST int <- ushort <- int
/--* t126 int
[000138] ------------ * PUTARG_STK [+0x08] void (1 slots)
N009 ( 3, 2) [000011] ------------ t11 = LCL_VAR int V05 arg4
/--* t11 int
N010 ( 4, 4) [000127] ------------ t127 = * CAST int <- ushort <- int
/--* t127 int
[000139] ------------ * PUTARG_STK [+0x0c] void (1 slots)
N011 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V06 arg5
/--* t12 int
N012 ( 4, 4) [000128] ------------ t128 = * CAST int <- ushort <- int
/--* t128 int
[000140] ------------ * PUTARG_STK [+0x10] void (1 slots)
N013 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V07 arg6
/--* t13 int
N014 ( 4, 4) [000129] ------------ t129 = * CAST int <- ushort <- int
/--* t129 int
[000141] ------------ * PUTARG_STK [+0x14] void (1 slots)
N015 ( 3, 2) [000014] ------------ t14 = LCL_VAR int V08 arg7
/--* t14 int
N016 ( 4, 4) [000130] ------------ t130 = * CAST int <- ushort <- int
/--* t130 int
[000142] ------------ * PUTARG_STK [+0x18] void (1 slots)
N026 ( 3, 2) [000007] ------------ t7 = LCL_VAR int V01 arg0
/--* t7 int
N027 ( 4, 4) [000123] ------------ t123 = * CAST int <- ushort <- int
/--* t123 int
[000143] ------------ t143 = * PUTARG_REG int REG edx
N028 ( 3, 2) [000024] ------------ t24 = LCL_VAR byref V00 RetBuf
/--* t24 byref
[000144] ------------ t144 = * PUTARG_REG byref REG ecx
/--* t143 int arg1 in edx
+--* t144 byref arg0 in ecx
N031 ( 70, 41) [000015] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
N001 ( 0, 0) [000027] ------------ RETURN void
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 RetBuf byref
; V01 arg0 ushort
; V02 arg1 ushort
; V03 arg2 ushort
; V04 arg3 ushort
; V05 arg4 ushort
; V06 arg5 ushort
; V07 arg6 ushort
; V08 arg7 ushort
; V09 loc0 simd16 do-not-enreg[SB]
In fgLocalVarLivenessInit
*************** In fgPerBlockLocalVarLiveness()
*************** In fgInterBlockLocalVarLiveness()
*** lvaComputeRefCounts ***
Liveness pass finished after lowering, IR:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [007..051) (return) i LIR
BB03 [0002] 1 BB01 1 [051..063) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 5) [000005] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000002] ------------ t2 = CNS_INT int 0
N002 ( 1, 1) [000001] -c---------- t1 = CNS_INT int 1
/--* t2 int
+--* t1 int
N003 ( 3, 3) [000003] J------N---- * EQ void
N004 ( 5, 5) [000004] ------------ * JTRUE void
------------ BB02 [007..051) (return), preds={BB01} succs={}
( 9, 8) [000035] ------------ IL_OFFSET void IL offset: 0x7
N001 ( 3, 2) [000030] ------------ t30 = LCL_VAR int V01 arg0
/--* t30 int
N002 ( 4, 4) [000115] ------------ t115 = * CAST int <- ushort <- int
/--* t115 int
N003 ( 5, 5) [000031] ------------ t31 = * HWIntrinsic simd16 ushort CreateScalarUnsafe
/--* t31 simd16
N005 ( 9, 8) [000034] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000046] ------------ IL_OFFSET void IL offset: 0xe
N001 ( 3, 2) [000036] ------------ t36 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V02 arg1
/--* t37 int
N003 ( 4, 4) [000116] ------------ t116 = * CAST int <- ushort <- int
N004 ( 1, 1) [000038] -c---------- t38 = CNS_INT int 1
/--* t36 simd16
+--* t116 int
+--* t38 int
N008 ( 11, 10) [000042] ------------ t42 = * HWIntrinsic simd16 ushort Insert
/--* t42 simd16
N010 ( 15, 13) [000045] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000057] ------------ IL_OFFSET void IL offset: 0x17
N001 ( 3, 2) [000047] ------------ t47 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000048] ------------ t48 = LCL_VAR int V03 arg2
/--* t48 int
N003 ( 4, 4) [000117] ------------ t117 = * CAST int <- ushort <- int
N004 ( 1, 1) [000049] -c---------- t49 = CNS_INT int 2
/--* t47 simd16
+--* t117 int
+--* t49 int
N008 ( 11, 10) [000053] ------------ t53 = * HWIntrinsic simd16 ushort Insert
/--* t53 simd16
N010 ( 15, 13) [000056] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000068] ------------ IL_OFFSET void IL offset: 0x20
N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V04 arg3
/--* t59 int
N003 ( 4, 4) [000118] ------------ t118 = * CAST int <- ushort <- int
N004 ( 1, 1) [000060] -c---------- t60 = CNS_INT int 3
/--* t58 simd16
+--* t118 int
+--* t60 int
N008 ( 11, 10) [000064] ------------ t64 = * HWIntrinsic simd16 ushort Insert
/--* t64 simd16
N010 ( 15, 13) [000067] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000079] ------------ IL_OFFSET void IL offset: 0x29
N001 ( 3, 2) [000069] ------------ t69 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V05 arg4
/--* t70 int
N003 ( 4, 4) [000119] ------------ t119 = * CAST int <- ushort <- int
N004 ( 1, 1) [000071] -c---------- t71 = CNS_INT int 4
/--* t69 simd16
+--* t119 int
+--* t71 int
N008 ( 11, 10) [000075] ------------ t75 = * HWIntrinsic simd16 ushort Insert
/--* t75 simd16
N010 ( 15, 13) [000078] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000090] ------------ IL_OFFSET void IL offset: 0x33
N001 ( 3, 2) [000080] ------------ t80 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V06 arg5
/--* t81 int
N003 ( 4, 4) [000120] ------------ t120 = * CAST int <- ushort <- int
N004 ( 1, 1) [000082] -c---------- t82 = CNS_INT int 5
/--* t80 simd16
+--* t120 int
+--* t82 int
N008 ( 11, 10) [000086] ------------ t86 = * HWIntrinsic simd16 ushort Insert
/--* t86 simd16
N010 ( 15, 13) [000089] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000101] ------------ IL_OFFSET void IL offset: 0x3d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000092] ------------ t92 = LCL_VAR int V07 arg6
/--* t92 int
N003 ( 4, 4) [000121] ------------ t121 = * CAST int <- ushort <- int
N004 ( 1, 1) [000093] -c---------- t93 = CNS_INT int 6
/--* t91 simd16
+--* t121 int
+--* t93 int
N008 ( 11, 10) [000097] ------------ t97 = * HWIntrinsic simd16 ushort Insert
/--* t97 simd16
N010 ( 15, 13) [000100] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 18, 15) [000112] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000102] ------------ t102 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V08 arg7
/--* t103 int
N003 ( 4, 4) [000122] ------------ t122 = * CAST int <- ushort <- int
N004 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 7
/--* t102 simd16
+--* t122 int
+--* t104 int
N008 ( 11, 10) [000108] ------------ t108 = * HWIntrinsic simd16 ushort Insert
N009 ( 3, 2) [000109] ------------ t109 = LCL_VAR byref V00 RetBuf
/--* t109 byref
+--* t108 simd16
[000135] -A-X-------- * STOREIND simd16
N001 ( 0, 0) [000113] ------------ RETURN void
------------ BB03 [051..063) (return), preds={BB01} succs={}
( 70, 41) [000026] ------------ IL_OFFSET void IL offset: 0x51
N003 ( 3, 2) [000008] ------------ t8 = LCL_VAR int V02 arg1
/--* t8 int
N004 ( 4, 4) [000124] ------------ t124 = * CAST int <- ushort <- int
/--* t124 int
[000136] ------------ * PUTARG_STK [+0x00] void (1 slots)
N005 ( 3, 2) [000009] ------------ t9 = LCL_VAR int V03 arg2
/--* t9 int
N006 ( 4, 4) [000125] ------------ t125 = * CAST int <- ushort <- int
/--* t125 int
[000137] ------------ * PUTARG_STK [+0x04] void (1 slots)
N007 ( 3, 2) [000010] ------------ t10 = LCL_VAR int V04 arg3
/--* t10 int
N008 ( 4, 4) [000126] ------------ t126 = * CAST int <- ushort <- int
/--* t126 int
[000138] ------------ * PUTARG_STK [+0x08] void (1 slots)
N009 ( 3, 2) [000011] ------------ t11 = LCL_VAR int V05 arg4
/--* t11 int
N010 ( 4, 4) [000127] ------------ t127 = * CAST int <- ushort <- int
/--* t127 int
[000139] ------------ * PUTARG_STK [+0x0c] void (1 slots)
N011 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V06 arg5
/--* t12 int
N012 ( 4, 4) [000128] ------------ t128 = * CAST int <- ushort <- int
/--* t128 int
[000140] ------------ * PUTARG_STK [+0x10] void (1 slots)
N013 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V07 arg6
/--* t13 int
N014 ( 4, 4) [000129] ------------ t129 = * CAST int <- ushort <- int
/--* t129 int
[000141] ------------ * PUTARG_STK [+0x14] void (1 slots)
N015 ( 3, 2) [000014] ------------ t14 = LCL_VAR int V08 arg7
/--* t14 int
N016 ( 4, 4) [000130] ------------ t130 = * CAST int <- ushort <- int
/--* t130 int
[000142] ------------ * PUTARG_STK [+0x18] void (1 slots)
N026 ( 3, 2) [000007] ------------ t7 = LCL_VAR int V01 arg0
/--* t7 int
N027 ( 4, 4) [000123] ------------ t123 = * CAST int <- ushort <- int
/--* t123 int
[000143] ------------ t143 = * PUTARG_REG int REG edx
N028 ( 3, 2) [000024] ------------ t24 = LCL_VAR byref V00 RetBuf
/--* t24 byref
[000144] ------------ t144 = * PUTARG_REG byref REG ecx
/--* t143 int arg1 in edx
+--* t144 byref arg0 in ecx
N031 ( 70, 41) [000015] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
N001 ( 0, 0) [000027] ------------ RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Lowering
Trees after Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [007..051) (return) i LIR
BB03 [0002] 1 BB01 1 [051..063) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 5) [000005] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000002] ------------ t2 = CNS_INT int 0
N002 ( 1, 1) [000001] -c---------- t1 = CNS_INT int 1
/--* t2 int
+--* t1 int
N003 ( 3, 3) [000003] J------N---- * EQ void
N004 ( 5, 5) [000004] ------------ * JTRUE void
------------ BB02 [007..051) (return), preds={BB01} succs={}
( 9, 8) [000035] ------------ IL_OFFSET void IL offset: 0x7
N001 ( 3, 2) [000030] ------------ t30 = LCL_VAR int V01 arg0
/--* t30 int
N002 ( 4, 4) [000115] ------------ t115 = * CAST int <- ushort <- int
/--* t115 int
N003 ( 5, 5) [000031] ------------ t31 = * HWIntrinsic simd16 ushort CreateScalarUnsafe
/--* t31 simd16
N005 ( 9, 8) [000034] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000046] ------------ IL_OFFSET void IL offset: 0xe
N001 ( 3, 2) [000036] ------------ t36 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V02 arg1
/--* t37 int
N003 ( 4, 4) [000116] ------------ t116 = * CAST int <- ushort <- int
N004 ( 1, 1) [000038] -c---------- t38 = CNS_INT int 1
/--* t36 simd16
+--* t116 int
+--* t38 int
N008 ( 11, 10) [000042] ------------ t42 = * HWIntrinsic simd16 ushort Insert
/--* t42 simd16
N010 ( 15, 13) [000045] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000057] ------------ IL_OFFSET void IL offset: 0x17
N001 ( 3, 2) [000047] ------------ t47 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000048] ------------ t48 = LCL_VAR int V03 arg2
/--* t48 int
N003 ( 4, 4) [000117] ------------ t117 = * CAST int <- ushort <- int
N004 ( 1, 1) [000049] -c---------- t49 = CNS_INT int 2
/--* t47 simd16
+--* t117 int
+--* t49 int
N008 ( 11, 10) [000053] ------------ t53 = * HWIntrinsic simd16 ushort Insert
/--* t53 simd16
N010 ( 15, 13) [000056] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000068] ------------ IL_OFFSET void IL offset: 0x20
N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V04 arg3
/--* t59 int
N003 ( 4, 4) [000118] ------------ t118 = * CAST int <- ushort <- int
N004 ( 1, 1) [000060] -c---------- t60 = CNS_INT int 3
/--* t58 simd16
+--* t118 int
+--* t60 int
N008 ( 11, 10) [000064] ------------ t64 = * HWIntrinsic simd16 ushort Insert
/--* t64 simd16
N010 ( 15, 13) [000067] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000079] ------------ IL_OFFSET void IL offset: 0x29
N001 ( 3, 2) [000069] ------------ t69 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V05 arg4
/--* t70 int
N003 ( 4, 4) [000119] ------------ t119 = * CAST int <- ushort <- int
N004 ( 1, 1) [000071] -c---------- t71 = CNS_INT int 4
/--* t69 simd16
+--* t119 int
+--* t71 int
N008 ( 11, 10) [000075] ------------ t75 = * HWIntrinsic simd16 ushort Insert
/--* t75 simd16
N010 ( 15, 13) [000078] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000090] ------------ IL_OFFSET void IL offset: 0x33
N001 ( 3, 2) [000080] ------------ t80 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V06 arg5
/--* t81 int
N003 ( 4, 4) [000120] ------------ t120 = * CAST int <- ushort <- int
N004 ( 1, 1) [000082] -c---------- t82 = CNS_INT int 5
/--* t80 simd16
+--* t120 int
+--* t82 int
N008 ( 11, 10) [000086] ------------ t86 = * HWIntrinsic simd16 ushort Insert
/--* t86 simd16
N010 ( 15, 13) [000089] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000101] ------------ IL_OFFSET void IL offset: 0x3d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000092] ------------ t92 = LCL_VAR int V07 arg6
/--* t92 int
N003 ( 4, 4) [000121] ------------ t121 = * CAST int <- ushort <- int
N004 ( 1, 1) [000093] -c---------- t93 = CNS_INT int 6
/--* t91 simd16
+--* t121 int
+--* t93 int
N008 ( 11, 10) [000097] ------------ t97 = * HWIntrinsic simd16 ushort Insert
/--* t97 simd16
N010 ( 15, 13) [000100] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 18, 15) [000112] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000102] ------------ t102 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V08 arg7
/--* t103 int
N003 ( 4, 4) [000122] ------------ t122 = * CAST int <- ushort <- int
N004 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 7
/--* t102 simd16
+--* t122 int
+--* t104 int
N008 ( 11, 10) [000108] ------------ t108 = * HWIntrinsic simd16 ushort Insert
N009 ( 3, 2) [000109] ------------ t109 = LCL_VAR byref V00 RetBuf
/--* t109 byref
+--* t108 simd16
[000135] -A-X-------- * STOREIND simd16
N001 ( 0, 0) [000113] ------------ RETURN void
------------ BB03 [051..063) (return), preds={BB01} succs={}
( 70, 41) [000026] ------------ IL_OFFSET void IL offset: 0x51
N003 ( 3, 2) [000008] ------------ t8 = LCL_VAR int V02 arg1
/--* t8 int
N004 ( 4, 4) [000124] ------------ t124 = * CAST int <- ushort <- int
/--* t124 int
[000136] ------------ * PUTARG_STK [+0x00] void (1 slots)
N005 ( 3, 2) [000009] ------------ t9 = LCL_VAR int V03 arg2
/--* t9 int
N006 ( 4, 4) [000125] ------------ t125 = * CAST int <- ushort <- int
/--* t125 int
[000137] ------------ * PUTARG_STK [+0x04] void (1 slots)
N007 ( 3, 2) [000010] ------------ t10 = LCL_VAR int V04 arg3
/--* t10 int
N008 ( 4, 4) [000126] ------------ t126 = * CAST int <- ushort <- int
/--* t126 int
[000138] ------------ * PUTARG_STK [+0x08] void (1 slots)
N009 ( 3, 2) [000011] ------------ t11 = LCL_VAR int V05 arg4
/--* t11 int
N010 ( 4, 4) [000127] ------------ t127 = * CAST int <- ushort <- int
/--* t127 int
[000139] ------------ * PUTARG_STK [+0x0c] void (1 slots)
N011 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V06 arg5
/--* t12 int
N012 ( 4, 4) [000128] ------------ t128 = * CAST int <- ushort <- int
/--* t128 int
[000140] ------------ * PUTARG_STK [+0x10] void (1 slots)
N013 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V07 arg6
/--* t13 int
N014 ( 4, 4) [000129] ------------ t129 = * CAST int <- ushort <- int
/--* t129 int
[000141] ------------ * PUTARG_STK [+0x14] void (1 slots)
N015 ( 3, 2) [000014] ------------ t14 = LCL_VAR int V08 arg7
/--* t14 int
N016 ( 4, 4) [000130] ------------ t130 = * CAST int <- ushort <- int
/--* t130 int
[000142] ------------ * PUTARG_STK [+0x18] void (1 slots)
N026 ( 3, 2) [000007] ------------ t7 = LCL_VAR int V01 arg0
/--* t7 int
N027 ( 4, 4) [000123] ------------ t123 = * CAST int <- ushort <- int
/--* t123 int
[000143] ------------ t143 = * PUTARG_REG int REG edx
N028 ( 3, 2) [000024] ------------ t24 = LCL_VAR byref V00 RetBuf
/--* t24 byref
[000144] ------------ t144 = * PUTARG_REG byref REG ecx
/--* t143 int arg1 in edx
+--* t144 byref arg0 in ecx
N031 ( 70, 41) [000015] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
N001 ( 0, 0) [000027] ------------ RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In StackLevelSetter
Trees before StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [007..051) (return) i LIR
BB03 [0002] 1 BB01 1 [051..063) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 5) [000005] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000002] ------------ t2 = CNS_INT int 0
N002 ( 1, 1) [000001] -c---------- t1 = CNS_INT int 1
/--* t2 int
+--* t1 int
N003 ( 3, 3) [000003] J------N---- * EQ void
N004 ( 5, 5) [000004] ------------ * JTRUE void
------------ BB02 [007..051) (return), preds={BB01} succs={}
( 9, 8) [000035] ------------ IL_OFFSET void IL offset: 0x7
N001 ( 3, 2) [000030] ------------ t30 = LCL_VAR int V01 arg0
/--* t30 int
N002 ( 4, 4) [000115] ------------ t115 = * CAST int <- ushort <- int
/--* t115 int
N003 ( 5, 5) [000031] ------------ t31 = * HWIntrinsic simd16 ushort CreateScalarUnsafe
/--* t31 simd16
N005 ( 9, 8) [000034] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000046] ------------ IL_OFFSET void IL offset: 0xe
N001 ( 3, 2) [000036] ------------ t36 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V02 arg1
/--* t37 int
N003 ( 4, 4) [000116] ------------ t116 = * CAST int <- ushort <- int
N004 ( 1, 1) [000038] -c---------- t38 = CNS_INT int 1
/--* t36 simd16
+--* t116 int
+--* t38 int
N008 ( 11, 10) [000042] ------------ t42 = * HWIntrinsic simd16 ushort Insert
/--* t42 simd16
N010 ( 15, 13) [000045] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000057] ------------ IL_OFFSET void IL offset: 0x17
N001 ( 3, 2) [000047] ------------ t47 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000048] ------------ t48 = LCL_VAR int V03 arg2
/--* t48 int
N003 ( 4, 4) [000117] ------------ t117 = * CAST int <- ushort <- int
N004 ( 1, 1) [000049] -c---------- t49 = CNS_INT int 2
/--* t47 simd16
+--* t117 int
+--* t49 int
N008 ( 11, 10) [000053] ------------ t53 = * HWIntrinsic simd16 ushort Insert
/--* t53 simd16
N010 ( 15, 13) [000056] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000068] ------------ IL_OFFSET void IL offset: 0x20
N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V04 arg3
/--* t59 int
N003 ( 4, 4) [000118] ------------ t118 = * CAST int <- ushort <- int
N004 ( 1, 1) [000060] -c---------- t60 = CNS_INT int 3
/--* t58 simd16
+--* t118 int
+--* t60 int
N008 ( 11, 10) [000064] ------------ t64 = * HWIntrinsic simd16 ushort Insert
/--* t64 simd16
N010 ( 15, 13) [000067] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000079] ------------ IL_OFFSET void IL offset: 0x29
N001 ( 3, 2) [000069] ------------ t69 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V05 arg4
/--* t70 int
N003 ( 4, 4) [000119] ------------ t119 = * CAST int <- ushort <- int
N004 ( 1, 1) [000071] -c---------- t71 = CNS_INT int 4
/--* t69 simd16
+--* t119 int
+--* t71 int
N008 ( 11, 10) [000075] ------------ t75 = * HWIntrinsic simd16 ushort Insert
/--* t75 simd16
N010 ( 15, 13) [000078] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000090] ------------ IL_OFFSET void IL offset: 0x33
N001 ( 3, 2) [000080] ------------ t80 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V06 arg5
/--* t81 int
N003 ( 4, 4) [000120] ------------ t120 = * CAST int <- ushort <- int
N004 ( 1, 1) [000082] -c---------- t82 = CNS_INT int 5
/--* t80 simd16
+--* t120 int
+--* t82 int
N008 ( 11, 10) [000086] ------------ t86 = * HWIntrinsic simd16 ushort Insert
/--* t86 simd16
N010 ( 15, 13) [000089] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000101] ------------ IL_OFFSET void IL offset: 0x3d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000092] ------------ t92 = LCL_VAR int V07 arg6
/--* t92 int
N003 ( 4, 4) [000121] ------------ t121 = * CAST int <- ushort <- int
N004 ( 1, 1) [000093] -c---------- t93 = CNS_INT int 6
/--* t91 simd16
+--* t121 int
+--* t93 int
N008 ( 11, 10) [000097] ------------ t97 = * HWIntrinsic simd16 ushort Insert
/--* t97 simd16
N010 ( 15, 13) [000100] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 18, 15) [000112] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000102] ------------ t102 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V08 arg7
/--* t103 int
N003 ( 4, 4) [000122] ------------ t122 = * CAST int <- ushort <- int
N004 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 7
/--* t102 simd16
+--* t122 int
+--* t104 int
N008 ( 11, 10) [000108] ------------ t108 = * HWIntrinsic simd16 ushort Insert
N009 ( 3, 2) [000109] ------------ t109 = LCL_VAR byref V00 RetBuf
/--* t109 byref
+--* t108 simd16
[000135] -A-X-------- * STOREIND simd16
N001 ( 0, 0) [000113] ------------ RETURN void
------------ BB03 [051..063) (return), preds={BB01} succs={}
( 70, 41) [000026] ------------ IL_OFFSET void IL offset: 0x51
N003 ( 3, 2) [000008] ------------ t8 = LCL_VAR int V02 arg1
/--* t8 int
N004 ( 4, 4) [000124] ------------ t124 = * CAST int <- ushort <- int
/--* t124 int
[000136] ------------ * PUTARG_STK [+0x00] void (1 slots)
N005 ( 3, 2) [000009] ------------ t9 = LCL_VAR int V03 arg2
/--* t9 int
N006 ( 4, 4) [000125] ------------ t125 = * CAST int <- ushort <- int
/--* t125 int
[000137] ------------ * PUTARG_STK [+0x04] void (1 slots)
N007 ( 3, 2) [000010] ------------ t10 = LCL_VAR int V04 arg3
/--* t10 int
N008 ( 4, 4) [000126] ------------ t126 = * CAST int <- ushort <- int
/--* t126 int
[000138] ------------ * PUTARG_STK [+0x08] void (1 slots)
N009 ( 3, 2) [000011] ------------ t11 = LCL_VAR int V05 arg4
/--* t11 int
N010 ( 4, 4) [000127] ------------ t127 = * CAST int <- ushort <- int
/--* t127 int
[000139] ------------ * PUTARG_STK [+0x0c] void (1 slots)
N011 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V06 arg5
/--* t12 int
N012 ( 4, 4) [000128] ------------ t128 = * CAST int <- ushort <- int
/--* t128 int
[000140] ------------ * PUTARG_STK [+0x10] void (1 slots)
N013 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V07 arg6
/--* t13 int
N014 ( 4, 4) [000129] ------------ t129 = * CAST int <- ushort <- int
/--* t129 int
[000141] ------------ * PUTARG_STK [+0x14] void (1 slots)
N015 ( 3, 2) [000014] ------------ t14 = LCL_VAR int V08 arg7
/--* t14 int
N016 ( 4, 4) [000130] ------------ t130 = * CAST int <- ushort <- int
/--* t130 int
[000142] ------------ * PUTARG_STK [+0x18] void (1 slots)
N026 ( 3, 2) [000007] ------------ t7 = LCL_VAR int V01 arg0
/--* t7 int
N027 ( 4, 4) [000123] ------------ t123 = * CAST int <- ushort <- int
/--* t123 int
[000143] ------------ t143 = * PUTARG_REG int REG edx
N028 ( 3, 2) [000024] ------------ t24 = LCL_VAR byref V00 RetBuf
/--* t24 byref
[000144] ------------ t144 = * PUTARG_REG byref REG ecx
/--* t143 int arg1 in edx
+--* t144 byref arg0 in ecx
N031 ( 70, 41) [000015] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
N001 ( 0, 0) [000027] ------------ RETURN void
-------------------------------------------------------------------------------------------------------------------
Too many pushed arguments for an ESP based encoding, forcing an EBP frame
*************** Exiting StackLevelSetter
Trees after StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [007..051) (return) i LIR
BB03 [0002] 1 BB01 1 [051..063) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
( 5, 5) [000005] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 1, 1) [000002] ------------ t2 = CNS_INT int 0
N002 ( 1, 1) [000001] -c---------- t1 = CNS_INT int 1
/--* t2 int
+--* t1 int
N003 ( 3, 3) [000003] J------N---- * EQ void
N004 ( 5, 5) [000004] ------------ * JTRUE void
------------ BB02 [007..051) (return), preds={BB01} succs={}
( 9, 8) [000035] ------------ IL_OFFSET void IL offset: 0x7
N001 ( 3, 2) [000030] ------------ t30 = LCL_VAR int V01 arg0
/--* t30 int
N002 ( 4, 4) [000115] ------------ t115 = * CAST int <- ushort <- int
/--* t115 int
N003 ( 5, 5) [000031] ------------ t31 = * HWIntrinsic simd16 ushort CreateScalarUnsafe
/--* t31 simd16
N005 ( 9, 8) [000034] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000046] ------------ IL_OFFSET void IL offset: 0xe
N001 ( 3, 2) [000036] ------------ t36 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V02 arg1
/--* t37 int
N003 ( 4, 4) [000116] ------------ t116 = * CAST int <- ushort <- int
N004 ( 1, 1) [000038] -c---------- t38 = CNS_INT int 1
/--* t36 simd16
+--* t116 int
+--* t38 int
N008 ( 11, 10) [000042] ------------ t42 = * HWIntrinsic simd16 ushort Insert
/--* t42 simd16
N010 ( 15, 13) [000045] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000057] ------------ IL_OFFSET void IL offset: 0x17
N001 ( 3, 2) [000047] ------------ t47 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000048] ------------ t48 = LCL_VAR int V03 arg2
/--* t48 int
N003 ( 4, 4) [000117] ------------ t117 = * CAST int <- ushort <- int
N004 ( 1, 1) [000049] -c---------- t49 = CNS_INT int 2
/--* t47 simd16
+--* t117 int
+--* t49 int
N008 ( 11, 10) [000053] ------------ t53 = * HWIntrinsic simd16 ushort Insert
/--* t53 simd16
N010 ( 15, 13) [000056] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000068] ------------ IL_OFFSET void IL offset: 0x20
N001 ( 3, 2) [000058] ------------ t58 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V04 arg3
/--* t59 int
N003 ( 4, 4) [000118] ------------ t118 = * CAST int <- ushort <- int
N004 ( 1, 1) [000060] -c---------- t60 = CNS_INT int 3
/--* t58 simd16
+--* t118 int
+--* t60 int
N008 ( 11, 10) [000064] ------------ t64 = * HWIntrinsic simd16 ushort Insert
/--* t64 simd16
N010 ( 15, 13) [000067] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000079] ------------ IL_OFFSET void IL offset: 0x29
N001 ( 3, 2) [000069] ------------ t69 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V05 arg4
/--* t70 int
N003 ( 4, 4) [000119] ------------ t119 = * CAST int <- ushort <- int
N004 ( 1, 1) [000071] -c---------- t71 = CNS_INT int 4
/--* t69 simd16
+--* t119 int
+--* t71 int
N008 ( 11, 10) [000075] ------------ t75 = * HWIntrinsic simd16 ushort Insert
/--* t75 simd16
N010 ( 15, 13) [000078] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000090] ------------ IL_OFFSET void IL offset: 0x33
N001 ( 3, 2) [000080] ------------ t80 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V06 arg5
/--* t81 int
N003 ( 4, 4) [000120] ------------ t120 = * CAST int <- ushort <- int
N004 ( 1, 1) [000082] -c---------- t82 = CNS_INT int 5
/--* t80 simd16
+--* t120 int
+--* t82 int
N008 ( 11, 10) [000086] ------------ t86 = * HWIntrinsic simd16 ushort Insert
/--* t86 simd16
N010 ( 15, 13) [000089] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 15, 13) [000101] ------------ IL_OFFSET void IL offset: 0x3d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000092] ------------ t92 = LCL_VAR int V07 arg6
/--* t92 int
N003 ( 4, 4) [000121] ------------ t121 = * CAST int <- ushort <- int
N004 ( 1, 1) [000093] -c---------- t93 = CNS_INT int 6
/--* t91 simd16
+--* t121 int
+--* t93 int
N008 ( 11, 10) [000097] ------------ t97 = * HWIntrinsic simd16 ushort Insert
/--* t97 simd16
N010 ( 15, 13) [000100] DA---------- * STORE_LCL_VAR simd16 V09 loc0
( 18, 15) [000112] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000102] ------------ t102 = LCL_VAR simd16 V09 loc0
N002 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V08 arg7
/--* t103 int
N003 ( 4, 4) [000122] ------------ t122 = * CAST int <- ushort <- int
N004 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 7
/--* t102 simd16
+--* t122 int
+--* t104 int
N008 ( 11, 10) [000108] ------------ t108 = * HWIntrinsic simd16 ushort Insert
N009 ( 3, 2) [000109] ------------ t109 = LCL_VAR byref V00 RetBuf
/--* t109 byref
+--* t108 simd16
[000135] -A-X-------- * STOREIND simd16
N001 ( 0, 0) [000113] ------------ RETURN void
------------ BB03 [051..063) (return), preds={BB01} succs={}
( 70, 41) [000026] ------------ IL_OFFSET void IL offset: 0x51
N003 ( 3, 2) [000008] ------------ t8 = LCL_VAR int V02 arg1
/--* t8 int
N004 ( 4, 4) [000124] ------------ t124 = * CAST int <- ushort <- int
/--* t124 int
[000136] ------------ * PUTARG_STK [+0x00] void (1 slots)
N005 ( 3, 2) [000009] ------------ t9 = LCL_VAR int V03 arg2
/--* t9 int
N006 ( 4, 4) [000125] ------------ t125 = * CAST int <- ushort <- int
/--* t125 int
[000137] ------------ * PUTARG_STK [+0x04] void (1 slots)
N007 ( 3, 2) [000010] ------------ t10 = LCL_VAR int V04 arg3
/--* t10 int
N008 ( 4, 4) [000126] ------------ t126 = * CAST int <- ushort <- int
/--* t126 int
[000138] ------------ * PUTARG_STK [+0x08] void (1 slots)
N009 ( 3, 2) [000011] ------------ t11 = LCL_VAR int V05 arg4
/--* t11 int
N010 ( 4, 4) [000127] ------------ t127 = * CAST int <- ushort <- int
/--* t127 int
[000139] ------------ * PUTARG_STK [+0x0c] void (1 slots)
N011 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V06 arg5
/--* t12 int
N012 ( 4, 4) [000128] ------------ t128 = * CAST int <- ushort <- int
/--* t128 int
[000140] ------------ * PUTARG_STK [+0x10] void (1 slots)
N013 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V07 arg6
/--* t13 int
N014 ( 4, 4) [000129] ------------ t129 = * CAST int <- ushort <- int
/--* t129 int
[000141] ------------ * PUTARG_STK [+0x14] void (1 slots)
N015 ( 3, 2) [000014] ------------ t14 = LCL_VAR int V08 arg7
/--* t14 int
N016 ( 4, 4) [000130] ------------ t130 = * CAST int <- ushort <- int
/--* t130 int
[000142] ------------ * PUTARG_STK [+0x18] void (1 slots)
N026 ( 3, 2) [000007] ------------ t7 = LCL_VAR int V01 arg0
/--* t7 int
N027 ( 4, 4) [000123] ------------ t123 = * CAST int <- ushort <- int
/--* t123 int
[000143] ------------ t143 = * PUTARG_REG int REG edx
N028 ( 3, 2) [000024] ------------ t24 = LCL_VAR byref V00 RetBuf
/--* t24 byref
[000144] ------------ t144 = * PUTARG_REG byref REG ecx
/--* t143 int arg1 in edx
+--* t144 byref arg0 in ecx
N031 ( 70, 41) [000015] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
N001 ( 0, 0) [000027] ------------ RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{}
{}
{}
{}
BB02 use def in out
{}
{}
{}
{}
BB03 use def in out
{}
{}
{}
{}
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 0, singleExit = 1
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 ) BB02( 1 ) BB03( 1 )
BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N000. IL_OFFSET IL offset: 0x0
N001. t2 = CNS_INT 0
N002. CNS_INT 1
N003. EQ ; t2
N004. JTRUE
BB02 [007..051) (return), preds={BB01} succs={}
=====
N000. IL_OFFSET IL offset: 0x7
N001. t30 = V01 MEM
N002. t115 = CAST ; t30
N003. t31 = HWIntrinsic; t115
N005. V09 MEM; t31
N000. IL_OFFSET IL offset: 0xe
N001. t36 = V09 MEM
N002. t37 = V02 MEM
N003. t116 = CAST ; t37
N004. CNS_INT 1
N008. t42 = HWIntrinsic; t36,t116
N010. V09 MEM; t42
N000. IL_OFFSET IL offset: 0x17
N001. t47 = V09 MEM
N002. t48 = V03 MEM
N003. t117 = CAST ; t48
N004. CNS_INT 2
N008. t53 = HWIntrinsic; t47,t117
N010. V09 MEM; t53
N000. IL_OFFSET IL offset: 0x20
N001. t58 = V09 MEM
N002. t59 = V04 MEM
N003. t118 = CAST ; t59
N004. CNS_INT 3
N008. t64 = HWIntrinsic; t58,t118
N010. V09 MEM; t64
N000. IL_OFFSET IL offset: 0x29
N001. t69 = V09 MEM
N002. t70 = V05 MEM
N003. t119 = CAST ; t70
N004. CNS_INT 4
N008. t75 = HWIntrinsic; t69,t119
N010. V09 MEM; t75
N000. IL_OFFSET IL offset: 0x33
N001. t80 = V09 MEM
N002. t81 = V06 MEM
N003. t120 = CAST ; t81
N004. CNS_INT 5
N008. t86 = HWIntrinsic; t80,t120
N010. V09 MEM; t86
N000. IL_OFFSET IL offset: 0x3d
N001. t91 = V09 MEM
N002. t92 = V07 MEM
N003. t121 = CAST ; t92
N004. CNS_INT 6
N008. t97 = HWIntrinsic; t91,t121
N010. V09 MEM; t97
N000. IL_OFFSET IL offset: 0x47
N001. t102 = V09 MEM
N002. t103 = V08 MEM
N003. t122 = CAST ; t103
N004. CNS_INT 7
N008. t108 = HWIntrinsic; t102,t122
N009. t109 = V00 MEM
N000. STOREIND ; t109,t108
N001. RETURN
BB03 [051..063) (return), preds={BB01} succs={}
=====
N000. IL_OFFSET IL offset: 0x51
N003. t8 = V02 MEM
N004. t124 = CAST ; t8
N000. PUTARG_STK [+0x00]; t124
N005. t9 = V03 MEM
N006. t125 = CAST ; t9
N000. PUTARG_STK [+0x04]; t125
N007. t10 = V04 MEM
N008. t126 = CAST ; t10
N000. PUTARG_STK [+0x08]; t126
N009. t11 = V05 MEM
N010. t127 = CAST ; t11
N000. PUTARG_STK [+0x0c]; t127
N011. t12 = V06 MEM
N012. t128 = CAST ; t12
N000. PUTARG_STK [+0x10]; t128
N013. t13 = V07 MEM
N014. t129 = CAST ; t13
N000. PUTARG_STK [+0x14]; t129
N015. t14 = V08 MEM
N016. t130 = CAST ; t14
N000. PUTARG_STK [+0x18]; t130
N026. t7 = V01 MEM
N027. t123 = CAST ; t7
N000. t143 = PUTARG_REG; t123
N028. t24 = V00 MEM
N000. t144 = PUTARG_REG; t24
N031. CALL ; t143,t144
N001. RETURN
buildIntervals second part ========
Int arg V00 in reg ecx
Int arg V01 in reg edx
NEW BLOCK BB01
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N002 ( 5, 5) [000005] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N004 ( 1, 1) [000002] ------------ * CNS_INT int 0 REG NA
Interval 0: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #1 @5 RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { N004.t2. CNS_INT }
N006 ( 1, 1) [000001] -c---------- * CNS_INT int 1 REG NA
Contained
DefList: { N004.t2. CNS_INT }
N008 ( 3, 3) [000003] J------N---- * EQ void REG NA
<RefPosition #2 @8 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N010 ( 5, 5) [000004] ------------ * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
NEW BLOCK BB02
Setting BB02 as the predecessor for determining incoming variable registers of BB01
<RefPosition #3 @12 RefTypeBB BB02 regmask=[] minReg=1>
DefList: { }
N014 ( 9, 8) [000035] ------------ * IL_OFFSET void IL offset: 0x7 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N016 ( 3, 2) [000030] ------------ * LCL_VAR int V01 arg0 NA REG NA
Interval 1: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #4 @17 RefTypeDef <Ivl:1> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N016.t30. LCL_VAR }
N018 ( 4, 4) [000115] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #5 @18 RefTypeUse <Ivl:1> BB02 regmask=[allInt] minReg=1 last>
Interval 2: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #6 @19 RefTypeDef <Ivl:2> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N018.t115. CAST }
N020 ( 5, 5) [000031] ------------ * HWIntrinsic simd16 ushort CreateScalarUnsafe REG NA
<RefPosition #7 @20 RefTypeUse <Ivl:2> BB02 regmask=[allInt] minReg=1 last>
Interval 3: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #8 @21 RefTypeDef <Ivl:3> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N020.t31. HWIntrinsic }
N022 ( 9, 8) [000034] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
<RefPosition #9 @22 RefTypeUse <Ivl:3> BB02 regmask=[allFloat] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N024 ( 15, 13) [000046] ------------ * IL_OFFSET void IL offset: 0xe REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N026 ( 3, 2) [000036] ------------ * LCL_VAR simd16 V09 loc0 NA REG NA
Interval 4: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #10 @27 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N026.t36. LCL_VAR }
N028 ( 3, 2) [000037] ------------ * LCL_VAR int V02 arg1 NA REG NA
Interval 5: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #11 @29 RefTypeDef <Ivl:5> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N026.t36. LCL_VAR; N028.t37. LCL_VAR }
N030 ( 4, 4) [000116] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #12 @30 RefTypeUse <Ivl:5> BB02 regmask=[allInt] minReg=1 last>
Interval 6: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #13 @31 RefTypeDef <Ivl:6> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N026.t36. LCL_VAR; N030.t116. CAST }
N032 ( 1, 1) [000038] -c---------- * CNS_INT int 1 REG NA
Contained
DefList: { N026.t36. LCL_VAR; N030.t116. CAST }
N034 ( 11, 10) [000042] ------------ * HWIntrinsic simd16 ushort Insert REG NA
<RefPosition #14 @34 RefTypeUse <Ivl:4> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #15 @34 RefTypeUse <Ivl:6> BB02 regmask=[allInt] minReg=1 last>
Interval 7: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #16 @35 RefTypeDef <Ivl:7> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N034.t42. HWIntrinsic }
N036 ( 15, 13) [000045] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
<RefPosition #17 @36 RefTypeUse <Ivl:7> BB02 regmask=[allFloat] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N038 ( 15, 13) [000057] ------------ * IL_OFFSET void IL offset: 0x17 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N040 ( 3, 2) [000047] ------------ * LCL_VAR simd16 V09 loc0 NA REG NA
Interval 8: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #18 @41 RefTypeDef <Ivl:8> LCL_VAR BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N040.t47. LCL_VAR }
N042 ( 3, 2) [000048] ------------ * LCL_VAR int V03 arg2 NA REG NA
Interval 9: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #19 @43 RefTypeDef <Ivl:9> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N040.t47. LCL_VAR; N042.t48. LCL_VAR }
N044 ( 4, 4) [000117] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #20 @44 RefTypeUse <Ivl:9> BB02 regmask=[allInt] minReg=1 last>
Interval 10: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #21 @45 RefTypeDef <Ivl:10> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N040.t47. LCL_VAR; N044.t117. CAST }
N046 ( 1, 1) [000049] -c---------- * CNS_INT int 2 REG NA
Contained
DefList: { N040.t47. LCL_VAR; N044.t117. CAST }
N048 ( 11, 10) [000053] ------------ * HWIntrinsic simd16 ushort Insert REG NA
<RefPosition #22 @48 RefTypeUse <Ivl:8> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #23 @48 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last>
Interval 11: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #24 @49 RefTypeDef <Ivl:11> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N048.t53. HWIntrinsic }
N050 ( 15, 13) [000056] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
<RefPosition #25 @50 RefTypeUse <Ivl:11> BB02 regmask=[allFloat] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N052 ( 15, 13) [000068] ------------ * IL_OFFSET void IL offset: 0x20 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N054 ( 3, 2) [000058] ------------ * LCL_VAR simd16 V09 loc0 NA REG NA
Interval 12: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #26 @55 RefTypeDef <Ivl:12> LCL_VAR BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N054.t58. LCL_VAR }
N056 ( 3, 2) [000059] ------------ * LCL_VAR int V04 arg3 NA REG NA
Interval 13: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #27 @57 RefTypeDef <Ivl:13> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N054.t58. LCL_VAR; N056.t59. LCL_VAR }
N058 ( 4, 4) [000118] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #28 @58 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last>
Interval 14: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #29 @59 RefTypeDef <Ivl:14> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N054.t58. LCL_VAR; N058.t118. CAST }
N060 ( 1, 1) [000060] -c---------- * CNS_INT int 3 REG NA
Contained
DefList: { N054.t58. LCL_VAR; N058.t118. CAST }
N062 ( 11, 10) [000064] ------------ * HWIntrinsic simd16 ushort Insert REG NA
<RefPosition #30 @62 RefTypeUse <Ivl:12> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #31 @62 RefTypeUse <Ivl:14> BB02 regmask=[allInt] minReg=1 last>
Interval 15: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #32 @63 RefTypeDef <Ivl:15> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N062.t64. HWIntrinsic }
N064 ( 15, 13) [000067] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
<RefPosition #33 @64 RefTypeUse <Ivl:15> BB02 regmask=[allFloat] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N066 ( 15, 13) [000079] ------------ * IL_OFFSET void IL offset: 0x29 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N068 ( 3, 2) [000069] ------------ * LCL_VAR simd16 V09 loc0 NA REG NA
Interval 16: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #34 @69 RefTypeDef <Ivl:16> LCL_VAR BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N068.t69. LCL_VAR }
N070 ( 3, 2) [000070] ------------ * LCL_VAR int V05 arg4 NA REG NA
Interval 17: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #35 @71 RefTypeDef <Ivl:17> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N068.t69. LCL_VAR; N070.t70. LCL_VAR }
N072 ( 4, 4) [000119] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #36 @72 RefTypeUse <Ivl:17> BB02 regmask=[allInt] minReg=1 last>
Interval 18: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #37 @73 RefTypeDef <Ivl:18> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N068.t69. LCL_VAR; N072.t119. CAST }
N074 ( 1, 1) [000071] -c---------- * CNS_INT int 4 REG NA
Contained
DefList: { N068.t69. LCL_VAR; N072.t119. CAST }
N076 ( 11, 10) [000075] ------------ * HWIntrinsic simd16 ushort Insert REG NA
<RefPosition #38 @76 RefTypeUse <Ivl:16> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #39 @76 RefTypeUse <Ivl:18> BB02 regmask=[allInt] minReg=1 last>
Interval 19: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #40 @77 RefTypeDef <Ivl:19> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N076.t75. HWIntrinsic }
N078 ( 15, 13) [000078] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
<RefPosition #41 @78 RefTypeUse <Ivl:19> BB02 regmask=[allFloat] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N080 ( 15, 13) [000090] ------------ * IL_OFFSET void IL offset: 0x33 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N082 ( 3, 2) [000080] ------------ * LCL_VAR simd16 V09 loc0 NA REG NA
Interval 20: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #42 @83 RefTypeDef <Ivl:20> LCL_VAR BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N082.t80. LCL_VAR }
N084 ( 3, 2) [000081] ------------ * LCL_VAR int V06 arg5 NA REG NA
Interval 21: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #43 @85 RefTypeDef <Ivl:21> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N082.t80. LCL_VAR; N084.t81. LCL_VAR }
N086 ( 4, 4) [000120] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #44 @86 RefTypeUse <Ivl:21> BB02 regmask=[allInt] minReg=1 last>
Interval 22: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #45 @87 RefTypeDef <Ivl:22> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N082.t80. LCL_VAR; N086.t120. CAST }
N088 ( 1, 1) [000082] -c---------- * CNS_INT int 5 REG NA
Contained
DefList: { N082.t80. LCL_VAR; N086.t120. CAST }
N090 ( 11, 10) [000086] ------------ * HWIntrinsic simd16 ushort Insert REG NA
<RefPosition #46 @90 RefTypeUse <Ivl:20> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #47 @90 RefTypeUse <Ivl:22> BB02 regmask=[allInt] minReg=1 last>
Interval 23: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #48 @91 RefTypeDef <Ivl:23> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N090.t86. HWIntrinsic }
N092 ( 15, 13) [000089] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
<RefPosition #49 @92 RefTypeUse <Ivl:23> BB02 regmask=[allFloat] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N094 ( 15, 13) [000101] ------------ * IL_OFFSET void IL offset: 0x3d REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N096 ( 3, 2) [000091] ------------ * LCL_VAR simd16 V09 loc0 NA REG NA
Interval 24: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #50 @97 RefTypeDef <Ivl:24> LCL_VAR BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N096.t91. LCL_VAR }
N098 ( 3, 2) [000092] ------------ * LCL_VAR int V07 arg6 NA REG NA
Interval 25: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #51 @99 RefTypeDef <Ivl:25> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N096.t91. LCL_VAR; N098.t92. LCL_VAR }
N100 ( 4, 4) [000121] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #52 @100 RefTypeUse <Ivl:25> BB02 regmask=[allInt] minReg=1 last>
Interval 26: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #53 @101 RefTypeDef <Ivl:26> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N096.t91. LCL_VAR; N100.t121. CAST }
N102 ( 1, 1) [000093] -c---------- * CNS_INT int 6 REG NA
Contained
DefList: { N096.t91. LCL_VAR; N100.t121. CAST }
N104 ( 11, 10) [000097] ------------ * HWIntrinsic simd16 ushort Insert REG NA
<RefPosition #54 @104 RefTypeUse <Ivl:24> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #55 @104 RefTypeUse <Ivl:26> BB02 regmask=[allInt] minReg=1 last>
Interval 27: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #56 @105 RefTypeDef <Ivl:27> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N104.t97. HWIntrinsic }
N106 ( 15, 13) [000100] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
<RefPosition #57 @106 RefTypeUse <Ivl:27> BB02 regmask=[allFloat] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N108 ( 18, 15) [000112] ------------ * IL_OFFSET void IL offset: 0x47 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N110 ( 3, 2) [000102] ------------ * LCL_VAR simd16 V09 loc0 NA REG NA
Interval 28: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #58 @111 RefTypeDef <Ivl:28> LCL_VAR BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N110.t102. LCL_VAR }
N112 ( 3, 2) [000103] ------------ * LCL_VAR int V08 arg7 NA REG NA
Interval 29: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #59 @113 RefTypeDef <Ivl:29> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N110.t102. LCL_VAR; N112.t103. LCL_VAR }
N114 ( 4, 4) [000122] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #60 @114 RefTypeUse <Ivl:29> BB02 regmask=[allInt] minReg=1 last>
Interval 30: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #61 @115 RefTypeDef <Ivl:30> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N110.t102. LCL_VAR; N114.t122. CAST }
N116 ( 1, 1) [000104] -c---------- * CNS_INT int 7 REG NA
Contained
DefList: { N110.t102. LCL_VAR; N114.t122. CAST }
N118 ( 11, 10) [000108] ------------ * HWIntrinsic simd16 ushort Insert REG NA
<RefPosition #62 @118 RefTypeUse <Ivl:28> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #63 @118 RefTypeUse <Ivl:30> BB02 regmask=[allInt] minReg=1 last>
Interval 31: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #64 @119 RefTypeDef <Ivl:31> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N118.t108. HWIntrinsic }
N120 ( 3, 2) [000109] ------------ * LCL_VAR byref V00 RetBuf NA REG NA
Interval 32: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #65 @121 RefTypeDef <Ivl:32> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N118.t108. HWIntrinsic; N120.t109. LCL_VAR }
N122 (???,???) [000135] -A-X-------- * STOREIND simd16 REG NA
<RefPosition #66 @122 RefTypeUse <Ivl:32> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #67 @122 RefTypeUse <Ivl:31> BB02 regmask=[allFloat] minReg=1 last>
+<TreeNodeInfo 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=0
DefList: { }
N124 ( 0, 0) [000113] ------------ * RETURN void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
NEW BLOCK BB03
Setting BB03 as the predecessor for determining incoming variable registers of BB01
<RefPosition #68 @126 RefTypeBB BB03 regmask=[] minReg=1>
DefList: { }
N128 ( 70, 41) [000026] ------------ * IL_OFFSET void IL offset: 0x51 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N130 ( 3, 2) [000008] ------------ * LCL_VAR int V02 arg1 NA REG NA
Interval 33: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #69 @131 RefTypeDef <Ivl:33> LCL_VAR BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N130.t8. LCL_VAR }
N132 ( 4, 4) [000124] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #70 @132 RefTypeUse <Ivl:33> BB03 regmask=[allInt] minReg=1 last>
Interval 34: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #71 @133 RefTypeDef <Ivl:34> CAST BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N132.t124. CAST }
N134 (???,???) [000136] ------------ * PUTARG_STK [+0x00] void (1 slots) REG NA
<RefPosition #72 @134 RefTypeUse <Ivl:34> BB03 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N136 ( 3, 2) [000009] ------------ * LCL_VAR int V03 arg2 NA REG NA
Interval 35: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #73 @137 RefTypeDef <Ivl:35> LCL_VAR BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N136.t9. LCL_VAR }
N138 ( 4, 4) [000125] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #74 @138 RefTypeUse <Ivl:35> BB03 regmask=[allInt] minReg=1 last>
Interval 36: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #75 @139 RefTypeDef <Ivl:36> CAST BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N138.t125. CAST }
N140 (???,???) [000137] ------------ * PUTARG_STK [+0x04] void (1 slots) REG NA
<RefPosition #76 @140 RefTypeUse <Ivl:36> BB03 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N142 ( 3, 2) [000010] ------------ * LCL_VAR int V04 arg3 NA REG NA
Interval 37: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #77 @143 RefTypeDef <Ivl:37> LCL_VAR BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N142.t10. LCL_VAR }
N144 ( 4, 4) [000126] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #78 @144 RefTypeUse <Ivl:37> BB03 regmask=[allInt] minReg=1 last>
Interval 38: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #79 @145 RefTypeDef <Ivl:38> CAST BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N144.t126. CAST }
N146 (???,???) [000138] ------------ * PUTARG_STK [+0x08] void (1 slots) REG NA
<RefPosition #80 @146 RefTypeUse <Ivl:38> BB03 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N148 ( 3, 2) [000011] ------------ * LCL_VAR int V05 arg4 NA REG NA
Interval 39: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #81 @149 RefTypeDef <Ivl:39> LCL_VAR BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N148.t11. LCL_VAR }
N150 ( 4, 4) [000127] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #82 @150 RefTypeUse <Ivl:39> BB03 regmask=[allInt] minReg=1 last>
Interval 40: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #83 @151 RefTypeDef <Ivl:40> CAST BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N150.t127. CAST }
N152 (???,???) [000139] ------------ * PUTARG_STK [+0x0c] void (1 slots) REG NA
<RefPosition #84 @152 RefTypeUse <Ivl:40> BB03 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N154 ( 3, 2) [000012] ------------ * LCL_VAR int V06 arg5 NA REG NA
Interval 41: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #85 @155 RefTypeDef <Ivl:41> LCL_VAR BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N154.t12. LCL_VAR }
N156 ( 4, 4) [000128] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #86 @156 RefTypeUse <Ivl:41> BB03 regmask=[allInt] minReg=1 last>
Interval 42: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #87 @157 RefTypeDef <Ivl:42> CAST BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N156.t128. CAST }
N158 (???,???) [000140] ------------ * PUTARG_STK [+0x10] void (1 slots) REG NA
<RefPosition #88 @158 RefTypeUse <Ivl:42> BB03 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N160 ( 3, 2) [000013] ------------ * LCL_VAR int V07 arg6 NA REG NA
Interval 43: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #89 @161 RefTypeDef <Ivl:43> LCL_VAR BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N160.t13. LCL_VAR }
N162 ( 4, 4) [000129] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #90 @162 RefTypeUse <Ivl:43> BB03 regmask=[allInt] minReg=1 last>
Interval 44: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #91 @163 RefTypeDef <Ivl:44> CAST BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N162.t129. CAST }
N164 (???,???) [000141] ------------ * PUTARG_STK [+0x14] void (1 slots) REG NA
<RefPosition #92 @164 RefTypeUse <Ivl:44> BB03 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N166 ( 3, 2) [000014] ------------ * LCL_VAR int V08 arg7 NA REG NA
Interval 45: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #93 @167 RefTypeDef <Ivl:45> LCL_VAR BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N166.t14. LCL_VAR }
N168 ( 4, 4) [000130] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #94 @168 RefTypeUse <Ivl:45> BB03 regmask=[allInt] minReg=1 last>
Interval 46: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #95 @169 RefTypeDef <Ivl:46> CAST BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N168.t130. CAST }
N170 (???,???) [000142] ------------ * PUTARG_STK [+0x18] void (1 slots) REG NA
<RefPosition #96 @170 RefTypeUse <Ivl:46> BB03 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N172 ( 3, 2) [000007] ------------ * LCL_VAR int V01 arg0 NA REG NA
Interval 47: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #97 @173 RefTypeDef <Ivl:47> LCL_VAR BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N172.t7. LCL_VAR }
N174 ( 4, 4) [000123] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #98 @174 RefTypeUse <Ivl:47> BB03 regmask=[allInt] minReg=1 last>
Interval 48: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #99 @175 RefTypeDef <Ivl:48> CAST BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N174.t123. CAST }
N176 (???,???) [000143] ------------ * PUTARG_REG int REG edx
<RefPosition #100 @176 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #101 @176 RefTypeUse <Ivl:48> BB03 regmask=[edx] minReg=1 last fixed>
Interval 49: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #102 @177 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #103 @177 RefTypeDef <Ivl:49> PUTARG_REG BB03 regmask=[edx] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N176.t143. PUTARG_REG }
N178 ( 3, 2) [000024] ------------ * LCL_VAR byref V00 RetBuf NA REG NA
Interval 50: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #104 @179 RefTypeDef <Ivl:50> LCL_VAR BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N176.t143. PUTARG_REG; N178.t24. LCL_VAR }
N180 (???,???) [000144] ------------ * PUTARG_REG byref REG ecx
<RefPosition #105 @180 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #106 @180 RefTypeUse <Ivl:50> BB03 regmask=[ecx] minReg=1 last fixed>
Interval 51: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #107 @181 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #108 @181 RefTypeDef <Ivl:51> PUTARG_REG BB03 regmask=[ecx] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N176.t143. PUTARG_REG; N180.t144. PUTARG_REG }
N182 ( 70, 41) [000015] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
<RefPosition #109 @182 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #110 @182 RefTypeUse <Ivl:49> BB03 regmask=[edx] minReg=1 last fixed>
<RefPosition #111 @182 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #112 @182 RefTypeUse <Ivl:51> BB03 regmask=[ecx] minReg=1 last fixed>
<RefPosition #113 @183 RefTypeKill <Reg:eax> BB03 regmask=[eax] minReg=1>
<RefPosition #114 @183 RefTypeKill <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #115 @183 RefTypeKill <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #116 @183 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1>
<RefPosition #117 @183 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1>
<RefPosition #118 @183 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1>
<RefPosition #119 @183 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1>
<RefPosition #120 @183 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1>
<RefPosition #121 @183 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1>
<RefPosition #122 @183 RefTypeKill <Reg:mm6> BB03 regmask=[mm6] minReg=1>
<RefPosition #123 @183 RefTypeKill <Reg:mm7> BB03 regmask=[mm7] minReg=1>
+<TreeNodeInfo 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=0
DefList: { }
N184 ( 0, 0) [000027] ------------ * RETURN void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (constant) RefPositions {#1@5 #2@8} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#4@17 #5@18} physReg:NA Preferences=[allInt]
Interval 2: RefPositions {#6@19 #7@20} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {#8@21 #9@22} physReg:NA Preferences=[allFloat]
Interval 4: RefPositions {#10@27 #14@34} physReg:NA Preferences=[allFloat]
Interval 5: RefPositions {#11@29 #12@30} physReg:NA Preferences=[allInt]
Interval 6: RefPositions {#13@31 #15@34} physReg:NA Preferences=[allInt]
Interval 7: RefPositions {#16@35 #17@36} physReg:NA Preferences=[allFloat]
Interval 8: RefPositions {#18@41 #22@48} physReg:NA Preferences=[allFloat]
Interval 9: RefPositions {#19@43 #20@44} physReg:NA Preferences=[allInt]
Interval 10: RefPositions {#21@45 #23@48} physReg:NA Preferences=[allInt]
Interval 11: RefPositions {#24@49 #25@50} physReg:NA Preferences=[allFloat]
Interval 12: RefPositions {#26@55 #30@62} physReg:NA Preferences=[allFloat]
Interval 13: RefPositions {#27@57 #28@58} physReg:NA Preferences=[allInt]
Interval 14: RefPositions {#29@59 #31@62} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#32@63 #33@64} physReg:NA Preferences=[allFloat]
Interval 16: RefPositions {#34@69 #38@76} physReg:NA Preferences=[allFloat]
Interval 17: RefPositions {#35@71 #36@72} physReg:NA Preferences=[allInt]
Interval 18: RefPositions {#37@73 #39@76} physReg:NA Preferences=[allInt]
Interval 19: RefPositions {#40@77 #41@78} physReg:NA Preferences=[allFloat]
Interval 20: RefPositions {#42@83 #46@90} physReg:NA Preferences=[allFloat]
Interval 21: RefPositions {#43@85 #44@86} physReg:NA Preferences=[allInt]
Interval 22: RefPositions {#45@87 #47@90} physReg:NA Preferences=[allInt]
Interval 23: RefPositions {#48@91 #49@92} physReg:NA Preferences=[allFloat]
Interval 24: RefPositions {#50@97 #54@104} physReg:NA Preferences=[allFloat]
Interval 25: RefPositions {#51@99 #52@100} physReg:NA Preferences=[allInt]
Interval 26: RefPositions {#53@101 #55@104} physReg:NA Preferences=[allInt]
Interval 27: RefPositions {#56@105 #57@106} physReg:NA Preferences=[allFloat]
Interval 28: RefPositions {#58@111 #62@118} physReg:NA Preferences=[allFloat]
Interval 29: RefPositions {#59@113 #60@114} physReg:NA Preferences=[allInt]
Interval 30: RefPositions {#61@115 #63@118} physReg:NA Preferences=[allInt]
Interval 31: RefPositions {#64@119 #67@122} physReg:NA Preferences=[allFloat]
Interval 32: RefPositions {#65@121 #66@122} physReg:NA Preferences=[allInt]
Interval 33: RefPositions {#69@131 #70@132} physReg:NA Preferences=[allInt]
Interval 34: RefPositions {#71@133 #72@134} physReg:NA Preferences=[allInt]
Interval 35: RefPositions {#73@137 #74@138} physReg:NA Preferences=[allInt]
Interval 36: RefPositions {#75@139 #76@140} physReg:NA Preferences=[allInt]
Interval 37: RefPositions {#77@143 #78@144} physReg:NA Preferences=[allInt]
Interval 38: RefPositions {#79@145 #80@146} physReg:NA Preferences=[allInt]
Interval 39: RefPositions {#81@149 #82@150} physReg:NA Preferences=[allInt]
Interval 40: RefPositions {#83@151 #84@152} physReg:NA Preferences=[allInt]
Interval 41: RefPositions {#85@155 #86@156} physReg:NA Preferences=[allInt]
Interval 42: RefPositions {#87@157 #88@158} physReg:NA Preferences=[allInt]
Interval 43: RefPositions {#89@161 #90@162} physReg:NA Preferences=[allInt]
Interval 44: RefPositions {#91@163 #92@164} physReg:NA Preferences=[allInt]
Interval 45: RefPositions {#93@167 #94@168} physReg:NA Preferences=[allInt]
Interval 46: RefPositions {#95@169 #96@170} physReg:NA Preferences=[allInt]
Interval 47: RefPositions {#97@173 #98@174} physReg:NA Preferences=[allInt]
Interval 48: RefPositions {#99@175 #101@176} physReg:NA Preferences=[edx]
Interval 49: RefPositions {#103@177 #110@182} physReg:NA Preferences=[edx]
Interval 50: RefPositions {#104@179 #106@180} physReg:NA Preferences=[ecx]
Interval 51: RefPositions {#108@181 #112@182} physReg:NA Preferences=[ecx]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #2 @8 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #3 @12 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #4 @17 RefTypeDef <Ivl:1> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #5 @18 RefTypeUse <Ivl:1> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #6 @19 RefTypeDef <Ivl:2> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #7 @20 RefTypeUse <Ivl:2> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #8 @21 RefTypeDef <Ivl:3> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #9 @22 RefTypeUse <Ivl:3> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #10 @27 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #11 @29 RefTypeDef <Ivl:5> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #12 @30 RefTypeUse <Ivl:5> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #13 @31 RefTypeDef <Ivl:6> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #14 @34 RefTypeUse <Ivl:4> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #15 @34 RefTypeUse <Ivl:6> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #16 @35 RefTypeDef <Ivl:7> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #17 @36 RefTypeUse <Ivl:7> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #18 @41 RefTypeDef <Ivl:8> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #19 @43 RefTypeDef <Ivl:9> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #20 @44 RefTypeUse <Ivl:9> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #21 @45 RefTypeDef <Ivl:10> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #22 @48 RefTypeUse <Ivl:8> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #23 @48 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #24 @49 RefTypeDef <Ivl:11> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #25 @50 RefTypeUse <Ivl:11> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #26 @55 RefTypeDef <Ivl:12> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #27 @57 RefTypeDef <Ivl:13> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #28 @58 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #29 @59 RefTypeDef <Ivl:14> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #30 @62 RefTypeUse <Ivl:12> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #31 @62 RefTypeUse <Ivl:14> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #32 @63 RefTypeDef <Ivl:15> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #33 @64 RefTypeUse <Ivl:15> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #34 @69 RefTypeDef <Ivl:16> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #35 @71 RefTypeDef <Ivl:17> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #36 @72 RefTypeUse <Ivl:17> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #37 @73 RefTypeDef <Ivl:18> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #38 @76 RefTypeUse <Ivl:16> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #39 @76 RefTypeUse <Ivl:18> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #40 @77 RefTypeDef <Ivl:19> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #41 @78 RefTypeUse <Ivl:19> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #42 @83 RefTypeDef <Ivl:20> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #43 @85 RefTypeDef <Ivl:21> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #44 @86 RefTypeUse <Ivl:21> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #45 @87 RefTypeDef <Ivl:22> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #46 @90 RefTypeUse <Ivl:20> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #47 @90 RefTypeUse <Ivl:22> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #48 @91 RefTypeDef <Ivl:23> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #49 @92 RefTypeUse <Ivl:23> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #50 @97 RefTypeDef <Ivl:24> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #51 @99 RefTypeDef <Ivl:25> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #52 @100 RefTypeUse <Ivl:25> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #53 @101 RefTypeDef <Ivl:26> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #54 @104 RefTypeUse <Ivl:24> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #55 @104 RefTypeUse <Ivl:26> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #56 @105 RefTypeDef <Ivl:27> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #57 @106 RefTypeUse <Ivl:27> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #58 @111 RefTypeDef <Ivl:28> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #59 @113 RefTypeDef <Ivl:29> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #60 @114 RefTypeUse <Ivl:29> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #61 @115 RefTypeDef <Ivl:30> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #62 @118 RefTypeUse <Ivl:28> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #63 @118 RefTypeUse <Ivl:30> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #64 @119 RefTypeDef <Ivl:31> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #65 @121 RefTypeDef <Ivl:32> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #66 @122 RefTypeUse <Ivl:32> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #67 @122 RefTypeUse <Ivl:31> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #68 @126 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #69 @131 RefTypeDef <Ivl:33> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #70 @132 RefTypeUse <Ivl:33> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #71 @133 RefTypeDef <Ivl:34> CAST BB03 regmask=[allInt] minReg=1>
<RefPosition #72 @134 RefTypeUse <Ivl:34> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #73 @137 RefTypeDef <Ivl:35> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #74 @138 RefTypeUse <Ivl:35> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #75 @139 RefTypeDef <Ivl:36> CAST BB03 regmask=[allInt] minReg=1>
<RefPosition #76 @140 RefTypeUse <Ivl:36> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #77 @143 RefTypeDef <Ivl:37> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #78 @144 RefTypeUse <Ivl:37> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #79 @145 RefTypeDef <Ivl:38> CAST BB03 regmask=[allInt] minReg=1>
<RefPosition #80 @146 RefTypeUse <Ivl:38> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #81 @149 RefTypeDef <Ivl:39> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #82 @150 RefTypeUse <Ivl:39> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #83 @151 RefTypeDef <Ivl:40> CAST BB03 regmask=[allInt] minReg=1>
<RefPosition #84 @152 RefTypeUse <Ivl:40> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #85 @155 RefTypeDef <Ivl:41> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #86 @156 RefTypeUse <Ivl:41> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #87 @157 RefTypeDef <Ivl:42> CAST BB03 regmask=[allInt] minReg=1>
<RefPosition #88 @158 RefTypeUse <Ivl:42> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #89 @161 RefTypeDef <Ivl:43> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #90 @162 RefTypeUse <Ivl:43> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #91 @163 RefTypeDef <Ivl:44> CAST BB03 regmask=[allInt] minReg=1>
<RefPosition #92 @164 RefTypeUse <Ivl:44> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #93 @167 RefTypeDef <Ivl:45> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #94 @168 RefTypeUse <Ivl:45> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #95 @169 RefTypeDef <Ivl:46> CAST BB03 regmask=[allInt] minReg=1>
<RefPosition #96 @170 RefTypeUse <Ivl:46> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #97 @173 RefTypeDef <Ivl:47> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #98 @174 RefTypeUse <Ivl:47> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #99 @175 RefTypeDef <Ivl:48> CAST BB03 regmask=[edx] minReg=1>
<RefPosition #100 @176 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #101 @176 RefTypeUse <Ivl:48> BB03 regmask=[edx] minReg=1 last fixed>
<RefPosition #102 @177 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #103 @177 RefTypeDef <Ivl:49> PUTARG_REG BB03 regmask=[edx] minReg=1 fixed>
<RefPosition #104 @179 RefTypeDef <Ivl:50> LCL_VAR BB03 regmask=[ecx] minReg=1>
<RefPosition #105 @180 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #106 @180 RefTypeUse <Ivl:50> BB03 regmask=[ecx] minReg=1 last fixed>
<RefPosition #107 @181 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #108 @181 RefTypeDef <Ivl:51> PUTARG_REG BB03 regmask=[ecx] minReg=1 fixed>
<RefPosition #109 @182 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #110 @182 RefTypeUse <Ivl:49> BB03 regmask=[edx] minReg=1 last fixed>
<RefPosition #111 @182 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #112 @182 RefTypeUse <Ivl:51> BB03 regmask=[ecx] minReg=1 last fixed>
<RefPosition #113 @183 RefTypeKill <Reg:eax> BB03 regmask=[eax] minReg=1 last>
<RefPosition #114 @183 RefTypeKill <Reg:ecx> BB03 regmask=[ecx] minReg=1 last>
<RefPosition #115 @183 RefTypeKill <Reg:edx> BB03 regmask=[edx] minReg=1 last>
<RefPosition #116 @183 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
<RefPosition #117 @183 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
<RefPosition #118 @183 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
<RefPosition #119 @183 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
<RefPosition #120 @183 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
<RefPosition #121 @183 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
<RefPosition #122 @183 RefTypeKill <Reg:mm6> BB03 regmask=[mm6] minReg=1 last>
<RefPosition #123 @183 RefTypeKill <Reg:mm7> BB03 regmask=[mm7] minReg=1 last>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:
BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N002. IL_OFFSET IL offset: 0x0 REG NA
N004. CNS_INT 0 REG NA
Def:<I0>(#1)
N006. CNS_INT 1 REG NA
N008. EQ
Use:<I0>(#2) *
N010. JTRUE
BB02 [007..051) (return), preds={BB01} succs={}
=====
N014. IL_OFFSET IL offset: 0x7 REG NA
N016. V01 MEM
Def:<I1>(#4)
N018. CAST
Use:<I1>(#5) *
Def:<I2>(#6)
N020. HWIntrinsic
Use:<I2>(#7) *
Def:<I3>(#8)
N022. V09 MEM
Use:<I3>(#9) *
N024. IL_OFFSET IL offset: 0xe REG NA
N026. V09 MEM
Def:<I4>(#10)
N028. V02 MEM
Def:<I5>(#11)
N030. CAST
Use:<I5>(#12) *
Def:<I6>(#13)
N032. CNS_INT 1 REG NA
N034. HWIntrinsic
Use:<I4>(#14) *
Use:<I6>(#15) *
Def:<I7>(#16)
N036. V09 MEM
Use:<I7>(#17) *
N038. IL_OFFSET IL offset: 0x17 REG NA
N040. V09 MEM
Def:<I8>(#18)
N042. V03 MEM
Def:<I9>(#19)
N044. CAST
Use:<I9>(#20) *
Def:<I10>(#21)
N046. CNS_INT 2 REG NA
N048. HWIntrinsic
Use:<I8>(#22) *
Use:<I10>(#23) *
Def:<I11>(#24)
N050. V09 MEM
Use:<I11>(#25) *
N052. IL_OFFSET IL offset: 0x20 REG NA
N054. V09 MEM
Def:<I12>(#26)
N056. V04 MEM
Def:<I13>(#27)
N058. CAST
Use:<I13>(#28) *
Def:<I14>(#29)
N060. CNS_INT 3 REG NA
N062. HWIntrinsic
Use:<I12>(#30) *
Use:<I14>(#31) *
Def:<I15>(#32)
N064. V09 MEM
Use:<I15>(#33) *
N066. IL_OFFSET IL offset: 0x29 REG NA
N068. V09 MEM
Def:<I16>(#34)
N070. V05 MEM
Def:<I17>(#35)
N072. CAST
Use:<I17>(#36) *
Def:<I18>(#37)
N074. CNS_INT 4 REG NA
N076. HWIntrinsic
Use:<I16>(#38) *
Use:<I18>(#39) *
Def:<I19>(#40)
N078. V09 MEM
Use:<I19>(#41) *
N080. IL_OFFSET IL offset: 0x33 REG NA
N082. V09 MEM
Def:<I20>(#42)
N084. V06 MEM
Def:<I21>(#43)
N086. CAST
Use:<I21>(#44) *
Def:<I22>(#45)
N088. CNS_INT 5 REG NA
N090. HWIntrinsic
Use:<I20>(#46) *
Use:<I22>(#47) *
Def:<I23>(#48)
N092. V09 MEM
Use:<I23>(#49) *
N094. IL_OFFSET IL offset: 0x3d REG NA
N096. V09 MEM
Def:<I24>(#50)
N098. V07 MEM
Def:<I25>(#51)
N100. CAST
Use:<I25>(#52) *
Def:<I26>(#53)
N102. CNS_INT 6 REG NA
N104. HWIntrinsic
Use:<I24>(#54) *
Use:<I26>(#55) *
Def:<I27>(#56)
N106. V09 MEM
Use:<I27>(#57) *
N108. IL_OFFSET IL offset: 0x47 REG NA
N110. V09 MEM
Def:<I28>(#58)
N112. V08 MEM
Def:<I29>(#59)
N114. CAST
Use:<I29>(#60) *
Def:<I30>(#61)
N116. CNS_INT 7 REG NA
N118. HWIntrinsic
Use:<I28>(#62) *
Use:<I30>(#63) *
Def:<I31>(#64)
N120. V00 MEM
Def:<I32>(#65)
N122. STOREIND
Use:<I32>(#66) *
Use:<I31>(#67) *
N124. RETURN
BB03 [051..063) (return), preds={BB01} succs={}
=====
N128. IL_OFFSET IL offset: 0x51 REG NA
N130. V02 MEM
Def:<I33>(#69)
N132. CAST
Use:<I33>(#70) *
Def:<I34>(#71)
N134. PUTARG_STK [+0x00]
Use:<I34>(#72) *
N136. V03 MEM
Def:<I35>(#73)
N138. CAST
Use:<I35>(#74) *
Def:<I36>(#75)
N140. PUTARG_STK [+0x04]
Use:<I36>(#76) *
N142. V04 MEM
Def:<I37>(#77)
N144. CAST
Use:<I37>(#78) *
Def:<I38>(#79)
N146. PUTARG_STK [+0x08]
Use:<I38>(#80) *
N148. V05 MEM
Def:<I39>(#81)
N150. CAST
Use:<I39>(#82) *
Def:<I40>(#83)
N152. PUTARG_STK [+0x0c]
Use:<I40>(#84) *
N154. V06 MEM
Def:<I41>(#85)
N156. CAST
Use:<I41>(#86) *
Def:<I42>(#87)
N158. PUTARG_STK [+0x10]
Use:<I42>(#88) *
N160. V07 MEM
Def:<I43>(#89)
N162. CAST
Use:<I43>(#90) *
Def:<I44>(#91)
N164. PUTARG_STK [+0x14]
Use:<I44>(#92) *
N166. V08 MEM
Def:<I45>(#93)
N168. CAST
Use:<I45>(#94) *
Def:<I46>(#95)
N170. PUTARG_STK [+0x18]
Use:<I46>(#96) *
N172. V01 MEM
Def:<I47>(#97)
N174. CAST
Use:<I47>(#98) *
Def:<I48>(#99)
N176. PUTARG_REG
Use:<I48>(#101) Fixed:edx(#100) *
Def:<I49>(#103) edx
N178. V00 MEM
Def:<I50>(#104)
N180. PUTARG_REG
Use:<I50>(#106) Fixed:ecx(#105) *
Def:<I51>(#108) ecx
N182. CALL
Use:<I49>(#110) Fixed:edx(#109) *
Use:<I51>(#112) Fixed:ecx(#111) *
Kill: eax ecx edx mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7
N184. RETURN
Linear scan intervals after buildIntervals:
Interval 0: (constant) RefPositions {#1@5 #2@8} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#4@17 #5@18} physReg:NA Preferences=[allInt]
Interval 2: RefPositions {#6@19 #7@20} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {#8@21 #9@22} physReg:NA Preferences=[allFloat]
Interval 4: RefPositions {#10@27 #14@34} physReg:NA Preferences=[allFloat]
Interval 5: RefPositions {#11@29 #12@30} physReg:NA Preferences=[allInt]
Interval 6: RefPositions {#13@31 #15@34} physReg:NA Preferences=[allInt]
Interval 7: RefPositions {#16@35 #17@36} physReg:NA Preferences=[allFloat]
Interval 8: RefPositions {#18@41 #22@48} physReg:NA Preferences=[allFloat]
Interval 9: RefPositions {#19@43 #20@44} physReg:NA Preferences=[allInt]
Interval 10: RefPositions {#21@45 #23@48} physReg:NA Preferences=[allInt]
Interval 11: RefPositions {#24@49 #25@50} physReg:NA Preferences=[allFloat]
Interval 12: RefPositions {#26@55 #30@62} physReg:NA Preferences=[allFloat]
Interval 13: RefPositions {#27@57 #28@58} physReg:NA Preferences=[allInt]
Interval 14: RefPositions {#29@59 #31@62} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#32@63 #33@64} physReg:NA Preferences=[allFloat]
Interval 16: RefPositions {#34@69 #38@76} physReg:NA Preferences=[allFloat]
Interval 17: RefPositions {#35@71 #36@72} physReg:NA Preferences=[allInt]
Interval 18: RefPositions {#37@73 #39@76} physReg:NA Preferences=[allInt]
Interval 19: RefPositions {#40@77 #41@78} physReg:NA Preferences=[allFloat]
Interval 20: RefPositions {#42@83 #46@90} physReg:NA Preferences=[allFloat]
Interval 21: RefPositions {#43@85 #44@86} physReg:NA Preferences=[allInt]
Interval 22: RefPositions {#45@87 #47@90} physReg:NA Preferences=[allInt]
Interval 23: RefPositions {#48@91 #49@92} physReg:NA Preferences=[allFloat]
Interval 24: RefPositions {#50@97 #54@104} physReg:NA Preferences=[allFloat]
Interval 25: RefPositions {#51@99 #52@100} physReg:NA Preferences=[allInt]
Interval 26: RefPositions {#53@101 #55@104} physReg:NA Preferences=[allInt]
Interval 27: RefPositions {#56@105 #57@106} physReg:NA Preferences=[allFloat]
Interval 28: RefPositions {#58@111 #62@118} physReg:NA Preferences=[allFloat]
Interval 29: RefPositions {#59@113 #60@114} physReg:NA Preferences=[allInt]
Interval 30: RefPositions {#61@115 #63@118} physReg:NA Preferences=[allInt]
Interval 31: RefPositions {#64@119 #67@122} physReg:NA Preferences=[allFloat]
Interval 32: RefPositions {#65@121 #66@122} physReg:NA Preferences=[allInt]
Interval 33: RefPositions {#69@131 #70@132} physReg:NA Preferences=[allInt]
Interval 34: RefPositions {#71@133 #72@134} physReg:NA Preferences=[allInt]
Interval 35: RefPositions {#73@137 #74@138} physReg:NA Preferences=[allInt]
Interval 36: RefPositions {#75@139 #76@140} physReg:NA Preferences=[allInt]
Interval 37: RefPositions {#77@143 #78@144} physReg:NA Preferences=[allInt]
Interval 38: RefPositions {#79@145 #80@146} physReg:NA Preferences=[allInt]
Interval 39: RefPositions {#81@149 #82@150} physReg:NA Preferences=[allInt]
Interval 40: RefPositions {#83@151 #84@152} physReg:NA Preferences=[allInt]
Interval 41: RefPositions {#85@155 #86@156} physReg:NA Preferences=[allInt]
Interval 42: RefPositions {#87@157 #88@158} physReg:NA Preferences=[allInt]
Interval 43: RefPositions {#89@161 #90@162} physReg:NA Preferences=[allInt]
Interval 44: RefPositions {#91@163 #92@164} physReg:NA Preferences=[allInt]
Interval 45: RefPositions {#93@167 #94@168} physReg:NA Preferences=[allInt]
Interval 46: RefPositions {#95@169 #96@170} physReg:NA Preferences=[allInt]
Interval 47: RefPositions {#97@173 #98@174} physReg:NA Preferences=[allInt]
Interval 48: RefPositions {#99@175 #101@176} physReg:NA Preferences=[edx]
Interval 49: RefPositions {#103@177 #110@182} physReg:NA Preferences=[edx]
Interval 50: RefPositions {#104@179 #106@180} physReg:NA Preferences=[ecx]
Interval 51: RefPositions {#108@181 #112@182} physReg:NA Preferences=[ecx]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (constant) RefPositions {#1@5 #2@8} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#4@17 #5@18} physReg:NA Preferences=[allInt]
Interval 2: RefPositions {#6@19 #7@20} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {#8@21 #9@22} physReg:NA Preferences=[allFloat]
Interval 4: RefPositions {#10@27 #14@34} physReg:NA Preferences=[allFloat]
Interval 5: RefPositions {#11@29 #12@30} physReg:NA Preferences=[allInt]
Interval 6: RefPositions {#13@31 #15@34} physReg:NA Preferences=[allInt]
Interval 7: RefPositions {#16@35 #17@36} physReg:NA Preferences=[allFloat]
Interval 8: RefPositions {#18@41 #22@48} physReg:NA Preferences=[allFloat]
Interval 9: RefPositions {#19@43 #20@44} physReg:NA Preferences=[allInt]
Interval 10: RefPositions {#21@45 #23@48} physReg:NA Preferences=[allInt]
Interval 11: RefPositions {#24@49 #25@50} physReg:NA Preferences=[allFloat]
Interval 12: RefPositions {#26@55 #30@62} physReg:NA Preferences=[allFloat]
Interval 13: RefPositions {#27@57 #28@58} physReg:NA Preferences=[allInt]
Interval 14: RefPositions {#29@59 #31@62} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#32@63 #33@64} physReg:NA Preferences=[allFloat]
Interval 16: RefPositions {#34@69 #38@76} physReg:NA Preferences=[allFloat]
Interval 17: RefPositions {#35@71 #36@72} physReg:NA Preferences=[allInt]
Interval 18: RefPositions {#37@73 #39@76} physReg:NA Preferences=[allInt]
Interval 19: RefPositions {#40@77 #41@78} physReg:NA Preferences=[allFloat]
Interval 20: RefPositions {#42@83 #46@90} physReg:NA Preferences=[allFloat]
Interval 21: RefPositions {#43@85 #44@86} physReg:NA Preferences=[allInt]
Interval 22: RefPositions {#45@87 #47@90} physReg:NA Preferences=[allInt]
Interval 23: RefPositions {#48@91 #49@92} physReg:NA Preferences=[allFloat]
Interval 24: RefPositions {#50@97 #54@104} physReg:NA Preferences=[allFloat]
Interval 25: RefPositions {#51@99 #52@100} physReg:NA Preferences=[allInt]
Interval 26: RefPositions {#53@101 #55@104} physReg:NA Preferences=[allInt]
Interval 27: RefPositions {#56@105 #57@106} physReg:NA Preferences=[allFloat]
Interval 28: RefPositions {#58@111 #62@118} physReg:NA Preferences=[allFloat]
Interval 29: RefPositions {#59@113 #60@114} physReg:NA Preferences=[allInt]
Interval 30: RefPositions {#61@115 #63@118} physReg:NA Preferences=[allInt]
Interval 31: RefPositions {#64@119 #67@122} physReg:NA Preferences=[allFloat]
Interval 32: RefPositions {#65@121 #66@122} physReg:NA Preferences=[allInt]
Interval 33: RefPositions {#69@131 #70@132} physReg:NA Preferences=[allInt]
Interval 34: RefPositions {#71@133 #72@134} physReg:NA Preferences=[allInt]
Interval 35: RefPositions {#73@137 #74@138} physReg:NA Preferences=[allInt]
Interval 36: RefPositions {#75@139 #76@140} physReg:NA Preferences=[allInt]
Interval 37: RefPositions {#77@143 #78@144} physReg:NA Preferences=[allInt]
Interval 38: RefPositions {#79@145 #80@146} physReg:NA Preferences=[allInt]
Interval 39: RefPositions {#81@149 #82@150} physReg:NA Preferences=[allInt]
Interval 40: RefPositions {#83@151 #84@152} physReg:NA Preferences=[allInt]
Interval 41: RefPositions {#85@155 #86@156} physReg:NA Preferences=[allInt]
Interval 42: RefPositions {#87@157 #88@158} physReg:NA Preferences=[allInt]
Interval 43: RefPositions {#89@161 #90@162} physReg:NA Preferences=[allInt]
Interval 44: RefPositions {#91@163 #92@164} physReg:NA Preferences=[allInt]
Interval 45: RefPositions {#93@167 #94@168} physReg:NA Preferences=[allInt]
Interval 46: RefPositions {#95@169 #96@170} physReg:NA Preferences=[allInt]
Interval 47: RefPositions {#97@173 #98@174} physReg:NA Preferences=[allInt]
Interval 48: RefPositions {#99@175 #101@176} physReg:NA Preferences=[edx]
Interval 49: RefPositions {#103@177 #110@182} physReg:NA Preferences=[edx]
Interval 50: RefPositions {#104@179 #106@180} physReg:NA Preferences=[ecx]
Interval 51: RefPositions {#108@181 #112@182} physReg:NA Preferences=[ecx]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #2 @8 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #3 @12 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #4 @17 RefTypeDef <Ivl:1> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #5 @18 RefTypeUse <Ivl:1> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #6 @19 RefTypeDef <Ivl:2> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #7 @20 RefTypeUse <Ivl:2> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #8 @21 RefTypeDef <Ivl:3> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #9 @22 RefTypeUse <Ivl:3> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #10 @27 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #11 @29 RefTypeDef <Ivl:5> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #12 @30 RefTypeUse <Ivl:5> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #13 @31 RefTypeDef <Ivl:6> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #14 @34 RefTypeUse <Ivl:4> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #15 @34 RefTypeUse <Ivl:6> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #16 @35 RefTypeDef <Ivl:7> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #17 @36 RefTypeUse <Ivl:7> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #18 @41 RefTypeDef <Ivl:8> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #19 @43 RefTypeDef <Ivl:9> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #20 @44 RefTypeUse <Ivl:9> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #21 @45 RefTypeDef <Ivl:10> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #22 @48 RefTypeUse <Ivl:8> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #23 @48 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #24 @49 RefTypeDef <Ivl:11> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #25 @50 RefTypeUse <Ivl:11> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #26 @55 RefTypeDef <Ivl:12> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #27 @57 RefTypeDef <Ivl:13> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #28 @58 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #29 @59 RefTypeDef <Ivl:14> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #30 @62 RefTypeUse <Ivl:12> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #31 @62 RefTypeUse <Ivl:14> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #32 @63 RefTypeDef <Ivl:15> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #33 @64 RefTypeUse <Ivl:15> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #34 @69 RefTypeDef <Ivl:16> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #35 @71 RefTypeDef <Ivl:17> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #36 @72 RefTypeUse <Ivl:17> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #37 @73 RefTypeDef <Ivl:18> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #38 @76 RefTypeUse <Ivl:16> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #39 @76 RefTypeUse <Ivl:18> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #40 @77 RefTypeDef <Ivl:19> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #41 @78 RefTypeUse <Ivl:19> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #42 @83 RefTypeDef <Ivl:20> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #43 @85 RefTypeDef <Ivl:21> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #44 @86 RefTypeUse <Ivl:21> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #45 @87 RefTypeDef <Ivl:22> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #46 @90 RefTypeUse <Ivl:20> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #47 @90 RefTypeUse <Ivl:22> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #48 @91 RefTypeDef <Ivl:23> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #49 @92 RefTypeUse <Ivl:23> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #50 @97 RefTypeDef <Ivl:24> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #51 @99 RefTypeDef <Ivl:25> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #52 @100 RefTypeUse <Ivl:25> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #53 @101 RefTypeDef <Ivl:26> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #54 @104 RefTypeUse <Ivl:24> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #55 @104 RefTypeUse <Ivl:26> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #56 @105 RefTypeDef <Ivl:27> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #57 @106 RefTypeUse <Ivl:27> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #58 @111 RefTypeDef <Ivl:28> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #59 @113 RefTypeDef <Ivl:29> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #60 @114 RefTypeUse <Ivl:29> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #61 @115 RefTypeDef <Ivl:30> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #62 @118 RefTypeUse <Ivl:28> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #63 @118 RefTypeUse <Ivl:30> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #64 @119 RefTypeDef <Ivl:31> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #65 @121 RefTypeDef <Ivl:32> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #66 @122 RefTypeUse <Ivl:32> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #67 @122 RefTypeUse <Ivl:31> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #68 @126 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #69 @131 RefTypeDef <Ivl:33> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #70 @132 RefTypeUse <Ivl:33> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #71 @133 RefTypeDef <Ivl:34> CAST BB03 regmask=[allInt] minReg=1>
<RefPosition #72 @134 RefTypeUse <Ivl:34> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #73 @137 RefTypeDef <Ivl:35> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #74 @138 RefTypeUse <Ivl:35> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #75 @139 RefTypeDef <Ivl:36> CAST BB03 regmask=[allInt] minReg=1>
<RefPosition #76 @140 RefTypeUse <Ivl:36> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #77 @143 RefTypeDef <Ivl:37> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #78 @144 RefTypeUse <Ivl:37> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #79 @145 RefTypeDef <Ivl:38> CAST BB03 regmask=[allInt] minReg=1>
<RefPosition #80 @146 RefTypeUse <Ivl:38> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #81 @149 RefTypeDef <Ivl:39> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #82 @150 RefTypeUse <Ivl:39> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #83 @151 RefTypeDef <Ivl:40> CAST BB03 regmask=[allInt] minReg=1>
<RefPosition #84 @152 RefTypeUse <Ivl:40> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #85 @155 RefTypeDef <Ivl:41> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #86 @156 RefTypeUse <Ivl:41> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #87 @157 RefTypeDef <Ivl:42> CAST BB03 regmask=[allInt] minReg=1>
<RefPosition #88 @158 RefTypeUse <Ivl:42> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #89 @161 RefTypeDef <Ivl:43> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #90 @162 RefTypeUse <Ivl:43> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #91 @163 RefTypeDef <Ivl:44> CAST BB03 regmask=[allInt] minReg=1>
<RefPosition #92 @164 RefTypeUse <Ivl:44> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #93 @167 RefTypeDef <Ivl:45> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #94 @168 RefTypeUse <Ivl:45> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #95 @169 RefTypeDef <Ivl:46> CAST BB03 regmask=[allInt] minReg=1>
<RefPosition #96 @170 RefTypeUse <Ivl:46> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #97 @173 RefTypeDef <Ivl:47> LCL_VAR BB03 regmask=[allInt] minReg=1>
<RefPosition #98 @174 RefTypeUse <Ivl:47> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #99 @175 RefTypeDef <Ivl:48> CAST BB03 regmask=[edx] minReg=1>
<RefPosition #100 @176 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #101 @176 RefTypeUse <Ivl:48> BB03 regmask=[edx] minReg=1 last fixed>
<RefPosition #102 @177 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #103 @177 RefTypeDef <Ivl:49> PUTARG_REG BB03 regmask=[edx] minReg=1 fixed>
<RefPosition #104 @179 RefTypeDef <Ivl:50> LCL_VAR BB03 regmask=[ecx] minReg=1>
<RefPosition #105 @180 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #106 @180 RefTypeUse <Ivl:50> BB03 regmask=[ecx] minReg=1 last fixed>
<RefPosition #107 @181 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #108 @181 RefTypeDef <Ivl:51> PUTARG_REG BB03 regmask=[ecx] minReg=1 fixed>
<RefPosition #109 @182 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #110 @182 RefTypeUse <Ivl:49> BB03 regmask=[edx] minReg=1 last fixed>
<RefPosition #111 @182 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #112 @182 RefTypeUse <Ivl:51> BB03 regmask=[ecx] minReg=1 last fixed>
<RefPosition #113 @183 RefTypeKill <Reg:eax> BB03 regmask=[eax] minReg=1 last>
<RefPosition #114 @183 RefTypeKill <Reg:ecx> BB03 regmask=[ecx] minReg=1 last>
<RefPosition #115 @183 RefTypeKill <Reg:edx> BB03 regmask=[edx] minReg=1 last>
<RefPosition #116 @183 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
<RefPosition #117 @183 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
<RefPosition #118 @183 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
<RefPosition #119 @183 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
<RefPosition #120 @183 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
<RefPosition #121 @183 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
<RefPosition #122 @183 RefTypeKill <Reg:mm6> BB03 regmask=[mm6] minReg=1 last>
<RefPosition #123 @183 RefTypeKill <Reg:mm7> BB03 regmask=[mm7] minReg=1 last>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which
may increase during allocation, in which case additional columns will appear. Registers which are
not marked modified have ---- in their column.
--------------------------------+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
--------------------------------+----+----+----+----+----+----+----+----+
| | | | | | | | |
0.#0 BB1 PredBB0 | | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
--------------------------------+----+----+----+----+----+----+----+----+----+
5.#1 C0 Def Alloc edx | | |C0 a| | | | | | |
8.#2 C0 Use * Keep edx | | |C0 a| | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
--------------------------------+----+----+----+----+----+----+----+----+----+
12.#3 BB2 PredBB1 | | | | | | | | | |
17.#4 I1 Def Alloc edx | | |I1 a| | | | | | |
18.#5 I1 Use * Keep edx | | |I1 a| | | | | | |
19.#6 I2 Def Alloc edx | | |I2 a| | | | | | |
20.#7 I2 Use * Keep edx | | |I2 a| | | | | | |
21.#8 I3 Def Alloc mm0 | | | | |I3 a| | | | |
22.#9 I3 Use * Keep mm0 | | | | |I3 a| | | | |
27.#10 I4 Def Alloc mm0 | | | | |I4 a| | | | |
29.#11 I5 Def Alloc edx | | |I5 a| |I4 a| | | | |
30.#12 I5 Use * Keep edx | | |I5 a| |I4 a| | | | |
31.#13 I6 Def Alloc edx | | |I6 a| |I4 a| | | | |
34.#14 I4 Use * Keep mm0 | | |I6 a| |I4 a| | | | |
34.#15 I6 Use * Keep edx | | |I6 a| |I4 a| | | | |
35.#16 I7 Def Alloc mm0 | | | | |I7 a| | | | |
36.#17 I7 Use * Keep mm0 | | | | |I7 a| | | | |
41.#18 I8 Def Alloc mm0 | | | | |I8 a| | | | |
43.#19 I9 Def Alloc edx | | |I9 a| |I8 a| | | | |
44.#20 I9 Use * Keep edx | | |I9 a| |I8 a| | | | |
45.#21 I10 Def Alloc edx | | |I10a| |I8 a| | | | |
48.#22 I8 Use * Keep mm0 | | |I10a| |I8 a| | | | |
48.#23 I10 Use * Keep edx | | |I10a| |I8 a| | | | |
49.#24 I11 Def Alloc mm0 | | | | |I11a| | | | |
50.#25 I11 Use * Keep mm0 | | | | |I11a| | | | |
55.#26 I12 Def Alloc mm0 | | | | |I12a| | | | |
57.#27 I13 Def Alloc edx | | |I13a| |I12a| | | | |
58.#28 I13 Use * Keep edx | | |I13a| |I12a| | | | |
59.#29 I14 Def Alloc edx | | |I14a| |I12a| | | | |
62.#30 I12 Use * Keep mm0 | | |I14a| |I12a| | | | |
62.#31 I14 Use * Keep edx | | |I14a| |I12a| | | | |
63.#32 I15 Def Alloc mm0 | | | | |I15a| | | | |
64.#33 I15 Use * Keep mm0 | | | | |I15a| | | | |
69.#34 I16 Def Alloc mm0 | | | | |I16a| | | | |
71.#35 I17 Def Alloc edx | | |I17a| |I16a| | | | |
72.#36 I17 Use * Keep edx | | |I17a| |I16a| | | | |
73.#37 I18 Def Alloc edx | | |I18a| |I16a| | | | |
76.#38 I16 Use * Keep mm0 | | |I18a| |I16a| | | | |
76.#39 I18 Use * Keep edx | | |I18a| |I16a| | | | |
77.#40 I19 Def Alloc mm0 | | | | |I19a| | | | |
78.#41 I19 Use * Keep mm0 | | | | |I19a| | | | |
83.#42 I20 Def Alloc mm0 | | | | |I20a| | | | |
85.#43 I21 Def Alloc edx | | |I21a| |I20a| | | | |
86.#44 I21 Use * Keep edx | | |I21a| |I20a| | | | |
87.#45 I22 Def Alloc edx | | |I22a| |I20a| | | | |
90.#46 I20 Use * Keep mm0 | | |I22a| |I20a| | | | |
90.#47 I22 Use * Keep edx | | |I22a| |I20a| | | | |
91.#48 I23 Def Alloc mm0 | | | | |I23a| | | | |
92.#49 I23 Use * Keep mm0 | | | | |I23a| | | | |
97.#50 I24 Def Alloc mm0 | | | | |I24a| | | | |
99.#51 I25 Def Alloc edx | | |I25a| |I24a| | | | |
100.#52 I25 Use * Keep edx | | |I25a| |I24a| | | | |
101.#53 I26 Def Alloc edx | | |I26a| |I24a| | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
--------------------------------+----+----+----+----+----+----+----+----+----+
104.#54 I24 Use * Keep mm0 | | |I26a| |I24a| | | | |
104.#55 I26 Use * Keep edx | | |I26a| |I24a| | | | |
105.#56 I27 Def Alloc mm0 | | | | |I27a| | | | |
106.#57 I27 Use * Keep mm0 | | | | |I27a| | | | |
111.#58 I28 Def Alloc mm0 | | | | |I28a| | | | |
113.#59 I29 Def Alloc edx | | |I29a| |I28a| | | | |
114.#60 I29 Use * Keep edx | | |I29a| |I28a| | | | |
115.#61 I30 Def Alloc edx | | |I30a| |I28a| | | | |
118.#62 I28 Use * Keep mm0 | | |I30a| |I28a| | | | |
118.#63 I30 Use * Keep edx | | |I30a| |I28a| | | | |
119.#64 I31 Def Alloc mm0 | | | | |I31a| | | | |
121.#65 I32 Def Alloc edx | | |I32a| |I31a| | | | |
122.#66 I32 Use * Keep edx | | |I32a| |I31a| | | | |
122.#67 I31 Use * Keep mm0 | | |I32a| |I31a| | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
--------------------------------+----+----+----+----+----+----+----+----+----+
126.#68 BB3 PredBB1 | | | | | | | | | |
131.#69 I33 Def Alloc edx | | |I33a| | | | | | |
132.#70 I33 Use * Keep edx | | |I33a| | | | | | |
133.#71 I34 Def Alloc edx | | |I34a| | | | | | |
134.#72 I34 Use * Keep edx | | |I34a| | | | | | |
137.#73 I35 Def Alloc edx | | |I35a| | | | | | |
138.#74 I35 Use * Keep edx | | |I35a| | | | | | |
139.#75 I36 Def Alloc edx | | |I36a| | | | | | |
140.#76 I36 Use * Keep edx | | |I36a| | | | | | |
143.#77 I37 Def Alloc edx | | |I37a| | | | | | |
144.#78 I37 Use * Keep edx | | |I37a| | | | | | |
145.#79 I38 Def Alloc edx | | |I38a| | | | | | |
146.#80 I38 Use * Keep edx | | |I38a| | | | | | |
149.#81 I39 Def Alloc edx | | |I39a| | | | | | |
150.#82 I39 Use * Keep edx | | |I39a| | | | | | |
151.#83 I40 Def Alloc edx | | |I40a| | | | | | |
152.#84 I40 Use * Keep edx | | |I40a| | | | | | |
155.#85 I41 Def Alloc edx | | |I41a| | | | | | |
156.#86 I41 Use * Keep edx | | |I41a| | | | | | |
157.#87 I42 Def Alloc edx | | |I42a| | | | | | |
158.#88 I42 Use * Keep edx | | |I42a| | | | | | |
161.#89 I43 Def Alloc edx | | |I43a| | | | | | |
162.#90 I43 Use * Keep edx | | |I43a| | | | | | |
163.#91 I44 Def Alloc edx | | |I44a| | | | | | |
164.#92 I44 Use * Keep edx | | |I44a| | | | | | |
167.#93 I45 Def Alloc edx | | |I45a| | | | | | |
168.#94 I45 Use * Keep edx | | |I45a| | | | | | |
169.#95 I46 Def Alloc edx | | |I46a| | | | | | |
170.#96 I46 Use * Keep edx | | |I46a| | | | | | |
173.#97 I47 Def Alloc edx | | |I47a| | | | | | |
174.#98 I47 Use * Keep edx | | |I47a| | | | | | |
175.#99 I48 Def Alloc edx | | |I48a| | | | | | |
176.#100 edx Fixd Keep edx | | |I48a| | | | | | |
176.#101 I48 Use * Keep edx | | |I48a| | | | | | |
177.#102 edx Fixd Keep edx | | | | | | | | | |
177.#103 I49 Def Alloc edx | | |I49a| | | | | | |
179.#104 I50 Def Alloc ecx | |I50a|I49a| | | | | | |
180.#105 ecx Fixd Keep ecx | |I50a|I49a| | | | | | |
180.#106 I50 Use * Keep ecx | |I50a|I49a| | | | | | |
181.#107 ecx Fixd Keep ecx | | |I49a| | | | | | |
181.#108 I51 Def Alloc ecx | |I51a|I49a| | | | | | |
182.#109 edx Fixd Keep edx | |I51a|I49a| | | | | | |
182.#110 I49 Use * Keep edx | |I51a|I49a| | | | | | |
182.#111 ecx Fixd Keep ecx | |I51a|I49a| | | | | | |
182.#112 I51 Use * Keep ecx | |I51a|I49a| | | | | | |
183.#113 eax Kill Keep eax | | | | | | | | | |
183.#114 ecx Kill Keep ecx | | | | | | | | | |
183.#115 edx Kill Keep edx | | | | | | | | | |
183.#116 mm0 Kill Keep mm0 | | | | | | | | | |
183.#117 mm1 Kill Keep mm1 | | | | | | | | | |
183.#118 mm2 Kill Keep mm2 | | | | | | | | | |
183.#119 mm3 Kill Keep mm3 | | | | | | | | | |
183.#120 mm4 Kill Keep mm4 | | | | | | | | | |
183.#121 mm5 Kill Keep mm5 | | | | | | | | | |
183.#122 mm6 Kill Keep mm6 | | | | | | | | | |
183.#123 mm7 Kill Keep mm7 | | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[edx] minReg=1>
<RefPosition #2 @8 RefTypeUse <Ivl:0> BB01 regmask=[edx] minReg=1 last regOptional>
<RefPosition #3 @12 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #4 @17 RefTypeDef <Ivl:1> LCL_VAR BB02 regmask=[edx] minReg=1>
<RefPosition #5 @18 RefTypeUse <Ivl:1> BB02 regmask=[edx] minReg=1 last>
<RefPosition #6 @19 RefTypeDef <Ivl:2> CAST BB02 regmask=[edx] minReg=1>
<RefPosition #7 @20 RefTypeUse <Ivl:2> BB02 regmask=[edx] minReg=1 last regOptional>
<RefPosition #8 @21 RefTypeDef <Ivl:3> HWIntrinsic BB02 regmask=[mm0] minReg=1>
<RefPosition #9 @22 RefTypeUse <Ivl:3> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #10 @27 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[mm0] minReg=1>
<RefPosition #11 @29 RefTypeDef <Ivl:5> LCL_VAR BB02 regmask=[edx] minReg=1>
<RefPosition #12 @30 RefTypeUse <Ivl:5> BB02 regmask=[edx] minReg=1 last>
<RefPosition #13 @31 RefTypeDef <Ivl:6> CAST BB02 regmask=[edx] minReg=1>
<RefPosition #14 @34 RefTypeUse <Ivl:4> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #15 @34 RefTypeUse <Ivl:6> BB02 regmask=[edx] minReg=1 last regOptional>
<RefPosition #16 @35 RefTypeDef <Ivl:7> HWIntrinsic BB02 regmask=[mm0] minReg=1>
<RefPosition #17 @36 RefTypeUse <Ivl:7> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #18 @41 RefTypeDef <Ivl:8> LCL_VAR BB02 regmask=[mm0] minReg=1>
<RefPosition #19 @43 RefTypeDef <Ivl:9> LCL_VAR BB02 regmask=[edx] minReg=1>
<RefPosition #20 @44 RefTypeUse <Ivl:9> BB02 regmask=[edx] minReg=1 last>
<RefPosition #21 @45 RefTypeDef <Ivl:10> CAST BB02 regmask=[edx] minReg=1>
<RefPosition #22 @48 RefTypeUse <Ivl:8> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #23 @48 RefTypeUse <Ivl:10> BB02 regmask=[edx] minReg=1 last regOptional>
<RefPosition #24 @49 RefTypeDef <Ivl:11> HWIntrinsic BB02 regmask=[mm0] minReg=1>
<RefPosition #25 @50 RefTypeUse <Ivl:11> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #26 @55 RefTypeDef <Ivl:12> LCL_VAR BB02 regmask=[mm0] minReg=1>
<RefPosition #27 @57 RefTypeDef <Ivl:13> LCL_VAR BB02 regmask=[edx] minReg=1>
<RefPosition #28 @58 RefTypeUse <Ivl:13> BB02 regmask=[edx] minReg=1 last>
<RefPosition #29 @59 RefTypeDef <Ivl:14> CAST BB02 regmask=[edx] minReg=1>
<RefPosition #30 @62 RefTypeUse <Ivl:12> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #31 @62 RefTypeUse <Ivl:14> BB02 regmask=[edx] minReg=1 last regOptional>
<RefPosition #32 @63 RefTypeDef <Ivl:15> HWIntrinsic BB02 regmask=[mm0] minReg=1>
<RefPosition #33 @64 RefTypeUse <Ivl:15> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #34 @69 RefTypeDef <Ivl:16> LCL_VAR BB02 regmask=[mm0] minReg=1>
<RefPosition #35 @71 RefTypeDef <Ivl:17> LCL_VAR BB02 regmask=[edx] minReg=1>
<RefPosition #36 @72 RefTypeUse <Ivl:17> BB02 regmask=[edx] minReg=1 last>
<RefPosition #37 @73 RefTypeDef <Ivl:18> CAST BB02 regmask=[edx] minReg=1>
<RefPosition #38 @76 RefTypeUse <Ivl:16> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #39 @76 RefTypeUse <Ivl:18> BB02 regmask=[edx] minReg=1 last regOptional>
<RefPosition #40 @77 RefTypeDef <Ivl:19> HWIntrinsic BB02 regmask=[mm0] minReg=1>
<RefPosition #41 @78 RefTypeUse <Ivl:19> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #42 @83 RefTypeDef <Ivl:20> LCL_VAR BB02 regmask=[mm0] minReg=1>
<RefPosition #43 @85 RefTypeDef <Ivl:21> LCL_VAR BB02 regmask=[edx] minReg=1>
<RefPosition #44 @86 RefTypeUse <Ivl:21> BB02 regmask=[edx] minReg=1 last>
<RefPosition #45 @87 RefTypeDef <Ivl:22> CAST BB02 regmask=[edx] minReg=1>
<RefPosition #46 @90 RefTypeUse <Ivl:20> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #47 @90 RefTypeUse <Ivl:22> BB02 regmask=[edx] minReg=1 last regOptional>
<RefPosition #48 @91 RefTypeDef <Ivl:23> HWIntrinsic BB02 regmask=[mm0] minReg=1>
<RefPosition #49 @92 RefTypeUse <Ivl:23> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #50 @97 RefTypeDef <Ivl:24> LCL_VAR BB02 regmask=[mm0] minReg=1>
<RefPosition #51 @99 RefTypeDef <Ivl:25> LCL_VAR BB02 regmask=[edx] minReg=1>
<RefPosition #52 @100 RefTypeUse <Ivl:25> BB02 regmask=[edx] minReg=1 last>
<RefPosition #53 @101 RefTypeDef <Ivl:26> CAST BB02 regmask=[edx] minReg=1>
<RefPosition #54 @104 RefTypeUse <Ivl:24> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #55 @104 RefTypeUse <Ivl:26> BB02 regmask=[edx] minReg=1 last regOptional>
<RefPosition #56 @105 RefTypeDef <Ivl:27> HWIntrinsic BB02 regmask=[mm0] minReg=1>
<RefPosition #57 @106 RefTypeUse <Ivl:27> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #58 @111 RefTypeDef <Ivl:28> LCL_VAR BB02 regmask=[mm0] minReg=1>
<RefPosition #59 @113 RefTypeDef <Ivl:29> LCL_VAR BB02 regmask=[edx] minReg=1>
<RefPosition #60 @114 RefTypeUse <Ivl:29> BB02 regmask=[edx] minReg=1 last>
<RefPosition #61 @115 RefTypeDef <Ivl:30> CAST BB02 regmask=[edx] minReg=1>
<RefPosition #62 @118 RefTypeUse <Ivl:28> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #63 @118 RefTypeUse <Ivl:30> BB02 regmask=[edx] minReg=1 last regOptional>
<RefPosition #64 @119 RefTypeDef <Ivl:31> HWIntrinsic BB02 regmask=[mm0] minReg=1>
<RefPosition #65 @121 RefTypeDef <Ivl:32> LCL_VAR BB02 regmask=[edx] minReg=1>
<RefPosition #66 @122 RefTypeUse <Ivl:32> BB02 regmask=[edx] minReg=1 last>
<RefPosition #67 @122 RefTypeUse <Ivl:31> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #68 @126 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #69 @131 RefTypeDef <Ivl:33> LCL_VAR BB03 regmask=[edx] minReg=1>
<RefPosition #70 @132 RefTypeUse <Ivl:33> BB03 regmask=[edx] minReg=1 last>
<RefPosition #71 @133 RefTypeDef <Ivl:34> CAST BB03 regmask=[edx] minReg=1>
<RefPosition #72 @134 RefTypeUse <Ivl:34> BB03 regmask=[edx] minReg=1 last>
<RefPosition #73 @137 RefTypeDef <Ivl:35> LCL_VAR BB03 regmask=[edx] minReg=1>
<RefPosition #74 @138 RefTypeUse <Ivl:35> BB03 regmask=[edx] minReg=1 last>
<RefPosition #75 @139 RefTypeDef <Ivl:36> CAST BB03 regmask=[edx] minReg=1>
<RefPosition #76 @140 RefTypeUse <Ivl:36> BB03 regmask=[edx] minReg=1 last>
<RefPosition #77 @143 RefTypeDef <Ivl:37> LCL_VAR BB03 regmask=[edx] minReg=1>
<RefPosition #78 @144 RefTypeUse <Ivl:37> BB03 regmask=[edx] minReg=1 last>
<RefPosition #79 @145 RefTypeDef <Ivl:38> CAST BB03 regmask=[edx] minReg=1>
<RefPosition #80 @146 RefTypeUse <Ivl:38> BB03 regmask=[edx] minReg=1 last>
<RefPosition #81 @149 RefTypeDef <Ivl:39> LCL_VAR BB03 regmask=[edx] minReg=1>
<RefPosition #82 @150 RefTypeUse <Ivl:39> BB03 regmask=[edx] minReg=1 last>
<RefPosition #83 @151 RefTypeDef <Ivl:40> CAST BB03 regmask=[edx] minReg=1>
<RefPosition #84 @152 RefTypeUse <Ivl:40> BB03 regmask=[edx] minReg=1 last>
<RefPosition #85 @155 RefTypeDef <Ivl:41> LCL_VAR BB03 regmask=[edx] minReg=1>
<RefPosition #86 @156 RefTypeUse <Ivl:41> BB03 regmask=[edx] minReg=1 last>
<RefPosition #87 @157 RefTypeDef <Ivl:42> CAST BB03 regmask=[edx] minReg=1>
<RefPosition #88 @158 RefTypeUse <Ivl:42> BB03 regmask=[edx] minReg=1 last>
<RefPosition #89 @161 RefTypeDef <Ivl:43> LCL_VAR BB03 regmask=[edx] minReg=1>
<RefPosition #90 @162 RefTypeUse <Ivl:43> BB03 regmask=[edx] minReg=1 last>
<RefPosition #91 @163 RefTypeDef <Ivl:44> CAST BB03 regmask=[edx] minReg=1>
<RefPosition #92 @164 RefTypeUse <Ivl:44> BB03 regmask=[edx] minReg=1 last>
<RefPosition #93 @167 RefTypeDef <Ivl:45> LCL_VAR BB03 regmask=[edx] minReg=1>
<RefPosition #94 @168 RefTypeUse <Ivl:45> BB03 regmask=[edx] minReg=1 last>
<RefPosition #95 @169 RefTypeDef <Ivl:46> CAST BB03 regmask=[edx] minReg=1>
<RefPosition #96 @170 RefTypeUse <Ivl:46> BB03 regmask=[edx] minReg=1 last>
<RefPosition #97 @173 RefTypeDef <Ivl:47> LCL_VAR BB03 regmask=[edx] minReg=1>
<RefPosition #98 @174 RefTypeUse <Ivl:47> BB03 regmask=[edx] minReg=1 last>
<RefPosition #99 @175 RefTypeDef <Ivl:48> CAST BB03 regmask=[edx] minReg=1>
<RefPosition #100 @176 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #101 @176 RefTypeUse <Ivl:48> BB03 regmask=[edx] minReg=1 last fixed>
<RefPosition #102 @177 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #103 @177 RefTypeDef <Ivl:49> PUTARG_REG BB03 regmask=[edx] minReg=1 fixed>
<RefPosition #104 @179 RefTypeDef <Ivl:50> LCL_VAR BB03 regmask=[ecx] minReg=1>
<RefPosition #105 @180 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #106 @180 RefTypeUse <Ivl:50> BB03 regmask=[ecx] minReg=1 last fixed>
<RefPosition #107 @181 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #108 @181 RefTypeDef <Ivl:51> PUTARG_REG BB03 regmask=[ecx] minReg=1 fixed>
<RefPosition #109 @182 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #110 @182 RefTypeUse <Ivl:49> BB03 regmask=[edx] minReg=1 last fixed>
<RefPosition #111 @182 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #112 @182 RefTypeUse <Ivl:51> BB03 regmask=[ecx] minReg=1 last fixed>
<RefPosition #113 @183 RefTypeKill <Reg:eax> BB03 regmask=[eax] minReg=1 last>
<RefPosition #114 @183 RefTypeKill <Reg:ecx> BB03 regmask=[ecx] minReg=1 last>
<RefPosition #115 @183 RefTypeKill <Reg:edx> BB03 regmask=[edx] minReg=1 last>
<RefPosition #116 @183 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
<RefPosition #117 @183 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
<RefPosition #118 @183 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
<RefPosition #119 @183 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
<RefPosition #120 @183 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
<RefPosition #121 @183 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
<RefPosition #122 @183 RefTypeKill <Reg:mm6> BB03 regmask=[mm6] minReg=1 last>
<RefPosition #123 @183 RefTypeKill <Reg:mm7> BB03 regmask=[mm7] minReg=1 last>
Active intervals at end of allocation:
Trees after linear scan register allocator (LSRA)
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [007..051) (return) i LIR
BB03 [0002] 1 BB01 1 [051..063) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
N002 ( 5, 5) [000005] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N004 ( 1, 1) [000002] ------------ t2 = CNS_INT int 0 REG edx
N006 ( 1, 1) [000001] -c---------- t1 = CNS_INT int 1 REG NA
/--* t2 int
+--* t1 int
N008 ( 3, 3) [000003] J------N---- * EQ void REG NA
N010 ( 5, 5) [000004] ------------ * JTRUE void REG NA
------------ BB02 [007..051) (return), preds={BB01} succs={}
N014 ( 9, 8) [000035] ------------ IL_OFFSET void IL offset: 0x7 REG NA
N016 ( 3, 2) [000030] ------------ t30 = LCL_VAR int V01 arg0 edx REG edx
/--* t30 int
N018 ( 4, 4) [000115] ------------ t115 = * CAST int <- ushort <- int REG edx
/--* t115 int
N020 ( 5, 5) [000031] ------------ t31 = * HWIntrinsic simd16 ushort CreateScalarUnsafe REG mm0
/--* t31 simd16
N022 ( 9, 8) [000034] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
N024 ( 15, 13) [000046] ------------ IL_OFFSET void IL offset: 0xe REG NA
N026 ( 3, 2) [000036] ------------ t36 = LCL_VAR simd16 V09 loc0 mm0 REG mm0
N028 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V02 arg1 edx REG edx
/--* t37 int
N030 ( 4, 4) [000116] ------------ t116 = * CAST int <- ushort <- int REG edx
N032 ( 1, 1) [000038] -c---------- t38 = CNS_INT int 1 REG NA
/--* t36 simd16
+--* t116 int
+--* t38 int
N034 ( 11, 10) [000042] ------------ t42 = * HWIntrinsic simd16 ushort Insert REG mm0
/--* t42 simd16
N036 ( 15, 13) [000045] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
N038 ( 15, 13) [000057] ------------ IL_OFFSET void IL offset: 0x17 REG NA
N040 ( 3, 2) [000047] ------------ t47 = LCL_VAR simd16 V09 loc0 mm0 REG mm0
N042 ( 3, 2) [000048] ------------ t48 = LCL_VAR int V03 arg2 edx REG edx
/--* t48 int
N044 ( 4, 4) [000117] ------------ t117 = * CAST int <- ushort <- int REG edx
N046 ( 1, 1) [000049] -c---------- t49 = CNS_INT int 2 REG NA
/--* t47 simd16
+--* t117 int
+--* t49 int
N048 ( 11, 10) [000053] ------------ t53 = * HWIntrinsic simd16 ushort Insert REG mm0
/--* t53 simd16
N050 ( 15, 13) [000056] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
N052 ( 15, 13) [000068] ------------ IL_OFFSET void IL offset: 0x20 REG NA
N054 ( 3, 2) [000058] ------------ t58 = LCL_VAR simd16 V09 loc0 mm0 REG mm0
N056 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V04 arg3 edx REG edx
/--* t59 int
N058 ( 4, 4) [000118] ------------ t118 = * CAST int <- ushort <- int REG edx
N060 ( 1, 1) [000060] -c---------- t60 = CNS_INT int 3 REG NA
/--* t58 simd16
+--* t118 int
+--* t60 int
N062 ( 11, 10) [000064] ------------ t64 = * HWIntrinsic simd16 ushort Insert REG mm0
/--* t64 simd16
N064 ( 15, 13) [000067] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
N066 ( 15, 13) [000079] ------------ IL_OFFSET void IL offset: 0x29 REG NA
N068 ( 3, 2) [000069] ------------ t69 = LCL_VAR simd16 V09 loc0 mm0 REG mm0
N070 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V05 arg4 edx REG edx
/--* t70 int
N072 ( 4, 4) [000119] ------------ t119 = * CAST int <- ushort <- int REG edx
N074 ( 1, 1) [000071] -c---------- t71 = CNS_INT int 4 REG NA
/--* t69 simd16
+--* t119 int
+--* t71 int
N076 ( 11, 10) [000075] ------------ t75 = * HWIntrinsic simd16 ushort Insert REG mm0
/--* t75 simd16
N078 ( 15, 13) [000078] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
N080 ( 15, 13) [000090] ------------ IL_OFFSET void IL offset: 0x33 REG NA
N082 ( 3, 2) [000080] ------------ t80 = LCL_VAR simd16 V09 loc0 mm0 REG mm0
N084 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V06 arg5 edx REG edx
/--* t81 int
N086 ( 4, 4) [000120] ------------ t120 = * CAST int <- ushort <- int REG edx
N088 ( 1, 1) [000082] -c---------- t82 = CNS_INT int 5 REG NA
/--* t80 simd16
+--* t120 int
+--* t82 int
N090 ( 11, 10) [000086] ------------ t86 = * HWIntrinsic simd16 ushort Insert REG mm0
/--* t86 simd16
N092 ( 15, 13) [000089] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
N094 ( 15, 13) [000101] ------------ IL_OFFSET void IL offset: 0x3d REG NA
N096 ( 3, 2) [000091] ------------ t91 = LCL_VAR simd16 V09 loc0 mm0 REG mm0
N098 ( 3, 2) [000092] ------------ t92 = LCL_VAR int V07 arg6 edx REG edx
/--* t92 int
N100 ( 4, 4) [000121] ------------ t121 = * CAST int <- ushort <- int REG edx
N102 ( 1, 1) [000093] -c---------- t93 = CNS_INT int 6 REG NA
/--* t91 simd16
+--* t121 int
+--* t93 int
N104 ( 11, 10) [000097] ------------ t97 = * HWIntrinsic simd16 ushort Insert REG mm0
/--* t97 simd16
N106 ( 15, 13) [000100] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
N108 ( 18, 15) [000112] ------------ IL_OFFSET void IL offset: 0x47 REG NA
N110 ( 3, 2) [000102] ------------ t102 = LCL_VAR simd16 V09 loc0 mm0 REG mm0
N112 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V08 arg7 edx REG edx
/--* t103 int
N114 ( 4, 4) [000122] ------------ t122 = * CAST int <- ushort <- int REG edx
N116 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 7 REG NA
/--* t102 simd16
+--* t122 int
+--* t104 int
N118 ( 11, 10) [000108] ------------ t108 = * HWIntrinsic simd16 ushort Insert REG mm0
N120 ( 3, 2) [000109] ------------ t109 = LCL_VAR byref V00 RetBuf edx REG edx
/--* t109 byref
+--* t108 simd16
N122 (???,???) [000135] -A-X-------- * STOREIND simd16 REG NA
N124 ( 0, 0) [000113] ------------ RETURN void REG NA
------------ BB03 [051..063) (return), preds={BB01} succs={}
N128 ( 70, 41) [000026] ------------ IL_OFFSET void IL offset: 0x51 REG NA
N130 ( 3, 2) [000008] ------------ t8 = LCL_VAR int V02 arg1 edx REG edx
/--* t8 int
N132 ( 4, 4) [000124] ------------ t124 = * CAST int <- ushort <- int REG edx
/--* t124 int
N134 (???,???) [000136] ------------ * PUTARG_STK [+0x00] void (1 slots) REG NA
N136 ( 3, 2) [000009] ------------ t9 = LCL_VAR int V03 arg2 edx REG edx
/--* t9 int
N138 ( 4, 4) [000125] ------------ t125 = * CAST int <- ushort <- int REG edx
/--* t125 int
N140 (???,???) [000137] ------------ * PUTARG_STK [+0x04] void (1 slots) REG NA
N142 ( 3, 2) [000010] ------------ t10 = LCL_VAR int V04 arg3 edx REG edx
/--* t10 int
N144 ( 4, 4) [000126] ------------ t126 = * CAST int <- ushort <- int REG edx
/--* t126 int
N146 (???,???) [000138] ------------ * PUTARG_STK [+0x08] void (1 slots) REG NA
N148 ( 3, 2) [000011] ------------ t11 = LCL_VAR int V05 arg4 edx REG edx
/--* t11 int
N150 ( 4, 4) [000127] ------------ t127 = * CAST int <- ushort <- int REG edx
/--* t127 int
N152 (???,???) [000139] ------------ * PUTARG_STK [+0x0c] void (1 slots) REG NA
N154 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V06 arg5 edx REG edx
/--* t12 int
N156 ( 4, 4) [000128] ------------ t128 = * CAST int <- ushort <- int REG edx
/--* t128 int
N158 (???,???) [000140] ------------ * PUTARG_STK [+0x10] void (1 slots) REG NA
N160 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V07 arg6 edx REG edx
/--* t13 int
N162 ( 4, 4) [000129] ------------ t129 = * CAST int <- ushort <- int REG edx
/--* t129 int
N164 (???,???) [000141] ------------ * PUTARG_STK [+0x14] void (1 slots) REG NA
N166 ( 3, 2) [000014] ------------ t14 = LCL_VAR int V08 arg7 edx REG edx
/--* t14 int
N168 ( 4, 4) [000130] ------------ t130 = * CAST int <- ushort <- int REG edx
/--* t130 int
N170 (???,???) [000142] ------------ * PUTARG_STK [+0x18] void (1 slots) REG NA
N172 ( 3, 2) [000007] ------------ t7 = LCL_VAR int V01 arg0 edx REG edx
/--* t7 int
N174 ( 4, 4) [000123] ------------ t123 = * CAST int <- ushort <- int REG edx
/--* t123 int
N176 (???,???) [000143] ------------ t143 = * PUTARG_REG int REG edx
N178 ( 3, 2) [000024] ------------ t24 = LCL_VAR byref V00 RetBuf ecx REG ecx
/--* t24 byref
N180 (???,???) [000144] ------------ t144 = * PUTARG_REG byref REG ecx
/--* t143 int arg1 in edx
+--* t144 byref arg0 in ecx
N182 ( 70, 41) [000015] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
N184 ( 0, 0) [000027] ------------ RETURN void REG NA
-------------------------------------------------------------------------------------------------------------------
Final allocation
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
--------------------------------+----+----+----+----+----+----+----+----+----+
0.#0 BB1 PredBB0 | | | | | | | | | |
5.#1 C0 Def Alloc edx | | |C0 a| | | | | | |
8.#2 C0 Use * Keep edx | | |C0 i| | | | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
--------------------------------+----+----+----+----+----+----+----+----+----+
12.#3 BB2 PredBB1 | | | | | | | | | |
17.#4 I1 Def Alloc edx | | |I1 a| | | | | | |
18.#5 I1 Use * Keep edx | | |I1 i| | | | | | |
19.#6 I2 Def Alloc edx | | |I2 a| | | | | | |
20.#7 I2 Use * Keep edx | | |I2 i| | | | | | |
21.#8 I3 Def Alloc mm0 | | | | |I3 a| | | | |
22.#9 I3 Use * Keep mm0 | | | | |I3 i| | | | |
27.#10 I4 Def Alloc mm0 | | | | |I4 a| | | | |
29.#11 I5 Def Alloc edx | | |I5 a| |I4 a| | | | |
30.#12 I5 Use * Keep edx | | |I5 i| |I4 a| | | | |
31.#13 I6 Def Alloc edx | | |I6 a| |I4 a| | | | |
34.#14 I4 Use * Keep mm0 | | |I6 a| |I4 i| | | | |
34.#15 I6 Use * Keep edx | | |I6 i| | | | | | |
35.#16 I7 Def Alloc mm0 | | | | |I7 a| | | | |
36.#17 I7 Use * Keep mm0 | | | | |I7 i| | | | |
41.#18 I8 Def Alloc mm0 | | | | |I8 a| | | | |
43.#19 I9 Def Alloc edx | | |I9 a| |I8 a| | | | |
44.#20 I9 Use * Keep edx | | |I9 i| |I8 a| | | | |
45.#21 I10 Def Alloc edx | | |I10a| |I8 a| | | | |
48.#22 I8 Use * Keep mm0 | | |I10a| |I8 i| | | | |
48.#23 I10 Use * Keep edx | | |I10i| | | | | | |
49.#24 I11 Def Alloc mm0 | | | | |I11a| | | | |
50.#25 I11 Use * Keep mm0 | | | | |I11i| | | | |
55.#26 I12 Def Alloc mm0 | | | | |I12a| | | | |
57.#27 I13 Def Alloc edx | | |I13a| |I12a| | | | |
58.#28 I13 Use * Keep edx | | |I13i| |I12a| | | | |
59.#29 I14 Def Alloc edx | | |I14a| |I12a| | | | |
62.#30 I12 Use * Keep mm0 | | |I14a| |I12i| | | | |
62.#31 I14 Use * Keep edx | | |I14i| | | | | | |
63.#32 I15 Def Alloc mm0 | | | | |I15a| | | | |
64.#33 I15 Use * Keep mm0 | | | | |I15i| | | | |
69.#34 I16 Def Alloc mm0 | | | | |I16a| | | | |
71.#35 I17 Def Alloc edx | | |I17a| |I16a| | | | |
72.#36 I17 Use * Keep edx | | |I17i| |I16a| | | | |
73.#37 I18 Def Alloc edx | | |I18a| |I16a| | | | |
76.#38 I16 Use * Keep mm0 | | |I18a| |I16i| | | | |
76.#39 I18 Use * Keep edx | | |I18i| | | | | | |
77.#40 I19 Def Alloc mm0 | | | | |I19a| | | | |
78.#41 I19 Use * Keep mm0 | | | | |I19i| | | | |
83.#42 I20 Def Alloc mm0 | | | | |I20a| | | | |
85.#43 I21 Def Alloc edx | | |I21a| |I20a| | | | |
86.#44 I21 Use * Keep edx | | |I21i| |I20a| | | | |
87.#45 I22 Def Alloc edx | | |I22a| |I20a| | | | |
90.#46 I20 Use * Keep mm0 | | |I22a| |I20i| | | | |
90.#47 I22 Use * Keep edx | | |I22i| | | | | | |
91.#48 I23 Def Alloc mm0 | | | | |I23a| | | | |
92.#49 I23 Use * Keep mm0 | | | | |I23i| | | | |
97.#50 I24 Def Alloc mm0 | | | | |I24a| | | | |
99.#51 I25 Def Alloc edx | | |I25a| |I24a| | | | |
100.#52 I25 Use * Keep edx | | |I25i| |I24a| | | | |
101.#53 I26 Def Alloc edx | | |I26a| |I24a| | | | |
104.#54 I24 Use * Keep mm0 | | |I26a| |I24i| | | | |
104.#55 I26 Use * Keep edx | | |I26i| | | | | | |
105.#56 I27 Def Alloc mm0 | | | | |I27a| | | | |
106.#57 I27 Use * Keep mm0 | | | | |I27i| | | | |
111.#58 I28 Def Alloc mm0 | | | | |I28a| | | | |
113.#59 I29 Def Alloc edx | | |I29a| |I28a| | | | |
114.#60 I29 Use * Keep edx | | |I29i| |I28a| | | | |
115.#61 I30 Def Alloc edx | | |I30a| |I28a| | | | |
118.#62 I28 Use * Keep mm0 | | |I30a| |I28i| | | | |
118.#63 I30 Use * Keep edx | | |I30i| | | | | | |
119.#64 I31 Def Alloc mm0 | | | | |I31a| | | | |
121.#65 I32 Def Alloc edx | | |I32a| |I31a| | | | |
122.#66 I32 Use * Keep edx | | |I32i| |I31a| | | | |
122.#67 I31 Use * Keep mm0 | | | | |I31i| | | | |
--------------------------------+----+----+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |eax |ecx |edx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
--------------------------------+----+----+----+----+----+----+----+----+----+
126.#68 BB3 PredBB1 | | | | | | | | | |
131.#69 I33 Def Alloc edx | | |I33a| | | | | | |
132.#70 I33 Use * Keep edx | | |I33i| | | | | | |
133.#71 I34 Def Alloc edx | | |I34a| | | | | | |
134.#72 I34 Use * Keep edx | | |I34i| | | | | | |
137.#73 I35 Def Alloc edx | | |I35a| | | | | | |
138.#74 I35 Use * Keep edx | | |I35i| | | | | | |
139.#75 I36 Def Alloc edx | | |I36a| | | | | | |
140.#76 I36 Use * Keep edx | | |I36i| | | | | | |
143.#77 I37 Def Alloc edx | | |I37a| | | | | | |
144.#78 I37 Use * Keep edx | | |I37i| | | | | | |
145.#79 I38 Def Alloc edx | | |I38a| | | | | | |
146.#80 I38 Use * Keep edx | | |I38i| | | | | | |
149.#81 I39 Def Alloc edx | | |I39a| | | | | | |
150.#82 I39 Use * Keep edx | | |I39i| | | | | | |
151.#83 I40 Def Alloc edx | | |I40a| | | | | | |
152.#84 I40 Use * Keep edx | | |I40i| | | | | | |
155.#85 I41 Def Alloc edx | | |I41a| | | | | | |
156.#86 I41 Use * Keep edx | | |I41i| | | | | | |
157.#87 I42 Def Alloc edx | | |I42a| | | | | | |
158.#88 I42 Use * Keep edx | | |I42i| | | | | | |
161.#89 I43 Def Alloc edx | | |I43a| | | | | | |
162.#90 I43 Use * Keep edx | | |I43i| | | | | | |
163.#91 I44 Def Alloc edx | | |I44a| | | | | | |
164.#92 I44 Use * Keep edx | | |I44i| | | | | | |
167.#93 I45 Def Alloc edx | | |I45a| | | | | | |
168.#94 I45 Use * Keep edx | | |I45i| | | | | | |
169.#95 I46 Def Alloc edx | | |I46a| | | | | | |
170.#96 I46 Use * Keep edx | | |I46i| | | | | | |
173.#97 I47 Def Alloc edx | | |I47a| | | | | | |
174.#98 I47 Use * Keep edx | | |I47i| | | | | | |
175.#99 I48 Def Alloc edx | | |I48a| | | | | | |
176.#100 edx Fixd Keep edx | | |I48a| | | | | | |
176.#101 I48 Use * Keep edx | | |I48i| | | | | | |
177.#102 edx Fixd Keep edx | | | | | | | | | |
177.#103 I49 Def Alloc edx | | |I49a| | | | | | |
179.#104 I50 Def Alloc ecx | |I50a|I49a| | | | | | |
180.#105 ecx Fixd Keep ecx | |I50a|I49a| | | | | | |
180.#106 I50 Use * Keep ecx | |I50i|I49a| | | | | | |
181.#107 ecx Fixd Keep ecx | | |I49a| | | | | | |
181.#108 I51 Def Alloc ecx | |I51a|I49a| | | | | | |
182.#109 edx Fixd Keep edx | |I51a|I49a| | | | | | |
182.#110 I49 Use * Keep edx | |I51a|I49i| | | | | | |
182.#111 ecx Fixd Keep ecx | |I51a| | | | | | | |
182.#112 I51 Use * Keep ecx | |I51i| | | | | | | |
183.#113 eax Kill Keep eax | | | | | | | | | |
183.#114 ecx Kill Keep ecx | | | | | | | | | |
183.#115 edx Kill Keep edx | | | | | | | | | |
183.#116 mm0 Kill Keep mm0 | | | | | | | | | |
183.#117 mm1 Kill Keep mm1 | | | | | | | | | |
183.#118 mm2 Kill Keep mm2 | | | | | | | | | |
183.#119 mm3 Kill Keep mm3 | | | | | | | | | |
183.#120 mm4 Kill Keep mm4 | | | | | | | | | |
183.#121 mm5 Kill Keep mm5 | | | | | | | | | |
183.#122 mm6 Kill Keep mm6 | | | | | | | | | |
183.#123 mm7 Kill Keep mm7 | | | | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Total Tracked Vars: 0
Total Reg Cand Vars: 0
Total number of Intervals: 51
Total number of RefPositions: 123
Total Spill Count: 0 Weighted: 0
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:
BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N002. IL_OFFSET IL offset: 0x0 REG NA
N004. edx = CNS_INT 0 REG edx
N006. CNS_INT 1 REG NA
N008. EQ ; edx
N010. JTRUE
BB02 [007..051) (return), preds={BB01} succs={}
=====
N014. IL_OFFSET IL offset: 0x7 REG NA
N016. edx = V01 MEM
N018. edx = CAST ; edx
N020. mm0 = HWIntrinsic; edx
N022. V09 MEM; mm0
N024. IL_OFFSET IL offset: 0xe REG NA
N026. mm0 = V09 MEM
N028. edx = V02 MEM
N030. edx = CAST ; edx
N032. CNS_INT 1 REG NA
N034. mm0 = HWIntrinsic; mm0,edx
N036. V09 MEM; mm0
N038. IL_OFFSET IL offset: 0x17 REG NA
N040. mm0 = V09 MEM
N042. edx = V03 MEM
N044. edx = CAST ; edx
N046. CNS_INT 2 REG NA
N048. mm0 = HWIntrinsic; mm0,edx
N050. V09 MEM; mm0
N052. IL_OFFSET IL offset: 0x20 REG NA
N054. mm0 = V09 MEM
N056. edx = V04 MEM
N058. edx = CAST ; edx
N060. CNS_INT 3 REG NA
N062. mm0 = HWIntrinsic; mm0,edx
N064. V09 MEM; mm0
N066. IL_OFFSET IL offset: 0x29 REG NA
N068. mm0 = V09 MEM
N070. edx = V05 MEM
N072. edx = CAST ; edx
N074. CNS_INT 4 REG NA
N076. mm0 = HWIntrinsic; mm0,edx
N078. V09 MEM; mm0
N080. IL_OFFSET IL offset: 0x33 REG NA
N082. mm0 = V09 MEM
N084. edx = V06 MEM
N086. edx = CAST ; edx
N088. CNS_INT 5 REG NA
N090. mm0 = HWIntrinsic; mm0,edx
N092. V09 MEM; mm0
N094. IL_OFFSET IL offset: 0x3d REG NA
N096. mm0 = V09 MEM
N098. edx = V07 MEM
N100. edx = CAST ; edx
N102. CNS_INT 6 REG NA
N104. mm0 = HWIntrinsic; mm0,edx
N106. V09 MEM; mm0
N108. IL_OFFSET IL offset: 0x47 REG NA
N110. mm0 = V09 MEM
N112. edx = V08 MEM
N114. edx = CAST ; edx
N116. CNS_INT 7 REG NA
N118. mm0 = HWIntrinsic; mm0,edx
N120. edx = V00 MEM
N122. STOREIND ; edx,mm0
N124. RETURN
BB03 [051..063) (return), preds={BB01} succs={}
=====
N128. IL_OFFSET IL offset: 0x51 REG NA
N130. edx = V02 MEM
N132. edx = CAST ; edx
N134. PUTARG_STK [+0x00]; edx
N136. edx = V03 MEM
N138. edx = CAST ; edx
N140. PUTARG_STK [+0x04]; edx
N142. edx = V04 MEM
N144. edx = CAST ; edx
N146. PUTARG_STK [+0x08]; edx
N148. edx = V05 MEM
N150. edx = CAST ; edx
N152. PUTARG_STK [+0x0c]; edx
N154. edx = V06 MEM
N156. edx = CAST ; edx
N158. PUTARG_STK [+0x10]; edx
N160. edx = V07 MEM
N162. edx = CAST ; edx
N164. PUTARG_STK [+0x14]; edx
N166. edx = V08 MEM
N168. edx = CAST ; edx
N170. PUTARG_STK [+0x18]; edx
N172. edx = V01 MEM
N174. edx = CAST ; edx
N176. edx = PUTARG_REG; edx
N178. ecx = V00 MEM
N180. ecx = PUTARG_REG; ecx
N182. CALL ; edx,ecx
N184. RETURN
*************** In genGenerateCode()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..007)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [007..051) (return) i LIR
BB03 [0002] 1 BB01 1 [051..063) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Finalizing stack frame
Modified regs: [eax ecx edx mm0-mm7]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V00 RetBuf, size=4, stkOffs=-0xc
Assign V01 arg0, size=4, stkOffs=-0x10
Assign V09 loc0, size=16, stkOffs=-0x20
; Final local variable assignments
;
; V00 RetBuf [V00 ] ( 1, 1 ) byref -> [ebp-0x04]
; V01 arg0 [V01 ] ( 1, 1 ) ushort -> [ebp-0x08]
; V02 arg1 [V02 ] ( 1, 1 ) ushort -> [ebp+0x20]
; V03 arg2 [V03 ] ( 1, 1 ) ushort -> [ebp+0x1C]
; V04 arg3 [V04 ] ( 1, 1 ) ushort -> [ebp+0x18]
; V05 arg4 [V05 ] ( 1, 1 ) ushort -> [ebp+0x14]
; V06 arg5 [V06 ] ( 1, 1 ) ushort -> [ebp+0x10]
; V07 arg6 [V07 ] ( 1, 1 ) ushort -> [ebp+0x0C]
; V08 arg7 [V08 ] ( 1, 1 ) ushort -> [ebp+0x08]
; V09 loc0 [V09 ] ( 1, 1 ) simd16 -> [ebp-0x18] do-not-enreg[SB]
;
; Lcl frame size = 24
=============== Generating BB01 [000..007) -> BB03 (cond), preds={} succs={BB02,BB03} flags=0x00000000.40030020: i label target LIR
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 00000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M18419_BB01:
Label: IG02, GCvars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Setting stack level from -572662307 to 0
Scope info: begin block BB01, IL range [000..007)
Scope info: opening scope, LVnum=0 [000..063)
Scope info: >> new scope, VarNum=0, tracked? no, VarIndex=0, bbLiveIn=00000000 {}
Scope info: opening scope, LVnum=1 [000..063)
Scope info: >> new scope, VarNum=1, tracked? no, VarIndex=0, bbLiveIn=00000000 {}
Scope info: opening scope, LVnum=2 [000..063)
Scope info: >> new scope, VarNum=2, tracked? no, VarIndex=0, bbLiveIn=00000000 {}
Scope info: opening scope, LVnum=3 [000..063)
Scope info: >> new scope, VarNum=3, tracked? no, VarIndex=0, bbLiveIn=00000000 {}
Scope info: opening scope, LVnum=4 [000..063)
Scope info: >> new scope, VarNum=4, tracked? no, VarIndex=0, bbLiveIn=00000000 {}
Scope info: opening scope, LVnum=5 [000..063)
Scope info: >> new scope, VarNum=5, tracked? no, VarIndex=0, bbLiveIn=00000000 {}
Scope info: opening scope, LVnum=6 [000..063)
Scope info: >> new scope, VarNum=6, tracked? no, VarIndex=0, bbLiveIn=00000000 {}
Scope info: opening scope, LVnum=7 [000..063)
Scope info: >> new scope, VarNum=7, tracked? no, VarIndex=0, bbLiveIn=00000000 {}
Scope info: opening scope, LVnum=8 [000..063)
Scope info: >> new scope, VarNum=8, tracked? no, VarIndex=0, bbLiveIn=00000000 {}
Scope info: opening scope, LVnum=9 [000..063)
Scope info: >> new scope, VarNum=9, tracked? no, VarIndex=0, bbLiveIn=00000000 {}
Scope info: open scopes =
0 (V00 RetBuf) [000..063)
1 (V01 arg0) [000..063)
2 (V02 arg1) [000..063)
3 (V03 arg2) [000..063)
4 (V04 arg3) [000..063)
5 (V05 arg4) [000..063)
6 (V06 arg5) [000..063)
7 (V07 arg6) [000..063)
8 (V08 arg7) [000..063)
9 (V09 loc0) [000..063)
Added IP mapping: 0x0000 STACK_EMPTY (G_M18419_IG02,ins#0,ofs#0) label
Generating: N002 ( 5, 5) [000005] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N004 ( 1, 1) [000002] ------------ t2 = CNS_INT int 0 REG edx
IN0001: xor edx, edx
Generating: N006 ( 1, 1) [000001] -c---------- t1 = CNS_INT int 1 REG NA
/--* t2 int
+--* t1 int
Generating: N008 ( 3, 3) [000003] J------N---- * EQ void REG NA
IN0002: cmp edx, 1
Generating: N010 ( 5, 5) [000004] ------------ * JTRUE void REG NA
IN0003: je L_M18419_BB03
Scope info: end block BB01, IL range [000..007)
Scope info: open scopes =
0 (V00 RetBuf) [000..063)
1 (V01 arg0) [000..063)
2 (V02 arg1) [000..063)
3 (V03 arg2) [000..063)
4 (V04 arg3) [000..063)
5 (V05 arg4) [000..063)
6 (V06 arg5) [000..063)
7 (V07 arg6) [000..063)
8 (V08 arg7) [000..063)
9 (V09 loc0) [000..063)
=============== Generating BB02 [007..051) (return), preds={BB01} succs={} flags=0x00000000.40000020: i LIR
BB02 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 00000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M18419_BB02:
Scope info: begin block BB02, IL range [007..051)
Scope info: open scopes =
0 (V00 RetBuf) [000..063)
1 (V01 arg0) [000..063)
2 (V02 arg1) [000..063)
3 (V03 arg2) [000..063)
4 (V04 arg3) [000..063)
5 (V05 arg4) [000..063)
6 (V06 arg5) [000..063)
7 (V07 arg6) [000..063)
8 (V08 arg7) [000..063)
9 (V09 loc0) [000..063)
Added IP mapping: 0x0007 STACK_EMPTY (G_M18419_IG02,ins#3,ofs#11) label
Generating: N014 ( 9, 8) [000035] ------------ IL_OFFSET void IL offset: 0x7 REG NA
Generating: N016 ( 3, 2) [000030] ------------ t30 = LCL_VAR int V01 arg0 edx REG edx
IN0004: mov edx, dword ptr [V01 ebp-08H]
/--* t30 int
Generating: N018 ( 4, 4) [000115] ------------ t115 = * CAST int <- ushort <- int REG edx
IN0005: movzx edx, dx
/--* t115 int
Generating: N020 ( 5, 5) [000031] ------------ t31 = * HWIntrinsic simd16 ushort CreateScalarUnsafe REG mm0
IN0006: vmovd xmm0, edx
/--* t31 simd16
Generating: N022 ( 9, 8) [000034] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
IN0007: vmovupd xmmword ptr [V09 ebp-18H], xmm0
Added IP mapping: 0x000E STACK_EMPTY (G_M18419_IG02,ins#7,ofs#28)
Generating: N024 ( 15, 13) [000046] ------------ IL_OFFSET void IL offset: 0xe REG NA
Generating: N026 ( 3, 2) [000036] ------------ t36 = LCL_VAR simd16 V09 loc0 mm0 REG mm0
IN0008: vmovupd xmm0, xmmword ptr [V09 ebp-18H]
Generating: N028 ( 3, 2) [000037] ------------ t37 = LCL_VAR int V02 arg1 edx REG edx
IN0009: mov edx, dword ptr [V02 ebp+20H]
/--* t37 int
Generating: N030 ( 4, 4) [000116] ------------ t116 = * CAST int <- ushort <- int REG edx
IN000a: movzx edx, dx
Generating: N032 ( 1, 1) [000038] -c---------- t38 = CNS_INT int 1 REG NA
/--* t36 simd16
+--* t116 int
+--* t38 int
Generating: N034 ( 11, 10) [000042] ------------ t42 = * HWIntrinsic simd16 ushort Insert REG mm0
IN000b: vpinsrw xmm0, xmm0, xedx, 1
/--* t42 simd16
Generating: N036 ( 15, 13) [000045] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
IN000c: vmovupd xmmword ptr [V09 ebp-18H], xmm0
Added IP mapping: 0x0017 STACK_EMPTY (G_M18419_IG02,ins#12,ofs#52)
Generating: N038 ( 15, 13) [000057] ------------ IL_OFFSET void IL offset: 0x17 REG NA
Generating: N040 ( 3, 2) [000047] ------------ t47 = LCL_VAR simd16 V09 loc0 mm0 REG mm0
IN000d: vmovupd xmm0, xmmword ptr [V09 ebp-18H]
Generating: N042 ( 3, 2) [000048] ------------ t48 = LCL_VAR int V03 arg2 edx REG edx
IN000e: mov edx, dword ptr [V03 ebp+1CH]
/--* t48 int
Generating: N044 ( 4, 4) [000117] ------------ t117 = * CAST int <- ushort <- int REG edx
IN000f: movzx edx, dx
Generating: N046 ( 1, 1) [000049] -c---------- t49 = CNS_INT int 2 REG NA
/--* t47 simd16
+--* t117 int
+--* t49 int
Generating: N048 ( 11, 10) [000053] ------------ t53 = * HWIntrinsic simd16 ushort Insert REG mm0
IN0010: vpinsrw xmm0, xmm0, xedx, 2
/--* t53 simd16
Generating: N050 ( 15, 13) [000056] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
IN0011: vmovupd xmmword ptr [V09 ebp-18H], xmm0
Added IP mapping: 0x0020 STACK_EMPTY (G_M18419_IG02,ins#17,ofs#76)
Generating: N052 ( 15, 13) [000068] ------------ IL_OFFSET void IL offset: 0x20 REG NA
Generating: N054 ( 3, 2) [000058] ------------ t58 = LCL_VAR simd16 V09 loc0 mm0 REG mm0
IN0012: vmovupd xmm0, xmmword ptr [V09 ebp-18H]
Generating: N056 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V04 arg3 edx REG edx
IN0013: mov edx, dword ptr [V04 ebp+18H]
/--* t59 int
Generating: N058 ( 4, 4) [000118] ------------ t118 = * CAST int <- ushort <- int REG edx
IN0014: movzx edx, dx
Generating: N060 ( 1, 1) [000060] -c---------- t60 = CNS_INT int 3 REG NA
/--* t58 simd16
+--* t118 int
+--* t60 int
Generating: N062 ( 11, 10) [000064] ------------ t64 = * HWIntrinsic simd16 ushort Insert REG mm0
IN0015: vpinsrw xmm0, xmm0, xedx, 3
/--* t64 simd16
Generating: N064 ( 15, 13) [000067] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
IN0016: vmovupd xmmword ptr [V09 ebp-18H], xmm0
Added IP mapping: 0x0029 STACK_EMPTY (G_M18419_IG02,ins#22,ofs#100)
Generating: N066 ( 15, 13) [000079] ------------ IL_OFFSET void IL offset: 0x29 REG NA
Generating: N068 ( 3, 2) [000069] ------------ t69 = LCL_VAR simd16 V09 loc0 mm0 REG mm0
IN0017: vmovupd xmm0, xmmword ptr [V09 ebp-18H]
Generating: N070 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V05 arg4 edx REG edx
IN0018: mov edx, dword ptr [V05 ebp+14H]
/--* t70 int
Generating: N072 ( 4, 4) [000119] ------------ t119 = * CAST int <- ushort <- int REG edx
IN0019: movzx edx, dx
Generating: N074 ( 1, 1) [000071] -c---------- t71 = CNS_INT int 4 REG NA
/--* t69 simd16
+--* t119 int
+--* t71 int
Generating: N076 ( 11, 10) [000075] ------------ t75 = * HWIntrinsic simd16 ushort Insert REG mm0
IN001a: vpinsrw xmm0, xmm0, xedx, 4
/--* t75 simd16
Generating: N078 ( 15, 13) [000078] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
IN001b: vmovupd xmmword ptr [V09 ebp-18H], xmm0
Added IP mapping: 0x0033 STACK_EMPTY (G_M18419_IG02,ins#27,ofs#124)
Generating: N080 ( 15, 13) [000090] ------------ IL_OFFSET void IL offset: 0x33 REG NA
Generating: N082 ( 3, 2) [000080] ------------ t80 = LCL_VAR simd16 V09 loc0 mm0 REG mm0
IN001c: vmovupd xmm0, xmmword ptr [V09 ebp-18H]
Generating: N084 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V06 arg5 edx REG edx
IN001d: mov edx, dword ptr [V06 ebp+10H]
/--* t81 int
Generating: N086 ( 4, 4) [000120] ------------ t120 = * CAST int <- ushort <- int REG edx
IN001e: movzx edx, dx
Generating: N088 ( 1, 1) [000082] -c---------- t82 = CNS_INT int 5 REG NA
/--* t80 simd16
+--* t120 int
+--* t82 int
Generating: N090 ( 11, 10) [000086] ------------ t86 = * HWIntrinsic simd16 ushort Insert REG mm0
IN001f: vpinsrw xmm0, xmm0, xedx, 5
/--* t86 simd16
Generating: N092 ( 15, 13) [000089] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
IN0020: vmovupd xmmword ptr [V09 ebp-18H], xmm0
Added IP mapping: 0x003D STACK_EMPTY (G_M18419_IG02,ins#32,ofs#148)
Generating: N094 ( 15, 13) [000101] ------------ IL_OFFSET void IL offset: 0x3d REG NA
Generating: N096 ( 3, 2) [000091] ------------ t91 = LCL_VAR simd16 V09 loc0 mm0 REG mm0
IN0021: vmovupd xmm0, xmmword ptr [V09 ebp-18H]
Generating: N098 ( 3, 2) [000092] ------------ t92 = LCL_VAR int V07 arg6 edx REG edx
IN0022: mov edx, dword ptr [V07 ebp+0CH]
/--* t92 int
Generating: N100 ( 4, 4) [000121] ------------ t121 = * CAST int <- ushort <- int REG edx
IN0023: movzx edx, dx
Generating: N102 ( 1, 1) [000093] -c---------- t93 = CNS_INT int 6 REG NA
/--* t91 simd16
+--* t121 int
+--* t93 int
Generating: N104 ( 11, 10) [000097] ------------ t97 = * HWIntrinsic simd16 ushort Insert REG mm0
IN0024: vpinsrw xmm0, xmm0, xedx, 6
/--* t97 simd16
Generating: N106 ( 15, 13) [000100] DA---------- * STORE_LCL_VAR simd16 V09 loc0 NA REG NA
IN0025: vmovupd xmmword ptr [V09 ebp-18H], xmm0
Added IP mapping: 0x0047 STACK_EMPTY (G_M18419_IG02,ins#37,ofs#172)
Generating: N108 ( 18, 15) [000112] ------------ IL_OFFSET void IL offset: 0x47 REG NA
Generating: N110 ( 3, 2) [000102] ------------ t102 = LCL_VAR simd16 V09 loc0 mm0 REG mm0
IN0026: vmovupd xmm0, xmmword ptr [V09 ebp-18H]
Generating: N112 ( 3, 2) [000103] ------------ t103 = LCL_VAR int V08 arg7 edx REG edx
IN0027: mov edx, dword ptr [V08 ebp+08H]
/--* t103 int
Generating: N114 ( 4, 4) [000122] ------------ t122 = * CAST int <- ushort <- int REG edx
IN0028: movzx edx, dx
Generating: N116 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 7 REG NA
/--* t102 simd16
+--* t122 int
+--* t104 int
Generating: N118 ( 11, 10) [000108] ------------ t108 = * HWIntrinsic simd16 ushort Insert REG mm0
IN0029: vpinsrw xmm0, xmm0, xedx, 7
Generating: N120 ( 3, 2) [000109] ------------ t109 = LCL_VAR byref V00 RetBuf edx REG edx
IN002a: mov edx, bword ptr [V00 ebp-04H]
Byref regs: 00000000 {} => 00000004 {edx}
/--* t109 byref
+--* t108 simd16
Generating: N122 (???,???) [000135] -A-X-------- * STOREIND simd16 REG NA
Byref regs: 00000004 {edx} => 00000000 {}
IN002b: vmovupd xmmword ptr [edx], xmm0
Generating: N124 ( 0, 0) [000113] ------------ RETURN void REG NA
Scope info: end block BB02, IL range [007..051)
Scope info: open scopes =
0 (V00 RetBuf) [000..063)
1 (V01 arg0) [000..063)
2 (V02 arg1) [000..063)
3 (V03 arg2) [000..063)
4 (V04 arg3) [000..063)
5 (V05 arg4) [000..063)
6 (V06 arg5) [000..063)
7 (V07 arg6) [000..063)
8 (V08 arg7) [000..063)
9 (V09 loc0) [000..063)
Added IP mapping: EPILOG STACK_EMPTY (G_M18419_IG02,ins#43,ofs#198) label
Reserving epilog IG for block BB02
G_M18419_IG02: ; offs=000000H, funclet=00
*************** After placeholder IG creation
G_M18419_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M18419_IG02: ; offs=000000H, size=00C6H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M18419_IG03: ; epilog placeholder, next placeholder=<END>, BB02 [0001], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M18419_IG04: ; offs=0001C6H, size=0000H, gcrefRegs=00000000 {} <-- Current IG
=============== Generating BB03 [051..063) (return), preds={BB01} succs={} flags=0x00000000.400b0020: i label target gcsafe LIR
BB03 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 00000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M18419_BB03:
Label: IG04, GCvars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB03, IL range [051..063)
Scope info: open scopes =
0 (V00 RetBuf) [000..063)
1 (V01 arg0) [000..063)
2 (V02 arg1) [000..063)
3 (V03 arg2) [000..063)
4 (V04 arg3) [000..063)
5 (V05 arg4) [000..063)
6 (V06 arg5) [000..063)
7 (V07 arg6) [000..063)
8 (V08 arg7) [000..063)
9 (V09 loc0) [000..063)
Added IP mapping: 0x0051 STACK_EMPTY (G_M18419_IG04,ins#0,ofs#0) label
Generating: N128 ( 70, 41) [000026] ------------ IL_OFFSET void IL offset: 0x51 REG NA
Generating: N130 ( 3, 2) [000008] ------------ t8 = LCL_VAR int V02 arg1 edx REG edx
IN002c: mov edx, dword ptr [V02 ebp+20H]
/--* t8 int
Generating: N132 ( 4, 4) [000124] ------------ t124 = * CAST int <- ushort <- int REG edx
IN002d: movzx edx, dx
/--* t124 int
Generating: N134 (???,???) [000136] ------------ * PUTARG_STK [+0x00] void (1 slots) REG NA
IN002e: push edx
Upping emitMaxStackDepth from 0 to 4
Adjusting stack level from 0 to 4
Generating: N136 ( 3, 2) [000009] ------------ t9 = LCL_VAR int V03 arg2 edx REG edx
IN002f: mov edx, dword ptr [V03 ebp+1CH]
/--* t9 int
Generating: N138 ( 4, 4) [000125] ------------ t125 = * CAST int <- ushort <- int REG edx
IN0030: movzx edx, dx
/--* t125 int
Generating: N140 (???,???) [000137] ------------ * PUTARG_STK [+0x04] void (1 slots) REG NA
IN0031: push edx
Upping emitMaxStackDepth from 4 to 8
Adjusting stack level from 4 to 8
Generating: N142 ( 3, 2) [000010] ------------ t10 = LCL_VAR int V04 arg3 edx REG edx
IN0032: mov edx, dword ptr [V04 ebp+18H]
/--* t10 int
Generating: N144 ( 4, 4) [000126] ------------ t126 = * CAST int <- ushort <- int REG edx
IN0033: movzx edx, dx
/--* t126 int
Generating: N146 (???,???) [000138] ------------ * PUTARG_STK [+0x08] void (1 slots) REG NA
IN0034: push edx
Upping emitMaxStackDepth from 8 to 12
Adjusting stack level from 8 to 12
Generating: N148 ( 3, 2) [000011] ------------ t11 = LCL_VAR int V05 arg4 edx REG edx
IN0035: mov edx, dword ptr [V05 ebp+14H]
/--* t11 int
Generating: N150 ( 4, 4) [000127] ------------ t127 = * CAST int <- ushort <- int REG edx
IN0036: movzx edx, dx
/--* t127 int
Generating: N152 (???,???) [000139] ------------ * PUTARG_STK [+0x0c] void (1 slots) REG NA
IN0037: push edx
Upping emitMaxStackDepth from 12 to 16
Adjusting stack level from 12 to 16
Generating: N154 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V06 arg5 edx REG edx
IN0038: mov edx, dword ptr [V06 ebp+10H]
/--* t12 int
Generating: N156 ( 4, 4) [000128] ------------ t128 = * CAST int <- ushort <- int REG edx
IN0039: movzx edx, dx
/--* t128 int
Generating: N158 (???,???) [000140] ------------ * PUTARG_STK [+0x10] void (1 slots) REG NA
IN003a: push edx
Upping emitMaxStackDepth from 16 to 20
Adjusting stack level from 16 to 20
Generating: N160 ( 3, 2) [000013] ------------ t13 = LCL_VAR int V07 arg6 edx REG edx
IN003b: mov edx, dword ptr [V07 ebp+0CH]
/--* t13 int
Generating: N162 ( 4, 4) [000129] ------------ t129 = * CAST int <- ushort <- int REG edx
IN003c: movzx edx, dx
/--* t129 int
Generating: N164 (???,???) [000141] ------------ * PUTARG_STK [+0x14] void (1 slots) REG NA
IN003d: push edx
Upping emitMaxStackDepth from 20 to 24
Adjusting stack level from 20 to 24
Generating: N166 ( 3, 2) [000014] ------------ t14 = LCL_VAR int V08 arg7 edx REG edx
IN003e: mov edx, dword ptr [V08 ebp+08H]
/--* t14 int
Generating: N168 ( 4, 4) [000130] ------------ t130 = * CAST int <- ushort <- int REG edx
IN003f: movzx edx, dx
/--* t130 int
Generating: N170 (???,???) [000142] ------------ * PUTARG_STK [+0x18] void (1 slots) REG NA
IN0040: push edx
Upping emitMaxStackDepth from 24 to 28
Adjusting stack level from 24 to 28
Generating: N172 ( 3, 2) [000007] ------------ t7 = LCL_VAR int V01 arg0 edx REG edx
IN0041: mov edx, dword ptr [V01 ebp-08H]
/--* t7 int
Generating: N174 ( 4, 4) [000123] ------------ t123 = * CAST int <- ushort <- int REG edx
IN0042: movzx edx, dx
/--* t123 int
Generating: N176 (???,???) [000143] ------------ t143 = * PUTARG_REG int REG edx
Generating: N178 ( 3, 2) [000024] ------------ t24 = LCL_VAR byref V00 RetBuf ecx REG ecx
IN0043: mov ecx, bword ptr [V00 ebp-04H]
Byref regs: 00000000 {} => 00000002 {ecx}
/--* t24 byref
Generating: N180 (???,???) [000144] ------------ t144 = * PUTARG_REG byref REG ecx
Byref regs: 00000002 {ecx} => 00000000 {}
Byref regs: 00000000 {} => 00000002 {ecx}
/--* t143 int arg1 in edx
+--* t144 byref arg0 in ecx
Generating: N182 ( 70, 41) [000015] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<Create>g__SoftwareFallback|18_0
Byref regs: 00000002 {ecx} => 00000000 {}
Call: GCvars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0044: call System.Runtime.Intrinsics.Vector128:<Create>g__SoftwareFallback|18_0(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct
Adjusting stack level from 28 to 0
Generating: N184 ( 0, 0) [000027] ------------ RETURN void REG NA
Scope info: end block BB03, IL range [051..063)
Scope info: ending scope, LVnum=0 [000..063)
Scope info: ending scope, LVnum=1 [000..063)
Scope info: ending scope, LVnum=2 [000..063)
Scope info: ending scope, LVnum=3 [000..063)
Scope info: ending scope, LVnum=4 [000..063)
Scope info: ending scope, LVnum=5 [000..063)
Scope info: ending scope, LVnum=6 [000..063)
Scope info: ending scope, LVnum=7 [000..063)
Scope info: ending scope, LVnum=8 [000..063)
Scope info: ending scope, LVnum=9 [000..063)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M18419_IG04,ins#25,ofs#63) label
Reserving epilog IG for block BB03
G_M18419_IG04: ; offs=0001C6H, funclet=00
*************** After placeholder IG creation
G_M18419_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M18419_IG02: ; offs=000000H, size=00C6H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M18419_IG03: ; epilog placeholder, next placeholder=IG05 , BB02 [0001], epilog, emitadd <-- First placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M18419_IG04: ; offs=0001C6H, size=003FH, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
G_M18419_IG05: ; epilog placeholder, next placeholder=<END>, BB03 [0002], epilog, emitadd <-- Last placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Liveness not changing: 00000000 {}
# compCycleEstimate = 192, compSizeEstimate = 147 System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct
; Final local variable assignments
;
; V00 RetBuf [V00 ] ( 1, 1 ) byref -> [ebp-0x04]
; V01 arg0 [V01 ] ( 1, 1 ) ushort -> [ebp-0x08]
; V02 arg1 [V02 ] ( 1, 1 ) ushort -> [ebp+0x20]
; V03 arg2 [V03 ] ( 1, 1 ) ushort -> [ebp+0x1C]
; V04 arg3 [V04 ] ( 1, 1 ) ushort -> [ebp+0x18]
; V05 arg4 [V05 ] ( 1, 1 ) ushort -> [ebp+0x14]
; V06 arg5 [V06 ] ( 1, 1 ) ushort -> [ebp+0x10]
; V07 arg6 [V07 ] ( 1, 1 ) ushort -> [ebp+0x0C]
; V08 arg7 [V08 ] ( 1, 1 ) ushort -> [ebp+0x08]
; V09 loc0 [V09 ] ( 1, 1 ) simd16 -> [ebp-0x18] do-not-enreg[SB]
;
; Lcl frame size = 24
*************** Before prolog / epilog generation
G_M18419_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M18419_IG02: ; offs=000000H, size=00C6H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M18419_IG03: ; epilog placeholder, next placeholder=IG05 , BB02 [0001], epilog, emitadd <-- First placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M18419_IG04: ; offs=0001C6H, size=003FH, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
G_M18419_IG05: ; epilog placeholder, next placeholder=<END>, BB03 [0002], epilog, emitadd <-- Last placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M18419_IG01,ins#0,ofs#0) label
__prolog:
IN0045: push ebp
IN0046: mov ebp, esp
IN0047: sub esp, 24
IN0048: vzeroupper
*************** In genFnPrologCalleeRegArgs() for int regs
IN0049: mov bword ptr [V00 ebp-04H], ecx
IN004a: mov dword ptr [V01 ebp-08H], edx
*************** In genEnregisterIncomingStackArgs()
G_M18419_IG01: ; offs=000000H, funclet=00
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=00000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN004b: mov esp, ebp
IN004c: pop ebp
IN004d: ret 28
G_M18419_IG03: ; offs=0000C6H, funclet=00
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=00000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN004e: mov esp, ebp
IN004f: pop ebp
IN0050: ret 28
G_M18419_IG05: ; offs=000205H, funclet=00
0 prologs, 2 epilogs
*************** After prolog / epilog generation
G_M18419_IG01: ; func=00, offs=000000H, size=000FH, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref, nogc <-- Prolog IG
G_M18419_IG02: ; offs=00000FH, size=00C6H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M18419_IG03: ; offs=0000D5H, size=0006H, epilog, nogc, emitadd
G_M18419_IG04: ; offs=0000DBH, size=003FH, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
G_M18419_IG05: ; offs=00011AH, size=0006H, epilog, nogc, emitadd
*************** In emitJumpDistBind()
Binding: IN0003: 000000 je L_M18419_BB03
Binding L_M18419_BB03to G_M18419_IG04
Estimate of fwd jump [0762B2DC/003]: 0014 -> 00DB = 00C5
Hot code size = 0x120 bytes
Cold code size = 0x0 bytes
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (28) to elements (7)
***************************************************************************
Instructions as they come out of the scheduler
G_M18419_IG01: ; func=00, offs=000000H, size=000FH, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref, nogc <-- Prolog IG
IN0045: 000000 55 push ebp
IN0046: 000001 8BEC mov ebp, esp
IN0047: 000003 83EC18 sub esp, 24
IN0048: 000006 C5F877 vzeroupper
IN0049: 000009 894DFC mov bword ptr [ebp-04H], ecx
IN004a: 00000C 8955F8 mov dword ptr [ebp-08H], edx
G_M18419_IG02: ; func=00, offs=00000FH, size=00C6H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0001: 00000F 33D2 xor edx, edx
IN0002: 000011 83FA01 cmp edx, 1
IN0003: 000014 0F84C1000000 je G_M18419_IG04
IN0004: 00001A 8B55F8 mov edx, dword ptr [ebp-08H]
IN0005: 00001D 0FB7D2 movzx edx, dx
IN0006: 000020 C5F96EC2 vmovd xmm0, edx (ECS:5, ACS:4)
Instruction predicted size = 5, actual = 4
IN0007: 000024 C5F91145E8 vmovupd xmmword ptr [ebp-18H], xmm0 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0008: 000029 C5F91045E8 vmovupd xmm0, xmmword ptr [ebp-18H] (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0009: 00002E 8B5520 mov edx, dword ptr [ebp+20H]
IN000a: 000031 0FB7D2 movzx edx, dx
IN000b: 000034 C5F9C4C201 vpinsrw xmm0, xmm0, xedx, 1 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN000c: 000039 C5F91145E8 vmovupd xmmword ptr [ebp-18H], xmm0 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN000d: 00003E C5F91045E8 vmovupd xmm0, xmmword ptr [ebp-18H] (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN000e: 000043 8B551C mov edx, dword ptr [ebp+1CH]
IN000f: 000046 0FB7D2 movzx edx, dx
IN0010: 000049 C5F9C4C202 vpinsrw xmm0, xmm0, xedx, 2 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0011: 00004E C5F91145E8 vmovupd xmmword ptr [ebp-18H], xmm0 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0012: 000053 C5F91045E8 vmovupd xmm0, xmmword ptr [ebp-18H] (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0013: 000058 8B5518 mov edx, dword ptr [ebp+18H]
IN0014: 00005B 0FB7D2 movzx edx, dx
IN0015: 00005E C5F9C4C203 vpinsrw xmm0, xmm0, xedx, 3 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0016: 000063 C5F91145E8 vmovupd xmmword ptr [ebp-18H], xmm0 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0017: 000068 C5F91045E8 vmovupd xmm0, xmmword ptr [ebp-18H] (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0018: 00006D 8B5514 mov edx, dword ptr [ebp+14H]
IN0019: 000070 0FB7D2 movzx edx, dx
IN001a: 000073 C5F9C4C204 vpinsrw xmm0, xmm0, xedx, 4 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN001b: 000078 C5F91145E8 vmovupd xmmword ptr [ebp-18H], xmm0 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN001c: 00007D C5F91045E8 vmovupd xmm0, xmmword ptr [ebp-18H] (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN001d: 000082 8B5510 mov edx, dword ptr [ebp+10H]
IN001e: 000085 0FB7D2 movzx edx, dx
IN001f: 000088 C5F9C4C205 vpinsrw xmm0, xmm0, xedx, 5 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0020: 00008D C5F91145E8 vmovupd xmmword ptr [ebp-18H], xmm0 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0021: 000092 C5F91045E8 vmovupd xmm0, xmmword ptr [ebp-18H] (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0022: 000097 8B550C mov edx, dword ptr [ebp+0CH]
IN0023: 00009A 0FB7D2 movzx edx, dx
IN0024: 00009D C5F9C4C206 vpinsrw xmm0, xmm0, xedx, 6 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0025: 0000A2 C5F91145E8 vmovupd xmmword ptr [ebp-18H], xmm0 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0026: 0000A7 C5F91045E8 vmovupd xmm0, xmmword ptr [ebp-18H] (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0027: 0000AC 8B5508 mov edx, dword ptr [ebp+08H]
IN0028: 0000AF 0FB7D2 movzx edx, dx
IN0029: 0000B2 C5F9C4C207 vpinsrw xmm0, xmm0, xedx, 7 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
byrReg +[edx]
IN002a: 0000B7 8B55FC mov edx, bword ptr [ebp-04H]
IN002b: 0000BA C5F91102 vmovupd xmmword ptr [edx], xmm0 (ECS:5, ACS:4)
Instruction predicted size = 5, actual = 4
G_M18419_IG03: ; func=00, offs=0000D5H, size=0006H, epilog, nogc, emitadd
Block predicted offs = 000000D5, actual = 000000BE -> size adj = 23
IN004b: 0000BE 8BE5 mov esp, ebp
IN004c: 0000C0 5D pop ebp
IN004d: 0000C1 C21C00 ret 28
G_M18419_IG04: ; func=00, offs=0000DBH, size=003FH, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
Block predicted offs = 000000DB, actual = 000000C4 -> size adj = 23
New byrReg live regs=00000000 {}
IN002c: 0000C4 8B5520 mov edx, dword ptr [ebp+20H]
IN002d: 0000C7 0FB7D2 movzx edx, dx
IN002e: 0000CA 52 push edx
IN002f: 0000CB 8B551C mov edx, dword ptr [ebp+1CH]
IN0030: 0000CE 0FB7D2 movzx edx, dx
IN0031: 0000D1 52 push edx
IN0032: 0000D2 8B5518 mov edx, dword ptr [ebp+18H]
IN0033: 0000D5 0FB7D2 movzx edx, dx
IN0034: 0000D8 52 push edx
IN0035: 0000D9 8B5514 mov edx, dword ptr [ebp+14H]
IN0036: 0000DC 0FB7D2 movzx edx, dx
IN0037: 0000DF 52 push edx
IN0038: 0000E0 8B5510 mov edx, dword ptr [ebp+10H]
IN0039: 0000E3 0FB7D2 movzx edx, dx
IN003a: 0000E6 52 push edx
IN003b: 0000E7 8B550C mov edx, dword ptr [ebp+0CH]
IN003c: 0000EA 0FB7D2 movzx edx, dx
IN003d: 0000ED 52 push edx
IN003e: 0000EE 8B5508 mov edx, dword ptr [ebp+08H]
IN003f: 0000F1 0FB7D2 movzx edx, dx
IN0040: 0000F4 52 push edx
IN0041: 0000F5 8B55F8 mov edx, dword ptr [ebp-08H]
IN0042: 0000F8 0FB7D2 movzx edx, dx
byrReg +[ecx]
IN0043: 0000FB 8B4DFC mov ecx, bword ptr [ebp-04H]
New byrReg live regs=00000000 {}
IN0044: 0000FE E87D625056 call System.Runtime.Intrinsics.Vector128:<Create>g__SoftwareFallback|18_0(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct
G_M18419_IG05: ; func=00, offs=00011AH, size=0006H, epilog, nogc, emitadd
Block predicted offs = 0000011A, actual = 00000103 -> size adj = 23
IN004e: 000103 8BE5 mov esp, ebp
IN004f: 000105 5D pop ebp
IN0050: 000106 C21C00 ret 28
Allocated method code size = 288 , actual size = 265
*************** After end code gen, before unwindEmit()
G_M18419_IG01: ; func=00, offs=000000H, size=000FH, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref, nogc <-- Prolog IG
IN0045: 000000 push ebp
IN0046: 000001 mov ebp, esp
IN0047: 000003 sub esp, 24
IN0048: 000006 vzeroupper
IN0049: 000009 mov bword ptr [V00 ebp-04H], ecx
IN004a: 00000C mov dword ptr [V01 ebp-08H], edx
G_M18419_IG02: ; offs=00000FH, size=00AFH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0001: 00000F xor edx, edx
IN0002: 000011 cmp edx, 1
IN0003: 000014 je G_M18419_IG04
IN0004: 00001A mov edx, dword ptr [V01 ebp-08H]
IN0005: 00001D movzx edx, dx
IN0006: 000020 vmovd xmm0, edx
IN0007: 000024 vmovupd xmmword ptr [V09 ebp-18H], xmm0
IN0008: 000029 vmovupd xmm0, xmmword ptr [V09 ebp-18H]
IN0009: 00002E mov edx, dword ptr [V02 ebp+20H]
IN000a: 000031 movzx edx, dx
IN000b: 000034 vpinsrw xmm0, xmm0, xedx, 1
IN000c: 000039 vmovupd xmmword ptr [V09 ebp-18H], xmm0
IN000d: 00003E vmovupd xmm0, xmmword ptr [V09 ebp-18H]
IN000e: 000043 mov edx, dword ptr [V03 ebp+1CH]
IN000f: 000046 movzx edx, dx
IN0010: 000049 vpinsrw xmm0, xmm0, xedx, 2
IN0011: 00004E vmovupd xmmword ptr [V09 ebp-18H], xmm0
IN0012: 000053 vmovupd xmm0, xmmword ptr [V09 ebp-18H]
IN0013: 000058 mov edx, dword ptr [V04 ebp+18H]
IN0014: 00005B movzx edx, dx
IN0015: 00005E vpinsrw xmm0, xmm0, xedx, 3
IN0016: 000063 vmovupd xmmword ptr [V09 ebp-18H], xmm0
IN0017: 000068 vmovupd xmm0, xmmword ptr [V09 ebp-18H]
IN0018: 00006D mov edx, dword ptr [V05 ebp+14H]
IN0019: 000070 movzx edx, dx
IN001a: 000073 vpinsrw xmm0, xmm0, xedx, 4
IN001b: 000078 vmovupd xmmword ptr [V09 ebp-18H], xmm0
IN001c: 00007D vmovupd xmm0, xmmword ptr [V09 ebp-18H]
IN001d: 000082 mov edx, dword ptr [V06 ebp+10H]
IN001e: 000085 movzx edx, dx
IN001f: 000088 vpinsrw xmm0, xmm0, xedx, 5
IN0020: 00008D vmovupd xmmword ptr [V09 ebp-18H], xmm0
IN0021: 000092 vmovupd xmm0, xmmword ptr [V09 ebp-18H]
IN0022: 000097 mov edx, dword ptr [V07 ebp+0CH]
IN0023: 00009A movzx edx, dx
IN0024: 00009D vpinsrw xmm0, xmm0, xedx, 6
IN0025: 0000A2 vmovupd xmmword ptr [V09 ebp-18H], xmm0
IN0026: 0000A7 vmovupd xmm0, xmmword ptr [V09 ebp-18H]
IN0027: 0000AC mov edx, dword ptr [V08 ebp+08H]
IN0028: 0000AF movzx edx, dx
IN0029: 0000B2 vpinsrw xmm0, xmm0, xedx, 7
IN002a: 0000B7 mov edx, bword ptr [V00 ebp-04H]
IN002b: 0000BA vmovupd xmmword ptr [edx], xmm0
G_M18419_IG03: ; offs=0000BEH, size=0006H, epilog, nogc, emitadd
IN004b: 0000BE mov esp, ebp
IN004c: 0000C0 pop ebp
IN004d: 0000C1 ret 28
G_M18419_IG04: ; offs=0000C4H, size=003FH, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
IN002c: 0000C4 mov edx, dword ptr [V02 ebp+20H]
IN002d: 0000C7 movzx edx, dx
IN002e: 0000CA push edx
IN002f: 0000CB mov edx, dword ptr [V03 ebp+1CH]
IN0030: 0000CE movzx edx, dx
IN0031: 0000D1 push edx
IN0032: 0000D2 mov edx, dword ptr [V04 ebp+18H]
IN0033: 0000D5 movzx edx, dx
IN0034: 0000D8 push edx
IN0035: 0000D9 mov edx, dword ptr [V05 ebp+14H]
IN0036: 0000DC movzx edx, dx
IN0037: 0000DF push edx
IN0038: 0000E0 mov edx, dword ptr [V06 ebp+10H]
IN0039: 0000E3 movzx edx, dx
IN003a: 0000E6 push edx
IN003b: 0000E7 mov edx, dword ptr [V07 ebp+0CH]
IN003c: 0000EA movzx edx, dx
IN003d: 0000ED push edx
IN003e: 0000EE mov edx, dword ptr [V08 ebp+08H]
IN003f: 0000F1 movzx edx, dx
IN0040: 0000F4 push edx
IN0041: 0000F5 mov edx, dword ptr [V01 ebp-08H]
IN0042: 0000F8 movzx edx, dx
IN0043: 0000FB mov ecx, bword ptr [V00 ebp-04H]
IN0044: 0000FE call System.Runtime.Intrinsics.Vector128:<Create>g__SoftwareFallback|18_0(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct
G_M18419_IG05: ; offs=000103H, size=0006H, epilog, nogc, emitadd
IN004e: 000103 mov esp, ebp
IN004f: 000105 pop ebp
IN0050: 000106 ret 28
*************** In genIPmappingGen()
IP mapping count : 13
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x0000000F ( STACK_EMPTY )
IL offs 0x0007 : 0x0000001A ( STACK_EMPTY )
IL offs 0x000E : 0x00000029 ( STACK_EMPTY )
IL offs 0x0017 : 0x0000003E ( STACK_EMPTY )
IL offs 0x0020 : 0x00000053 ( STACK_EMPTY )
IL offs 0x0029 : 0x00000068 ( STACK_EMPTY )
IL offs 0x0033 : 0x0000007D ( STACK_EMPTY )
IL offs 0x003D : 0x00000092 ( STACK_EMPTY )
IL offs 0x0047 : 0x000000A7 ( STACK_EMPTY )
IL offs EPILOG : 0x000000BE ( STACK_EMPTY )
IL offs 0x0051 : 0x000000C4 ( STACK_EMPTY )
IL offs EPILOG : 0x00000103 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 19
*************** Variable debug info
19 vars
-2( retBuff) : From 00000000h to 0000000Fh, in ecx
0( UNKNOWN) : From 00000000h to 0000000Fh, in edx
1( UNKNOWN) : From 00000000h to 0000000Fh, in esp[28] (1 slot)
2( UNKNOWN) : From 00000000h to 0000000Fh, in esp[24] (1 slot)
3( UNKNOWN) : From 00000000h to 0000000Fh, in esp[20] (1 slot)
4( UNKNOWN) : From 00000000h to 0000000Fh, in esp[16] (1 slot)
5( UNKNOWN) : From 00000000h to 0000000Fh, in esp[12] (1 slot)
6( UNKNOWN) : From 00000000h to 0000000Fh, in esp[8] (1 slot)
7( UNKNOWN) : From 00000000h to 0000000Fh, in esp[4] (1 slot)
-2( retBuff) : From 0000000Fh to 00000103h, in ebp[-4] (1 slot)
0( UNKNOWN) : From 0000000Fh to 00000103h, in ebp[-8] (1 slot)
1( UNKNOWN) : From 0000000Fh to 00000103h, in ebp[32] (1 slot)
2( UNKNOWN) : From 0000000Fh to 00000103h, in ebp[28] (1 slot)
3( UNKNOWN) : From 0000000Fh to 00000103h, in ebp[24] (1 slot)
4( UNKNOWN) : From 0000000Fh to 00000103h, in ebp[20] (1 slot)
5( UNKNOWN) : From 0000000Fh to 00000103h, in ebp[16] (1 slot)
6( UNKNOWN) : From 0000000Fh to 00000103h, in ebp[12] (1 slot)
7( UNKNOWN) : From 0000000Fh to 00000103h, in ebp[8] (1 slot)
8( UNKNOWN) : From 0000000Fh to 00000103h, in ebp[-24] (1 slot)
*************** In gcInfoBlockHdrSave()
GCINFO: untrckd byr lcl at [ebp-04H]
GCINFO: untrckVars = 1
GCINFO: trackdLcls = 0
*************** In gcInfoBlockHdrSave()
GCINFO: methodSize = 0109
GCINFO: prologSize = 0009
GCINFO: epilogSize = 0006
GC Info for method System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct
GC info size = 15
Method info block:
method size = 0109
prolog size = 9
epilog size = 6
epilog count = 2
epilog end = no
callee-saved regs = EBP
ebp frame = yes
fully interruptible= no
double align = no
arguments size = 7 DWORDs
stack frame size = 6 DWORDs
untracked count = 1
var ptr tab count = 0
epilog # 0 at 00BE
epilog # 1 at 0103
82 09 82 8F 86 |
B8 A8 9A BE 3F |
81 3E 45 |
Pointer table:
03 | [EBP-04H] an untracked byref local
FF |
Method code size: 265
Allocations for System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct (MethodHash=1e6cb80c)
count: 797, size: 48166, max = 1680
allocateMemory: 65536, nraUsed: 49780
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 0 | 0.00%
ASTNode | 14196 | 29.47%
InstDesc | 4336 | 9.00%
ImpStack | 192 | 0.40%
BasicBlock | 564 | 1.17%
fgArgInfo | 396 | 0.82%
fgArgInfoPtrArr | 248 | 0.51%
FlowList | 40 | 0.08%
TreeStatementList | 0 | 0.00%
SiScope | 796 | 1.65%
DominatorMemory | 0 | 0.00%
LSRA | 1412 | 2.93%
LSRA_Interval | 2704 | 5.61%
LSRA_RefPosition | 5456 | 11.33%
Reachability | 0 | 0.00%
SSA | 0 | 0.00%
ValueNumber | 0 | 0.00%
LvaTable | 1684 | 3.50%
UnwindInfo | 0 | 0.00%
hashBv | 60 | 0.12%
bitset | 204 | 0.42%
FixedBitVect | 20 | 0.04%
Generic | 622 | 1.29%
LocalAddressVisitor | 256 | 0.53%
FieldSeqStore | 0 | 0.00%
ZeroOffsetFieldMap | 0 | 0.00%
ArrayInfoMap | 0 | 0.00%
MemoryPhiArg | 0 | 0.00%
CSE | 0 | 0.00%
GC | 24 | 0.05%
CorSig | 52 | 0.11%
Inlining | 100 | 0.21%
ArrayStack | 64 | 0.13%
DebugInfo | 540 | 1.12%
DebugOnly | 13538 | 28.11%
Codegen | 572 | 1.19%
LoopOpt | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 90 | 0.19%
RangeCheck | 0 | 0.00%
CopyProp | 0 | 0.00%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
****** DONE compiling System.Runtime.Intrinsics.Vector128:Create(ushort,ushort,ushort,ushort,ushort,ushort,ushort,ushort):struct
Beginning scenario: RunReflectionScenario
Ending test case at 1/7/2019 10:23:08 AM
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