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tannergooding/JitDump_CreateScalar.UInt16_Base.txt

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JitDump_CreateScalar.UInt16_Base.txt
Beginning test case CreateScalar.UInt16 at 1/5/2019 8:30:02 AM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro
Beginning scenario: RunBasicScenario
****** START compiling System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct (MethodHash=16b94f02)
Generating code for Windows x86
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Stack probing is DISABLED
IL to import:
IL_0000 12 00 ldloca.s 0x0
IL_0002 02 ldarg.0
IL_0003 7d 10 14 00 04 stfld 0x4001410
IL_0008 28 d3 40 00 06 call 0x60040D3
IL_000d 2c 14 brfalse.s 20 (IL_0023)
IL_000f 06 ldloc.0
IL_0010 7b 10 14 00 04 ldfld 0x4001410
IL_0015 28 33 41 00 06 call 0x6004133
IL_001a 0b stloc.1
IL_001b 12 01 ldloca.s 0x1
IL_001d 28 c1 08 00 0a call 0xA0008C1
IL_0022 2a ret
IL_0023 06 ldloc.0
IL_0024 7b 10 14 00 04 ldfld 0x4001410
IL_0029 12 00 ldloca.s 0x0
IL_002b 28 56 3c 00 06 call 0x6003C56
IL_0030 2a ret
HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type UInt16
Found type Hardware Intrinsic SIMD Vector128<ushort>
Known type Vector128<ushort>
'__retBuf' passed in register ecx
Arg #1 passed in register(s) edx
HW Intrinsic SIMD Candidate Type Vector128`1 with Base Type UInt32
Found type Hardware Intrinsic SIMD Vector128<uint>
; Initial local variable assignments
;
; V00 RetBuf byref
; V01 arg0 ushort
; V02 loc0 struct ( 4)
; V03 loc1 simd16
*************** In compInitDebuggingInfo() for System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 4
VarNum LVNum Name Beg End
0: 00h 00h V00 RetBuf 000h 031h
1: 01h 01h V01 arg0 000h 031h
2: 02h 02h V02 loc0 000h 031h
3: 03h 03h V03 loc1 000h 031h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct
Jump targets:
IL_0023
New Basic Block BB01 [0000] created.
BB01 [000..00F)
New Basic Block BB02 [0001] created.
BB02 [00F..023)
New Basic Block BB03 [0002] created.
BB03 [023..031)
CLFLG_MINOPT set for method System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct
IL Code Size,Instr 49, 17, Basic Block count 3, Local Variable Num,Ref count 4, 7 for method System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct
IL Code Size,Instr 49, 17, Basic Block count 3, Local Variable Num,Ref count 4, 7 for method System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct
OPTIONS: opts.MinOpts() == true
Basic block list for 'System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond )
BB02 [0001] 1 1 [00F..023) (return)
BB03 [0002] 1 1 [023..031) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct'
[ 0] 0 (0x000) ldloca.s 0
[ 1] 2 (0x002) ldarg.0
[ 2] 3 (0x003) stfld 04001410
[000006] ------------ * STMT void (IL 0x000... ???)
[000003] ------------ | /--* LCL_VAR ushort V01 arg0
[000005] -A---------- \--* ASG ushort
[000004] -------N---- \--* FIELD ushort value
[000002] L----------- \--* ADDR byref
[000001] ------------ \--* LCL_VAR struct V02 loc0
[ 0] 8 (0x008) call 060040D3
In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0
[ 1] 13 (0x00d) brfalse.s
[000011] ------------ * STMT void (IL 0x008... ???)
[000010] ------------ \--* JTRUE void
[000008] ------------ | /--* CNS_INT int 0
[000009] ------------ \--* EQ int
[000007] ------------ \--* CNS_INT int 1
impImportBlockPending for BB02
impImportBlockPending for BB03
Importing BB03 (PC=035) of 'System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct'
[ 0] 35 (0x023) ldloc.0
[ 1] 36 (0x024) ldfld 04001410
[ 1] 41 (0x029) ldloca.s 0
[ 2] 43 (0x02b) call 06003C56
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Known type Vector128<ushort>
[ 1] 48 (0x030) ret
[000023] ------------ * STMT void (IL 0x023... ???)
[000018] S-C-G------- \--* CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
[000021] ------------ arg0 +--* LCL_VAR byref V00 RetBuf
[000015] ------------ arg1 +--* FIELD ushort value
[000014] L----------- | \--* ADDR byref
[000013] ------------ | \--* LCL_VAR struct V02 loc0
[000017] L----------- arg2 \--* ADDR byref
[000016] ------------ \--* LCL_VAR struct V02 loc0
[000025] ------------ * STMT void (IL ???... ???)
[000024] ------------ \--* RETURN void
Importing BB02 (PC=015) of 'System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct'
[ 0] 15 (0x00f) ldloc.0
[ 1] 16 (0x010) ldfld 04001410
[ 1] 21 (0x015) call 06004133
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Known type Vector128<uint>
[ 1] 26 (0x01a) stloc.1
[000034] ------------ * STMT void (IL 0x00F... ???)
[000030] ------------ | /--* HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
[000029] ------------ | | \--* FIELD ushort value
[000028] L----------- | | \--* ADDR byref
[000027] ------------ | | \--* LCL_VAR struct V02 loc0
[000033] -A---------- \--* ASG simd16 (copy)
[000031] D----------- \--* LCL_VAR simd16 V03 loc1
[ 0] 27 (0x01b) ldloca.s 1
[ 1] 29 (0x01d) call 0A0008C1
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Known type Vector128<uint>
Known type Vector128<ushort>
Known type Vector128<ushort>
[ 1] 34 (0x022) ret
[000040] ------------ * STMT void (IL 0x01B... ???)
[000035] ------------ | /--* LCL_VAR simd16 V03 loc1
[000039] -A---------- \--* ASG simd16 (copy)
[000038] ------------ \--* BLK(16) simd16
[000037] ------------ \--* LCL_VAR byref V00 RetBuf
[000042] ------------ * STMT void (IL ???... ???)
[000041] ------------ \--* RETURN void
*************** in fgTransformIndirectCalls(root)
-- no candidates to transform
New BlockSet epoch 1, # of blocks (including unused BB00): 4, bitset array size: 1 (short)
*************** In fgMorph()
*************** In fgDebugCheckBBlist
*************** In Allocate Objects
Trees before Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i
BB02 [0001] 1 1 [00F..023) (return) i
BB03 [0002] 1 1 [023..031) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000006] ------------ * STMT void (IL 0x000...0x003)
[000003] ------------ | /--* LCL_VAR ushort V01 arg0
[000005] -A---------- \--* ASG ushort
[000004] -------N---- \--* FIELD ushort value
[000002] L----------- \--* ADDR byref
[000001] ------------ \--* LCL_VAR struct V02 loc0
***** BB01, stmt 2
[000011] ------------ * STMT void (IL 0x008...0x00D)
[000010] ------------ \--* JTRUE void
[000008] ------------ | /--* CNS_INT int 0
[000009] ------------ \--* EQ int
[000007] ------------ \--* CNS_INT int 1
------------ BB02 [00F..023) (return), preds={} succs={}
***** BB02, stmt 3
[000034] ------------ * STMT void (IL 0x00F...0x01A)
[000030] ------------ | /--* HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
[000029] ------------ | | \--* FIELD ushort value
[000028] L----------- | | \--* ADDR byref
[000027] ------------ | | \--* LCL_VAR struct V02 loc0
[000033] -A---------- \--* ASG simd16 (copy)
[000031] D----------- \--* LCL_VAR simd16 V03 loc1
***** BB02, stmt 4
[000040] ------------ * STMT void (IL 0x01B...0x022)
[000035] ------------ | /--* LCL_VAR simd16 V03 loc1
[000039] -A---------- \--* ASG simd16 (copy)
[000038] ------------ \--* BLK(16) simd16
[000037] ------------ \--* LCL_VAR byref V00 RetBuf
***** BB02, stmt 5
[000042] ------------ * STMT void (IL ???... ???)
[000041] ------------ \--* RETURN void
------------ BB03 [023..031) (return), preds={} succs={}
***** BB03, stmt 6
[000023] ------------ * STMT void (IL 0x023...0x030)
[000018] S-C-G------- \--* CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
[000021] ------------ arg0 +--* LCL_VAR byref V00 RetBuf
[000015] ------------ arg1 +--* FIELD ushort value
[000014] L----------- | \--* ADDR byref
[000013] ------------ | \--* LCL_VAR struct V02 loc0
[000017] L----------- arg2 \--* ADDR byref
[000016] ------------ \--* LCL_VAR struct V02 loc0
***** BB03, stmt 7
[000025] ------------ * STMT void (IL ???... ???)
[000024] ------------ \--* RETURN void
-------------------------------------------------------------------------------------------------------------------
*** ObjectAllocationPhase: no newobjs in this method; punting
*************** Exiting Allocate Objects
Trees after Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i
BB02 [0001] 1 1 [00F..023) (return) i
BB03 [0002] 1 1 [023..031) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
[000006] ------------ * STMT void (IL 0x000...0x003)
[000003] ------------ | /--* LCL_VAR ushort V01 arg0
[000005] -A---------- \--* ASG ushort
[000004] -------N---- \--* FIELD ushort value
[000002] L----------- \--* ADDR byref
[000001] ------------ \--* LCL_VAR struct V02 loc0
***** BB01, stmt 2
[000011] ------------ * STMT void (IL 0x008...0x00D)
[000010] ------------ \--* JTRUE void
[000008] ------------ | /--* CNS_INT int 0
[000009] ------------ \--* EQ int
[000007] ------------ \--* CNS_INT int 1
------------ BB02 [00F..023) (return), preds={} succs={}
***** BB02, stmt 3
[000034] ------------ * STMT void (IL 0x00F...0x01A)
[000030] ------------ | /--* HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
[000029] ------------ | | \--* FIELD ushort value
[000028] L----------- | | \--* ADDR byref
[000027] ------------ | | \--* LCL_VAR struct V02 loc0
[000033] -A---------- \--* ASG simd16 (copy)
[000031] D----------- \--* LCL_VAR simd16 V03 loc1
***** BB02, stmt 4
[000040] ------------ * STMT void (IL 0x01B...0x022)
[000035] ------------ | /--* LCL_VAR simd16 V03 loc1
[000039] -A---------- \--* ASG simd16 (copy)
[000038] ------------ \--* BLK(16) simd16
[000037] ------------ \--* LCL_VAR byref V00 RetBuf
***** BB02, stmt 5
[000042] ------------ * STMT void (IL ???... ???)
[000041] ------------ \--* RETURN void
------------ BB03 [023..031) (return), preds={} succs={}
***** BB03, stmt 6
[000023] ------------ * STMT void (IL 0x023...0x030)
[000018] S-C-G------- \--* CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
[000021] ------------ arg0 +--* LCL_VAR byref V00 RetBuf
[000015] ------------ arg1 +--* FIELD ushort value
[000014] L----------- | \--* ADDR byref
[000013] ------------ | \--* LCL_VAR struct V02 loc0
[000017] L----------- arg2 \--* ADDR byref
[000016] ------------ \--* LCL_VAR struct V02 loc0
***** BB03, stmt 7
[000025] ------------ * STMT void (IL ???... ???)
[000024] ------------ \--* RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** After fgAddInternal()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i
BB02 [0001] 1 1 [00F..023) (return) i
BB03 [0002] 1 1 [023..031) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** In fgCloneFinally()
No EH in this method, no cloning.
*************** In fgPromoteStructs()
promotion opt flag not enabled
*************** In fgMarkAddressExposedLocals()
LocalAddressVisitor visiting statement:
[000006] ------------ * STMT void (IL 0x000...0x003)
[000003] ------------ | /--* LCL_VAR ushort V01 arg0
[000005] -A---------- \--* ASG ushort
[000004] -------N---- \--* FIELD ushort value
[000002] L----------- \--* ADDR byref
[000001] ------------ \--* LCL_VAR struct V02 loc0
LocalAddressVisitor visiting statement:
[000011] ------------ * STMT void (IL 0x008...0x00D)
[000010] ------------ \--* JTRUE void
[000008] ------------ | /--* CNS_INT int 0
[000009] ------------ \--* EQ int
[000007] ------------ \--* CNS_INT int 1
LocalAddressVisitor visiting statement:
[000034] ------------ * STMT void (IL 0x00F...0x01A)
[000030] ------------ | /--* HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
[000029] ------------ | | \--* FIELD ushort value
[000028] L----------- | | \--* ADDR byref
[000027] ------------ | | \--* LCL_VAR struct V02 loc0
[000033] -A---------- \--* ASG simd16 (copy)
[000031] D----------- \--* LCL_VAR simd16 V03 loc1
LocalAddressVisitor visiting statement:
[000040] ------------ * STMT void (IL 0x01B...0x022)
[000035] ------------ | /--* LCL_VAR simd16 V03 loc1
[000039] -A---------- \--* ASG simd16 (copy)
[000038] ------------ \--* BLK(16) simd16
[000037] ------------ \--* LCL_VAR byref V00 RetBuf
LocalAddressVisitor visiting statement:
[000042] ------------ * STMT void (IL ???... ???)
[000041] ------------ \--* RETURN void
LocalAddressVisitor visiting statement:
[000023] ------------ * STMT void (IL 0x023...0x030)
[000018] S-C-G------- \--* CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
[000021] ------------ arg0 +--* LCL_VAR byref V00 RetBuf
[000015] ------------ arg1 +--* FIELD ushort value
[000014] L----------- | \--* ADDR byref
[000013] ------------ | \--* LCL_VAR struct V02 loc0
[000017] L----------- arg2 \--* ADDR byref
[000016] ------------ \--* LCL_VAR struct V02 loc0
Local V02 should not be enregistered because: it is address exposed
LocalAddressVisitor visiting statement:
[000025] ------------ * STMT void (IL ???... ???)
[000024] ------------ \--* RETURN void
*************** In fgMorphBlocks()
Morphing BB01 of 'System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct'
fgMorphTree BB01, stmt 1 (before)
[000003] ------------ /--* LCL_VAR ushort V01 arg0
[000005] -A---------- * ASG ushort
[000004] -------N---- \--* FIELD ushort value
[000002] L----------- \--* ADDR byref
[000001] ------------ \--* LCL_VAR struct(AX) V02 loc0
Local V02 should not be enregistered because: was accessed as a local field
fgMorphTree BB01, stmt 1 (after)
[000043] -----+------ /--* CAST int <- ushort <- int
[000003] -----+------ | \--* LCL_VAR int V01 arg0
[000005] -A--G+------ * ASG ushort
[000001] D---G+-N---- \--* LCL_FLD ushort V02 loc0 [+0] Fseq[value]
fgMorphTree BB01, stmt 2 (before)
[000010] ------------ * JTRUE void
[000008] ------------ | /--* CNS_INT int 0
[000009] ------------ \--* EQ int
[000007] ------------ \--* CNS_INT int 1
Morphing BB02 of 'System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct'
fgMorphTree BB02, stmt 3 (before)
[000030] ------------ /--* HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
[000029] ------------ | \--* FIELD ushort value
[000028] L----------- | \--* ADDR byref
[000027] ------------ | \--* LCL_VAR struct(AX) V02 loc0
[000033] -A---------- * ASG simd16 (copy)
[000031] D----------- \--* LCL_VAR simd16 V03 loc1
Local V02 should not be enregistered because: was accessed as a local field
fgMorphCopyBlock:block assignment to morph:
[000030] ----G+------ /--* HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
[000027] ----G+------ | \--* LCL_FLD ushort V02 loc0 [+0] Fseq[value]
[000033] -A--G------- * ASG simd16 (copy)
[000031] D----+-N---- \--* LCL_VAR simd16 V03 loc1
with no promoted structs this requires a CopyBlock.
Local V03 should not be enregistered because: written in a block op
fgMorphTree BB02, stmt 3 (after)
[000030] ----G+------ /--* HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
[000027] ----G+------ | \--* LCL_FLD ushort V02 loc0 [+0] Fseq[value]
[000033] -A--G+------ * ASG simd16 (copy)
[000031] D----+-N---- \--* LCL_VAR simd16 V03 loc1
fgMorphTree BB02, stmt 4 (before)
[000035] ------------ /--* LCL_VAR simd16 V03 loc1
[000039] -A---------- * ASG simd16 (copy)
[000038] ------------ \--* BLK(16) simd16
[000037] ------------ \--* LCL_VAR byref V00 RetBuf
fgMorphCopyBlock:fgMorphOneAsgBlock (after):
[000035] -----+------ /--* LCL_VAR simd16 V03 loc1
[000039] -A-XG------- * ASG simd16 (copy)
[000038] *--XG+-N---- \--* IND simd16
[000037] -----+------ \--* LCL_VAR byref V00 RetBuf
using oneAsgTree.
fgMorphCopyBlock (after):
[000035] -----+------ /--* LCL_VAR simd16 V03 loc1
[000039] -A-XG------- * ASG simd16 (copy)
[000038] *--XG+-N---- \--* IND simd16
[000037] -----+------ \--* LCL_VAR byref V00 RetBuf
fgMorphTree BB02, stmt 4 (after)
[000035] -----+------ /--* LCL_VAR simd16 V03 loc1
[000039] -A-XG+------ * ASG simd16 (copy)
[000038] *--XG+-N---- \--* IND simd16
[000037] -----+------ \--* LCL_VAR byref V00 RetBuf
fgMorphTree BB02, stmt 5 (before)
[000041] ------------ * RETURN void
Morphing BB03 of 'System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct'
fgMorphTree BB03, stmt 6 (before)
[000018] S-C-G------- * CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
[000021] ------------ arg0 +--* LCL_VAR byref V00 RetBuf
[000015] ------------ arg1 +--* FIELD ushort value
[000014] L----------- | \--* ADDR byref
[000013] ------------ | \--* LCL_VAR struct(AX) V02 loc0
[000017] L----------- arg2 \--* ADDR byref
[000016] ------------ \--* LCL_VAR struct(AX) V02 loc0
Initializing arg info for 18.CALL:
fgArgTabEntry[arg 0 21.LCL_VAR, 1 reg: ecx, align=1]
fgArgTabEntry[arg 1 15.FIELD, 1 reg: edx, align=1]
fgArgTabEntry[arg 2 17.ADDR, numSlots=1, slotNum=0, align=1]
Morphing args for 18.CALL:
Local V02 should not be enregistered because: was accessed as a local field
Sorting the arguments:
Deferred argument ('ecx'):
[000021] -----+------ * LCL_VAR byref V00 RetBuf
Replaced with placeholder node:
[000044] ----------L- * ARGPLACE byref
Deferred argument ('edx'):
[000013] ----G+------ * LCL_FLD ushort V02 loc0 [+0] Fseq[value]
Replaced with placeholder node:
[000046] ----------L- * ARGPLACE ushort
Shuffled argument table: ecx edx
fgArgTabEntry[arg 2 17.ADDR, numSlots=1, slotNum=0, align=1, processed]
fgArgTabEntry[arg 0 21.LCL_VAR, 1 reg: ecx, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 1 13.LCL_FLD, 1 reg: edx, align=1, lateArgInx=1, processed]
fgMorphTree BB03, stmt 6 (after)
[000018] S-CXG+------ * CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
[000017] L----+------ arg2 on STK +--* ADDR int
[000016] ----G+-N---- | \--* LCL_VAR struct(AX) V02 loc0
[000021] -----+------ arg0 in ecx +--* LCL_VAR byref V00 RetBuf
[000013] ----G+------ arg1 in edx \--* LCL_FLD ushort V02 loc0 [+0] Fseq[value]
fgMorphTree BB03, stmt 7 (before)
[000024] ------------ * RETURN void
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i
BB02 [0001] 1 1 [00F..023) (return) i
BB03 [0002] 1 1 [023..031) (return) i gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
*************** In fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i
BB02 [0001] 1 1 [00F..023) (return) i
BB03 [0002] 1 1 [023..031) (return) i gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [00F..023) (return) i
BB03 [0002] 1 BB01 1 [023..031) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeBlockAndEdgeWeights()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [00F..023) (return) i
BB03 [0002] 1 BB01 1 [023..031) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
-- not optimizing, so not computing edge weights
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*************** In fgFindOperOrder()
*************** In fgSetBlockOrder()
The biggest BB has 12 tree nodes
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [00F..023) (return) i
BB03 [0002] 1 BB01 1 [023..031) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 9, 10) [000006] ------------ * STMT void (IL 0x000...0x003)
N002 ( 4, 4) [000043] ------------ | /--* CAST int <- ushort <- int
N001 ( 3, 2) [000003] ------------ | | \--* LCL_VAR int V01 arg0
N004 ( 9, 10) [000005] -A--G---R--- \--* ASG ushort
N003 ( 4, 5) [000001] D---G--N---- \--* LCL_FLD ushort V02 loc0 [+0] Fseq[value]
***** BB01, stmt 2
( 5, 5) [000011] ------------ * STMT void (IL 0x008...0x00D)
N004 ( 5, 5) [000010] ------------ \--* JTRUE void
N002 ( 1, 1) [000007] ------------ | /--* CNS_INT int 1
N003 ( 3, 3) [000009] J------N---- \--* EQ int
N001 ( 1, 1) [000008] ------------ \--* CNS_INT int 0
------------ BB02 [00F..023) (return), preds={BB01} succs={}
***** BB02, stmt 3
( 9, 9) [000034] ------------ * STMT void (IL 0x00F...0x01A)
N002 ( 5, 6) [000030] ----G------- | /--* HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
N001 ( 4, 5) [000027] ----G------- | | \--* LCL_FLD ushort V02 loc0 [+0] Fseq[value]
N004 ( 9, 9) [000033] -A--G---R--- \--* ASG simd16 (copy)
N003 ( 3, 2) [000031] D------N---- \--* LCL_VAR simd16 V03 loc1
***** BB02, stmt 4
( 10, 7) [000040] ------------ * STMT void (IL 0x01B...0x022)
N003 ( 3, 2) [000035] ------------ | /--* LCL_VAR simd16 V03 loc1
N004 ( 10, 7) [000039] -A-XG------- \--* ASG simd16 (copy)
N002 ( 6, 4) [000038] *--XG--N---- \--* IND simd16
N001 ( 3, 2) [000037] ------------ \--* LCL_VAR byref V00 RetBuf
***** BB02, stmt 5
( 0, 0) [000042] ------------ * STMT void (IL ???... ???)
N001 ( 0, 0) [000041] ------------ \--* RETURN void
------------ BB03 [023..031) (return), preds={BB01} succs={}
***** BB03, stmt 6
( 27, 17) [000023] ------------ * STMT void (IL 0x023...0x030)
N012 ( 27, 17) [000018] S-CXG------- \--* CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
N004 ( 3, 3) [000017] L----------- arg2 on STK +--* ADDR int
N003 ( 3, 2) [000016] ----G--N---- | \--* LCL_VAR struct(AX) V02 loc0
N008 ( 3, 2) [000021] ------------ arg0 in ecx +--* LCL_VAR byref V00 RetBuf
N009 ( 4, 5) [000013] ----G------- arg1 in edx \--* LCL_FLD ushort V02 loc0 [+0] Fseq[value]
***** BB03, stmt 7
( 0, 0) [000025] ------------ * STMT void (IL ???... ???)
N001 ( 0, 0) [000024] ------------ \--* RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** In IR Rationalize
Trees before IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i label target
BB02 [0001] 1 BB01 1 [00F..023) (return) i
BB03 [0002] 1 BB01 1 [023..031) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
***** BB01, stmt 1
( 9, 10) [000006] ------------ * STMT void (IL 0x000...0x003)
N002 ( 4, 4) [000043] ------------ | /--* CAST int <- ushort <- int
N001 ( 3, 2) [000003] ------------ | | \--* LCL_VAR int V01 arg0
N004 ( 9, 10) [000005] -A--G---R--- \--* ASG ushort
N003 ( 4, 5) [000001] D---G--N---- \--* LCL_FLD ushort V02 loc0 [+0] Fseq[value]
***** BB01, stmt 2
( 5, 5) [000011] ------------ * STMT void (IL 0x008...0x00D)
N004 ( 5, 5) [000010] ------------ \--* JTRUE void
N002 ( 1, 1) [000007] ------------ | /--* CNS_INT int 1
N003 ( 3, 3) [000009] J------N---- \--* EQ int
N001 ( 1, 1) [000008] ------------ \--* CNS_INT int 0
------------ BB02 [00F..023) (return), preds={BB01} succs={}
***** BB02, stmt 3
( 9, 9) [000034] ------------ * STMT void (IL 0x00F...0x01A)
N002 ( 5, 6) [000030] ----G------- | /--* HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
N001 ( 4, 5) [000027] ----G------- | | \--* LCL_FLD ushort V02 loc0 [+0] Fseq[value]
N004 ( 9, 9) [000033] -A--G---R--- \--* ASG simd16 (copy)
N003 ( 3, 2) [000031] D------N---- \--* LCL_VAR simd16 V03 loc1
***** BB02, stmt 4
( 10, 7) [000040] ------------ * STMT void (IL 0x01B...0x022)
N003 ( 3, 2) [000035] ------------ | /--* LCL_VAR simd16 V03 loc1
N004 ( 10, 7) [000039] -A-XG------- \--* ASG simd16 (copy)
N002 ( 6, 4) [000038] *--XG--N---- \--* IND simd16
N001 ( 3, 2) [000037] ------------ \--* LCL_VAR byref V00 RetBuf
***** BB02, stmt 5
( 0, 0) [000042] ------------ * STMT void (IL ???... ???)
N001 ( 0, 0) [000041] ------------ \--* RETURN void
------------ BB03 [023..031) (return), preds={BB01} succs={}
***** BB03, stmt 6
( 27, 17) [000023] ------------ * STMT void (IL 0x023...0x030)
N012 ( 27, 17) [000018] S-CXG------- \--* CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
N004 ( 3, 3) [000017] L----------- arg2 on STK +--* ADDR int
N003 ( 3, 2) [000016] ----G--N---- | \--* LCL_VAR struct(AX) V02 loc0
N008 ( 3, 2) [000021] ------------ arg0 in ecx +--* LCL_VAR byref V00 RetBuf
N009 ( 4, 5) [000013] ----G------- arg1 in edx \--* LCL_FLD ushort V02 loc0 [+0] Fseq[value]
***** BB03, stmt 7
( 0, 0) [000025] ------------ * STMT void (IL ???... ???)
N001 ( 0, 0) [000024] ------------ \--* RETURN void
-------------------------------------------------------------------------------------------------------------------
rewriting asg(LCL_FLD, X) to STORE_LCL_FLD(X)
N004 ( 9, 10) [000005] DA--G------- * STORE_LCL_FLD ushort V02 loc0 [+0] Fseq[value]
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N004 ( 9, 9) [000033] DA--G------- * STORE_LCL_VAR simd16 V03 loc1
Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR:
N003 ( 3, 2) [000016] -------N---- t16 = LCL_VAR_ADDR byref V02 loc0
*************** Exiting IR Rationalize
Trees after IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [00F..023) (return) i LIR
BB03 [0002] 1 BB01 1 [023..031) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
( 9, 10) [000006] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V01 arg0
/--* t3 int
N002 ( 4, 4) [000043] ------------ t43 = * CAST int <- ushort <- int
/--* t43 int
N004 ( 9, 10) [000005] DA--G------- * STORE_LCL_FLD ushort V02 loc0 [+0] Fseq[value]
( 5, 5) [000011] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000008] ------------ t8 = CNS_INT int 0
N002 ( 1, 1) [000007] ------------ t7 = CNS_INT int 1
/--* t8 int
+--* t7 int
N003 ( 3, 3) [000009] J------N---- t9 = * EQ int
/--* t9 int
N004 ( 5, 5) [000010] ------------ * JTRUE void
------------ BB02 [00F..023) (return), preds={BB01} succs={}
( 9, 9) [000034] ------------ IL_OFFSET void IL offset: 0xf
N001 ( 4, 5) [000027] ------------ t27 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t27 ushort
N002 ( 5, 6) [000030] ----G------- t30 = * HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
/--* t30 simd16
N004 ( 9, 9) [000033] DA--G------- * STORE_LCL_VAR simd16 V03 loc1
( 10, 7) [000040] ------------ IL_OFFSET void IL offset: 0x1b
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 RetBuf
N003 ( 3, 2) [000035] ------------ t35 = LCL_VAR simd16 V03 loc1
/--* t37 byref
+--* t35 simd16
[000048] -A-XG------- * STOREIND simd16
N001 ( 0, 0) [000041] ------------ RETURN void
------------ BB03 [023..031) (return), preds={BB01} succs={}
( 27, 17) [000023] ------------ IL_OFFSET void IL offset: 0x23
N003 ( 3, 2) [000016] -------N---- t16 = LCL_VAR_ADDR byref V02 loc0
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR byref V00 RetBuf
N009 ( 4, 5) [000013] ------------ t13 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t16 byref arg2 on STK
+--* t21 byref arg0 in ecx
+--* t13 ushort arg1 in edx
N012 ( 27, 17) [000018] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
N001 ( 0, 0) [000024] ------------ RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckBBlist
*************** In Lowering
Trees before Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [00F..023) (return) i LIR
BB03 [0002] 1 BB01 1 [023..031) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
( 9, 10) [000006] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V01 arg0
/--* t3 int
N002 ( 4, 4) [000043] ------------ t43 = * CAST int <- ushort <- int
/--* t43 int
N004 ( 9, 10) [000005] DA--G------- * STORE_LCL_FLD ushort V02 loc0 [+0] Fseq[value]
( 5, 5) [000011] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000008] ------------ t8 = CNS_INT int 0
N002 ( 1, 1) [000007] ------------ t7 = CNS_INT int 1
/--* t8 int
+--* t7 int
N003 ( 3, 3) [000009] J------N---- t9 = * EQ int
/--* t9 int
N004 ( 5, 5) [000010] ------------ * JTRUE void
------------ BB02 [00F..023) (return), preds={BB01} succs={}
( 9, 9) [000034] ------------ IL_OFFSET void IL offset: 0xf
N001 ( 4, 5) [000027] ------------ t27 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t27 ushort
N002 ( 5, 6) [000030] ----G------- t30 = * HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
/--* t30 simd16
N004 ( 9, 9) [000033] DA--G------- * STORE_LCL_VAR simd16 V03 loc1
( 10, 7) [000040] ------------ IL_OFFSET void IL offset: 0x1b
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 RetBuf
N003 ( 3, 2) [000035] ------------ t35 = LCL_VAR simd16 V03 loc1
/--* t37 byref
+--* t35 simd16
[000048] -A-XG------- * STOREIND simd16
N001 ( 0, 0) [000041] ------------ RETURN void
------------ BB03 [023..031) (return), preds={BB01} succs={}
( 27, 17) [000023] ------------ IL_OFFSET void IL offset: 0x23
N003 ( 3, 2) [000016] -------N---- t16 = LCL_VAR_ADDR byref V02 loc0
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR byref V00 RetBuf
N009 ( 4, 5) [000013] ------------ t13 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t16 byref arg2 on STK
+--* t21 byref arg0 in ecx
+--* t13 ushort arg1 in edx
N012 ( 27, 17) [000018] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
N001 ( 0, 0) [000024] ------------ RETURN void
-------------------------------------------------------------------------------------------------------------------
No addressing mode:
N001 ( 3, 2) [000037] ------------ * LCL_VAR byref V00 RetBuf
Lower of StoreInd didn't mark the node as self contained for reason: 4
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 RetBuf
N003 ( 3, 2) [000035] ------------ t35 = LCL_VAR simd16 V03 loc1
/--* t37 byref
+--* t35 simd16
[000048] -A-XG------- * STOREIND simd16
lowering GT_RETURN
N001 ( 0, 0) [000041] ------------ * RETURN void
============lowering call (before):
N003 ( 3, 2) [000016] -------N---- t16 = LCL_VAR_ADDR byref V02 loc0
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR byref V00 RetBuf
N009 ( 4, 5) [000013] ------------ t13 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t16 byref arg2 on STK
+--* t21 byref arg0 in ecx
+--* t13 ushort arg1 in edx
N012 ( 27, 17) [000018] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000044] ----------L- * ARGPLACE byref
lowering arg : N002 ( 0, 0) [000046] ----------L- * ARGPLACE ushort
lowering arg : N003 ( 3, 2) [000016] -------N---- * LCL_VAR_ADDR byref V02 loc0
new node is : [000049] ------------ * PUTARG_STK [+0x00] void (1 slots)
late:
======
lowering arg : N008 ( 3, 2) [000021] ------------ * LCL_VAR byref V00 RetBuf
new node is : [000050] ------------ * PUTARG_REG byref REG ecx
lowering arg : N009 ( 4, 5) [000013] ------------ * LCL_FLD ushort V02 loc0 [+0] Fseq[value]
new node is : [000051] ------------ * PUTARG_REG int REG edx
lowering call (after):
N003 ( 3, 2) [000016] -------N---- t16 = LCL_VAR_ADDR byref V02 loc0
/--* t16 byref
[000049] ------------ * PUTARG_STK [+0x00] void (1 slots)
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR byref V00 RetBuf
/--* t21 byref
[000050] ------------ t50 = * PUTARG_REG byref REG ecx
N009 ( 4, 5) [000013] ------------ t13 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t13 ushort
[000051] ------------ t51 = * PUTARG_REG int REG edx
/--* t50 byref arg0 in ecx
+--* t51 int arg1 in edx
N012 ( 27, 17) [000018] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
lowering GT_RETURN
N001 ( 0, 0) [000024] ------------ * RETURN void
============Lower has completed modifying nodes.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [00F..023) (return) i LIR
BB03 [0002] 1 BB01 1 [023..031) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
( 9, 10) [000006] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V01 arg0
/--* t3 int
N002 ( 4, 4) [000043] ------------ t43 = * CAST int <- ushort <- int
/--* t43 int
N004 ( 9, 10) [000005] DA--G------- * STORE_LCL_FLD ushort V02 loc0 [+0] Fseq[value]
( 5, 5) [000011] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000008] ------------ t8 = CNS_INT int 0
N002 ( 1, 1) [000007] -c---------- t7 = CNS_INT int 1
/--* t8 int
+--* t7 int
N003 ( 3, 3) [000009] J------N---- * EQ void
N004 ( 5, 5) [000010] ------------ * JTRUE void
------------ BB02 [00F..023) (return), preds={BB01} succs={}
( 9, 9) [000034] ------------ IL_OFFSET void IL offset: 0xf
N001 ( 4, 5) [000027] -c---------- t27 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t27 ushort
N002 ( 5, 6) [000030] ----G------- t30 = * HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
/--* t30 simd16
N004 ( 9, 9) [000033] DA--G------- * STORE_LCL_VAR simd16 V03 loc1
( 10, 7) [000040] ------------ IL_OFFSET void IL offset: 0x1b
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 RetBuf
N003 ( 3, 2) [000035] ------------ t35 = LCL_VAR simd16 V03 loc1
/--* t37 byref
+--* t35 simd16
[000048] -A-XG------- * STOREIND simd16
N001 ( 0, 0) [000041] ------------ RETURN void
------------ BB03 [023..031) (return), preds={BB01} succs={}
( 27, 17) [000023] ------------ IL_OFFSET void IL offset: 0x23
N003 ( 3, 2) [000016] -------N---- t16 = LCL_VAR_ADDR byref V02 loc0
/--* t16 byref
[000049] ------------ * PUTARG_STK [+0x00] void (1 slots)
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR byref V00 RetBuf
/--* t21 byref
[000050] ------------ t50 = * PUTARG_REG byref REG ecx
N009 ( 4, 5) [000013] ------------ t13 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t13 ushort
[000051] ------------ t51 = * PUTARG_REG int REG edx
/--* t50 byref arg0 in ecx
+--* t51 int arg1 in edx
N012 ( 27, 17) [000018] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
N001 ( 0, 0) [000024] ------------ RETURN void
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 RetBuf byref
; V01 arg0 ushort
; V02 loc0 struct ( 4) do-not-enreg[XSF] addr-exposed ld-addr-op
; V03 loc1 simd16 do-not-enreg[SB] ld-addr-op
In fgLocalVarLivenessInit
*************** In fgPerBlockLocalVarLiveness()
*************** In fgInterBlockLocalVarLiveness()
*** lvaComputeRefCounts ***
Liveness pass finished after lowering, IR:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [00F..023) (return) i LIR
BB03 [0002] 1 BB01 1 [023..031) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
( 9, 10) [000006] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V01 arg0
/--* t3 int
N002 ( 4, 4) [000043] ------------ t43 = * CAST int <- ushort <- int
/--* t43 int
N004 ( 9, 10) [000005] DA--G------- * STORE_LCL_FLD ushort V02 loc0 [+0] Fseq[value]
( 5, 5) [000011] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000008] ------------ t8 = CNS_INT int 0
N002 ( 1, 1) [000007] -c---------- t7 = CNS_INT int 1
/--* t8 int
+--* t7 int
N003 ( 3, 3) [000009] J------N---- * EQ void
N004 ( 5, 5) [000010] ------------ * JTRUE void
------------ BB02 [00F..023) (return), preds={BB01} succs={}
( 9, 9) [000034] ------------ IL_OFFSET void IL offset: 0xf
N001 ( 4, 5) [000027] -c---------- t27 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t27 ushort
N002 ( 5, 6) [000030] ----G------- t30 = * HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
/--* t30 simd16
N004 ( 9, 9) [000033] DA--G------- * STORE_LCL_VAR simd16 V03 loc1
( 10, 7) [000040] ------------ IL_OFFSET void IL offset: 0x1b
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 RetBuf
N003 ( 3, 2) [000035] ------------ t35 = LCL_VAR simd16 V03 loc1
/--* t37 byref
+--* t35 simd16
[000048] -A-XG------- * STOREIND simd16
N001 ( 0, 0) [000041] ------------ RETURN void
------------ BB03 [023..031) (return), preds={BB01} succs={}
( 27, 17) [000023] ------------ IL_OFFSET void IL offset: 0x23
N003 ( 3, 2) [000016] -------N---- t16 = LCL_VAR_ADDR byref V02 loc0
/--* t16 byref
[000049] ------------ * PUTARG_STK [+0x00] void (1 slots)
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR byref V00 RetBuf
/--* t21 byref
[000050] ------------ t50 = * PUTARG_REG byref REG ecx
N009 ( 4, 5) [000013] ------------ t13 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t13 ushort
[000051] ------------ t51 = * PUTARG_REG int REG edx
/--* t50 byref arg0 in ecx
+--* t51 int arg1 in edx
N012 ( 27, 17) [000018] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
N001 ( 0, 0) [000024] ------------ RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Lowering
Trees after Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [00F..023) (return) i LIR
BB03 [0002] 1 BB01 1 [023..031) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
( 9, 10) [000006] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V01 arg0
/--* t3 int
N002 ( 4, 4) [000043] ------------ t43 = * CAST int <- ushort <- int
/--* t43 int
N004 ( 9, 10) [000005] DA--G------- * STORE_LCL_FLD ushort V02 loc0 [+0] Fseq[value]
( 5, 5) [000011] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000008] ------------ t8 = CNS_INT int 0
N002 ( 1, 1) [000007] -c---------- t7 = CNS_INT int 1
/--* t8 int
+--* t7 int
N003 ( 3, 3) [000009] J------N---- * EQ void
N004 ( 5, 5) [000010] ------------ * JTRUE void
------------ BB02 [00F..023) (return), preds={BB01} succs={}
( 9, 9) [000034] ------------ IL_OFFSET void IL offset: 0xf
N001 ( 4, 5) [000027] -c---------- t27 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t27 ushort
N002 ( 5, 6) [000030] ----G------- t30 = * HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
/--* t30 simd16
N004 ( 9, 9) [000033] DA--G------- * STORE_LCL_VAR simd16 V03 loc1
( 10, 7) [000040] ------------ IL_OFFSET void IL offset: 0x1b
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 RetBuf
N003 ( 3, 2) [000035] ------------ t35 = LCL_VAR simd16 V03 loc1
/--* t37 byref
+--* t35 simd16
[000048] -A-XG------- * STOREIND simd16
N001 ( 0, 0) [000041] ------------ RETURN void
------------ BB03 [023..031) (return), preds={BB01} succs={}
( 27, 17) [000023] ------------ IL_OFFSET void IL offset: 0x23
N003 ( 3, 2) [000016] -------N---- t16 = LCL_VAR_ADDR byref V02 loc0
/--* t16 byref
[000049] ------------ * PUTARG_STK [+0x00] void (1 slots)
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR byref V00 RetBuf
/--* t21 byref
[000050] ------------ t50 = * PUTARG_REG byref REG ecx
N009 ( 4, 5) [000013] ------------ t13 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t13 ushort
[000051] ------------ t51 = * PUTARG_REG int REG edx
/--* t50 byref arg0 in ecx
+--* t51 int arg1 in edx
N012 ( 27, 17) [000018] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
N001 ( 0, 0) [000024] ------------ RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In StackLevelSetter
Trees before StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [00F..023) (return) i LIR
BB03 [0002] 1 BB01 1 [023..031) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
( 9, 10) [000006] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V01 arg0
/--* t3 int
N002 ( 4, 4) [000043] ------------ t43 = * CAST int <- ushort <- int
/--* t43 int
N004 ( 9, 10) [000005] DA--G------- * STORE_LCL_FLD ushort V02 loc0 [+0] Fseq[value]
( 5, 5) [000011] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000008] ------------ t8 = CNS_INT int 0
N002 ( 1, 1) [000007] -c---------- t7 = CNS_INT int 1
/--* t8 int
+--* t7 int
N003 ( 3, 3) [000009] J------N---- * EQ void
N004 ( 5, 5) [000010] ------------ * JTRUE void
------------ BB02 [00F..023) (return), preds={BB01} succs={}
( 9, 9) [000034] ------------ IL_OFFSET void IL offset: 0xf
N001 ( 4, 5) [000027] -c---------- t27 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t27 ushort
N002 ( 5, 6) [000030] ----G------- t30 = * HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
/--* t30 simd16
N004 ( 9, 9) [000033] DA--G------- * STORE_LCL_VAR simd16 V03 loc1
( 10, 7) [000040] ------------ IL_OFFSET void IL offset: 0x1b
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 RetBuf
N003 ( 3, 2) [000035] ------------ t35 = LCL_VAR simd16 V03 loc1
/--* t37 byref
+--* t35 simd16
[000048] -A-XG------- * STOREIND simd16
N001 ( 0, 0) [000041] ------------ RETURN void
------------ BB03 [023..031) (return), preds={BB01} succs={}
( 27, 17) [000023] ------------ IL_OFFSET void IL offset: 0x23
N003 ( 3, 2) [000016] -------N---- t16 = LCL_VAR_ADDR byref V02 loc0
/--* t16 byref
[000049] ------------ * PUTARG_STK [+0x00] void (1 slots)
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR byref V00 RetBuf
/--* t21 byref
[000050] ------------ t50 = * PUTARG_REG byref REG ecx
N009 ( 4, 5) [000013] ------------ t13 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t13 ushort
[000051] ------------ t51 = * PUTARG_REG int REG edx
/--* t50 byref arg0 in ecx
+--* t51 int arg1 in edx
N012 ( 27, 17) [000018] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
N001 ( 0, 0) [000024] ------------ RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** Exiting StackLevelSetter
Trees after StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [00F..023) (return) i LIR
BB03 [0002] 1 BB01 1 [023..031) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
( 9, 10) [000006] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V01 arg0
/--* t3 int
N002 ( 4, 4) [000043] ------------ t43 = * CAST int <- ushort <- int
/--* t43 int
N004 ( 9, 10) [000005] DA--G------- * STORE_LCL_FLD ushort V02 loc0 [+0] Fseq[value]
( 5, 5) [000011] ------------ IL_OFFSET void IL offset: 0x8
N001 ( 1, 1) [000008] ------------ t8 = CNS_INT int 0
N002 ( 1, 1) [000007] -c---------- t7 = CNS_INT int 1
/--* t8 int
+--* t7 int
N003 ( 3, 3) [000009] J------N---- * EQ void
N004 ( 5, 5) [000010] ------------ * JTRUE void
------------ BB02 [00F..023) (return), preds={BB01} succs={}
( 9, 9) [000034] ------------ IL_OFFSET void IL offset: 0xf
N001 ( 4, 5) [000027] -c---------- t27 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t27 ushort
N002 ( 5, 6) [000030] ----G------- t30 = * HWIntrinsic simd16 uint ConvertScalarToVector128UInt32
/--* t30 simd16
N004 ( 9, 9) [000033] DA--G------- * STORE_LCL_VAR simd16 V03 loc1
( 10, 7) [000040] ------------ IL_OFFSET void IL offset: 0x1b
N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 RetBuf
N003 ( 3, 2) [000035] ------------ t35 = LCL_VAR simd16 V03 loc1
/--* t37 byref
+--* t35 simd16
[000048] -A-XG------- * STOREIND simd16
N001 ( 0, 0) [000041] ------------ RETURN void
------------ BB03 [023..031) (return), preds={BB01} succs={}
( 27, 17) [000023] ------------ IL_OFFSET void IL offset: 0x23
N003 ( 3, 2) [000016] -------N---- t16 = LCL_VAR_ADDR byref V02 loc0
/--* t16 byref
[000049] ------------ * PUTARG_STK [+0x00] void (1 slots)
N008 ( 3, 2) [000021] ------------ t21 = LCL_VAR byref V00 RetBuf
/--* t21 byref
[000050] ------------ t50 = * PUTARG_REG byref REG ecx
N009 ( 4, 5) [000013] ------------ t13 = LCL_FLD ushort V02 loc0 [+0] Fseq[value]
/--* t13 ushort
[000051] ------------ t51 = * PUTARG_REG int REG edx
/--* t50 byref arg0 in ecx
+--* t51 int arg1 in edx
N012 ( 27, 17) [000018] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
N001 ( 0, 0) [000024] ------------ RETURN void
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{}
{}
{}
{}
BB02 use def in out
{}
{}
{}
{}
BB03 use def in out
{}
{}
{}
{}
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 0, singleExit = 1
; Decided to create an EBP based frame for ETW stackwalking (Debug Code)
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 ) BB02( 1 ) BB03( 1 )
BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N000. IL_OFFSET IL offset: 0x0
N001. t3 = V01 MEM
N002. t43 = CAST ; t3
N004. V02 MEM; t43
N000. IL_OFFSET IL offset: 0x8
N001. t8 = CNS_INT 0
N002. CNS_INT 1
N003. EQ ; t8
N004. JTRUE
BB02 [00F..023) (return), preds={BB01} succs={}
=====
N000. IL_OFFSET IL offset: 0xf
N001. V02 MEM
N002. t30 = HWIntrinsic
N004. V03 MEM; t30
N000. IL_OFFSET IL offset: 0x1b
N001. t37 = V00 MEM
N003. t35 = V03 MEM
N000. STOREIND ; t37,t35
N001. RETURN
BB03 [023..031) (return), preds={BB01} succs={}
=====
N000. IL_OFFSET IL offset: 0x23
N003. t16 = LCL_VAR_ADDR V02 loc0
N000. PUTARG_STK [+0x00]; t16
N008. t21 = V00 MEM
N000. t50 = PUTARG_REG; t21
N009. t13 = V02 MEM
N000. t51 = PUTARG_REG; t13
N012. CALL ; t50,t51
N001. RETURN
buildIntervals second part ========
Int arg V00 in reg ecx
Int arg V01 in reg edx
NEW BLOCK BB01
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N002 ( 9, 10) [000006] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N004 ( 3, 2) [000003] ------------ * LCL_VAR int V01 arg0 NA REG NA
Interval 0: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #1 @5 RefTypeDef <Ivl:0> LCL_VAR BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N004.t3. LCL_VAR }
N006 ( 4, 4) [000043] ------------ * CAST int <- ushort <- int REG NA
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
Interval 1: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #3 @7 RefTypeDef <Ivl:1> CAST BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N006.t43. CAST }
N008 ( 9, 10) [000005] DA--G------- * STORE_LCL_FLD ushort V02 loc0 [+0] Fseq[value] NA REG NA
<RefPosition #4 @8 RefTypeUse <Ivl:1> BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N010 ( 5, 5) [000011] ------------ * IL_OFFSET void IL offset: 0x8 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N012 ( 1, 1) [000008] ------------ * CNS_INT int 0 REG NA
Interval 2: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #5 @13 RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 0 produce=1
DefList: { N012.t8. CNS_INT }
N014 ( 1, 1) [000007] -c---------- * CNS_INT int 1 REG NA
Contained
DefList: { N012.t8. CNS_INT }
N016 ( 3, 3) [000009] J------N---- * EQ void REG NA
<RefPosition #6 @16 RefTypeUse <Ivl:2> BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N018 ( 5, 5) [000010] ------------ * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
NEW BLOCK BB02
Setting BB02 as the predecessor for determining incoming variable registers of BB01
<RefPosition #7 @20 RefTypeBB BB02 regmask=[] minReg=1>
DefList: { }
N022 ( 9, 9) [000034] ------------ * IL_OFFSET void IL offset: 0xf REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N024 ( 4, 5) [000027] -c---------- * LCL_FLD ushort V02 loc0 [+0] Fseq[value] NA REG NA
Contained
DefList: { }
N026 ( 5, 6) [000030] ----G------- * HWIntrinsic simd16 uint ConvertScalarToVector128UInt32 REG NA
Interval 3: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #8 @27 RefTypeDef <Ivl:3> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N026.t30. HWIntrinsic }
N028 ( 9, 9) [000033] DA--G------- * STORE_LCL_VAR simd16 V03 loc1 NA REG NA
<RefPosition #9 @28 RefTypeUse <Ivl:3> BB02 regmask=[allFloat] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N030 ( 10, 7) [000040] ------------ * IL_OFFSET void IL offset: 0x1b REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N032 ( 3, 2) [000037] ------------ * LCL_VAR byref V00 RetBuf NA REG NA
Interval 4: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #10 @33 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N032.t37. LCL_VAR }
N034 ( 3, 2) [000035] ------------ * LCL_VAR simd16 V03 loc1 NA REG NA
Interval 5: RefPositions {} physReg:NA Preferences=[allFloat]
<RefPosition #11 @35 RefTypeDef <Ivl:5> LCL_VAR BB02 regmask=[allFloat] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N032.t37. LCL_VAR; N034.t35. LCL_VAR }
N036 (???,???) [000048] -A-XG------- * STOREIND simd16 REG NA
<RefPosition #12 @36 RefTypeUse <Ivl:4> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #13 @36 RefTypeUse <Ivl:5> BB02 regmask=[allFloat] minReg=1 last>
+<TreeNodeInfo 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=0
DefList: { }
N038 ( 0, 0) [000041] ------------ * RETURN void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
NEW BLOCK BB03
Setting BB03 as the predecessor for determining incoming variable registers of BB01
<RefPosition #14 @40 RefTypeBB BB03 regmask=[] minReg=1>
DefList: { }
N042 ( 27, 17) [000023] ------------ * IL_OFFSET void IL offset: 0x23 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N044 ( 3, 2) [000016] -------N---- * LCL_VAR_ADDR byref V02 loc0 NA REG NA
Interval 6: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #15 @45 RefTypeDef <Ivl:6> LCL_VAR_ADDR BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N044.t16. LCL_VAR_ADDR }
N046 (???,???) [000049] ------------ * PUTARG_STK [+0x00] void (1 slots) REG NA
<RefPosition #16 @46 RefTypeUse <Ivl:6> BB03 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N048 ( 3, 2) [000021] ------------ * LCL_VAR byref V00 RetBuf NA REG NA
Interval 7: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #17 @49 RefTypeDef <Ivl:7> LCL_VAR BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N048.t21. LCL_VAR }
N050 (???,???) [000050] ------------ * PUTARG_REG byref REG ecx
<RefPosition #18 @50 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #19 @50 RefTypeUse <Ivl:7> BB03 regmask=[ecx] minReg=1 last fixed>
Interval 8: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #20 @51 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #21 @51 RefTypeDef <Ivl:8> PUTARG_REG BB03 regmask=[ecx] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N050.t50. PUTARG_REG }
N052 ( 4, 5) [000013] ------------ * LCL_FLD ushort V02 loc0 [+0] Fseq[value] NA REG NA
Interval 9: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #22 @53 RefTypeDef <Ivl:9> LCL_FLD BB03 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N050.t50. PUTARG_REG; N052.t13. LCL_FLD }
N054 (???,???) [000051] ------------ * PUTARG_REG int REG edx
<RefPosition #23 @54 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #24 @54 RefTypeUse <Ivl:9> BB03 regmask=[edx] minReg=1 last fixed>
Interval 10: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #25 @55 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #26 @55 RefTypeDef <Ivl:10> PUTARG_REG BB03 regmask=[edx] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N050.t50. PUTARG_REG; N054.t51. PUTARG_REG }
N056 ( 27, 17) [000018] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
<RefPosition #27 @56 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #28 @56 RefTypeUse <Ivl:8> BB03 regmask=[ecx] minReg=1 last fixed>
<RefPosition #29 @56 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #30 @56 RefTypeUse <Ivl:10> BB03 regmask=[edx] minReg=1 last fixed>
<RefPosition #31 @57 RefTypeKill <Reg:eax> BB03 regmask=[eax] minReg=1>
<RefPosition #32 @57 RefTypeKill <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #33 @57 RefTypeKill <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #34 @57 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1>
<RefPosition #35 @57 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1>
<RefPosition #36 @57 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1>
<RefPosition #37 @57 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1>
<RefPosition #38 @57 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1>
<RefPosition #39 @57 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1>
<RefPosition #40 @57 RefTypeKill <Reg:mm6> BB03 regmask=[mm6] minReg=1>
<RefPosition #41 @57 RefTypeKill <Reg:mm7> BB03 regmask=[mm7] minReg=1>
+<TreeNodeInfo 0=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=0
DefList: { }
N058 ( 0, 0) [000024] ------------ * RETURN void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#3@7 #4@8} physReg:NA Preferences=[allInt]
Interval 2: (constant) RefPositions {#5@13 #6@16} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {#8@27 #9@28} physReg:NA Preferences=[allFloat]
Interval 4: RefPositions {#10@33 #12@36} physReg:NA Preferences=[allInt]
Interval 5: RefPositions {#11@35 #13@36} physReg:NA Preferences=[allFloat]
Interval 6: RefPositions {#15@45 #16@46} physReg:NA Preferences=[allInt]
Interval 7: RefPositions {#17@49 #19@50} physReg:NA Preferences=[ecx]
Interval 8: RefPositions {#21@51 #28@56} physReg:NA Preferences=[ecx]
Interval 9: RefPositions {#22@53 #24@54} physReg:NA Preferences=[edx]
Interval 10: RefPositions {#26@55 #30@56} physReg:NA Preferences=[edx]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #3 @7 RefTypeDef <Ivl:1> CAST BB01 regmask=[allInt] minReg=1>
<RefPosition #4 @8 RefTypeUse <Ivl:1> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #5 @13 RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #6 @16 RefTypeUse <Ivl:2> BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #7 @20 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #8 @27 RefTypeDef <Ivl:3> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #9 @28 RefTypeUse <Ivl:3> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #10 @33 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #11 @35 RefTypeDef <Ivl:5> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #12 @36 RefTypeUse <Ivl:4> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #13 @36 RefTypeUse <Ivl:5> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #14 @40 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #15 @45 RefTypeDef <Ivl:6> LCL_VAR_ADDR BB03 regmask=[allInt] minReg=1>
<RefPosition #16 @46 RefTypeUse <Ivl:6> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #17 @49 RefTypeDef <Ivl:7> LCL_VAR BB03 regmask=[ecx] minReg=1>
<RefPosition #18 @50 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #19 @50 RefTypeUse <Ivl:7> BB03 regmask=[ecx] minReg=1 last fixed>
<RefPosition #20 @51 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #21 @51 RefTypeDef <Ivl:8> PUTARG_REG BB03 regmask=[ecx] minReg=1 fixed>
<RefPosition #22 @53 RefTypeDef <Ivl:9> LCL_FLD BB03 regmask=[edx] minReg=1>
<RefPosition #23 @54 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #24 @54 RefTypeUse <Ivl:9> BB03 regmask=[edx] minReg=1 last fixed>
<RefPosition #25 @55 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #26 @55 RefTypeDef <Ivl:10> PUTARG_REG BB03 regmask=[edx] minReg=1 fixed>
<RefPosition #27 @56 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #28 @56 RefTypeUse <Ivl:8> BB03 regmask=[ecx] minReg=1 last fixed>
<RefPosition #29 @56 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #30 @56 RefTypeUse <Ivl:10> BB03 regmask=[edx] minReg=1 last fixed>
<RefPosition #31 @57 RefTypeKill <Reg:eax> BB03 regmask=[eax] minReg=1 last>
<RefPosition #32 @57 RefTypeKill <Reg:ecx> BB03 regmask=[ecx] minReg=1 last>
<RefPosition #33 @57 RefTypeKill <Reg:edx> BB03 regmask=[edx] minReg=1 last>
<RefPosition #34 @57 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
<RefPosition #35 @57 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
<RefPosition #36 @57 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
<RefPosition #37 @57 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
<RefPosition #38 @57 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
<RefPosition #39 @57 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
<RefPosition #40 @57 RefTypeKill <Reg:mm6> BB03 regmask=[mm6] minReg=1 last>
<RefPosition #41 @57 RefTypeKill <Reg:mm7> BB03 regmask=[mm7] minReg=1 last>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:
BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N002. IL_OFFSET IL offset: 0x0 REG NA
N004. V01 MEM
Def:<I0>(#1)
N006. CAST
Use:<I0>(#2) *
Def:<I1>(#3)
N008. V02 MEM
Use:<I1>(#4) *
N010. IL_OFFSET IL offset: 0x8 REG NA
N012. CNS_INT 0 REG NA
Def:<I2>(#5)
N014. CNS_INT 1 REG NA
N016. EQ
Use:<I2>(#6) *
N018. JTRUE
BB02 [00F..023) (return), preds={BB01} succs={}
=====
N022. IL_OFFSET IL offset: 0xf REG NA
N024. V02 MEM
N026. HWIntrinsic
Def:<I3>(#8)
N028. V03 MEM
Use:<I3>(#9) *
N030. IL_OFFSET IL offset: 0x1b REG NA
N032. V00 MEM
Def:<I4>(#10)
N034. V03 MEM
Def:<I5>(#11)
N036. STOREIND
Use:<I4>(#12) *
Use:<I5>(#13) *
N038. RETURN
BB03 [023..031) (return), preds={BB01} succs={}
=====
N042. IL_OFFSET IL offset: 0x23 REG NA
N044. LCL_VAR_ADDR V02 loc0 NA REG NA
Def:<I6>(#15)
N046. PUTARG_STK [+0x00]
Use:<I6>(#16) *
N048. V00 MEM
Def:<I7>(#17)
N050. PUTARG_REG
Use:<I7>(#19) Fixed:ecx(#18) *
Def:<I8>(#21) ecx
N052. V02 MEM
Def:<I9>(#22)
N054. PUTARG_REG
Use:<I9>(#24) Fixed:edx(#23) *
Def:<I10>(#26) edx
N056. CALL
Use:<I8>(#28) Fixed:ecx(#27) *
Use:<I10>(#30) Fixed:edx(#29) *
Kill: eax ecx edx mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7
N058. RETURN
Linear scan intervals after buildIntervals:
Interval 0: RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#3@7 #4@8} physReg:NA Preferences=[allInt]
Interval 2: (constant) RefPositions {#5@13 #6@16} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {#8@27 #9@28} physReg:NA Preferences=[allFloat]
Interval 4: RefPositions {#10@33 #12@36} physReg:NA Preferences=[allInt]
Interval 5: RefPositions {#11@35 #13@36} physReg:NA Preferences=[allFloat]
Interval 6: RefPositions {#15@45 #16@46} physReg:NA Preferences=[allInt]
Interval 7: RefPositions {#17@49 #19@50} physReg:NA Preferences=[ecx]
Interval 8: RefPositions {#21@51 #28@56} physReg:NA Preferences=[ecx]
Interval 9: RefPositions {#22@53 #24@54} physReg:NA Preferences=[edx]
Interval 10: RefPositions {#26@55 #30@56} physReg:NA Preferences=[edx]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#3@7 #4@8} physReg:NA Preferences=[allInt]
Interval 2: (constant) RefPositions {#5@13 #6@16} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {#8@27 #9@28} physReg:NA Preferences=[allFloat]
Interval 4: RefPositions {#10@33 #12@36} physReg:NA Preferences=[allInt]
Interval 5: RefPositions {#11@35 #13@36} physReg:NA Preferences=[allFloat]
Interval 6: RefPositions {#15@45 #16@46} physReg:NA Preferences=[allInt]
Interval 7: RefPositions {#17@49 #19@50} physReg:NA Preferences=[ecx]
Interval 8: RefPositions {#21@51 #28@56} physReg:NA Preferences=[ecx]
Interval 9: RefPositions {#22@53 #24@54} physReg:NA Preferences=[edx]
Interval 10: RefPositions {#26@55 #30@56} physReg:NA Preferences=[edx]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #3 @7 RefTypeDef <Ivl:1> CAST BB01 regmask=[allInt] minReg=1>
<RefPosition #4 @8 RefTypeUse <Ivl:1> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #5 @13 RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #6 @16 RefTypeUse <Ivl:2> BB01 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #7 @20 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #8 @27 RefTypeDef <Ivl:3> HWIntrinsic BB02 regmask=[allFloat] minReg=1>
<RefPosition #9 @28 RefTypeUse <Ivl:3> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #10 @33 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #11 @35 RefTypeDef <Ivl:5> LCL_VAR BB02 regmask=[allFloat] minReg=1>
<RefPosition #12 @36 RefTypeUse <Ivl:4> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #13 @36 RefTypeUse <Ivl:5> BB02 regmask=[allFloat] minReg=1 last>
<RefPosition #14 @40 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #15 @45 RefTypeDef <Ivl:6> LCL_VAR_ADDR BB03 regmask=[allInt] minReg=1>
<RefPosition #16 @46 RefTypeUse <Ivl:6> BB03 regmask=[allInt] minReg=1 last>
<RefPosition #17 @49 RefTypeDef <Ivl:7> LCL_VAR BB03 regmask=[ecx] minReg=1>
<RefPosition #18 @50 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #19 @50 RefTypeUse <Ivl:7> BB03 regmask=[ecx] minReg=1 last fixed>
<RefPosition #20 @51 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #21 @51 RefTypeDef <Ivl:8> PUTARG_REG BB03 regmask=[ecx] minReg=1 fixed>
<RefPosition #22 @53 RefTypeDef <Ivl:9> LCL_FLD BB03 regmask=[edx] minReg=1>
<RefPosition #23 @54 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #24 @54 RefTypeUse <Ivl:9> BB03 regmask=[edx] minReg=1 last fixed>
<RefPosition #25 @55 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #26 @55 RefTypeDef <Ivl:10> PUTARG_REG BB03 regmask=[edx] minReg=1 fixed>
<RefPosition #27 @56 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #28 @56 RefTypeUse <Ivl:8> BB03 regmask=[ecx] minReg=1 last fixed>
<RefPosition #29 @56 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #30 @56 RefTypeUse <Ivl:10> BB03 regmask=[edx] minReg=1 last fixed>
<RefPosition #31 @57 RefTypeKill <Reg:eax> BB03 regmask=[eax] minReg=1 last>
<RefPosition #32 @57 RefTypeKill <Reg:ecx> BB03 regmask=[ecx] minReg=1 last>
<RefPosition #33 @57 RefTypeKill <Reg:edx> BB03 regmask=[edx] minReg=1 last>
<RefPosition #34 @57 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
<RefPosition #35 @57 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
<RefPosition #36 @57 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
<RefPosition #37 @57 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
<RefPosition #38 @57 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
<RefPosition #39 @57 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
<RefPosition #40 @57 RefTypeKill <Reg:mm6> BB03 regmask=[mm6] minReg=1 last>
<RefPosition #41 @57 RefTypeKill <Reg:mm7> BB03 regmask=[mm7] minReg=1 last>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which
may increase during allocation, in which case additional columns will appear. Registers which are
not marked modified have ---- in their column.
------------------------------+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+
| | | | | | | | |
0.#0 BB1 PredBB0 | | | | | | | | |
5.#1 I0 Def Alloc ecx | |I0 a| | | | | | |
6.#2 I0 Use * Keep ecx | |I0 a| | | | | | |
7.#3 I1 Def Alloc ecx | |I1 a| | | | | | |
8.#4 I1 Use * Keep ecx | |I1 a| | | | | | |
13.#5 C2 Def Alloc ecx | |C2 a| | | | | | |
16.#6 C2 Use * Keep ecx | |C2 a| | | | | | |
------------------------------+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+
20.#7 BB2 PredBB1 | | | | | | | | |
27.#8 I3 Def Alloc mm0 | | | |I3 a| | | | |
28.#9 I3 Use * Keep mm0 | | | |I3 a| | | | |
33.#10 I4 Def Alloc ecx | |I4 a| | | | | | |
35.#11 I5 Def Alloc mm0 | |I4 a| |I5 a| | | | |
36.#12 I4 Use * Keep ecx | |I4 a| |I5 a| | | | |
36.#13 I5 Use * Keep mm0 | |I4 a| |I5 a| | | | |
------------------------------+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+
40.#14 BB3 PredBB1 | | | | | | | | |
45.#15 I6 Def Alloc ecx | |I6 a| | | | | | |
46.#16 I6 Use * Keep ecx | |I6 a| | | | | | |
49.#17 I7 Def Alloc ecx | |I7 a| | | | | | |
50.#18 ecx Fixd Keep ecx | |I7 a| | | | | | |
50.#19 I7 Use * Keep ecx | |I7 a| | | | | | |
51.#20 ecx Fixd Keep ecx | | | | | | | | |
51.#21 I8 Def Alloc ecx | |I8 a| | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+----+
53.#22 I9 Def Alloc edx | |I8 a|I9 a| | | | | | |
54.#23 edx Fixd Keep edx | |I8 a|I9 a| | | | | | |
54.#24 I9 Use * Keep edx | |I8 a|I9 a| | | | | | |
55.#25 edx Fixd Keep edx | |I8 a| | | | | | | |
55.#26 I10 Def Alloc edx | |I8 a|I10a| | | | | | |
56.#27 ecx Fixd Keep ecx | |I8 a|I10a| | | | | | |
56.#28 I8 Use * Keep ecx | |I8 a|I10a| | | | | | |
56.#29 edx Fixd Keep edx | |I8 a|I10a| | | | | | |
56.#30 I10 Use * Keep edx | |I8 a|I10a| | | | | | |
57.#31 eax Kill Keep eax | | | | | | | | | |
57.#32 ecx Kill Keep ecx | | | | | | | | | |
57.#33 edx Kill Keep edx | | | | | | | | | |
57.#34 mm0 Kill Keep mm0 | | | | | | | | | |
57.#35 mm1 Kill Keep mm1 | | | | | | | | | |
57.#36 mm2 Kill Keep mm2 | | | | | | | | | |
57.#37 mm3 Kill Keep mm3 | | | | | | | | | |
57.#38 mm4 Kill Keep mm4 | | | | | | | | | |
57.#39 mm5 Kill Keep mm5 | | | | | | | | | |
57.#40 mm6 Kill Keep mm6 | | | | | | | | | |
57.#41 mm7 Kill Keep mm7 | | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> LCL_VAR BB01 regmask=[ecx] minReg=1>
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[ecx] minReg=1 last>
<RefPosition #3 @7 RefTypeDef <Ivl:1> CAST BB01 regmask=[ecx] minReg=1>
<RefPosition #4 @8 RefTypeUse <Ivl:1> BB01 regmask=[ecx] minReg=1 last>
<RefPosition #5 @13 RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[ecx] minReg=1>
<RefPosition #6 @16 RefTypeUse <Ivl:2> BB01 regmask=[ecx] minReg=1 last regOptional>
<RefPosition #7 @20 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #8 @27 RefTypeDef <Ivl:3> HWIntrinsic BB02 regmask=[mm0] minReg=1>
<RefPosition #9 @28 RefTypeUse <Ivl:3> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #10 @33 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[ecx] minReg=1>
<RefPosition #11 @35 RefTypeDef <Ivl:5> LCL_VAR BB02 regmask=[mm0] minReg=1>
<RefPosition #12 @36 RefTypeUse <Ivl:4> BB02 regmask=[ecx] minReg=1 last>
<RefPosition #13 @36 RefTypeUse <Ivl:5> BB02 regmask=[mm0] minReg=1 last>
<RefPosition #14 @40 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #15 @45 RefTypeDef <Ivl:6> LCL_VAR_ADDR BB03 regmask=[ecx] minReg=1>
<RefPosition #16 @46 RefTypeUse <Ivl:6> BB03 regmask=[ecx] minReg=1 last>
<RefPosition #17 @49 RefTypeDef <Ivl:7> LCL_VAR BB03 regmask=[ecx] minReg=1>
<RefPosition #18 @50 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #19 @50 RefTypeUse <Ivl:7> BB03 regmask=[ecx] minReg=1 last fixed>
<RefPosition #20 @51 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #21 @51 RefTypeDef <Ivl:8> PUTARG_REG BB03 regmask=[ecx] minReg=1 fixed>
<RefPosition #22 @53 RefTypeDef <Ivl:9> LCL_FLD BB03 regmask=[edx] minReg=1>
<RefPosition #23 @54 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #24 @54 RefTypeUse <Ivl:9> BB03 regmask=[edx] minReg=1 last fixed>
<RefPosition #25 @55 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #26 @55 RefTypeDef <Ivl:10> PUTARG_REG BB03 regmask=[edx] minReg=1 fixed>
<RefPosition #27 @56 RefTypeFixedReg <Reg:ecx> BB03 regmask=[ecx] minReg=1>
<RefPosition #28 @56 RefTypeUse <Ivl:8> BB03 regmask=[ecx] minReg=1 last fixed>
<RefPosition #29 @56 RefTypeFixedReg <Reg:edx> BB03 regmask=[edx] minReg=1>
<RefPosition #30 @56 RefTypeUse <Ivl:10> BB03 regmask=[edx] minReg=1 last fixed>
<RefPosition #31 @57 RefTypeKill <Reg:eax> BB03 regmask=[eax] minReg=1 last>
<RefPosition #32 @57 RefTypeKill <Reg:ecx> BB03 regmask=[ecx] minReg=1 last>
<RefPosition #33 @57 RefTypeKill <Reg:edx> BB03 regmask=[edx] minReg=1 last>
<RefPosition #34 @57 RefTypeKill <Reg:mm0> BB03 regmask=[mm0] minReg=1 last>
<RefPosition #35 @57 RefTypeKill <Reg:mm1> BB03 regmask=[mm1] minReg=1 last>
<RefPosition #36 @57 RefTypeKill <Reg:mm2> BB03 regmask=[mm2] minReg=1 last>
<RefPosition #37 @57 RefTypeKill <Reg:mm3> BB03 regmask=[mm3] minReg=1 last>
<RefPosition #38 @57 RefTypeKill <Reg:mm4> BB03 regmask=[mm4] minReg=1 last>
<RefPosition #39 @57 RefTypeKill <Reg:mm5> BB03 regmask=[mm5] minReg=1 last>
<RefPosition #40 @57 RefTypeKill <Reg:mm6> BB03 regmask=[mm6] minReg=1 last>
<RefPosition #41 @57 RefTypeKill <Reg:mm7> BB03 regmask=[mm7] minReg=1 last>
Active intervals at end of allocation:
Trees after linear scan register allocator (LSRA)
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [00F..023) (return) i LIR
BB03 [0002] 1 BB01 1 [023..031) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
N002 ( 9, 10) [000006] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N004 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V01 arg0 ecx REG ecx
/--* t3 int
N006 ( 4, 4) [000043] ------------ t43 = * CAST int <- ushort <- int REG ecx
/--* t43 int
N008 ( 9, 10) [000005] DA--G------- * STORE_LCL_FLD ushort V02 loc0 [+0] Fseq[value] NA REG NA
N010 ( 5, 5) [000011] ------------ IL_OFFSET void IL offset: 0x8 REG NA
N012 ( 1, 1) [000008] ------------ t8 = CNS_INT int 0 REG ecx
N014 ( 1, 1) [000007] -c---------- t7 = CNS_INT int 1 REG NA
/--* t8 int
+--* t7 int
N016 ( 3, 3) [000009] J------N---- * EQ void REG NA
N018 ( 5, 5) [000010] ------------ * JTRUE void REG NA
------------ BB02 [00F..023) (return), preds={BB01} succs={}
N022 ( 9, 9) [000034] ------------ IL_OFFSET void IL offset: 0xf REG NA
N024 ( 4, 5) [000027] -c---------- t27 = LCL_FLD ushort V02 loc0 [+0] Fseq[value] NA REG NA
/--* t27 ushort
N026 ( 5, 6) [000030] ----G------- t30 = * HWIntrinsic simd16 uint ConvertScalarToVector128UInt32 REG mm0
/--* t30 simd16
N028 ( 9, 9) [000033] DA--G------- * STORE_LCL_VAR simd16 V03 loc1 NA REG NA
N030 ( 10, 7) [000040] ------------ IL_OFFSET void IL offset: 0x1b REG NA
N032 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 RetBuf ecx REG ecx
N034 ( 3, 2) [000035] ------------ t35 = LCL_VAR simd16 V03 loc1 mm0 REG mm0
/--* t37 byref
+--* t35 simd16
N036 (???,???) [000048] -A-XG------- * STOREIND simd16 REG NA
N038 ( 0, 0) [000041] ------------ RETURN void REG NA
------------ BB03 [023..031) (return), preds={BB01} succs={}
N042 ( 27, 17) [000023] ------------ IL_OFFSET void IL offset: 0x23 REG NA
N044 ( 3, 2) [000016] -------N---- t16 = LCL_VAR_ADDR byref V02 loc0 ecx REG ecx
/--* t16 byref
N046 (???,???) [000049] ------------ * PUTARG_STK [+0x00] void (1 slots) REG NA
N048 ( 3, 2) [000021] ------------ t21 = LCL_VAR byref V00 RetBuf ecx REG ecx
/--* t21 byref
N050 (???,???) [000050] ------------ t50 = * PUTARG_REG byref REG ecx
N052 ( 4, 5) [000013] ------------ t13 = LCL_FLD ushort V02 loc0 [+0] Fseq[value] edx REG edx
/--* t13 ushort
N054 (???,???) [000051] ------------ t51 = * PUTARG_REG int REG edx
/--* t50 byref arg0 in ecx
+--* t51 int arg1 in edx
N056 ( 27, 17) [000018] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
N058 ( 0, 0) [000024] ------------ RETURN void REG NA
-------------------------------------------------------------------------------------------------------------------
Final allocation
------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+----+
0.#0 BB1 PredBB0 | | | | | | | | | |
5.#1 I0 Def Alloc ecx | |I0 a| | | | | | | |
6.#2 I0 Use * Keep ecx | |I0 i| | | | | | | |
7.#3 I1 Def Alloc ecx | |I1 a| | | | | | | |
8.#4 I1 Use * Keep ecx | |I1 i| | | | | | | |
13.#5 C2 Def Alloc ecx | |C2 a| | | | | | | |
16.#6 C2 Use * Keep ecx | |C2 i| | | | | | | |
------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+----+
20.#7 BB2 PredBB1 | | | | | | | | | |
27.#8 I3 Def Alloc mm0 | | | | |I3 a| | | | |
28.#9 I3 Use * Keep mm0 | | | | |I3 i| | | | |
33.#10 I4 Def Alloc ecx | |I4 a| | | | | | | |
35.#11 I5 Def Alloc mm0 | |I4 a| | |I5 a| | | | |
36.#12 I4 Use * Keep ecx | |I4 i| | |I5 a| | | | |
36.#13 I5 Use * Keep mm0 | | | | |I5 i| | | | |
------------------------------+----+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |eax |ecx |edx |edi |mm0 |mm1 |mm2 |mm6 |mm7 |
------------------------------+----+----+----+----+----+----+----+----+----+
40.#14 BB3 PredBB1 | | | | | | | | | |
45.#15 I6 Def Alloc ecx | |I6 a| | | | | | | |
46.#16 I6 Use * Keep ecx | |I6 i| | | | | | | |
49.#17 I7 Def Alloc ecx | |I7 a| | | | | | | |
50.#18 ecx Fixd Keep ecx | |I7 a| | | | | | | |
50.#19 I7 Use * Keep ecx | |I7 i| | | | | | | |
51.#20 ecx Fixd Keep ecx | | | | | | | | | |
51.#21 I8 Def Alloc ecx | |I8 a| | | | | | | |
53.#22 I9 Def Alloc edx | |I8 a|I9 a| | | | | | |
54.#23 edx Fixd Keep edx | |I8 a|I9 a| | | | | | |
54.#24 I9 Use * Keep edx | |I8 a|I9 i| | | | | | |
55.#25 edx Fixd Keep edx | |I8 a| | | | | | | |
55.#26 I10 Def Alloc edx | |I8 a|I10a| | | | | | |
56.#27 ecx Fixd Keep ecx | |I8 a|I10a| | | | | | |
56.#28 I8 Use * Keep ecx | |I8 i|I10a| | | | | | |
56.#29 edx Fixd Keep edx | | |I10a| | | | | | |
56.#30 I10 Use * Keep edx | | |I10i| | | | | | |
57.#31 eax Kill Keep eax | | | | | | | | | |
57.#32 ecx Kill Keep ecx | | | | | | | | | |
57.#33 edx Kill Keep edx | | | | | | | | | |
57.#34 mm0 Kill Keep mm0 | | | | | | | | | |
57.#35 mm1 Kill Keep mm1 | | | | | | | | | |
57.#36 mm2 Kill Keep mm2 | | | | | | | | | |
57.#37 mm3 Kill Keep mm3 | | | | | | | | | |
57.#38 mm4 Kill Keep mm4 | | | | | | | | | |
57.#39 mm5 Kill Keep mm5 | | | | | | | | | |
57.#40 mm6 Kill Keep mm6 | | | | | | | | | |
57.#41 mm7 Kill Keep mm7 | | | | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Total Tracked Vars: 0
Total Reg Cand Vars: 0
Total number of Intervals: 10
Total number of RefPositions: 41
Total Spill Count: 0 Weighted: 0
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:
BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03}
=====
N002. IL_OFFSET IL offset: 0x0 REG NA
N004. ecx = V01 MEM
N006. ecx = CAST ; ecx
N008. V02 MEM; ecx
N010. IL_OFFSET IL offset: 0x8 REG NA
N012. ecx = CNS_INT 0 REG ecx
N014. CNS_INT 1 REG NA
N016. EQ ; ecx
N018. JTRUE
BB02 [00F..023) (return), preds={BB01} succs={}
=====
N022. IL_OFFSET IL offset: 0xf REG NA
N024. V02 MEM
N026. mm0 = HWIntrinsic
N028. V03 MEM; mm0
N030. IL_OFFSET IL offset: 0x1b REG NA
N032. ecx = V00 MEM
N034. mm0 = V03 MEM
N036. STOREIND ; ecx,mm0
N038. RETURN
BB03 [023..031) (return), preds={BB01} succs={}
=====
N042. IL_OFFSET IL offset: 0x23 REG NA
N044. ecx = LCL_VAR_ADDR V02 loc0 ecx REG ecx
N046. PUTARG_STK [+0x00]; ecx
N048. ecx = V00 MEM
N050. ecx = PUTARG_REG; ecx
N052. edx = V02 MEM
N054. edx = PUTARG_REG; edx
N056. CALL ; ecx,edx
N058. RETURN
*************** In genGenerateCode()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..00F)-> BB03 ( cond ) i label target LIR
BB02 [0001] 1 BB01 1 [00F..023) (return) i LIR
BB03 [0002] 1 BB01 1 [023..031) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Finalizing stack frame
Modified regs: [eax ecx edx mm0-mm7]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V00 RetBuf, size=4, stkOffs=-0xc
Assign V01 arg0, size=4, stkOffs=-0x10
Assign V02 loc0, size=4, stkOffs=-0x14
Assign V03 loc1, size=16, stkOffs=-0x24
; Final local variable assignments
;
; V00 RetBuf [V00 ] ( 1, 1 ) byref -> [ebp-0x04]
; V01 arg0 [V01 ] ( 1, 1 ) ushort -> [ebp-0x08]
; V02 loc0 [V02 ] ( 1, 1 ) struct ( 4) [ebp-0x0C] do-not-enreg[XSF] addr-exposed ld-addr-op
; V03 loc1 [V03 ] ( 1, 1 ) simd16 -> [ebp-0x1C] do-not-enreg[SB] ld-addr-op
;
; Lcl frame size = 28
=============== Generating BB01 [000..00F) -> BB03 (cond), preds={} succs={BB02,BB03} flags=0x00000000.40030020: i label target LIR
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 00000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45309_BB01:
Label: IG02, GCvars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Setting stack level from -572662307 to 0
Scope info: begin block BB01, IL range [000..00F)
Scope info: opening scope, LVnum=1 [000..031)
Scope info: >> new scope, VarNum=1, tracked? no, VarIndex=0, bbLiveIn=00000000 {}
Scope info: opening scope, LVnum=2 [000..031)
Scope info: >> new scope, VarNum=2, tracked? no, VarIndex=0, bbLiveIn=00000000 {}
Scope info: opening scope, LVnum=3 [000..031)
Scope info: >> new scope, VarNum=3, tracked? no, VarIndex=0, bbLiveIn=00000000 {}
Scope info: opening scope, LVnum=0 [000..031)
Scope info: >> new scope, VarNum=0, tracked? no, VarIndex=0, bbLiveIn=00000000 {}
Scope info: open scopes =
1 (V01 arg0) [000..031)
2 (V02 loc0) [000..031)
3 (V03 loc1) [000..031)
0 (V00 RetBuf) [000..031)
Added IP mapping: 0x0000 STACK_EMPTY (G_M45309_IG02,ins#0,ofs#0) label
Generating: N002 ( 9, 10) [000006] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N004 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V01 arg0 ecx REG ecx
IN0001: mov ecx, dword ptr [V01 ebp-08H]
/--* t3 int
Generating: N006 ( 4, 4) [000043] ------------ t43 = * CAST int <- ushort <- int REG ecx
IN0002: movzx ecx, cx
/--* t43 int
Generating: N008 ( 9, 10) [000005] DA--G------- * STORE_LCL_FLD ushort V02 loc0 [+0] Fseq[value] NA REG NA
IN0003: mov word ptr [V02 ebp-0CH], cx
Added IP mapping: 0x0008 STACK_EMPTY (G_M45309_IG02,ins#3,ofs#10)
Generating: N010 ( 5, 5) [000011] ------------ IL_OFFSET void IL offset: 0x8 REG NA
Generating: N012 ( 1, 1) [000008] ------------ t8 = CNS_INT int 0 REG ecx
IN0004: xor ecx, ecx
Generating: N014 ( 1, 1) [000007] -c---------- t7 = CNS_INT int 1 REG NA
/--* t8 int
+--* t7 int
Generating: N016 ( 3, 3) [000009] J------N---- * EQ void REG NA
IN0005: cmp ecx, 1
Generating: N018 ( 5, 5) [000010] ------------ * JTRUE void REG NA
IN0006: je L_M45309_BB03
Scope info: end block BB01, IL range [000..00F)
Scope info: open scopes =
1 (V01 arg0) [000..031)
2 (V02 loc0) [000..031)
3 (V03 loc1) [000..031)
0 (V00 RetBuf) [000..031)
=============== Generating BB02 [00F..023) (return), preds={BB01} succs={} flags=0x00000000.40000020: i LIR
BB02 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 00000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45309_BB02:
Scope info: begin block BB02, IL range [00F..023)
Scope info: open scopes =
1 (V01 arg0) [000..031)
2 (V02 loc0) [000..031)
3 (V03 loc1) [000..031)
0 (V00 RetBuf) [000..031)
Added IP mapping: 0x000F STACK_EMPTY (G_M45309_IG02,ins#6,ofs#21) label
Generating: N022 ( 9, 9) [000034] ------------ IL_OFFSET void IL offset: 0xf REG NA
Generating: N024 ( 4, 5) [000027] -c---------- t27 = LCL_FLD ushort V02 loc0 [+0] Fseq[value] NA REG NA
/--* t27 ushort
Generating: N026 ( 5, 6) [000030] ----G------- t30 = * HWIntrinsic simd16 uint ConvertScalarToVector128UInt32 REG mm0
IN0007: vmovd xmm0, xmmword ptr [V02 ebp-0CH]
/--* t30 simd16
Generating: N028 ( 9, 9) [000033] DA--G------- * STORE_LCL_VAR simd16 V03 loc1 NA REG NA
IN0008: vmovupd xmmword ptr [V03 ebp-1CH], xmm0
Added IP mapping: 0x001B STACK_EMPTY (G_M45309_IG02,ins#8,ofs#33)
Generating: N030 ( 10, 7) [000040] ------------ IL_OFFSET void IL offset: 0x1b REG NA
Generating: N032 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 RetBuf ecx REG ecx
IN0009: mov ecx, bword ptr [V00 ebp-04H]
Byref regs: 00000000 {} => 00000002 {ecx}
Generating: N034 ( 3, 2) [000035] ------------ t35 = LCL_VAR simd16 V03 loc1 mm0 REG mm0
IN000a: vmovupd xmm0, xmmword ptr [V03 ebp-1CH]
/--* t37 byref
+--* t35 simd16
Generating: N036 (???,???) [000048] -A-XG------- * STOREIND simd16 REG NA
Byref regs: 00000002 {ecx} => 00000000 {}
IN000b: vmovupd xmmword ptr [ecx], xmm0
Generating: N038 ( 0, 0) [000041] ------------ RETURN void REG NA
Scope info: end block BB02, IL range [00F..023)
Scope info: open scopes =
1 (V01 arg0) [000..031)
2 (V02 loc0) [000..031)
3 (V03 loc1) [000..031)
0 (V00 RetBuf) [000..031)
Added IP mapping: EPILOG STACK_EMPTY (G_M45309_IG02,ins#11,ofs#47) label
Reserving epilog IG for block BB02
G_M45309_IG02: ; offs=000000H, funclet=00
*************** After placeholder IG creation
G_M45309_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M45309_IG02: ; offs=000000H, size=002FH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45309_IG03: ; epilog placeholder, next placeholder=<END>, BB02 [0001], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M45309_IG04: ; offs=00012FH, size=0000H, gcrefRegs=00000000 {} <-- Current IG
=============== Generating BB03 [023..031) (return), preds={BB01} succs={} flags=0x00000000.400b0020: i label target gcsafe LIR
BB03 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 00000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M45309_BB03:
Label: IG04, GCvars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB03, IL range [023..031)
Scope info: open scopes =
1 (V01 arg0) [000..031)
2 (V02 loc0) [000..031)
3 (V03 loc1) [000..031)
0 (V00 RetBuf) [000..031)
Added IP mapping: 0x0023 STACK_EMPTY (G_M45309_IG04,ins#0,ofs#0) label
Generating: N042 ( 27, 17) [000023] ------------ IL_OFFSET void IL offset: 0x23 REG NA
Generating: N044 ( 3, 2) [000016] -------N---- t16 = LCL_VAR_ADDR byref V02 loc0 ecx REG ecx
IN000c: lea ecx, bword ptr [V02 ebp-0CH]
Byref regs: 00000000 {} => 00000002 {ecx}
/--* t16 byref
Generating: N046 (???,???) [000049] ------------ * PUTARG_STK [+0x00] void (1 slots) REG NA
Byref regs: 00000002 {ecx} => 00000000 {}
IN000d: push ecx
Upping emitMaxStackDepth from 0 to 4
Adjusting stack level from 0 to 4
Generating: N048 ( 3, 2) [000021] ------------ t21 = LCL_VAR byref V00 RetBuf ecx REG ecx
IN000e: mov ecx, bword ptr [V00 ebp-04H]
Byref regs: 00000000 {} => 00000002 {ecx}
/--* t21 byref
Generating: N050 (???,???) [000050] ------------ t50 = * PUTARG_REG byref REG ecx
Byref regs: 00000002 {ecx} => 00000000 {}
Byref regs: 00000000 {} => 00000002 {ecx}
Generating: N052 ( 4, 5) [000013] ------------ t13 = LCL_FLD ushort V02 loc0 [+0] Fseq[value] edx REG edx
IN000f: movzx edx, word ptr [V02 ebp-0CH]
/--* t13 ushort
Generating: N054 (???,???) [000051] ------------ t51 = * PUTARG_REG int REG edx
/--* t50 byref arg0 in ecx
+--* t51 int arg1 in edx
Generating: N056 ( 27, 17) [000018] S-CXG------- * CALL void System.Runtime.Intrinsics.Vector128.<CreateScalar>g__SoftwareFallback|38_0
Byref regs: 00000002 {ecx} => 00000000 {}
Call: GCvars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0010: call System.Runtime.Intrinsics.Vector128:<CreateScalar>g__SoftwareFallback|38_0(ushort,byref):struct
Adjusting stack level from 4 to 0
Generating: N058 ( 0, 0) [000024] ------------ RETURN void REG NA
Scope info: end block BB03, IL range [023..031)
Scope info: ending scope, LVnum=1 [000..031)
Scope info: ending scope, LVnum=2 [000..031)
Scope info: ending scope, LVnum=3 [000..031)
Scope info: ending scope, LVnum=0 [000..031)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M45309_IG04,ins#5,ofs#16) label
Reserving epilog IG for block BB03
G_M45309_IG04: ; offs=00012FH, funclet=00
*************** After placeholder IG creation
G_M45309_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M45309_IG02: ; offs=000000H, size=002FH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45309_IG03: ; epilog placeholder, next placeholder=IG05 , BB02 [0001], epilog, emitadd <-- First placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M45309_IG04: ; offs=00012FH, size=0010H, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
G_M45309_IG05: ; epilog placeholder, next placeholder=<END>, BB03 [0002], epilog, emitadd <-- Last placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Liveness not changing: 00000000 {}
# compCycleEstimate = 60, compSizeEstimate = 48 System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct
; Final local variable assignments
;
; V00 RetBuf [V00 ] ( 1, 1 ) byref -> [ebp-0x04]
; V01 arg0 [V01 ] ( 1, 1 ) ushort -> [ebp-0x08]
; V02 loc0 [V02 ] ( 1, 1 ) struct ( 4) [ebp-0x0C] do-not-enreg[XSF] addr-exposed ld-addr-op
; V03 loc1 [V03 ] ( 1, 1 ) simd16 -> [ebp-0x1C] do-not-enreg[SB] ld-addr-op
;
; Lcl frame size = 28
*************** Before prolog / epilog generation
G_M45309_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M45309_IG02: ; offs=000000H, size=002FH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45309_IG03: ; epilog placeholder, next placeholder=IG05 , BB02 [0001], epilog, emitadd <-- First placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
G_M45309_IG04: ; offs=00012FH, size=0010H, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
G_M45309_IG05: ; epilog placeholder, next placeholder=<END>, BB03 [0002], epilog, emitadd <-- Last placeholder
; PrevGCVars=00000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=00000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M45309_IG01,ins#0,ofs#0) label
__prolog:
IN0011: push ebp
IN0012: mov ebp, esp
IN0013: sub esp, 28
IN0014: vzeroupper
*************** In genFnPrologCalleeRegArgs() for int regs
IN0015: mov bword ptr [V00 ebp-04H], ecx
IN0016: mov dword ptr [V01 ebp-08H], edx
*************** In genEnregisterIncomingStackArgs()
G_M45309_IG01: ; offs=000000H, funclet=00
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=00000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN0017: mov esp, ebp
IN0018: pop ebp
IN0019: ret
G_M45309_IG03: ; offs=00002FH, funclet=00
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=00000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN001a: mov esp, ebp
IN001b: pop ebp
IN001c: ret
G_M45309_IG05: ; offs=00013FH, funclet=00
0 prologs, 2 epilogs
*************** After prolog / epilog generation
G_M45309_IG01: ; func=00, offs=000000H, size=000FH, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref, nogc <-- Prolog IG
G_M45309_IG02: ; offs=00000FH, size=002FH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M45309_IG03: ; offs=00003EH, size=0004H, epilog, nogc, emitadd
G_M45309_IG04: ; offs=000042H, size=0010H, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
G_M45309_IG05: ; offs=000052H, size=0004H, epilog, nogc, emitadd
*************** In emitJumpDistBind()
Binding: IN0006: 000000 je L_M45309_BB03
Binding L_M45309_BB03to G_M45309_IG04
Estimate of fwd jump [079B5C08/006]: 001E -> 0042 = 0022
Shrinking jump [079B5C08/006]
Adjusted offset of BB03 from 003E to 003A
Adjusted offset of BB04 from 0042 to 003E
Adjusted offset of BB05 from 0052 to 004E
Total shrinkage = 4, min extra jump size = 4294967295
Hot code size = 0x52 bytes
Cold code size = 0x0 bytes
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (4) to elements (1)
***************************************************************************
Instructions as they come out of the scheduler
G_M45309_IG01: ; func=00, offs=000000H, size=000FH, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref, nogc <-- Prolog IG
IN0011: 000000 55 push ebp
IN0012: 000001 8BEC mov ebp, esp
IN0013: 000003 83EC1C sub esp, 28
IN0014: 000006 C5F877 vzeroupper
IN0015: 000009 894DFC mov bword ptr [ebp-04H], ecx
IN0016: 00000C 8955F8 mov dword ptr [ebp-08H], edx
G_M45309_IG02: ; func=00, offs=00000FH, size=002BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0001: 00000F 8B4DF8 mov ecx, dword ptr [ebp-08H]
IN0002: 000012 0FB7C9 movzx ecx, cx
IN0003: 000015 66894DF4 mov word ptr [ebp-0CH], cx
IN0004: 000019 33C9 xor ecx, ecx
IN0005: 00001B 83F901 cmp ecx, 1
IN0006: 00001E 741E je SHORT G_M45309_IG04
IN0007: 000020 C5F96E45F4 vmovd xmm0, xmmword ptr [ebp-0CH] (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN0008: 000025 C5F91145E4 vmovupd xmmword ptr [ebp-1CH], xmm0 (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
byrReg +[ecx]
IN0009: 00002A 8B4DFC mov ecx, bword ptr [ebp-04H]
IN000a: 00002D C5F91045E4 vmovupd xmm0, xmmword ptr [ebp-1CH] (ECS:6, ACS:5)
Instruction predicted size = 6, actual = 5
IN000b: 000032 C5F91101 vmovupd xmmword ptr [ecx], xmm0 (ECS:5, ACS:4)
Instruction predicted size = 5, actual = 4
G_M45309_IG03: ; func=00, offs=00003AH, size=0004H, epilog, nogc, emitadd
Block predicted offs = 0000003A, actual = 00000036 -> size adj = 4
IN0017: 000036 8BE5 mov esp, ebp
IN0018: 000038 5D pop ebp
IN0019: 000039 C3 ret
G_M45309_IG04: ; func=00, offs=00003EH, size=0010H, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
Block predicted offs = 0000003E, actual = 0000003A -> size adj = 4
New byrReg live regs=00000000 {}
byrReg +[ecx]
IN000c: 00003A 8D4DF4 lea ecx, bword ptr [ebp-0CH]
IN000d: 00003D 51 push ecx
IN000e: 00003E 8B4DFC mov ecx, bword ptr [ebp-04H]
IN000f: 000041 0FB755F4 movzx edx, word ptr [ebp-0CH]
New byrReg live regs=00000000 {}
IN0010: 000045 E89665D768 call System.Runtime.Intrinsics.Vector128:<CreateScalar>g__SoftwareFallback|38_0(ushort,byref):struct
G_M45309_IG05: ; func=00, offs=00004EH, size=0004H, epilog, nogc, emitadd
Block predicted offs = 0000004E, actual = 0000004A -> size adj = 4
IN001a: 00004A 8BE5 mov esp, ebp
IN001b: 00004C 5D pop ebp
IN001c: 00004D C3 ret
Allocated method code size = 82 , actual size = 78
*************** After end code gen, before unwindEmit()
G_M45309_IG01: ; func=00, offs=000000H, size=000FH, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref, nogc <-- Prolog IG
IN0011: 000000 push ebp
IN0012: 000001 mov ebp, esp
IN0013: 000003 sub esp, 28
IN0014: 000006 vzeroupper
IN0015: 000009 mov bword ptr [V00 ebp-04H], ecx
IN0016: 00000C mov dword ptr [V01 ebp-08H], edx
G_M45309_IG02: ; offs=00000FH, size=0027H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN0001: 00000F mov ecx, dword ptr [V01 ebp-08H]
IN0002: 000012 movzx ecx, cx
IN0003: 000015 mov word ptr [V02 ebp-0CH], cx
IN0004: 000019 xor ecx, ecx
IN0005: 00001B cmp ecx, 1
IN0006: 00001E je SHORT G_M45309_IG04
IN0007: 000020 vmovd xmm0, xmmword ptr [V02 ebp-0CH]
IN0008: 000025 vmovupd xmmword ptr [V03 ebp-1CH], xmm0
IN0009: 00002A mov ecx, bword ptr [V00 ebp-04H]
IN000a: 00002D vmovupd xmm0, xmmword ptr [V03 ebp-1CH]
IN000b: 000032 vmovupd xmmword ptr [ecx], xmm0
G_M45309_IG03: ; offs=000036H, size=0004H, epilog, nogc, emitadd
IN0017: 000036 mov esp, ebp
IN0018: 000038 pop ebp
IN0019: 000039 ret
G_M45309_IG04: ; offs=00003AH, size=0010H, gcVars=00000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref
IN000c: 00003A lea ecx, bword ptr [V02 ebp-0CH]
IN000d: 00003D push ecx
IN000e: 00003E mov ecx, bword ptr [V00 ebp-04H]
IN000f: 000041 movzx edx, word ptr [V02 ebp-0CH]
IN0010: 000045 call System.Runtime.Intrinsics.Vector128:<CreateScalar>g__SoftwareFallback|38_0(ushort,byref):struct
G_M45309_IG05: ; offs=00004AH, size=0004H, epilog, nogc, emitadd
IN001a: 00004A mov esp, ebp
IN001b: 00004C pop ebp
IN001c: 00004D ret
*************** In genIPmappingGen()
IP mapping count : 8
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x0000000F ( STACK_EMPTY )
IL offs 0x0008 : 0x00000019 ( STACK_EMPTY )
IL offs 0x000F : 0x00000020 ( STACK_EMPTY )
IL offs 0x001B : 0x0000002A ( STACK_EMPTY )
IL offs EPILOG : 0x00000036 ( STACK_EMPTY )
IL offs 0x0023 : 0x0000003A ( STACK_EMPTY )
IL offs EPILOG : 0x0000004A ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 6
*************** Variable debug info
6 vars
0( UNKNOWN) : From 00000000h to 0000000Fh, in edx
-2( retBuff) : From 00000000h to 0000000Fh, in ecx
0( UNKNOWN) : From 0000000Fh to 0000004Ah, in ebp[-8] (1 slot)
1( UNKNOWN) : From 0000000Fh to 0000004Ah, in ebp[-12] (1 slot)
2( UNKNOWN) : From 0000000Fh to 0000004Ah, in ebp[-28] (1 slot)
-2( retBuff) : From 0000000Fh to 0000004Ah, in ebp[-4] (1 slot)
*************** In gcInfoBlockHdrSave()
GCINFO: untrckd byr lcl at [ebp-04H]
GCINFO: untrckVars = 1
GCINFO: trackdLcls = 0
*************** In gcInfoBlockHdrSave()
GCINFO: methodSize = 004E
GCINFO: prologSize = 0009
GCINFO: epilogSize = 0004
GC Info for method System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct
GC info size = 11
Method info block:
method size = 004E
prolog size = 9
epilog size = 4
epilog count = 2
epilog end = no
callee-saved regs = EBP
ebp frame = yes
fully interruptible= no
double align = no
arguments size = 0 DWORDs
stack frame size = 7 DWORDs
untracked count = 1
var ptr tab count = 0
epilog # 0 at 0036
epilog # 1 at 004A
4E D1 87 B1 C6 |
B8 1A 36 14 |
Pointer table:
03 | [EBP-04H] an untracked byref local
FF |
Method code size: 78
Allocations for System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct (MethodHash=16b94f02)
count: 370, size: 22197, max = 1344
allocateMemory: 65536, nraUsed: 23784
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 0 | 0.00%
ASTNode | 5096 | 22.96%
InstDesc | 2352 | 10.60%
ImpStack | 192 | 0.86%
BasicBlock | 564 | 2.54%
fgArgInfo | 132 | 0.59%
fgArgInfoPtrArr | 60 | 0.27%
FlowList | 40 | 0.18%
TreeStatementList | 0 | 0.00%
SiScope | 248 | 1.12%
DominatorMemory | 0 | 0.00%
LSRA | 1412 | 6.36%
LSRA_Interval | 572 | 2.58%
LSRA_RefPosition | 1848 | 8.33%
Reachability | 0 | 0.00%
SSA | 0 | 0.00%
ValueNumber | 0 | 0.00%
LvaTable | 1349 | 6.08%
UnwindInfo | 0 | 0.00%
hashBv | 60 | 0.27%
bitset | 100 | 0.45%
FixedBitVect | 12 | 0.05%
Generic | 622 | 2.80%
LocalAddressVisitor | 0 | 0.00%
FieldSeqStore | 96 | 0.43%
ZeroOffsetFieldMap | 100 | 0.45%
ArrayInfoMap | 0 | 0.00%
MemoryPhiArg | 0 | 0.00%
CSE | 0 | 0.00%
GC | 24 | 0.11%
CorSig | 52 | 0.23%
Inlining | 100 | 0.45%
ArrayStack | 0 | 0.00%
DebugInfo | 272 | 1.23%
DebugOnly | 6238 | 28.10%
Codegen | 572 | 2.58%
LoopOpt | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 84 | 0.38%
RangeCheck | 0 | 0.00%
CopyProp | 0 | 0.00%
SideEffects | 0 | 0.00%
ObjectAllocator | 0 | 0.00%
****** DONE compiling System.Runtime.Intrinsics.Vector128:CreateScalar(ushort):struct
Vector128.CreateScalar(UInt16): RunBasicScenario failed:
value: 3387
result: (3387, 823, 0, 0, 0, 0, 0, 0)
Beginning scenario: RunReflectionScenario
Vector128.CreateScalar(UInt16): RunReflectionScenario failed:
value: 11422
result: (11422, 823, 0, 0, 0, 0, 0, 0)
ERROR!!!-System.Exception: One or more scenarios did not complete as expected.
Ending test case at 1/5/2019 8:30:03 AM
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