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@taylorza
Last active September 7, 2023 11:26
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ZX Spectrum Next Samples
SLDOPT COMMENT WPMEM, LOGPOINT, ASSERTION
DEVICE ZXSPECTRUMNEXT
CSPECTMAP "ctctest.map"
org $8000
ctc0 equ $183b
main:
nextreg 7,0 ; set speed
di ; disable interrupts
nextreg $c0, (ivt & %11100000) | 1 ; setup vector table, enable Next IM2
nextreg $c4, %00000000 ; disable /INT and ULA interrupts
nextreg $c5, %00000001 ; enable CTC channel 0 interrupts, disable CTC channel 1-7 interrupts
nextreg $c6, %00000000 ; disable UART interrupts
ld bc, ctc0 ; load CTC Channel 0 Port
ld a, 1
out (c), a ; disable CTC Channel 0
ld a, %10100101 ; enable intertupt, counter mode, 256 prescaler, 0,0,0, time const follows, reset, control word
out (c), a ; write control word to CTC Channel 0
ld a, 249 ; time constant
out (c), a ; write time constant to CTC Channel 0
ld a, high ivt ; high byte of the interrupt vector table
ld i, a ; loaded into the I register
im 2 ; switch CPU to interrupt mode 2
ei ; enable interrupts
jr $ ; loop forever
;------------------------------------------------------------------------------
; CTC Channel 0 Interrupt Handler
ctc0handler:
push af ; Save AF
ld a, (beeper) ; Load current beeper and border value
xor %00010000 ; Flip beeper bit
ld (beeper), a ; Store new beeper value
out ($fe), a ; Write new value to the IO Port
pop af ; Restore AF
ei ; Reenable interrupts
reti ; Return from Interrupt
beeper db %00000011 ; Default to beeper off and a magenta border
;------------------------------------------------------------------------------
; Default Interrupt Handler - Does nothing but reenable interrupts and return
; This is not called because all the associated interrupt have been disabled
inthandler:
ei ; Reenable interrupts
reti ; Return from Interrupt
;------------------------------------------------------------------------------
; Interupt Vector Table
align 32
ivt:
dw inthandler ; 0 - line interrupt
dw inthandler ; 1 - uart0 rx
dw inthandler ; 2 - uart1 rx
dw ctc0handler ; 3 - ctc 0 <--- Our handler for the CTC Channel 0
dw inthandler ; 4 - ctc 1
dw inthandler ; 5 - ctc 2
dw inthandler ; 6 - ctc 3
dw inthandler ; 7 - ctc 4
dw inthandler ; 8 - ctc 5
dw inthandler ; 9 - ctc 6
dw inthandler ; 10 - ctc 7
dw inthandler ; 11 - ula
dw inthandler ; 12 - uart0 tx
dw inthandler ; 13 - uart1 tx
dw inthandler ; 14
dw inthandler ; 15
;------------------------------------------------------------------------------
; Stack reservation
STACK_SIZE equ 100
stack_bottom:
defs STACK_SIZE * 2
stack_top:
defw 0
;------------------------------------------------------------------------------
; Output configuration
SAVENEX OPEN "ctctest.nex", main, stack_top
SAVENEX CORE 2,0,0
SAVENEX CFG 7,0,0,0
SAVENEX SCREEN SCR
SAVENEX AUTO
SAVENEX CLOSE
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