Example makefile with proper dependency handling

Makefile

SRCS := foo.c bar.c
OBJS := $($(SRC):.c=.o)

foo: $(OBJS)
  $(CPP) -o $@ $^ $(LINKFLAGS)

-include $(OBJS:.o=.d)

%.o: %.cc
  $(CPP) -c  $(CFLAGS) $*.cc -o $*.o
  $(CPP) -MM $(CFLAGS) $*.cc  > $*.d # generates .d files which will detect header file changes as well
  @sed -i -e 's|.*:|$*.o:|' $*.d     # corrects a problem in the generated .d files

%.o: %.c
  $(CC) -c  $(CFLAGS) $*.c -o $*.o
  $(CC) -MM $(CFLAGS) $*.c  > $*.d
  @sed -i -e 's|.*:|$*.o:|' $*.d