VHDL 7SEGLED encoder.

encode_7seg.vhd

library ieee;
use ieee.std_logic_1164.all;

entity encode_7seg is
  generic(COMMON: integer range 0 to 1 := 0);
  port(DIN: in integer range 0 to 127;
       DOT: in std_logic;
       SEG7LED: out std_logic_vector(7 downto 0));
end encode_7seg;

architecture RTL of encode_7seg is
  signal S7SEG: std_logic_vector(7 downto 0);
begin

  process(DIN)
  begin
    case DIN is
      when  0 => S7SEG <= "1111110" & DOT; -- 0
      when  1 => S7SEG <= "0110000" & DOT; -- 1
      when  2 => S7SEG <= "1101101" & DOT; -- 2
      when  3 => S7SEG <= "1111001" & DOT; -- 3
      when  4 => S7SEG <= "0110011" & DOT; -- 4
      when  5 => S7SEG <= "1011011" & DOT; -- 5
      when  6 => S7SEG <= "1011111" & DOT; -- 6
      when  7 => S7SEG <= "1110010" & DOT; -- 7
      when  8 => S7SEG <= "1111111" & DOT; -- 8
      when  9 => S7SEG <= "1111011" & DOT; -- 9
      when 32 => S7SEG <= "0000000" & DOT; -- 
      when 45 => S7SEG <= "0000001" & DOT; -- -
      when 48 => S7SEG <= "1111110" & DOT; -- 0
      when 49 => S7SEG <= "0110000" & DOT; -- 1
      when 50 => S7SEG <= "1101101" & DOT; -- 2
      when 51 => S7SEG <= "1111001" & DOT; -- 3
      when 52 => S7SEG <= "0110011" & DOT; -- 4
      when 53 => S7SEG <= "1011011" & DOT; -- 5
      when 54 => S7SEG <= "1011111" & DOT; -- 6
      when 55 => S7SEG <= "1110010" & DOT; -- 7
      when 56 => S7SEG <= "1111111" & DOT; -- 8
      when 57 => S7SEG <= "1111011" & DOT; -- 9
      when 61 => S7SEG <= "1000001" & DOT; -- =
      when 65 => S7SEG <= "1110111" & DOT; -- A
      when 66 => S7SEG <= "0011111" & DOT; -- B
      when 67 => S7SEG <= "1001111" & DOT; -- C
      when 68 => S7SEG <= "0111101" & DOT; -- D
      when 69 => S7SEG <= "1001111" & DOT; -- E
      when 70 => S7SEG <= "1000111" & DOT; -- F
      when 71 => S7SEG <= "1011110" & DOT; -- G
      when 72 => S7SEG <= "0010111" & DOT; -- H
      when 73 => S7SEG <= "0010000" & DOT; -- I
      when 74 => S7SEG <= "0111000" & DOT; -- J
      when 75 => S7SEG <= "1010111" & DOT; -- K
      when 76 => S7SEG <= "0001110" & DOT; -- L
      when 77 => S7SEG <= "1110110" & DOT; -- M
      when 78 => S7SEG <= "0010101" & DOT; -- N
      when 79 => S7SEG <= "0011101" & DOT; -- O
      when 80 => S7SEG <= "1100111" & DOT; -- P
      when 81 => S7SEG <= "1101111" & DOT; -- Q
      when 82 => S7SEG <= "0000101" & DOT; -- R
      when 83 => S7SEG <= "0011011" & DOT; -- S
      when 84 => S7SEG <= "0001111" & DOT; -- T
      when 85 => S7SEG <= "0011100" & DOT; -- U
      when 86 => S7SEG <= "0111110" & DOT; -- V
      when 87 => S7SEG <= "0111111" & DOT; -- W
      when 88 => S7SEG <= "0110111" & DOT; -- X
      when 89 => S7SEG <= "0111011" & DOT; -- Y
      when 90 => S7SEG <= "1101100" & DOT; -- Z
      when 95 => S7SEG <= "0001000" & DOT; -- _
      when 97 => S7SEG <= "1110111" & DOT; -- A
      when 98 => S7SEG <= "0011111" & DOT; -- B
      when 99 => S7SEG <= "1001111" & DOT; -- C
      when 100 => S7SEG <= "0111101" & DOT; -- D
      when 101 => S7SEG <= "1001111" & DOT; -- E
      when 102 => S7SEG <= "1000111" & DOT; -- F
      when 103 => S7SEG <= "1011110" & DOT; -- G
      when 104 => S7SEG <= "0010111" & DOT; -- H
      when 105 => S7SEG <= "0010000" & DOT; -- I
      when 106 => S7SEG <= "0111000" & DOT; -- J
      when 107 => S7SEG <= "1010111" & DOT; -- K
      when 108 => S7SEG <= "0001110" & DOT; -- L
      when 109 => S7SEG <= "1110110" & DOT; -- M
      when 110 => S7SEG <= "0010101" & DOT; -- N
      when 111 => S7SEG <= "0011101" & DOT; -- O
      when 112 => S7SEG <= "1100111" & DOT; -- P
      when 113 => S7SEG <= "1101111" & DOT; -- Q
      when 114 => S7SEG <= "0000101" & DOT; -- R
      when 115 => S7SEG <= "0011011" & DOT; -- S
      when 116 => S7SEG <= "0001111" & DOT; -- T
      when 117 => S7SEG <= "0011100" & DOT; -- U
      when 118 => S7SEG <= "0111110" & DOT; -- V
      when 119 => S7SEG <= "0111111" & DOT; -- W
      when 120 => S7SEG <= "0110111" & DOT; -- X
      when 121 => S7SEG <= "0111011" & DOT; -- Y
      when 122 => S7SEG <= "1101100" & DOT; -- Z
      when others => S7SEG <= "00000000";
    end case;

    if(COMMON = 1) then
      S7SEG <= not S7SEG;
    end if;

    SEG7LED <= S7SEG;

  end process;

end RTL;