Partial product generator for 16 bit radix 4 Booth multiplier

BoothPartialProductGenerater.vhdl

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:00:36 01/16/2014 
-- Design Name: 
-- Module Name:    BoothPartProdGen - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BoothPartProdGen is
	PORT (
		bin3: in STD_LOGIC_VECTOR(2 downto 0);
		a: in STD_LOGIC_VECTOR(15 downto 0);
		product: out STD_LOGIC_VECTOR(16 downto 0)
	);
end BoothPartProdGen;

architecture Behavioral of BoothPartProdGen is
	constant ONE17: STD_LOGIC_VECTOR(16 downto 0) := "00000000000000001";
begin

--product <= '0' & a when bin3 = "001" or bin3 = "010" else
--			  a & '0' when bin3 = "011" else
--			  std_logic_vector(unsigned(not('0' & a)) + unsigned(ONE17)) when bin3 = "101" or bin3 = "110" else
--			  std_logic_vector(unsigned(not(a & '0')) + unsigned(ONE17)) when bin3 = "100" else
--			  (others => '0');
			  
PROCESS(bin3, a)
BEGIN

if bin3 = "001" or bin3 = "010" then
	product <= "0" & a;
elsif bin3 = "011" then
	product <= a & '0';
elsif bin3 = "101" or bin3 = "110" then
	product <= std_logic_vector(unsigned(not('0' & a)) + unsigned(ONE17));
elsif bin3 = "100" then
	product <= std_logic_vector(unsigned(not(a & '0')) + unsigned(ONE17));
else
	product <= (others => '0');
end if;
END PROCESS;

end Behavioral;

BoothPartialProductGenerater_tb.vhdl

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   13:08:56 01/16/2014
-- Design Name:   
-- Module Name:   /home/tejainece/learnings/xilinx/BoothPartProdGen/BoothPartProdGen_tb.vhd
-- Project Name:  BoothPartProdGen
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: BoothPartProdGen
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY BoothPartProdGen_tb IS
END BoothPartProdGen_tb;
 
ARCHITECTURE behavior OF BoothPartProdGen_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT BoothPartProdGen
    PORT(
         bin3 : IN  std_logic_vector(2 downto 0);
         a : IN  std_logic_vector(15 downto 0);
         product : OUT  std_logic_vector(16 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal bin3 : std_logic_vector(2 downto 0) := (others => '0');
   signal a : std_logic_vector(15 downto 0) := (others => '0');

 	--Outputs
   signal product : std_logic_vector(16 downto 0);
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: BoothPartProdGen PORT MAP (
          bin3 => bin3,
          a => a,
          product => product
        );

	stim_proc: process
	begin         
		a <= "0000000000000101";
		bin3 <= "000";
		wait for 10 ns;
		bin3 <= "001";
		wait for 10 ns;
		bin3 <= "010";
		wait for 10 ns;
		bin3 <= "011";
		wait for 10 ns;
		bin3 <= "100";
		wait for 10 ns;
		bin3 <= "101";
		wait for 10 ns;
		bin3 <= "110";
		wait for 10 ns;
		bin3 <= "111";
		wait for 10 ns;
		wait;
  end process;

END;