Read output ports in Verilog and VHDL. This was written for my blog post.

read_output_correct.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ReadOutputCorrect is
	PORT (
		in1  : IN  STD_LOGIC;
		in2  : IN  STD_LOGIC;
		in3  : IN  STD_LOGIC;
		o1   : OUT STD_LOGIC;
		o2   : OUT STD_LOGIC
	);
end ReadOutputCorrect;

architecture Behavioral of ReadOutputCorrect is

SIGNAL tmp1_o1 : STD_LOGIC;

begin

	tmp1_o1 <= in1 and in2;
	o1 <= tmp1_o1;
	o2 <= tmp1_o1 and in3;

end Behavioral;

read_output_wrong.vhd

entity ReadOutputWrong is
	PORT (
		in1  : IN  STD_LOGIC;
		in2  : IN  STD_LOGIC;
		in3  : IN  STD_LOGIC;
		o1   : OUT STD_LOGIC;
		o2   : OUT STD_LOGIC
	);
end ReadOutputWrong;

architecture Behavioral of ReadOutputWrong is

begin

	o1 <= in1 and in2;
	o2 <= o1 and in3;

end Behavioral;

readtheout.v

module ReadTheOut(
		in1, in2, in3, o1, o2
    );

input in1, in2, in3;
output o1, o2;

assign o1 = in1 & in2;
assign o2 = o1 & in3;

endmodule