Not all variables declared as reg gets synthesized to registers in verilog.

ThisRegWontProduceReg.v

module ThisRegWontProduceReg(
	output reg o1,
	input i1, i2, i3
    );

	always @(i1, i2, i3) begin
		if (i1 == 1'b1) begin
			o1 <= i2;
		end else begin
			o1 <= i3;
		end
	end

endmodule