Where not to assign wire and reg in Verilog. This was written for demonstration purposes in my blog post.

RegAssignmentWrong.v

module RegAssignmentWrong(
	output reg o,
	input in1,
	input in2
    );

	assign o = in1 & in2;

endmodule

WireAssignmentWrong.v

module WireAssignmentWrong(
		output o1,
		input in1,
		input in2
    );

	always @(in1, in2) begin
		o1 <= in1 & in2;
	end

endmodule