Created
February 16, 2023 23:52
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| /dts-v1/; | |
| / { | |
| compatible = "xlnx,zynqmp-zcu102-rev1.0\0xlnx,zynqmp-zcu102\0xlnx,zynqmp"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| model = "ZynqMP ZCU102 Rev1.0"; | |
| cpus { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| cpu@0 { | |
| compatible = "arm,cortex-a53"; | |
| device_type = "cpu"; | |
| enable-method = "psci"; | |
| operating-points-v2 = <0x01>; | |
| reg = <0x00>; | |
| cpu-idle-states = <0x02>; | |
| clocks = <0x03 0x0a>; | |
| }; | |
| cpu@1 { | |
| compatible = "arm,cortex-a53"; | |
| device_type = "cpu"; | |
| enable-method = "psci"; | |
| reg = <0x01>; | |
| operating-points-v2 = <0x01>; | |
| cpu-idle-states = <0x02>; | |
| }; | |
| cpu@2 { | |
| compatible = "arm,cortex-a53"; | |
| device_type = "cpu"; | |
| enable-method = "psci"; | |
| reg = <0x02>; | |
| operating-points-v2 = <0x01>; | |
| cpu-idle-states = <0x02>; | |
| }; | |
| cpu@3 { | |
| compatible = "arm,cortex-a53"; | |
| device_type = "cpu"; | |
| enable-method = "psci"; | |
| reg = <0x03>; | |
| operating-points-v2 = <0x01>; | |
| cpu-idle-states = <0x02>; | |
| }; | |
| idle-states { | |
| entry-method = "psci"; | |
| cpu-sleep-0 { | |
| compatible = "arm,idle-state"; | |
| arm,psci-suspend-param = <0x40000000>; | |
| local-timer-stop; | |
| entry-latency-us = <0x12c>; | |
| exit-latency-us = <0x258>; | |
| min-residency-us = <0x2710>; | |
| phandle = <0x02>; | |
| }; | |
| }; | |
| }; | |
| cpu-opp-table { | |
| compatible = "operating-points-v2"; | |
| opp-shared; | |
| phandle = <0x01>; | |
| opp00 { | |
| opp-hz = <0x00 0x47868bf4>; | |
| opp-microvolt = <0xf4240>; | |
| clock-latency-ns = <0x7a120>; | |
| }; | |
| opp01 { | |
| opp-hz = <0x00 0x23c345fa>; | |
| opp-microvolt = <0xf4240>; | |
| clock-latency-ns = <0x7a120>; | |
| }; | |
| opp02 { | |
| opp-hz = <0x00 0x17d783fc>; | |
| opp-microvolt = <0xf4240>; | |
| clock-latency-ns = <0x7a120>; | |
| }; | |
| opp03 { | |
| opp-hz = <0x00 0x11e1a2fd>; | |
| opp-microvolt = <0xf4240>; | |
| clock-latency-ns = <0x7a120>; | |
| }; | |
| }; | |
| zynqmp_ipi { | |
| u-boot,dm-pre-reloc; | |
| compatible = "xlnx,zynqmp-ipi-mailbox"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x23 0x04>; | |
| xlnx,ipi-id = <0x00>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| mailbox@ff990400 { | |
| u-boot,dm-pre-reloc; | |
| reg = <0x00 0xff9905c0 0x00 0x20 0x00 0xff9905e0 0x00 0x20 0x00 0xff990e80 0x00 0x20 0x00 0xff990ea0 0x00 0x20>; | |
| reg-names = "local_request_region\0local_response_region\0remote_request_region\0remote_response_region"; | |
| #mbox-cells = <0x01>; | |
| xlnx,ipi-id = <0x04>; | |
| phandle = <0x05>; | |
| }; | |
| }; | |
| dcc { | |
| compatible = "arm,dcc"; | |
| status = "okay"; | |
| u-boot,dm-pre-reloc; | |
| }; | |
| pmu { | |
| compatible = "arm,armv8-pmuv3"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04>; | |
| }; | |
| psci { | |
| compatible = "arm,psci-0.2"; | |
| method = "smc"; | |
| }; | |
| firmware { | |
| zynqmp-firmware { | |
| compatible = "xlnx,zynqmp-firmware"; | |
| #power-domain-cells = <0x01>; | |
| method = "smc"; | |
| u-boot,dm-pre-reloc; | |
| phandle = <0x0c>; | |
| zynqmp-power { | |
| u-boot,dm-pre-reloc; | |
| compatible = "xlnx,zynqmp-power"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x23 0x04>; | |
| mboxes = <0x05 0x00 0x05 0x01>; | |
| mbox-names = "tx\0rx"; | |
| }; | |
| nvmem_firmware { | |
| compatible = "xlnx,zynqmp-nvmem-fw"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| soc_revision@0 { | |
| reg = <0x00 0x04>; | |
| phandle = <0x1e>; | |
| }; | |
| efuse_dna@c { | |
| reg = <0x0c 0x0c>; | |
| }; | |
| efuse_usr0@20 { | |
| reg = <0x20 0x04>; | |
| }; | |
| efuse_usr1@24 { | |
| reg = <0x24 0x04>; | |
| }; | |
| efuse_usr2@28 { | |
| reg = <0x28 0x04>; | |
| }; | |
| efuse_usr3@2c { | |
| reg = <0x2c 0x04>; | |
| }; | |
| efuse_usr4@30 { | |
| reg = <0x30 0x04>; | |
| }; | |
| efuse_usr5@34 { | |
| reg = <0x34 0x04>; | |
| }; | |
| efuse_usr6@38 { | |
| reg = <0x38 0x04>; | |
| }; | |
| efuse_usr7@3c { | |
| reg = <0x3c 0x04>; | |
| }; | |
| efuse_miscusr@40 { | |
| reg = <0x40 0x04>; | |
| }; | |
| efuse_chash@50 { | |
| reg = <0x50 0x04>; | |
| }; | |
| efuse_pufmisc@54 { | |
| reg = <0x54 0x04>; | |
| }; | |
| efuse_sec@58 { | |
| reg = <0x58 0x04>; | |
| }; | |
| efuse_spkid@5c { | |
| reg = <0x5c 0x04>; | |
| }; | |
| efuse_ppk0hash@a0 { | |
| reg = <0xa0 0x30>; | |
| }; | |
| efuse_ppk1hash@d0 { | |
| reg = <0xd0 0x30>; | |
| }; | |
| }; | |
| pcap { | |
| compatible = "xlnx,zynqmp-pcap-fpga"; | |
| clock-names = "ref_clk"; | |
| clocks = <0x03 0x29>; | |
| phandle = <0x0b>; | |
| }; | |
| zynqmp-aes { | |
| compatible = "xlnx,zynqmp-aes"; | |
| }; | |
| reset-controller { | |
| compatible = "xlnx,zynqmp-reset"; | |
| #reset-cells = <0x01>; | |
| phandle = <0x1c>; | |
| }; | |
| pinctrl { | |
| compatible = "xlnx,zynqmp-pinctrl"; | |
| status = "okay"; | |
| i2c0-default { | |
| phandle = <0x12>; | |
| mux { | |
| groups = "i2c0_3_grp"; | |
| function = "i2c0"; | |
| }; | |
| conf { | |
| groups = "i2c0_3_grp"; | |
| bias-pull-up; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| }; | |
| }; | |
| i2c0-gpio { | |
| phandle = <0x13>; | |
| mux { | |
| groups = "gpio0_14_grp\0gpio0_15_grp"; | |
| function = "gpio0"; | |
| }; | |
| conf { | |
| groups = "gpio0_14_grp\0gpio0_15_grp"; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| }; | |
| }; | |
| i2c1-default { | |
| phandle = <0x15>; | |
| mux { | |
| groups = "i2c1_4_grp"; | |
| function = "i2c1"; | |
| }; | |
| conf { | |
| groups = "i2c1_4_grp"; | |
| bias-pull-up; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| }; | |
| }; | |
| i2c1-gpio { | |
| phandle = <0x16>; | |
| mux { | |
| groups = "gpio0_16_grp\0gpio0_17_grp"; | |
| function = "gpio0"; | |
| }; | |
| conf { | |
| groups = "gpio0_16_grp\0gpio0_17_grp"; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| }; | |
| }; | |
| uart0-default { | |
| phandle = <0x2b>; | |
| mux { | |
| groups = "uart0_4_grp"; | |
| function = "uart0"; | |
| }; | |
| conf { | |
| groups = "uart0_4_grp"; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| }; | |
| conf-rx { | |
| pins = "MIO18"; | |
| bias-high-impedance; | |
| }; | |
| conf-tx { | |
| pins = "MIO19"; | |
| bias-disable; | |
| }; | |
| }; | |
| uart1-default { | |
| phandle = <0x2c>; | |
| mux { | |
| groups = "uart1_5_grp"; | |
| function = "uart1"; | |
| }; | |
| conf { | |
| groups = "uart1_5_grp"; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| }; | |
| conf-rx { | |
| pins = "MIO21"; | |
| bias-high-impedance; | |
| }; | |
| conf-tx { | |
| pins = "MIO20"; | |
| bias-disable; | |
| }; | |
| }; | |
| usb0-default { | |
| phandle = <0x2e>; | |
| mux { | |
| groups = "usb0_0_grp"; | |
| function = "usb0"; | |
| }; | |
| conf { | |
| groups = "usb0_0_grp"; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| }; | |
| conf-rx { | |
| pins = "MIO52\0MIO53\0MIO55"; | |
| bias-high-impedance; | |
| }; | |
| conf-tx { | |
| pins = "MIO54\0MIO56\0MIO57\0MIO58\0MIO59\0MIO60\0MIO61\0MIO62\0MIO63"; | |
| bias-disable; | |
| }; | |
| }; | |
| gem3-default { | |
| phandle = <0x10>; | |
| mux { | |
| function = "ethernet3"; | |
| groups = "ethernet3_0_grp"; | |
| }; | |
| conf { | |
| groups = "ethernet3_0_grp"; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| }; | |
| conf-rx { | |
| pins = "MIO70\0MIO71\0MIO72\0MIO73\0MIO74\0MIO75"; | |
| bias-high-impedance; | |
| low-power-disable; | |
| }; | |
| conf-tx { | |
| pins = "MIO64\0MIO65\0MIO66\0MIO67\0MIO68\0MIO69"; | |
| bias-disable; | |
| low-power-enable; | |
| }; | |
| mux-mdio { | |
| function = "mdio3"; | |
| groups = "mdio3_0_grp"; | |
| }; | |
| conf-mdio { | |
| groups = "mdio3_0_grp"; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| bias-disable; | |
| }; | |
| }; | |
| can1-default { | |
| phandle = <0x0d>; | |
| mux { | |
| function = "can1"; | |
| groups = "can1_6_grp"; | |
| }; | |
| conf { | |
| groups = "can1_6_grp"; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| }; | |
| conf-rx { | |
| pins = "MIO25"; | |
| bias-high-impedance; | |
| }; | |
| conf-tx { | |
| pins = "MIO24"; | |
| bias-disable; | |
| }; | |
| }; | |
| sdhci1-default { | |
| phandle = <0x1f>; | |
| mux { | |
| groups = "sdio1_0_grp"; | |
| function = "sdio1"; | |
| }; | |
| conf { | |
| groups = "sdio1_0_grp"; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| bias-disable; | |
| }; | |
| mux-cd { | |
| groups = "sdio1_cd_0_grp"; | |
| function = "sdio1_cd"; | |
| }; | |
| conf-cd { | |
| groups = "sdio1_cd_0_grp"; | |
| bias-high-impedance; | |
| bias-pull-up; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| }; | |
| mux-wp { | |
| groups = "sdio1_wp_0_grp"; | |
| function = "sdio1_wp"; | |
| }; | |
| conf-wp { | |
| groups = "sdio1_wp_0_grp"; | |
| bias-high-impedance; | |
| bias-pull-up; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| }; | |
| }; | |
| gpio-default { | |
| phandle = <0x11>; | |
| mux-sw { | |
| function = "gpio0"; | |
| groups = "gpio0_22_grp\0gpio0_23_grp"; | |
| }; | |
| conf-sw { | |
| groups = "gpio0_22_grp\0gpio0_23_grp"; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| }; | |
| mux-msp { | |
| function = "gpio0"; | |
| groups = "gpio0_13_grp\0gpio0_38_grp"; | |
| }; | |
| conf-msp { | |
| groups = "gpio0_13_grp\0gpio0_38_grp"; | |
| slew-rate = <0x01>; | |
| power-source = <0x01>; | |
| }; | |
| conf-pull-up { | |
| pins = "MIO22\0MIO23"; | |
| bias-pull-up; | |
| }; | |
| conf-pull-none { | |
| pins = "MIO13\0MIO38"; | |
| bias-disable; | |
| }; | |
| }; | |
| }; | |
| sha384 { | |
| compatible = "xlnx,zynqmp-keccak-384"; | |
| }; | |
| zynqmp-rsa { | |
| compatible = "xlnx,zynqmp-rsa"; | |
| }; | |
| gpio { | |
| compatible = "xlnx,zynqmp-gpio-modepin"; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| phandle = <0x2d>; | |
| }; | |
| clock-controller { | |
| u-boot,dm-pre-reloc; | |
| #clock-cells = <0x01>; | |
| compatible = "xlnx,zynqmp-clk"; | |
| clocks = <0x06 0x07 0x08 0x09 0x0a>; | |
| clock-names = "pss_ref_clk\0video_clk\0pss_alt_ref_clk\0aux_ref_clk\0gt_crx_ref_clk"; | |
| phandle = <0x03>; | |
| }; | |
| }; | |
| }; | |
| timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>; | |
| }; | |
| edac { | |
| compatible = "arm,cortex-a53-edac"; | |
| }; | |
| fpga-full { | |
| compatible = "fpga-region"; | |
| fpga-mgr = <0x0b>; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| }; | |
| smmu@fd800000 { | |
| compatible = "arm,mmu-500"; | |
| reg = <0x00 0xfd800000 0x00 0x20000>; | |
| #iommu-cells = <0x01>; | |
| status = "disabled"; | |
| #global-interrupts = <0x01>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04>; | |
| phandle = <0x0e>; | |
| }; | |
| axi { | |
| compatible = "simple-bus"; | |
| u-boot,dm-pre-reloc; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| ranges; | |
| can@ff060000 { | |
| compatible = "xlnx,zynq-can-1.0"; | |
| status = "disabled"; | |
| clock-names = "can_clk\0pclk"; | |
| reg = <0x00 0xff060000 0x00 0x1000>; | |
| interrupts = <0x00 0x17 0x04>; | |
| interrupt-parent = <0x04>; | |
| tx-fifo-depth = <0x40>; | |
| rx-fifo-depth = <0x40>; | |
| power-domains = <0x0c 0x2f>; | |
| clocks = <0x03 0x3f 0x03 0x1f>; | |
| }; | |
| can@ff070000 { | |
| compatible = "xlnx,zynq-can-1.0"; | |
| status = "okay"; | |
| clock-names = "can_clk\0pclk"; | |
| reg = <0x00 0xff070000 0x00 0x1000>; | |
| interrupts = <0x00 0x18 0x04>; | |
| interrupt-parent = <0x04>; | |
| tx-fifo-depth = <0x40>; | |
| rx-fifo-depth = <0x40>; | |
| power-domains = <0x0c 0x30>; | |
| clocks = <0x03 0x40 0x03 0x1f>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x0d>; | |
| }; | |
| cci@fd6e0000 { | |
| compatible = "arm,cci-400"; | |
| status = "disabled"; | |
| reg = <0x00 0xfd6e0000 0x00 0x9000>; | |
| ranges = <0x00 0x00 0xfd6e0000 0x10000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| pmu@9000 { | |
| compatible = "arm,cci-400-pmu,r1"; | |
| reg = <0x9000 0x5000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04>; | |
| }; | |
| }; | |
| dma@fd500000 { | |
| status = "okay"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xfd500000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x7c 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x80>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x14e8>; | |
| power-domains = <0x0c 0x2a>; | |
| clocks = <0x03 0x13 0x03 0x1f>; | |
| }; | |
| dma@fd510000 { | |
| status = "okay"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xfd510000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x7d 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x80>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x14e9>; | |
| power-domains = <0x0c 0x2a>; | |
| clocks = <0x03 0x13 0x03 0x1f>; | |
| }; | |
| dma@fd520000 { | |
| status = "okay"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xfd520000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x7e 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x80>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x14ea>; | |
| power-domains = <0x0c 0x2a>; | |
| clocks = <0x03 0x13 0x03 0x1f>; | |
| }; | |
| dma@fd530000 { | |
| status = "okay"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xfd530000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x7f 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x80>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x14eb>; | |
| power-domains = <0x0c 0x2a>; | |
| clocks = <0x03 0x13 0x03 0x1f>; | |
| }; | |
| dma@fd540000 { | |
| status = "okay"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xfd540000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x80 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x80>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x14ec>; | |
| power-domains = <0x0c 0x2a>; | |
| clocks = <0x03 0x13 0x03 0x1f>; | |
| }; | |
| dma@fd550000 { | |
| status = "okay"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xfd550000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x81 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x80>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x14ed>; | |
| power-domains = <0x0c 0x2a>; | |
| clocks = <0x03 0x13 0x03 0x1f>; | |
| }; | |
| dma@fd560000 { | |
| status = "okay"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xfd560000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x82 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x80>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x14ee>; | |
| power-domains = <0x0c 0x2a>; | |
| clocks = <0x03 0x13 0x03 0x1f>; | |
| }; | |
| dma@fd570000 { | |
| status = "okay"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xfd570000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x83 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x80>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x14ef>; | |
| power-domains = <0x0c 0x2a>; | |
| clocks = <0x03 0x13 0x03 0x1f>; | |
| }; | |
| interrupt-controller@f9010000 { | |
| compatible = "arm,gic-400"; | |
| #interrupt-cells = <0x03>; | |
| reg = <0x00 0xf9010000 0x00 0x10000 0x00 0xf9020000 0x00 0x20000 0x00 0xf9040000 0x00 0x20000 0x00 0xf9060000 0x00 0x20000>; | |
| interrupt-controller; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x01 0x09 0xf04>; | |
| phandle = <0x04>; | |
| }; | |
| gpu@fd4b0000 { | |
| status = "okay"; | |
| compatible = "arm,mali-400\0arm,mali-utgard"; | |
| reg = <0x00 0xfd4b0000 0x00 0x10000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04>; | |
| interrupt-names = "IRQGP\0IRQGPMMU\0IRQPP0\0IRQPPMMU0\0IRQPP1\0IRQPPMMU1"; | |
| clock-names = "gpu\0gpu_pp0\0gpu_pp1"; | |
| power-domains = <0x0c 0x3a>; | |
| clocks = <0x03 0x18 0x03 0x19 0x03 0x1a>; | |
| }; | |
| dma@ffa80000 { | |
| status = "disabled"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xffa80000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x4d 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x40>; | |
| #stream-id-cells = <0x01>; | |
| power-domains = <0x0c 0x2b>; | |
| clocks = <0x03 0x44 0x03 0x1f>; | |
| }; | |
| dma@ffa90000 { | |
| status = "disabled"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xffa90000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x4e 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x40>; | |
| #stream-id-cells = <0x01>; | |
| power-domains = <0x0c 0x2b>; | |
| clocks = <0x03 0x44 0x03 0x1f>; | |
| }; | |
| dma@ffaa0000 { | |
| status = "disabled"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xffaa0000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x4f 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x40>; | |
| #stream-id-cells = <0x01>; | |
| power-domains = <0x0c 0x2b>; | |
| clocks = <0x03 0x44 0x03 0x1f>; | |
| }; | |
| dma@ffab0000 { | |
| status = "disabled"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xffab0000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x50 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x40>; | |
| #stream-id-cells = <0x01>; | |
| power-domains = <0x0c 0x2b>; | |
| clocks = <0x03 0x44 0x03 0x1f>; | |
| }; | |
| dma@ffac0000 { | |
| status = "disabled"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xffac0000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x51 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x40>; | |
| #stream-id-cells = <0x01>; | |
| power-domains = <0x0c 0x2b>; | |
| clocks = <0x03 0x44 0x03 0x1f>; | |
| }; | |
| dma@ffad0000 { | |
| status = "disabled"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xffad0000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x52 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x40>; | |
| #stream-id-cells = <0x01>; | |
| power-domains = <0x0c 0x2b>; | |
| clocks = <0x03 0x44 0x03 0x1f>; | |
| }; | |
| dma@ffae0000 { | |
| status = "disabled"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xffae0000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x53 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x40>; | |
| #stream-id-cells = <0x01>; | |
| power-domains = <0x0c 0x2b>; | |
| clocks = <0x03 0x44 0x03 0x1f>; | |
| }; | |
| dma@ffaf0000 { | |
| status = "disabled"; | |
| compatible = "xlnx,zynqmp-dma-1.0"; | |
| reg = <0x00 0xffaf0000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x54 0x04>; | |
| clock-names = "clk_main\0clk_apb"; | |
| xlnx,bus-width = <0x40>; | |
| #stream-id-cells = <0x01>; | |
| power-domains = <0x0c 0x2b>; | |
| clocks = <0x03 0x44 0x03 0x1f>; | |
| }; | |
| memory-controller@fd070000 { | |
| compatible = "xlnx,zynqmp-ddrc-2.40a"; | |
| reg = <0x00 0xfd070000 0x00 0x30000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x70 0x04>; | |
| }; | |
| nand-controller@ff100000 { | |
| compatible = "xlnx,zynqmp-nand-controller\0arasan,nfc-v3p10"; | |
| status = "disabled"; | |
| reg = <0x00 0xff100000 0x00 0x1000>; | |
| clock-names = "controller\0bus"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x0e 0x04>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x872>; | |
| power-domains = <0x0c 0x2c>; | |
| clocks = <0x03 0x3c 0x03 0x1f>; | |
| }; | |
| ethernet@ff0b0000 { | |
| compatible = "cdns,zynqmp-gem\0cdns,gem"; | |
| status = "disabled"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x39 0x04 0x00 0x39 0x04>; | |
| reg = <0x00 0xff0b0000 0x00 0x1000>; | |
| clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x874>; | |
| power-domains = <0x0c 0x1d>; | |
| clocks = <0x03 0x1f 0x03 0x68 0x03 0x2d 0x03 0x31 0x03 0x2c>; | |
| }; | |
| ethernet@ff0c0000 { | |
| compatible = "cdns,zynqmp-gem\0cdns,gem"; | |
| status = "disabled"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x3b 0x04 0x00 0x3b 0x04>; | |
| reg = <0x00 0xff0c0000 0x00 0x1000>; | |
| clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x875>; | |
| power-domains = <0x0c 0x1e>; | |
| clocks = <0x03 0x1f 0x03 0x69 0x03 0x2e 0x03 0x32 0x03 0x2c>; | |
| }; | |
| ethernet@ff0d0000 { | |
| compatible = "cdns,zynqmp-gem\0cdns,gem"; | |
| status = "disabled"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x3d 0x04 0x00 0x3d 0x04>; | |
| reg = <0x00 0xff0d0000 0x00 0x1000>; | |
| clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x876>; | |
| power-domains = <0x0c 0x1f>; | |
| clocks = <0x03 0x1f 0x03 0x6a 0x03 0x2f 0x03 0x33 0x03 0x2c>; | |
| }; | |
| ethernet@ff0e0000 { | |
| compatible = "cdns,zynqmp-gem\0cdns,gem"; | |
| status = "okay"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x3f 0x04 0x00 0x3f 0x04>; | |
| reg = <0x00 0xff0e0000 0x00 0x1000>; | |
| clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x877>; | |
| power-domains = <0x0c 0x20>; | |
| clocks = <0x03 0x1f 0x03 0x6b 0x03 0x30 0x03 0x34 0x03 0x2c>; | |
| phy-handle = <0x0f>; | |
| phy-mode = "rgmii-id"; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x10>; | |
| ethernet-phy@c { | |
| reg = <0x0c>; | |
| ti,rx-internal-delay = <0x08>; | |
| ti,tx-internal-delay = <0x0a>; | |
| ti,fifo-depth = <0x01>; | |
| ti,dp83867-rxctrl-strap-quirk; | |
| phandle = <0x0f>; | |
| }; | |
| }; | |
| gpio@ff0a0000 { | |
| compatible = "xlnx,zynqmp-gpio-1.0"; | |
| status = "okay"; | |
| #gpio-cells = <0x02>; | |
| gpio-controller; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x10 0x04>; | |
| interrupt-controller; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x00 0xff0a0000 0x00 0x1000>; | |
| power-domains = <0x0c 0x2e>; | |
| clocks = <0x03 0x1f>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x11>; | |
| phandle = <0x14>; | |
| }; | |
| i2c@ff020000 { | |
| compatible = "cdns,i2c-r1p14"; | |
| status = "okay"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x11 0x04>; | |
| reg = <0x00 0xff020000 0x00 0x1000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x0c 0x25>; | |
| clocks = <0x03 0x3d>; | |
| clock-frequency = <0x61a80>; | |
| pinctrl-names = "default\0gpio"; | |
| pinctrl-0 = <0x12>; | |
| pinctrl-1 = <0x13>; | |
| scl-gpios = <0x14 0x0e 0x00>; | |
| sda-gpios = <0x14 0x0f 0x00>; | |
| gpio@20 { | |
| compatible = "ti,tca6416"; | |
| reg = <0x20>; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| gpio-line-names = "PS_GTR_LAN_SEL0\0PS_GTR_LAN_SEL1\0PS_GTR_LAN_SEL2\0PS_GTR_LAN_SEL3\0PCI_CLK_DIR_SEL\0IIC_MUX_RESET_B\0GEM3_EXP_RESET_B\0\0\0\0\0\0\0\0\0"; | |
| gtr-sel0-hog { | |
| gpio-hog; | |
| gpios = <0x00 0x00>; | |
| output-low; | |
| line-name = "sel0"; | |
| }; | |
| gtr-sel1-hog { | |
| gpio-hog; | |
| gpios = <0x01 0x00>; | |
| output-high; | |
| line-name = "sel1"; | |
| }; | |
| gtr-sel2-hog { | |
| gpio-hog; | |
| gpios = <0x02 0x00>; | |
| output-high; | |
| line-name = "sel2"; | |
| }; | |
| gtr-sel3-hog { | |
| gpio-hog; | |
| gpios = <0x03 0x00>; | |
| output-high; | |
| line-name = "sel3"; | |
| }; | |
| }; | |
| gpio@21 { | |
| compatible = "ti,tca6416"; | |
| reg = <0x21>; | |
| gpio-controller; | |
| #gpio-cells = <0x02>; | |
| gpio-line-names = "VCCPSPLL_EN\0MGTRAVCC_EN\0MGTRAVTT_EN\0VCCPSDDRPLL_EN\0MIO26_PMU_INPUT_LS\0PL_PMBUS_ALERT\0PS_PMBUS_ALERT\0MAXIM_PMBUS_ALERT\0PL_DDR4_VTERM_EN\0PL_DDR4_VPP_2V5_EN\0PS_DIMM_VDDQ_TO_PSVCCO_ON\0PS_DIMM_SUSPEND_EN\0PS_DDR4_VTERM_EN\0PS_DDR4_VPP_2V5_EN\0\0"; | |
| }; | |
| i2c-mux@75 { | |
| compatible = "nxp,pca9544"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x75>; | |
| i2c@0 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x00>; | |
| ina226@40 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u76"; | |
| reg = <0x40>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x34>; | |
| }; | |
| ina226@41 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u77"; | |
| reg = <0x41>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x35>; | |
| }; | |
| ina226@42 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u78"; | |
| reg = <0x42>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x36>; | |
| }; | |
| ina226@43 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u87"; | |
| reg = <0x43>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x37>; | |
| }; | |
| ina226@44 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u85"; | |
| reg = <0x44>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x38>; | |
| }; | |
| ina226@45 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u86"; | |
| reg = <0x45>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x39>; | |
| }; | |
| ina226@46 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u93"; | |
| reg = <0x46>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x3a>; | |
| }; | |
| ina226@47 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u88"; | |
| reg = <0x47>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x3b>; | |
| }; | |
| ina226@4a { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u15"; | |
| reg = <0x4a>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x3c>; | |
| }; | |
| ina226@4b { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u92"; | |
| reg = <0x4b>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x3d>; | |
| }; | |
| }; | |
| i2c@1 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x01>; | |
| ina226@40 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u79"; | |
| reg = <0x40>; | |
| shunt-resistor = <0x7d0>; | |
| phandle = <0x3e>; | |
| }; | |
| ina226@41 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u81"; | |
| reg = <0x41>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x3f>; | |
| }; | |
| ina226@42 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u80"; | |
| reg = <0x42>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x40>; | |
| }; | |
| ina226@43 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u84"; | |
| reg = <0x43>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x41>; | |
| }; | |
| ina226@44 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u16"; | |
| reg = <0x44>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x42>; | |
| }; | |
| ina226@45 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u65"; | |
| reg = <0x45>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x43>; | |
| }; | |
| ina226@46 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u74"; | |
| reg = <0x46>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x44>; | |
| }; | |
| ina226@47 { | |
| compatible = "ti,ina226"; | |
| #io-channel-cells = <0x01>; | |
| label = "ina226-u75"; | |
| reg = <0x47>; | |
| shunt-resistor = <0x1388>; | |
| phandle = <0x45>; | |
| }; | |
| }; | |
| i2c@2 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x02>; | |
| max15301@a { | |
| compatible = "maxim,max15301"; | |
| reg = <0x0a>; | |
| }; | |
| max15303@b { | |
| compatible = "maxim,max15303"; | |
| reg = <0x0b>; | |
| }; | |
| max15303@10 { | |
| compatible = "maxim,max15303"; | |
| reg = <0x10>; | |
| }; | |
| max15301@13 { | |
| compatible = "maxim,max15301"; | |
| reg = <0x13>; | |
| }; | |
| max15303@14 { | |
| compatible = "maxim,max15303"; | |
| reg = <0x14>; | |
| }; | |
| max15303@15 { | |
| compatible = "maxim,max15303"; | |
| reg = <0x15>; | |
| }; | |
| max15303@16 { | |
| compatible = "maxim,max15303"; | |
| reg = <0x16>; | |
| }; | |
| max15303@17 { | |
| compatible = "maxim,max15303"; | |
| reg = <0x17>; | |
| }; | |
| max15301@18 { | |
| compatible = "maxim,max15301"; | |
| reg = <0x18>; | |
| }; | |
| max15303@1a { | |
| compatible = "maxim,max15303"; | |
| reg = <0x1a>; | |
| }; | |
| max15303@1d { | |
| compatible = "maxim,max15303"; | |
| reg = <0x1d>; | |
| }; | |
| max20751@72 { | |
| compatible = "maxim,max20751"; | |
| reg = <0x72>; | |
| }; | |
| max20751@73 { | |
| compatible = "maxim,max20751"; | |
| reg = <0x73>; | |
| }; | |
| max15303@1b { | |
| compatible = "maxim,max15303"; | |
| reg = <0x1b>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| i2c@ff030000 { | |
| compatible = "cdns,i2c-r1p14"; | |
| status = "okay"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x12 0x04>; | |
| reg = <0x00 0xff030000 0x00 0x1000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x0c 0x26>; | |
| clocks = <0x03 0x3e>; | |
| clock-frequency = <0x61a80>; | |
| pinctrl-names = "default\0gpio"; | |
| pinctrl-0 = <0x15>; | |
| pinctrl-1 = <0x16>; | |
| scl-gpios = <0x14 0x10 0x00>; | |
| sda-gpios = <0x14 0x11 0x00>; | |
| i2c-mux@74 { | |
| compatible = "nxp,pca9548"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x74>; | |
| i2c@0 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x00>; | |
| eeprom@54 { | |
| compatible = "atmel,24c08"; | |
| reg = <0x54>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| board-sn@0 { | |
| reg = <0x00 0x14>; | |
| }; | |
| eth-mac@20 { | |
| reg = <0x20 0x06>; | |
| }; | |
| board-name@d0 { | |
| reg = <0xd0 0x06>; | |
| }; | |
| board-revision@e0 { | |
| reg = <0xe0 0x03>; | |
| }; | |
| }; | |
| }; | |
| i2c@1 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x01>; | |
| clock-generator@36 { | |
| compatible = "silabs,si5341"; | |
| reg = <0x36>; | |
| #clock-cells = <0x02>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| clocks = <0x17>; | |
| clock-names = "xtal"; | |
| clock-output-names = "si5341"; | |
| phandle = <0x1b>; | |
| out@0 { | |
| reg = <0x00>; | |
| always-on; | |
| }; | |
| out@2 { | |
| reg = <0x02>; | |
| always-on; | |
| }; | |
| out@3 { | |
| reg = <0x03>; | |
| always-on; | |
| }; | |
| out@4 { | |
| reg = <0x04>; | |
| always-on; | |
| }; | |
| out@5 { | |
| reg = <0x05>; | |
| always-on; | |
| }; | |
| out@6 { | |
| reg = <0x06>; | |
| always-on; | |
| }; | |
| out@7 { | |
| reg = <0x07>; | |
| always-on; | |
| }; | |
| out@9 { | |
| reg = <0x09>; | |
| always-on; | |
| }; | |
| }; | |
| }; | |
| i2c@2 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x02>; | |
| clock-generator@5d { | |
| #clock-cells = <0x00>; | |
| compatible = "silabs,si570"; | |
| reg = <0x5d>; | |
| temperature-stability = <0x32>; | |
| factory-fout = <0x11e1a300>; | |
| clock-frequency = <0x11e1a300>; | |
| clock-output-names = "si570_user"; | |
| }; | |
| }; | |
| i2c@3 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x03>; | |
| clock-generator@5d { | |
| #clock-cells = <0x00>; | |
| compatible = "silabs,si570"; | |
| reg = <0x5d>; | |
| temperature-stability = <0x32>; | |
| factory-fout = <0x9502f90>; | |
| clock-frequency = <0x8d9ee20>; | |
| clock-output-names = "si570_mgt"; | |
| }; | |
| }; | |
| i2c@4 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x04>; | |
| clock-generator@69 { | |
| compatible = "silabs,si5328"; | |
| reg = <0x69>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| #clock-cells = <0x01>; | |
| clocks = <0x18>; | |
| clock-names = "xtal"; | |
| clock-output-names = "si5328"; | |
| clk0@0 { | |
| reg = <0x00>; | |
| clock-frequency = <0x19bfcc0>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| i2c-mux@75 { | |
| compatible = "nxp,pca9548"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x75>; | |
| i2c@0 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x00>; | |
| eeprom@50 { | |
| compatible = "at24,24c02"; | |
| reg = <0x50>; | |
| }; | |
| }; | |
| i2c@1 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x01>; | |
| eeprom@50 { | |
| compatible = "at24,24c02"; | |
| reg = <0x50>; | |
| }; | |
| }; | |
| i2c@2 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x02>; | |
| }; | |
| i2c@3 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x03>; | |
| }; | |
| i2c@4 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x04>; | |
| }; | |
| i2c@5 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x05>; | |
| }; | |
| i2c@6 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x06>; | |
| }; | |
| i2c@7 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x07>; | |
| }; | |
| }; | |
| }; | |
| memory-controller@ff960000 { | |
| compatible = "xlnx,zynqmp-ocmc-1.0"; | |
| reg = <0x00 0xff960000 0x00 0x1000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x0a 0x04>; | |
| }; | |
| perf-monitor@ffa00000 { | |
| compatible = "xlnx,axi-perf-monitor"; | |
| reg = <0x00 0xffa00000 0x00 0x10000>; | |
| interrupts = <0x00 0x19 0x04>; | |
| interrupt-parent = <0x04>; | |
| xlnx,enable-profile = <0x00>; | |
| xlnx,enable-trace = <0x00>; | |
| xlnx,num-monitor-slots = <0x01>; | |
| xlnx,enable-event-count = <0x01>; | |
| xlnx,enable-event-log = <0x01>; | |
| xlnx,have-sampled-metric-cnt = <0x01>; | |
| xlnx,num-of-counters = <0x08>; | |
| xlnx,metric-count-width = <0x20>; | |
| xlnx,metrics-sample-count-width = <0x20>; | |
| xlnx,global-count-width = <0x20>; | |
| xlnx,metric-count-scale = <0x01>; | |
| clocks = <0x03 0x1f>; | |
| }; | |
| perf-monitor@fd0b0000 { | |
| compatible = "xlnx,axi-perf-monitor"; | |
| reg = <0x00 0xfd0b0000 0x00 0x10000>; | |
| interrupts = <0x00 0x7b 0x04>; | |
| interrupt-parent = <0x04>; | |
| xlnx,enable-profile = <0x00>; | |
| xlnx,enable-trace = <0x00>; | |
| xlnx,num-monitor-slots = <0x06>; | |
| xlnx,enable-event-count = <0x01>; | |
| xlnx,enable-event-log = <0x00>; | |
| xlnx,have-sampled-metric-cnt = <0x01>; | |
| xlnx,num-of-counters = <0x0a>; | |
| xlnx,metric-count-width = <0x20>; | |
| xlnx,metrics-sample-count-width = <0x20>; | |
| xlnx,global-count-width = <0x20>; | |
| xlnx,metric-count-scale = <0x01>; | |
| clocks = <0x03 0x1c>; | |
| }; | |
| perf-monitor@fd490000 { | |
| compatible = "xlnx,axi-perf-monitor"; | |
| reg = <0x00 0xfd490000 0x00 0x10000>; | |
| interrupts = <0x00 0x7b 0x04>; | |
| interrupt-parent = <0x04>; | |
| xlnx,enable-profile = <0x00>; | |
| xlnx,enable-trace = <0x00>; | |
| xlnx,num-monitor-slots = <0x01>; | |
| xlnx,enable-event-count = <0x01>; | |
| xlnx,enable-event-log = <0x00>; | |
| xlnx,have-sampled-metric-cnt = <0x01>; | |
| xlnx,num-of-counters = <0x08>; | |
| xlnx,metric-count-width = <0x20>; | |
| xlnx,metrics-sample-count-width = <0x20>; | |
| xlnx,global-count-width = <0x20>; | |
| xlnx,metric-count-scale = <0x01>; | |
| clocks = <0x03 0x1c>; | |
| }; | |
| perf-monitor@ffa10000 { | |
| compatible = "xlnx,axi-perf-monitor"; | |
| reg = <0x00 0xffa10000 0x00 0x10000>; | |
| interrupts = <0x00 0x19 0x04>; | |
| interrupt-parent = <0x04>; | |
| xlnx,enable-profile = <0x00>; | |
| xlnx,enable-trace = <0x00>; | |
| xlnx,num-monitor-slots = <0x01>; | |
| xlnx,enable-event-count = <0x01>; | |
| xlnx,enable-event-log = <0x01>; | |
| xlnx,have-sampled-metric-cnt = <0x01>; | |
| xlnx,num-of-counters = <0x08>; | |
| xlnx,metric-count-width = <0x20>; | |
| xlnx,metrics-sample-count-width = <0x20>; | |
| xlnx,global-count-width = <0x20>; | |
| xlnx,metric-count-scale = <0x01>; | |
| clocks = <0x03 0x1f>; | |
| }; | |
| pcie@fd0e0000 { | |
| compatible = "xlnx,nwl-pcie-2.11"; | |
| status = "okay"; | |
| #address-cells = <0x03>; | |
| #size-cells = <0x02>; | |
| #interrupt-cells = <0x01>; | |
| msi-controller; | |
| device_type = "pci"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x76 0x04 0x00 0x75 0x04 0x00 0x74 0x04 0x00 0x73 0x04 0x00 0x72 0x04>; | |
| interrupt-names = "misc\0dummy\0intx\0msi1\0msi0"; | |
| msi-parent = <0x19>; | |
| reg = <0x00 0xfd0e0000 0x00 0x1000 0x00 0xfd480000 0x00 0x1000 0x80 0x00 0x00 0x1000000>; | |
| reg-names = "breg\0pcireg\0cfg"; | |
| ranges = <0x2000000 0x00 0xe0000000 0x00 0xe0000000 0x00 0x10000000 0x43000000 0x06 0x00 0x06 0x00 0x02 0x00>; | |
| bus-range = <0x00 0xff>; | |
| interrupt-map-mask = <0x00 0x00 0x00 0x07>; | |
| interrupt-map = <0x00 0x00 0x00 0x01 0x1a 0x01 0x00 0x00 0x00 0x02 0x1a 0x02 0x00 0x00 0x00 0x03 0x1a 0x03 0x00 0x00 0x00 0x04 0x1a 0x04>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x4d0>; | |
| power-domains = <0x0c 0x3b>; | |
| clocks = <0x03 0x17>; | |
| phandle = <0x19>; | |
| legacy-interrupt-controller { | |
| interrupt-controller; | |
| #address-cells = <0x00>; | |
| #interrupt-cells = <0x01>; | |
| phandle = <0x1a>; | |
| }; | |
| }; | |
| spi@ff0f0000 { | |
| u-boot,dm-pre-reloc; | |
| compatible = "xlnx,zynqmp-qspi-1.0"; | |
| status = "okay"; | |
| clock-names = "ref_clk\0pclk"; | |
| interrupts = <0x00 0x0f 0x04>; | |
| interrupt-parent = <0x04>; | |
| num-cs = <0x01>; | |
| reg = <0x00 0xff0f0000 0x00 0x1000 0x00 0xc0000000 0x00 0x8000000>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x873>; | |
| power-domains = <0x0c 0x2d>; | |
| clocks = <0x03 0x35 0x03 0x1f>; | |
| is-dual = <0x01>; | |
| flash@0 { | |
| compatible = "m25p80\0jedec,spi-nor"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| reg = <0x00>; | |
| spi-tx-bus-width = <0x01>; | |
| spi-rx-bus-width = <0x04>; | |
| spi-max-frequency = <0x66ff300>; | |
| partition@0 { | |
| label = "qspi-fsbl-uboot"; | |
| reg = <0x00 0x100000>; | |
| }; | |
| partition@100000 { | |
| label = "qspi-linux"; | |
| reg = <0x100000 0x500000>; | |
| }; | |
| partition@600000 { | |
| label = "qspi-device-tree"; | |
| reg = <0x600000 0x20000>; | |
| }; | |
| partition@620000 { | |
| label = "qspi-rootfs"; | |
| reg = <0x620000 0x5e0000>; | |
| }; | |
| }; | |
| }; | |
| phy@fd400000 { | |
| compatible = "xlnx,zynqmp-psgtr-v1.1"; | |
| status = "okay"; | |
| reg = <0x00 0xfd400000 0x00 0x40000 0x00 0xfd3d0000 0x00 0x1000>; | |
| reg-names = "serdes\0siou"; | |
| #phy-cells = <0x04>; | |
| clocks = <0x1b 0x00 0x05 0x1b 0x00 0x03 0x1b 0x00 0x02 0x1b 0x00 0x00>; | |
| clock-names = "ref0\0ref1\0ref2\0ref3"; | |
| phandle = <0x1d>; | |
| }; | |
| rtc@ffa60000 { | |
| compatible = "xlnx,zynqmp-rtc"; | |
| status = "okay"; | |
| reg = <0x00 0xffa60000 0x00 0x100>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x1a 0x04 0x00 0x1b 0x04>; | |
| interrupt-names = "alarm\0sec"; | |
| calibration = <0x7fff>; | |
| }; | |
| ahci@fd0c0000 { | |
| compatible = "ceva,ahci-1v84"; | |
| status = "okay"; | |
| reg = <0x00 0xfd0c0000 0x00 0x2000>; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x85 0x04>; | |
| power-domains = <0x0c 0x1c>; | |
| resets = <0x1c 0x10>; | |
| #stream-id-cells = <0x04>; | |
| clocks = <0x03 0x16>; | |
| ceva,p0-cominit-params = <0x18401828>; | |
| ceva,p0-comwake-params = <0x614080e>; | |
| ceva,p0-burst-params = <0x13084a06>; | |
| ceva,p0-retry-params = <0x96a43ffc>; | |
| ceva,p1-cominit-params = <0x18401828>; | |
| ceva,p1-comwake-params = <0x614080e>; | |
| ceva,p1-burst-params = <0x13084a06>; | |
| ceva,p1-retry-params = <0x96a43ffc>; | |
| phy-names = "sata-phy"; | |
| phys = <0x1d 0x03 0x01 0x01 0x01>; | |
| }; | |
| mmc@ff160000 { | |
| u-boot,dm-pre-reloc; | |
| compatible = "xlnx,zynqmp-8.9a\0arasan,sdhci-8.9a"; | |
| status = "disabled"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x30 0x04>; | |
| reg = <0x00 0xff160000 0x00 0x1000>; | |
| clock-names = "clk_xin\0clk_ahb"; | |
| xlnx,device_id = <0x00>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x870>; | |
| nvmem-cells = <0x1e>; | |
| nvmem-cell-names = "soc_revision"; | |
| #clock-cells = <0x01>; | |
| clock-output-names = "clk_out_sd0\0clk_in_sd0"; | |
| power-domains = <0x0c 0x27>; | |
| clocks = <0x03 0x36 0x03 0x1f>; | |
| }; | |
| mmc@ff170000 { | |
| u-boot,dm-pre-reloc; | |
| compatible = "xlnx,zynqmp-8.9a\0arasan,sdhci-8.9a"; | |
| status = "okay"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x31 0x04>; | |
| reg = <0x00 0xff170000 0x00 0x1000>; | |
| clock-names = "clk_xin\0clk_ahb"; | |
| xlnx,device_id = <0x01>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x871>; | |
| nvmem-cells = <0x1e>; | |
| nvmem-cell-names = "soc_revision"; | |
| #clock-cells = <0x01>; | |
| clock-output-names = "clk_out_sd1\0clk_in_sd1"; | |
| power-domains = <0x0c 0x28>; | |
| clocks = <0x03 0x37 0x03 0x1f>; | |
| no-1-8-v; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x1f>; | |
| xlnx,mio-bank = <0x01>; | |
| }; | |
| spi@ff040000 { | |
| compatible = "cdns,spi-r1p6"; | |
| status = "okay"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x13 0x04>; | |
| reg = <0x00 0xff040000 0x00 0x1000>; | |
| clock-names = "ref_clk\0pclk"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x0c 0x23>; | |
| clocks = <0x03 0x3a 0x03 0x1f>; | |
| ad9081@0 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "adi,ad9081"; | |
| reg = <0x00>; | |
| spi-max-frequency = <0x4c4b40>; | |
| clocks = <0x20 0x02>; | |
| clock-names = "dev_clk"; | |
| clock-output-names = "rx_sampl_clk\0tx_sampl_clk"; | |
| #clock-cells = <0x01>; | |
| jesd204-device; | |
| #jesd204-cells = <0x02>; | |
| jesd204-top-device = <0x00>; | |
| jesd204-link-ids = <0x02 0x00>; | |
| jesd204-inputs = <0x21 0x00 0x02 0x22 0x00 0x00>; | |
| reset-gpios = <0x14 0x85 0x00>; | |
| sysref-req-gpios = <0x14 0x79 0x00>; | |
| rx2-enable-gpios = <0x14 0x87 0x00>; | |
| rx1-enable-gpios = <0x14 0x86 0x00>; | |
| tx2-enable-gpios = <0x14 0x89 0x00>; | |
| tx1-enable-gpios = <0x14 0x88 0x00>; | |
| phandle = <0x47>; | |
| adi,tx-dacs { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| adi,dac-frequency-hz = <0x02 0xcb417800>; | |
| adi,main-data-paths { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| adi,interpolation = <0x08>; | |
| dac@0 { | |
| reg = <0x00>; | |
| adi,crossbar-select = <0x23>; | |
| adi,nco-frequency-shift-hz = <0x00 0x3b9aca00>; | |
| }; | |
| dac@1 { | |
| reg = <0x01>; | |
| adi,crossbar-select = <0x24>; | |
| adi,nco-frequency-shift-hz = <0x00 0x4190ab00>; | |
| }; | |
| dac@2 { | |
| reg = <0x02>; | |
| adi,crossbar-select = <0x25>; | |
| adi,nco-frequency-shift-hz = <0x00 0x47868c00>; | |
| }; | |
| dac@3 { | |
| reg = <0x03>; | |
| adi,crossbar-select = <0x26>; | |
| adi,nco-frequency-shift-hz = <0x00 0x4d7c6d00>; | |
| }; | |
| }; | |
| adi,channelizer-paths { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| adi,interpolation = <0x06>; | |
| channel@0 { | |
| reg = <0x00>; | |
| adi,gain = <0x800>; | |
| adi,nco-frequency-shift-hz = <0x00 0x00>; | |
| phandle = <0x23>; | |
| }; | |
| channel@1 { | |
| reg = <0x01>; | |
| adi,gain = <0x800>; | |
| adi,nco-frequency-shift-hz = <0x00 0x00>; | |
| phandle = <0x24>; | |
| }; | |
| channel@2 { | |
| reg = <0x02>; | |
| adi,gain = <0x800>; | |
| adi,nco-frequency-shift-hz = <0x00 0x00>; | |
| phandle = <0x25>; | |
| }; | |
| channel@3 { | |
| reg = <0x03>; | |
| adi,gain = <0x800>; | |
| adi,nco-frequency-shift-hz = <0x00 0x00>; | |
| phandle = <0x26>; | |
| }; | |
| }; | |
| adi,jesd-links { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| link@0 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| reg = <0x00>; | |
| adi,converter-select = <0x23 0x00 0x23 0x01 0x24 0x00 0x24 0x01>; | |
| adi,logical-lane-mapping = <0x20707 0x1070703>; | |
| adi,link-mode = <0x09>; | |
| adi,subclass = <0x01>; | |
| adi,version = <0x01>; | |
| adi,dual-link = <0x00>; | |
| adi,converters-per-device = <0x08>; | |
| adi,octets-per-frame = <0x04>; | |
| adi,frames-per-multiframe = <0x20>; | |
| adi,converter-resolution = <0x10>; | |
| adi,bits-per-sample = <0x10>; | |
| adi,control-bits-per-sample = <0x00>; | |
| adi,lanes-per-device = <0x04>; | |
| adi,samples-per-converter-per-frame = <0x01>; | |
| adi,high-density = <0x00>; | |
| adi,tpl-phase-adjust = <0x03>; | |
| }; | |
| }; | |
| }; | |
| adi,rx-adcs { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| adi,adc-frequency-hz = <0x00 0xee6b2800>; | |
| adi,main-data-paths { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| adc@0 { | |
| reg = <0x00>; | |
| adi,decimation = <0x04>; | |
| adi,nco-frequency-shift-hz = <0x00 0x17d78400>; | |
| adi,nco-mixer-mode = <0x00>; | |
| }; | |
| adc@1 { | |
| reg = <0x01>; | |
| adi,decimation = <0x04>; | |
| adi,nco-frequency-shift-hz = <0xffffffff 0xe8287c00>; | |
| adi,nco-mixer-mode = <0x00>; | |
| }; | |
| adc@2 { | |
| reg = <0x02>; | |
| adi,decimation = <0x04>; | |
| adi,nco-frequency-shift-hz = <0x00 0x5f5e100>; | |
| adi,nco-mixer-mode = <0x00>; | |
| }; | |
| adc@3 { | |
| reg = <0x03>; | |
| adi,decimation = <0x04>; | |
| adi,nco-frequency-shift-hz = <0x00 0x5f5e100>; | |
| adi,nco-mixer-mode = <0x00>; | |
| }; | |
| }; | |
| adi,channelizer-paths { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| channel@0 { | |
| reg = <0x00>; | |
| adi,decimation = <0x04>; | |
| adi,gain = <0x800>; | |
| adi,nco-frequency-shift-hz = <0x00 0x00>; | |
| phandle = <0x27>; | |
| }; | |
| channel@1 { | |
| reg = <0x01>; | |
| adi,decimation = <0x04>; | |
| adi,gain = <0x800>; | |
| adi,nco-frequency-shift-hz = <0x00 0x00>; | |
| phandle = <0x28>; | |
| }; | |
| channel@4 { | |
| reg = <0x04>; | |
| adi,decimation = <0x04>; | |
| adi,gain = <0x800>; | |
| adi,nco-frequency-shift-hz = <0x00 0x00>; | |
| phandle = <0x29>; | |
| }; | |
| channel@5 { | |
| reg = <0x05>; | |
| adi,decimation = <0x04>; | |
| adi,gain = <0x800>; | |
| adi,nco-frequency-shift-hz = <0x00 0x00>; | |
| phandle = <0x2a>; | |
| }; | |
| }; | |
| adi,jesd-links { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| link@0 { | |
| reg = <0x00>; | |
| adi,converter-select = <0x27 0x00 0x27 0x01 0x28 0x00 0x28 0x01 0x29 0x00 0x29 0x01 0x2a 0x00 0x2a 0x01>; | |
| adi,logical-lane-mapping = <0x2000707 0x7070301>; | |
| adi,link-mode = <0x0a>; | |
| adi,subclass = <0x01>; | |
| adi,version = <0x01>; | |
| adi,dual-link = <0x00>; | |
| adi,converters-per-device = <0x08>; | |
| adi,octets-per-frame = <0x04>; | |
| adi,frames-per-multiframe = <0x20>; | |
| adi,converter-resolution = <0x10>; | |
| adi,bits-per-sample = <0x10>; | |
| adi,control-bits-per-sample = <0x00>; | |
| adi,lanes-per-device = <0x04>; | |
| adi,samples-per-converter-per-frame = <0x01>; | |
| adi,high-density = <0x00>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| }; | |
| spi@ff050000 { | |
| compatible = "cdns,spi-r1p6"; | |
| status = "okay"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x14 0x04>; | |
| reg = <0x00 0xff050000 0x00 0x1000>; | |
| clock-names = "ref_clk\0pclk"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| power-domains = <0x0c 0x24>; | |
| clocks = <0x03 0x3b 0x03 0x1f>; | |
| hmc7044@0 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| #clock-cells = <0x01>; | |
| compatible = "adi,hmc7044"; | |
| reg = <0x00>; | |
| spi-max-frequency = <0xf4240>; | |
| jesd204-device; | |
| #jesd204-cells = <0x02>; | |
| jesd204-sysref-provider; | |
| adi,jesd204-max-sysref-frequency-hz = <0x1e8480>; | |
| adi,pll1-clkin-frequencies = <0x5f5e100 0x5f5e100 0x00 0x00>; | |
| adi,vcxo-frequency = <0x5f5e100>; | |
| adi,pll1-loop-bandwidth-hz = <0xc8>; | |
| adi,pll2-output-frequency = <0xb2d05e00>; | |
| adi,sysref-timer-divider = <0x400>; | |
| adi,pulse-generator-mode = <0x00>; | |
| adi,clkin0-buffer-mode = <0x07>; | |
| adi,clkin1-buffer-mode = <0x07>; | |
| adi,oscin-buffer-mode = <0x15>; | |
| adi,gpi-controls = <0x00 0x00 0x00 0x00>; | |
| adi,gpo-controls = <0x37 0x33 0x00 0x00>; | |
| clock-output-names = "hmc7044_out0\0hmc7044_out1\0hmc7044_out2\0hmc7044_out3\0hmc7044_out4\0hmc7044_out5\0hmc7044_out6\0hmc7044_out7\0hmc7044_out8\0hmc7044_out9\0hmc7044_out10\0hmc7044_out11\0hmc7044_out12\0hmc7044_out13"; | |
| adi,pll1-ref-prio-ctrl = <0xe1>; | |
| adi,pll1-ref-autorevert-enable; | |
| phandle = <0x20>; | |
| channel@0 { | |
| reg = <0x00>; | |
| adi,extended-name = "CORE_CLK_RX"; | |
| adi,divider = <0x0c>; | |
| adi,driver-mode = <0x02>; | |
| }; | |
| channel@2 { | |
| reg = <0x02>; | |
| adi,extended-name = "DEV_REFCLK"; | |
| adi,divider = <0x0c>; | |
| adi,driver-mode = <0x02>; | |
| }; | |
| channel@3 { | |
| reg = <0x03>; | |
| adi,extended-name = "DEV_SYSREF"; | |
| adi,divider = <0x600>; | |
| adi,driver-mode = <0x02>; | |
| adi,jesd204-sysref-chan; | |
| }; | |
| channel@6 { | |
| reg = <0x06>; | |
| adi,extended-name = "CORE_CLK_TX"; | |
| adi,divider = <0x0c>; | |
| adi,driver-mode = <0x02>; | |
| }; | |
| channel@8 { | |
| reg = <0x08>; | |
| adi,extended-name = "FPGA_REFCLK1"; | |
| adi,divider = <0x06>; | |
| adi,driver-mode = <0x02>; | |
| }; | |
| channel@10 { | |
| reg = <0x0a>; | |
| adi,extended-name = "CORE_CLK_RX_ALT"; | |
| adi,divider = <0x0c>; | |
| adi,driver-mode = <0x02>; | |
| }; | |
| channel@12 { | |
| reg = <0x0c>; | |
| adi,extended-name = "FPGA_REFCLK2"; | |
| adi,divider = <0x06>; | |
| adi,driver-mode = <0x02>; | |
| }; | |
| channel@13 { | |
| reg = <0x0d>; | |
| adi,extended-name = "FPGA_SYSREF"; | |
| adi,divider = <0x600>; | |
| adi,driver-mode = <0x02>; | |
| adi,jesd204-sysref-chan; | |
| }; | |
| }; | |
| }; | |
| timer@ff110000 { | |
| compatible = "cdns,ttc"; | |
| status = "disabled"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x24 0x04 0x00 0x25 0x04 0x00 0x26 0x04>; | |
| reg = <0x00 0xff110000 0x00 0x1000>; | |
| timer-width = <0x20>; | |
| power-domains = <0x0c 0x18>; | |
| clocks = <0x03 0x1f>; | |
| }; | |
| timer@ff120000 { | |
| compatible = "cdns,ttc"; | |
| status = "disabled"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x27 0x04 0x00 0x28 0x04 0x00 0x29 0x04>; | |
| reg = <0x00 0xff120000 0x00 0x1000>; | |
| timer-width = <0x20>; | |
| power-domains = <0x0c 0x19>; | |
| clocks = <0x03 0x1f>; | |
| }; | |
| timer@ff130000 { | |
| compatible = "cdns,ttc"; | |
| status = "disabled"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x2a 0x04 0x00 0x2b 0x04 0x00 0x2c 0x04>; | |
| reg = <0x00 0xff130000 0x00 0x1000>; | |
| timer-width = <0x20>; | |
| power-domains = <0x0c 0x1a>; | |
| clocks = <0x03 0x1f>; | |
| }; | |
| timer@ff140000 { | |
| compatible = "cdns,ttc"; | |
| status = "disabled"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x2d 0x04 0x00 0x2e 0x04 0x00 0x2f 0x04>; | |
| reg = <0x00 0xff140000 0x00 0x1000>; | |
| timer-width = <0x20>; | |
| power-domains = <0x0c 0x1b>; | |
| clocks = <0x03 0x1f>; | |
| }; | |
| serial@ff000000 { | |
| u-boot,dm-pre-reloc; | |
| compatible = "cdns,uart-r1p12\0xlnx,xuartps"; | |
| status = "okay"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x15 0x04>; | |
| reg = <0x00 0xff000000 0x00 0x1000>; | |
| clock-names = "uart_clk\0pclk"; | |
| power-domains = <0x0c 0x21>; | |
| clocks = <0x03 0x38 0x03 0x1f>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x2b>; | |
| }; | |
| serial@ff010000 { | |
| u-boot,dm-pre-reloc; | |
| compatible = "cdns,uart-r1p12\0xlnx,xuartps"; | |
| status = "okay"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x16 0x04>; | |
| reg = <0x00 0xff010000 0x00 0x1000>; | |
| clock-names = "uart_clk\0pclk"; | |
| power-domains = <0x0c 0x22>; | |
| clocks = <0x03 0x39 0x03 0x1f>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x2c>; | |
| }; | |
| usb0@ff9d0000 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| status = "okay"; | |
| compatible = "xlnx,zynqmp-dwc3"; | |
| reg = <0x00 0xff9d0000 0x00 0x100>; | |
| clock-names = "bus_clk\0ref_clk"; | |
| power-domains = <0x0c 0x16>; | |
| resets = <0x1c 0x3b 0x1c 0x3d 0x1c 0x3f>; | |
| reset-names = "usb_crst\0usb_hibrst\0usb_apbrst"; | |
| reset-gpio = <0x2d 0x01 0x00>; | |
| ranges; | |
| nvmem-cells = <0x1e>; | |
| nvmem-cell-names = "soc_revision"; | |
| clocks = <0x03 0x20 0x03 0x22>; | |
| pinctrl-names = "default"; | |
| pinctrl-0 = <0x2e>; | |
| dwc3@fe200000 { | |
| compatible = "snps,dwc3"; | |
| status = "okay"; | |
| reg = <0x00 0xfe200000 0x00 0x40000>; | |
| interrupt-parent = <0x04>; | |
| interrupt-names = "dwc_usb3\0otg\0hiber"; | |
| interrupts = <0x00 0x41 0x04 0x00 0x45 0x04 0x00 0x4b 0x04>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x860>; | |
| snps,quirk-frame-length-adjustment = <0x20>; | |
| snps,refclk_fladj; | |
| snps,enable_guctl1_resume_quirk; | |
| snps,enable_guctl1_ipd_quirk; | |
| snps,xhci-stream-quirk; | |
| dr_mode = "host"; | |
| snps,usb3_lpm_capable; | |
| phy-names = "usb3-phy"; | |
| phys = <0x1d 0x02 0x04 0x00 0x02>; | |
| maximum-speed = "super-speed"; | |
| }; | |
| }; | |
| usb1@ff9e0000 { | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| status = "disabled"; | |
| compatible = "xlnx,zynqmp-dwc3"; | |
| reg = <0x00 0xff9e0000 0x00 0x100>; | |
| clock-names = "bus_clk\0ref_clk"; | |
| power-domains = <0x0c 0x17>; | |
| resets = <0x1c 0x3c 0x1c 0x3e 0x1c 0x40>; | |
| reset-names = "usb_crst\0usb_hibrst\0usb_apbrst"; | |
| ranges; | |
| nvmem-cells = <0x1e>; | |
| nvmem-cell-names = "soc_revision"; | |
| clocks = <0x03 0x21 0x03 0x22>; | |
| dwc3@fe300000 { | |
| compatible = "snps,dwc3"; | |
| status = "disabled"; | |
| reg = <0x00 0xfe300000 0x00 0x40000>; | |
| interrupt-parent = <0x04>; | |
| interrupt-names = "dwc_usb3\0otg\0hiber"; | |
| interrupts = <0x00 0x46 0x04 0x00 0x4a 0x04 0x00 0x4c 0x04>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0x861>; | |
| snps,quirk-frame-length-adjustment = <0x20>; | |
| snps,refclk_fladj; | |
| snps,enable_guctl1_resume_quirk; | |
| snps,enable_guctl1_ipd_quirk; | |
| snps,xhci-stream-quirk; | |
| }; | |
| }; | |
| watchdog@fd4d0000 { | |
| compatible = "cdns,wdt-r1p2"; | |
| status = "okay"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x71 0x01>; | |
| reg = <0x00 0xfd4d0000 0x00 0x1000>; | |
| timeout-sec = <0x3c>; | |
| reset-on-timeout; | |
| clocks = <0x03 0x4b>; | |
| }; | |
| watchdog@ff150000 { | |
| compatible = "cdns,wdt-r1p2"; | |
| status = "disabled"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x34 0x01>; | |
| reg = <0x00 0xff150000 0x00 0x1000>; | |
| timeout-sec = <0x0a>; | |
| clocks = <0x03 0x70>; | |
| }; | |
| ams@ffa50000 { | |
| compatible = "xlnx,zynqmp-ams"; | |
| status = "okay"; | |
| interrupt-parent = <0x04>; | |
| interrupts = <0x00 0x38 0x04>; | |
| interrupt-names = "ams-irq"; | |
| reg = <0x00 0xffa50000 0x00 0x800>; | |
| reg-names = "ams-base"; | |
| #address-cells = <0x02>; | |
| #size-cells = <0x02>; | |
| #io-channel-cells = <0x01>; | |
| ranges; | |
| clocks = <0x03 0x46>; | |
| ams_ps@ffa50800 { | |
| compatible = "xlnx,zynqmp-ams-ps"; | |
| status = "okay"; | |
| reg = <0x00 0xffa50800 0x00 0x400>; | |
| }; | |
| ams_pl@ffa50c00 { | |
| compatible = "xlnx,zynqmp-ams-pl"; | |
| status = "okay"; | |
| reg = <0x00 0xffa50c00 0x00 0x400>; | |
| }; | |
| }; | |
| dma-controller@fd4c0000 { | |
| compatible = "xlnx,zynqmp-dpdma"; | |
| status = "okay"; | |
| reg = <0x00 0xfd4c0000 0x00 0x1000>; | |
| interrupts = <0x00 0x7a 0x04>; | |
| interrupt-parent = <0x04>; | |
| clock-names = "axi_clk"; | |
| power-domains = <0x0c 0x29>; | |
| dma-channels = <0x06>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0xce4>; | |
| #dma-cells = <0x01>; | |
| clocks = <0x03 0x14>; | |
| phandle = <0x2f>; | |
| }; | |
| display@fd4a0000 { | |
| compatible = "xlnx,zynqmp-dpsub-1.7"; | |
| status = "okay"; | |
| reg = <0x00 0xfd4a0000 0x00 0x1000 0x00 0xfd4aa000 0x00 0x1000 0x00 0xfd4ab000 0x00 0x1000 0x00 0xfd4ac000 0x00 0x1000>; | |
| reg-names = "dp\0blend\0av_buf\0aud"; | |
| interrupts = <0x00 0x77 0x04>; | |
| interrupt-parent = <0x04>; | |
| #stream-id-cells = <0x01>; | |
| iommus = <0x0e 0xce3>; | |
| clock-names = "dp_apb_clk\0dp_aud_clk\0dp_vtc_pixel_clk_in"; | |
| power-domains = <0x0c 0x29>; | |
| resets = <0x1c 0x03>; | |
| dma-names = "vid0\0vid1\0vid2\0gfx0"; | |
| dmas = <0x2f 0x00 0x2f 0x01 0x2f 0x02 0x2f 0x03>; | |
| clocks = <0x30 0x03 0x11 0x03 0x10>; | |
| phy-names = "dp-phy0"; | |
| phys = <0x1d 0x01 0x06 0x00 0x03>; | |
| i2c-bus { | |
| }; | |
| zynqmp_dp_snd_codec0 { | |
| compatible = "xlnx,dp-snd-codec"; | |
| clock-names = "aud_clk"; | |
| clocks = <0x03 0x11>; | |
| status = "okay"; | |
| phandle = <0x33>; | |
| }; | |
| zynqmp_dp_snd_pcm0 { | |
| compatible = "xlnx,dp-snd-pcm"; | |
| dmas = <0x2f 0x04>; | |
| dma-names = "tx"; | |
| status = "okay"; | |
| phandle = <0x31>; | |
| }; | |
| zynqmp_dp_snd_pcm1 { | |
| compatible = "xlnx,dp-snd-pcm"; | |
| dmas = <0x2f 0x05>; | |
| dma-names = "tx"; | |
| status = "okay"; | |
| phandle = <0x32>; | |
| }; | |
| zynqmp_dp_snd_card { | |
| compatible = "xlnx,dp-snd-card"; | |
| xlnx,dp-snd-pcm = <0x31 0x32>; | |
| xlnx,dp-snd-codec = <0x33>; | |
| status = "okay"; | |
| }; | |
| }; | |
| }; | |
| fclk0 { | |
| status = "okay"; | |
| compatible = "xlnx,fclk"; | |
| clocks = <0x03 0x47>; | |
| }; | |
| fclk1 { | |
| status = "okay"; | |
| compatible = "xlnx,fclk"; | |
| clocks = <0x03 0x48>; | |
| }; | |
| fclk2 { | |
| status = "okay"; | |
| compatible = "xlnx,fclk"; | |
| clocks = <0x03 0x49>; | |
| }; | |
| fclk3 { | |
| status = "okay"; | |
| compatible = "xlnx,fclk"; | |
| clocks = <0x03 0x4a>; | |
| }; | |
| pss_ref_clk { | |
| u-boot,dm-pre-reloc; | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x1fca055>; | |
| phandle = <0x06>; | |
| }; | |
| video_clk { | |
| u-boot,dm-pre-reloc; | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x19bfcc0>; | |
| phandle = <0x07>; | |
| }; | |
| pss_alt_ref_clk { | |
| u-boot,dm-pre-reloc; | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x00>; | |
| phandle = <0x08>; | |
| }; | |
| gt_crx_ref_clk { | |
| u-boot,dm-pre-reloc; | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x66ff300>; | |
| phandle = <0x0a>; | |
| }; | |
| aux_ref_clk { | |
| u-boot,dm-pre-reloc; | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x19bfcc0>; | |
| phandle = <0x09>; | |
| }; | |
| dp_aclk { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x5f5e100>; | |
| clock-accuracy = <0x64>; | |
| phandle = <0x30>; | |
| }; | |
| aliases { | |
| ethernet0 = "/axi/ethernet@ff0e0000"; | |
| gpio0 = "/axi/gpio@ff0a0000"; | |
| i2c0 = "/axi/i2c@ff020000"; | |
| i2c1 = "/axi/i2c@ff030000"; | |
| mmc0 = "/axi/mmc@ff170000"; | |
| rtc0 = "/axi/rtc@ffa60000"; | |
| serial0 = "/axi/serial@ff000000"; | |
| serial1 = "/axi/serial@ff010000"; | |
| serial2 = "/dcc"; | |
| spi0 = "/axi/spi@ff0f0000"; | |
| usb0 = "/axi/usb0@ff9d0000"; | |
| }; | |
| chosen { | |
| bootargs = "earlycon"; | |
| stdout-path = "serial0:115200n8"; | |
| xlnx,eeprom = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54"; | |
| }; | |
| memory@0 { | |
| device_type = "memory"; | |
| reg = <0x00 0x00 0x00 0x80000000 0x08 0x00 0x00 0x80000000>; | |
| }; | |
| gpio-keys { | |
| compatible = "gpio-keys"; | |
| autorepeat; | |
| sw19 { | |
| label = "sw19"; | |
| gpios = <0x14 0x16 0x00>; | |
| linux,code = <0x6c>; | |
| wakeup-source; | |
| autorepeat; | |
| }; | |
| }; | |
| leds { | |
| compatible = "gpio-leds"; | |
| heartbeat-led { | |
| label = "heartbeat"; | |
| gpios = <0x14 0x17 0x00>; | |
| linux,default-trigger = "heartbeat"; | |
| }; | |
| }; | |
| ina226-u76 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x34 0x00 0x34 0x01 0x34 0x02 0x34 0x03>; | |
| }; | |
| ina226-u77 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x35 0x00 0x35 0x01 0x35 0x02 0x35 0x03>; | |
| }; | |
| ina226-u78 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x36 0x00 0x36 0x01 0x36 0x02 0x36 0x03>; | |
| }; | |
| ina226-u87 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x37 0x00 0x37 0x01 0x37 0x02 0x37 0x03>; | |
| }; | |
| ina226-u85 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x38 0x00 0x38 0x01 0x38 0x02 0x38 0x03>; | |
| }; | |
| ina226-u86 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x39 0x00 0x39 0x01 0x39 0x02 0x39 0x03>; | |
| }; | |
| ina226-u93 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x3a 0x00 0x3a 0x01 0x3a 0x02 0x3a 0x03>; | |
| }; | |
| ina226-u88 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x3b 0x00 0x3b 0x01 0x3b 0x02 0x3b 0x03>; | |
| }; | |
| ina226-u15 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x3c 0x00 0x3c 0x01 0x3c 0x02 0x3c 0x03>; | |
| }; | |
| ina226-u92 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x3d 0x00 0x3d 0x01 0x3d 0x02 0x3d 0x03>; | |
| }; | |
| ina226-u79 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x3e 0x00 0x3e 0x01 0x3e 0x02 0x3e 0x03>; | |
| }; | |
| ina226-u81 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x3f 0x00 0x3f 0x01 0x3f 0x02 0x3f 0x03>; | |
| }; | |
| ina226-u80 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x40 0x00 0x40 0x01 0x40 0x02 0x40 0x03>; | |
| }; | |
| ina226-u84 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x41 0x00 0x41 0x01 0x41 0x02 0x41 0x03>; | |
| }; | |
| ina226-u16 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x42 0x00 0x42 0x01 0x42 0x02 0x42 0x03>; | |
| }; | |
| ina226-u65 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x43 0x00 0x43 0x01 0x43 0x02 0x43 0x03>; | |
| }; | |
| ina226-u74 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x44 0x00 0x44 0x01 0x44 0x02 0x44 0x03>; | |
| }; | |
| ina226-u75 { | |
| compatible = "iio-hwmon"; | |
| io-channels = <0x45 0x00 0x45 0x01 0x45 0x02 0x45 0x03>; | |
| }; | |
| ref48M { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x2dc6c00>; | |
| phandle = <0x17>; | |
| }; | |
| refhdmi { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x6cfd9c8>; | |
| phandle = <0x18>; | |
| }; | |
| fpga-axi@0 { | |
| interrupt-parent = <0x04>; | |
| compatible = "simple-bus"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x01>; | |
| ranges = <0x00 0x00 0x00 0xffffffff>; | |
| dma@9c420000 { | |
| compatible = "adi,axi-dmac-1.00.a"; | |
| reg = <0x9c420000 0x10000>; | |
| #dma-cells = <0x01>; | |
| #clock-cells = <0x00>; | |
| interrupts = <0x00 0x6d 0x04>; | |
| clocks = <0x03 0x49>; | |
| phandle = <0x46>; | |
| }; | |
| dma@9c430000 { | |
| compatible = "adi,axi-dmac-1.00.a"; | |
| reg = <0x9c430000 0x10000>; | |
| #dma-cells = <0x01>; | |
| #clock-cells = <0x00>; | |
| interrupts = <0x00 0x6c 0x04>; | |
| clocks = <0x03 0x49>; | |
| phandle = <0x49>; | |
| }; | |
| axi-ad9081-rx-hpc@84a10000 { | |
| compatible = "adi,axi-ad9081-rx-1.0"; | |
| reg = <0x84a10000 0x8000>; | |
| dmas = <0x46 0x00>; | |
| dma-names = "rx"; | |
| spibus-connected = <0x47>; | |
| jesd204-device; | |
| #jesd204-cells = <0x02>; | |
| jesd204-inputs = <0x48 0x00 0x02>; | |
| phandle = <0x21>; | |
| }; | |
| axi-ad9081-tx-hpc@84b10000 { | |
| compatible = "adi,axi-ad9081-tx-1.0"; | |
| reg = <0x84b10000 0x4000>; | |
| dmas = <0x49 0x00>; | |
| dma-names = "tx"; | |
| clocks = <0x47 0x01>; | |
| clock-names = "sampl_clk"; | |
| spibus-connected = <0x47>; | |
| adi,axi-data-offload-connected = <0x4a>; | |
| jesd204-device; | |
| #jesd204-cells = <0x02>; | |
| jesd204-inputs = <0x4b 0x00 0x00>; | |
| plddrbypass-gpios = <0x14 0x8a 0x00>; | |
| adi,axi-pl-fifo-enable; | |
| phandle = <0x22>; | |
| }; | |
| axi-jesd204-rx@84a90000 { | |
| compatible = "adi,axi-jesd204-rx-1.0"; | |
| reg = <0x84a90000 0x1000>; | |
| interrupts = <0x00 0x6b 0x04>; | |
| clocks = <0x03 0x47 0x20 0x0a 0x4c 0x00>; | |
| clock-names = "s_axi_aclk\0device_clk\0lane_clk"; | |
| #clock-cells = <0x00>; | |
| clock-output-names = "jesd_rx_lane_clk"; | |
| jesd204-device; | |
| #jesd204-cells = <0x02>; | |
| jesd204-inputs = <0x4c 0x00 0x02>; | |
| phandle = <0x48>; | |
| }; | |
| axi-jesd204-tx@84b90000 { | |
| compatible = "adi,axi-jesd204-tx-1.0"; | |
| reg = <0x84b90000 0x1000>; | |
| interrupts = <0x00 0x6a 0x04>; | |
| clocks = <0x03 0x47 0x20 0x06 0x4d 0x00>; | |
| clock-names = "s_axi_aclk\0device_clk\0lane_clk"; | |
| #clock-cells = <0x00>; | |
| clock-output-names = "jesd_tx_lane_clk"; | |
| jesd204-device; | |
| #jesd204-cells = <0x02>; | |
| jesd204-inputs = <0x4d 0x00 0x00>; | |
| phandle = <0x4b>; | |
| }; | |
| axi-adxcvr-rx@84a60000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "adi,axi-adxcvr-1.0"; | |
| reg = <0x84a60000 0x1000>; | |
| clocks = <0x20 0x0c>; | |
| clock-names = "conv"; | |
| #clock-cells = <0x01>; | |
| clock-output-names = "rx_gt_clk\0rx_out_clk"; | |
| adi,sys-clk-select = <0x00>; | |
| adi,out-clk-select = <0x04>; | |
| adi,use-lpm-enable; | |
| jesd204-device; | |
| #jesd204-cells = <0x02>; | |
| jesd204-inputs = <0x20 0x00 0x02>; | |
| phandle = <0x4c>; | |
| }; | |
| axi-adxcvr-tx@84b60000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "adi,axi-adxcvr-1.0"; | |
| reg = <0x84b60000 0x1000>; | |
| clocks = <0x20 0x0c>; | |
| clock-names = "conv"; | |
| #clock-cells = <0x01>; | |
| clock-output-names = "tx_gt_clk\0tx_out_clk"; | |
| adi,sys-clk-select = <0x03>; | |
| adi,out-clk-select = <0x04>; | |
| jesd204-device; | |
| #jesd204-cells = <0x02>; | |
| jesd204-inputs = <0x20 0x00 0x00>; | |
| phandle = <0x4d>; | |
| }; | |
| axi-sysid-0@85000000 { | |
| compatible = "adi,axi-sysid-1.00.a"; | |
| reg = <0x85000000 0x10000>; | |
| }; | |
| axi-data-offload-0@9c440000 { | |
| compatible = "adi,axi-data-offload-1.0.a"; | |
| reg = <0x9c440000 0x10000>; | |
| adi,oneshot; | |
| adi,sync-config = <0x01>; | |
| phandle = <0x4a>; | |
| }; | |
| axi-data-offload-1@9c450000 { | |
| compatible = "adi,axi-data-offload-1.0.a"; | |
| reg = <0x9c450000 0x10000>; | |
| adi,oneshot; | |
| adi,sync-config = <0x01>; | |
| }; | |
| axi-tdd-0@9c460000 { | |
| compatible = "adi,axi-tdd-1.00"; | |
| reg = <0x9c460000 0x10000>; | |
| clocks = <0x03 0x47 0x20 0x06>; | |
| clock-names = "s_axi_aclk\0intf_clk"; | |
| }; | |
| spi@85200000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| bits-per-word = <0x08>; | |
| compatible = "xlnx,xps-spi-2.00.a"; | |
| fifo-size = <0x10>; | |
| interrupts = <0x00 0x6f 0x04>; | |
| num-cs = <0x08>; | |
| reg = <0x85200000 0x10000>; | |
| xlnx,num-ss-bits = <0x08>; | |
| xlnx,spi-mode = <0x00>; | |
| adar1000_csb_1@1 { | |
| compatible = "adi,adar1000"; | |
| reg = <0x01>; | |
| spi-max-frequency = <0xbebc20>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| adar1000_csb_1_1@0 { | |
| reg = <0x00>; | |
| label = "csb1_chip1"; | |
| }; | |
| adar1000_csb_1_2@1 { | |
| reg = <0x01>; | |
| label = "csb1_chip2"; | |
| }; | |
| adar1000_csb_1_3@2 { | |
| reg = <0x02>; | |
| label = "csb1_chip3"; | |
| }; | |
| adar1000_csb_1_4@3 { | |
| reg = <0x03>; | |
| label = "csb1_chip4"; | |
| }; | |
| }; | |
| adar1000_csb_2@2 { | |
| compatible = "adi,adar1000"; | |
| reg = <0x02>; | |
| spi-max-frequency = <0xbebc20>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| adar1000_csb_2_1@0 { | |
| reg = <0x00>; | |
| label = "csb2_chip1"; | |
| }; | |
| adar1000_csb_2_2@1 { | |
| reg = <0x01>; | |
| label = "csb2_chip2"; | |
| }; | |
| adar1000_csb_2_3@2 { | |
| reg = <0x02>; | |
| label = "csb2_chip3"; | |
| }; | |
| adar1000_csb_2_4@3 { | |
| reg = <0x03>; | |
| label = "csb2_chip4"; | |
| }; | |
| }; | |
| adar1000_csb_3@3 { | |
| compatible = "adi,adar1000"; | |
| reg = <0x03>; | |
| spi-max-frequency = <0xbebc20>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| adar1000_csb_3_1@0 { | |
| reg = <0x00>; | |
| label = "csb3_chip1"; | |
| }; | |
| adar1000_csb_3_2@1 { | |
| reg = <0x01>; | |
| label = "csb3_chip2"; | |
| }; | |
| adar1000_csb_3_3@2 { | |
| reg = <0x02>; | |
| label = "csb3_chip3"; | |
| }; | |
| adar1000_csb_3_4@3 { | |
| reg = <0x03>; | |
| label = "csb3_chip4"; | |
| }; | |
| }; | |
| adar1000_csb_4@4 { | |
| compatible = "adi,adar1000"; | |
| reg = <0x04>; | |
| spi-max-frequency = <0xbebc20>; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| adar1000_csb_4_1@0 { | |
| reg = <0x00>; | |
| label = "csb4_chip1"; | |
| }; | |
| adar1000_csb_4_2@1 { | |
| reg = <0x01>; | |
| label = "csb4_chip2"; | |
| }; | |
| adar1000_csb_4_3@2 { | |
| reg = <0x02>; | |
| label = "csb4_chip3"; | |
| }; | |
| adar1000_csb_4_4@3 { | |
| reg = <0x03>; | |
| label = "csb4_chip4"; | |
| }; | |
| }; | |
| ltc2314@5 { | |
| compatible = "adi,ltc2314-14"; | |
| reg = <0x05>; | |
| spi-max-frequency = <0xbebc20>; | |
| vcc-supply = <0x4e>; | |
| }; | |
| }; | |
| spi@85300000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| bits-per-word = <0x08>; | |
| compatible = "xlnx,xps-spi-2.00.a"; | |
| fifo-size = <0x10>; | |
| interrupts = <0x00 0x69 0x04>; | |
| num-cs = <0x08>; | |
| reg = <0x85300000 0x10000>; | |
| xlnx,num-ss-bits = <0x08>; | |
| xlnx,spi-mode = <0x00>; | |
| adf4371-0@6 { | |
| compatible = "adi,adf4371"; | |
| reg = <0x06>; | |
| #address-cells = <0x01>; | |
| #clock-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| spi-max-frequency = <0x5f5e10>; | |
| clocks = <0x4f>; | |
| clock-names = "clkin"; | |
| clock-output-names = "pll0-clk-rf8\0pll0-clk-rfaux8\0pll0-clk-rf16\0pll0-clk-rf32"; | |
| }; | |
| }; | |
| i2c@85100000 { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| clock-names = "s_axi_aclk"; | |
| clocks = <0x03 0x47>; | |
| compatible = "xlnx,axi-iic-2.0\0xlnx,xps-iic-2.00.a"; | |
| interrupt-names = "iic2intc_irpt"; | |
| interrupts = <0x00 0x6e 0x04>; | |
| reg = <0x85100000 0x1000>; | |
| ltc2992@6a { | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "adi,ltc2992"; | |
| reg = <0x6a>; | |
| channel@0 { | |
| reg = <0x00>; | |
| shunt-resistor-micro-ohms = <0x1f40>; | |
| }; | |
| channel@1 { | |
| reg = <0x01>; | |
| shunt-resistor-micro-ohms = <0xdac>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| clocks { | |
| clock@0 { | |
| #clock-cells = <0x00>; | |
| compatible = "fixed-clock"; | |
| clock-frequency = <0x5f5e100>; | |
| clock-output-names = "adf4371_clkin"; | |
| phandle = <0x4f>; | |
| }; | |
| }; | |
| fixedregulator@0 { | |
| compatible = "regulator-fixed"; | |
| regulator-name = "fixed-supply"; | |
| regulator-min-microvolt = <0x1f4000>; | |
| regulator-max-microvolt = <0x1f4000>; | |
| regulator-boot-on; | |
| phandle = <0x4e>; | |
| }; | |
| stingray_control@0 { | |
| compatible = "adi,one-bit-adc-dac"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| out-gpios = <0x14 0x8b 0x00 0x14 0x8c 0x00 0x14 0x8d 0x00 0x14 0x8e 0x00 0x14 0x8f 0x00 0x14 0x90 0x00>; | |
| label = "stingray_control"; | |
| channel@0 { | |
| reg = <0x00>; | |
| label = "PA_ON"; | |
| }; | |
| channel@1 { | |
| reg = <0x01>; | |
| label = "TR"; | |
| }; | |
| channel@2 { | |
| reg = <0x02>; | |
| label = "TX_LOAD"; | |
| }; | |
| channel@3 { | |
| reg = <0x03>; | |
| label = "RX_LOAD"; | |
| }; | |
| channel@4 { | |
| reg = <0x04>; | |
| label = "5V_CTRL"; | |
| }; | |
| channel@5 { | |
| reg = <0x05>; | |
| label = "PWR_UP_DOWN"; | |
| }; | |
| }; | |
| xud_control@1 { | |
| compatible = "adi,one-bit-adc-dac"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| out-gpios = <0x14 0x91 0x00 0x14 0x92 0x00 0x14 0x93 0x00 0x14 0x94 0x00 0x14 0x95 0x00 0x14 0x96 0x00>; | |
| label = "xud_control"; | |
| channel@0 { | |
| reg = <0x00>; | |
| label = "RX_GAIN_MODE"; | |
| }; | |
| channel@1 { | |
| reg = <0x01>; | |
| label = "TXRX0"; | |
| }; | |
| channel@2 { | |
| reg = <0x02>; | |
| label = "TXRX1"; | |
| }; | |
| channel@3 { | |
| reg = <0x03>; | |
| label = "TXRX2"; | |
| }; | |
| channel@4 { | |
| reg = <0x04>; | |
| label = "TXRX3"; | |
| }; | |
| channel@5 { | |
| reg = <0x05>; | |
| label = "PLL_OUTPUT_SEL"; | |
| }; | |
| }; | |
| imu_control@2 { | |
| compatible = "adi,one-bit-adc-dac"; | |
| #address-cells = <0x01>; | |
| #size-cells = <0x00>; | |
| out-gpios = <0x14 0x97 0x00 0x14 0x98 0x00 0x14 0x99 0x00 0x14 0x9a 0x00 0x14 0x9b 0x00>; | |
| label = "imu_control"; | |
| channel@0 { | |
| reg = <0x00>; | |
| label = "GPIO0"; | |
| }; | |
| channel@1 { | |
| reg = <0x01>; | |
| label = "GPIO1"; | |
| }; | |
| channel@2 { | |
| reg = <0x02>; | |
| label = "GPIO2"; | |
| }; | |
| channel@3 { | |
| reg = <0x03>; | |
| label = "GPIO3"; | |
| }; | |
| channel@4 { | |
| reg = <0x04>; | |
| label = "RST"; | |
| }; | |
| }; | |
| }; |
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