dma_memory.rs

#![no_std]
#![no_main]

use core::{
    panic::PanicInfo,
    sync::atomic::{compiler_fence, Ordering},
};

use cortex_m::singleton;
use rtic::app;
use rtt_target::{rprintln, rtt_init_print};
use stm32f4xx_hal::{
    dma::{
        config::DmaConfig, traits::Direction, Channel0, MemoryToMemory, Stream0, StreamsTuple,
        Transfer,
    },
    pac::DMA2,
    prelude::*,
};

type DmaTransfer = Transfer<
    Stream0<DMA2>,
    Channel0,
    MemoryToMemory<u8>,
    MemoryToMemory<u8>,
    &'static mut [u8; 128],
>;

#[app(device = stm32f4xx_hal::pac, peripherals = true)]
const APP: () = {
    struct Resources {
        transfer: Option<DmaTransfer>,
    }

    #[init]
    fn init(cx: init::Context) -> init::LateResources {
        let rcc = cx.device.RCC.constrain();

        rtt_init_print!();
        rprintln!("Init");

        let _clocks = rcc
            .cfgr
            .sysclk(84.mhz())
            .pclk2(28.mhz())
            .pclk1(28.mhz())
            .freeze();

        let stream_0 = StreamsTuple::new(cx.device.DMA2).0;
        let config = DmaConfig::default()
            .fifo_enable(true)
            .transfer_complete_interrupt(true)
            .memory_increment(true)
            .peripheral_increment(true);

        let first_buffer = singleton!(: [u8; 128] = [0; 128]).unwrap();
        let second_buffer = singleton!(: [u8; 128] = [42; 128]).unwrap();
        let peri = <MemoryToMemory<u8> as Direction>::new();

        let transfer = Some(Transfer::init(
            stream_0,
            peri,
            first_buffer,
            Some(second_buffer),
            config,
        ));

        rprintln!("Finished init");
        init::LateResources { transfer }
    }

    #[idle(resources = [transfer])]
    fn idle(mut cx: idle::Context) -> ! {
        cx.resources.transfer.lock(|shared| {
            if let Some(transfer) = shared {
                transfer.start(|_| {});
            }
        });
        rprintln!("DMA started");
        loop {
            compiler_fence(Ordering::SeqCst);
        }
    }

    #[task(binds = DMA2_STREAM0, priority = 2, resources = [transfer])]
    fn dma(cx: dma::Context) {
        let transfer = cx.resources.transfer.take().unwrap();
        let (_, _, buf, _) = transfer.free();
        rprintln!("Buf 1: {:?}", &buf[0..10]);
    }
};

#[inline(never)]
#[panic_handler]
fn panic(info: &PanicInfo) -> ! {
    cortex_m::interrupt::disable();
    rprintln!("{}", info);
    loop {
        compiler_fence(Ordering::SeqCst);
    }
}