top.sv

// uart 送信テスト
module top(
    input clk,
    input wire RsRx,
    output wire RsTx,
    output led
);

  logic s_axi_aresetn = 1'b1;
  logic interrupt;

  logic [3 : 0] s_axi_awaddr = 4'h04; 
  logic s_axi_awvalid = 1'b1;
  logic s_axi_awready;
  logic [31 : 0] s_axi_wdata = 32'h41; // "A"
  logic [3 : 0] s_axi_wstrb = 4'b0;
  logic s_axi_wvalid = 1'b1;
  logic s_axi_wready;
  logic [1 : 0] s_axi_bresp;
  logic s_axi_bvalid;
  logic s_axi_bready = 1'b1;
  logic [3 : 0] s_axi_araddr = 4'b0;
  logic s_axi_arvalid = 1'b0;
  logic s_axi_arready;
  logic [31 : 0] s_axi_rdata;
  logic [1 : 0] s_axi_rresp;
  logic s_axi_rvalid;
  logic s_axi_rready = 1'b1;

axi_uartlite_0 uart (
  .s_axi_aclk(clk),        // input wire s_axi_aclk
  .s_axi_aresetn(s_axi_aresetn),  // input wire s_axi_aresetn
  .interrupt(interrupt),          // output wire interrupt
  .s_axi_awaddr(s_axi_awaddr),    // input wire [3 : 0] s_axi_awaddr
  .s_axi_awvalid(s_axi_awvalid),  // input wire s_axi_awvalid
  .s_axi_awready(s_axi_awready),  // output wire s_axi_awready
  .s_axi_wdata(s_axi_wdata),      // input wire [31 : 0] s_axi_wdata
  .s_axi_wstrb(s_axi_wstrb),      // input wire [3 : 0] s_axi_wstrb
  .s_axi_wvalid(s_axi_wvalid),    // input wire s_axi_wvalid
  .s_axi_wready(s_axi_wready),    // output wire s_axi_wready
  .s_axi_bresp(s_axi_bresp),      // output wire [1 : 0] s_axi_bresp
  .s_axi_bvalid(s_axi_bvalid),    // output wire s_axi_bvalid
  .s_axi_bready(s_axi_bready),    // input wire s_axi_bready
  .s_axi_araddr(s_axi_araddr),    // input wire [3 : 0] s_axi_araddr
  .s_axi_arvalid(s_axi_arvalid),  // input wire s_axi_arvalid
  .s_axi_arready(s_axi_arready),  // output wire s_axi_arready
  .s_axi_rdata(s_axi_rdata),      // output wire [31 : 0] s_axi_rdata
  .s_axi_rresp(s_axi_rresp),      // output wire [1 : 0] s_axi_rresp
  .s_axi_rvalid(s_axi_rvalid),    // output wire s_axi_rvalid
  .s_axi_rready(s_axi_rready),    // input wire s_axi_rready
  .rx(RsRx),                        // input wire rx
  .tx(RsTx)                        // output wire tx
);

assign led = RsTx;

endmodule