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the-snowwhite/Mksocfpga_Developer_Notes.asciidoc

Created May 13, 2019 15:59
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Mksocfpga_Developer_Notes.asciidoc

Mksocfpga Developer:

A presentation from one of the Machinekit meetups regarding the SoC+FPGA stuff: https://www.youtube.com/watch?v=veM83KCytuQ

In addition to the recorded presentation, you can get the slides used from github:

The Current Altera division has 2 basic types of projects:

xxx_DB25

The xxx_DB25 ones are geared towards connecting MESA hardware using the [DB25 connector](http://blog.machinekit.io/2016/11/you-will-recall-that-while-back-charles.html)

The xxx_Cramps ones are more geared towards having an easy upgrade path for bbb users that allready have a Cramps board via:
[Cramps2nano-soc bob](https://github.com/the-snowwhite/socfpga-kicad/tree/master/Cramps2nano-soc) providing full 3d-printing functionality

xxx_Cramps

The xxx_Cramps versions are (initially) geared towards interfacing with the Cramps interface made by Charles for the BBB( with full ADC functionality), Enabling 3D printing. (Hence the), providing an easy path to upgrade from a Beagle B setup. But also provide Cramps independent breadboard based experimenting

There is allready an Interface design created for interfacing the DExx Nano (soc) boards to the Cramps and the design files are here:

The DE10_Nano_FB_Cramps project is as the name implies designed to interface with a Cramps board and provide a framebuffer on the hdmi pins of the DE10 Nano.

The DExx ADC’s are actually connected directly to the FPGA via dedicated non changable I/O pins. via these 4 pins: https://github.com/machinekit/mksocfpga/blob/master/HW/QuartusProjects/DE10_Nano_FB_Cramps/DE10_Nano_FB_Cramps.sv#L12 However they are specific for the Terasic boards so this functionality is keept somewhat separate as it is hard to make generiric enough for all possible future additions.

How:

The VHD files are VHDL code describing the logic inside the FPGA. This code gets compiled by the vendor tool-chain and turned into a configuration file used to program the FPGA.

Basically, if you want to customize something, you need to create a new config or modify an existing one. The existing configs are found here:

The PIN_*.vhd file is where the "magic" happens. The rest of the design will elaborate and instantiate the logic defined in the PIN file. So you edit/create an appropriate PIN file, then make sure your FPGA project uses that PIN file when building.

When you are laying out your own custom DExx interface board, you don’t have to stay restricted to allready made pinouts. you can create your own custom pinout containing any of the mesa cores contained in the top level of this folder: https://github.com/machinekit/mksocfpga/tree/master/HW/hm2

this commit shows all that is needed to do to to add a customized core/pin configuration: https://github.com/machinekit/mksocfpga/commit/0c48daa7620a16c132b70140297063a5fb889025

there are some notes written during the process of creating the mksocfpga project which also may be usefull: https://github.com/machinekit/mksocfpga/tree/master/docs

The current workin quartus bitfile generators are the (DE0_xxx / DE10_xxx) projects residing in this folder:

the xxxx_DB25 contain only the original Mesa functionality (ie no display and no DExx_Nano adc), and are geared towards the DB25 connector Charles has made to interface directly to Mesa hardware. It is importaint to note that some of the pinouts on the route from the .PIN file to the actual GPIO’s are rerouted to different pins.

Remember it is very easy/simple to change pinouts inside the FPGA, you can also route to the Arduino connectors if so needed…​!

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