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Last active August 29, 2015 13:55
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Notes from Bruce Land video - microcontrollers #2
// see http://people.ece.cornell.edu/land/courses/ece4760/labs/s2012/Sched1GCC644.c
// see http://people.ece.cornell.edu/land/courses/ece4760/Timers/index.html
//**********************************************************
//timer 0 compare ISR
ISR (TIMER0_COMPA_vect)
{
// Called every millis
// 75 cycles in
// 32 cycles save cpu state
// 8 cycles overhead
// 32 cycles resume cpu state
// 75 cycles out
}
//**********************************************************
//**********************************************************
//Set it all up
void initialize(void)
{
//set up timer 0 for 1 mSec ticks
TIMSK0 = 2; // turn on timer 0 cmp match ISR (Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable)
OCR0A = 249; //set the compare reg to 250 time ticks
TCCR0A = 0b00000010; // (1<<WGM01) turn on clear-on-match
TCCR0B = 0b00000011; // clock prescalar to 64
//crank up the ISRs
sei();
}
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