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October 7, 2017 16:45
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Pixel readout architecture simulation
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import numpy as np | |
import random | |
from numba import jit | |
@jit | |
def fei3_sim(PIXEL_AREA = 36.4*36.4, HIT_RATE_CM = 200*(10**6), ): | |
SIM_TIME = 100000 | |
PIXEL_NO = 512*2 | |
MEAN_TOT = 10 | |
READ_BX = 2 | |
PIXEL_MAX_LATENCY = 63 | |
TRIG_MEM_SIZE = 128 | |
LATENCY = 800 | |
WAIT_FOR_TRIG_MEM = False | |
analog_pileup = 0.0 | |
digital_pileup = 0.0 | |
late_copy = 0.0 | |
total_hits = 0.0 | |
trig_mem_pileup = 0.0 | |
trig_mem = np.zeros((TRIG_MEM_SIZE) ,dtype=np.int) | |
pix_mem = np.zeros((PIXEL_NO) ,dtype=[('tot_cnt', int), ('bx_cnt', int)]) | |
pixel_hit_rate_bx = ((float(PIXEL_AREA)/(10000*10000)) * HIT_RATE_CM )/ (40*(10**6)) | |
read_cnt = 0 | |
for _ in range(SIM_TIME): | |
#hit counter/tot | |
pix_mem['tot_cnt'][pix_mem['tot_cnt']>0] -= 1 | |
#bx counter | |
pix_mem['bx_cnt'][pix_mem['bx_cnt'] > 0] += 1 | |
trig_mem[trig_mem == LATENCY] = 0 #remove hits after latency | |
trig_mem[trig_mem > 0] += 1 | |
late_copy += len(pix_mem['bx_cnt'][pix_mem['bx_cnt'] == PIXEL_MAX_LATENCY]) #Late copy | |
#process eoc | |
if read_cnt >= READ_BX-1: | |
for read_pix in np.where((pix_mem['bx_cnt'] > 0) & (pix_mem['tot_cnt']==0))[0]: #something to read | |
empty_mems = np.where(trig_mem == 0) | |
if len(empty_mems[0]): | |
mem_loc = empty_mems[0][0] | |
val = pix_mem['bx_cnt'][read_pix] % (PIXEL_MAX_LATENCY +1) | |
trig_mem[mem_loc] = val | |
if WAIT_FOR_TRIG_MEM == True: | |
pix_mem['bx_cnt'][read_pix] = 0 #clear this pixel | |
read_cnt = 0 | |
else: | |
trig_mem_pileup += 1 | |
if WAIT_FOR_TRIG_MEM == False: | |
pix_mem['bx_cnt'][read_pix] = 0 #clear this pixel | |
read_cnt = 0 | |
break | |
else: | |
read_cnt += 1 | |
#process hits | |
for pix in range(pix_mem.size): | |
if random.random() < pixel_hit_rate_bx: | |
total_hits += 1 | |
if pix_mem['tot_cnt'][pix] > 0: | |
analog_pileup += 1 #Analog pielup | |
else: | |
pix_mem['tot_cnt'][pix] = pix_mem['tot_cnt'][pix] + MEAN_TOT +1 | |
if pix_mem['bx_cnt'][pix] > 0: | |
digital_pileup += 1 #Digital pielup | |
elif pix_mem['bx_cnt'][pix] == 0: #start bx_cnt | |
pix_mem['bx_cnt'][pix] = 1 | |
return analog_pileup, digital_pileup, late_copy, trig_mem_pileup, total_hits | |
@jit | |
def cba_sim(PIXEL_AREA = 50*50, HIT_RATE_CM = 4000*(10**6), TRIGGER = 1*(10**6)): | |
SIM_TIME = 100000 | |
PIXEL_NO = 400*8 | |
REGION_SIZE = 4 | |
MEAN_TOT = 4 | |
READ_BX = 2 | |
PIXEL_LATENCY = 500 | |
LTENCY_MEM = 8 | |
analog_pileup = 0.0 | |
digital_pileup = 0.0 | |
total_hits = 0.0 | |
pix_array = np.zeros((PIXEL_NO) ,dtype = np.int) | |
region_array = np.zeros((PIXEL_NO/REGION_SIZE, LTENCY_MEM) ,dtype = np.int) | |
pixel_hit_rate_bx = ((float(PIXEL_AREA)/(10000*10000)) * HIT_RATE_CM )/ (40*(10**6)) | |
trigger_rate_bx = float(TRIGGER) / (40*(10**6)) | |
read_cnt = 0 | |
for bx in range(SIM_TIME): | |
#trigger | |
if random.random() < trigger_rate_bx: | |
region_array[region_array==1] = -1 | |
#hit counter/tot | |
pix_array[pix_array>0] -= 1 | |
region_array[region_array>0] -= 1 | |
#readout | |
if read_cnt >= READ_BX-1: | |
to_read = np.where(region_array==-1) | |
for readi in range(len(to_read[0])): | |
region_array[to_read[0][readi], to_read[1][readi]] = 0 | |
read_cnt = 0 | |
break | |
else: | |
read_cnt += 1 | |
region_hits = np.zeros((PIXEL_NO/REGION_SIZE) ,dtype = np.int) | |
hits = np.random.random_sample((PIXEL_NO,)) | |
for pix in np.where(hits<pixel_hit_rate_bx)[0]: | |
total_hits += 1 | |
if pix_array[pix] > 0: | |
analog_pileup += 1.0 #Analog pielup | |
else: | |
pix_array[pix] = pix_array[pix] + MEAN_TOT +1 | |
region_hits[pix/REGION_SIZE] = 1 | |
for reg in np.where(region_hits==1)[0]: | |
stored = False | |
for mem in range(LTENCY_MEM): | |
if(region_array[reg][mem] == 0): | |
region_array[reg][mem] = PIXEL_LATENCY | |
stored = True | |
break | |
if stored == False: | |
digital_pileup +=1 | |
return analog_pileup, digital_pileup, total_hits |
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