theokelo/logic_gate.v Secret

## logic_gate.v
`timescale 1ns / 1ps

module logic_gate(y,a,b);

input a,b;
output y;

assign y = ~ (a & b);

endmodule
	`timescale 1ns / 1ps

	module logic_gate(y,a,b);

	input a,b;
	output y;

	assign y = ~ (a & b);

	endmodule