Skip to content

Instantly share code, notes, and snippets.

@theokelo
Created November 2, 2021 00:02
Embed
What would you like to do?
`timescale 1ns / 1ps
module logic_gate(y,a,b);
input a,b;
output y;
assign y = ~ (a & b);
endmodule
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment